diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c linux-2.6.27.6.yaffs/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
--- linux-2.6.27.6/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+	struct stat sb;
+	uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
+
+	if (argc != 3) {
+		fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
+				argv[0]);
+		return EXIT_FAILURE;
+	}
+
+	if (stat(argv[1], &sb) == -1) {
+		perror("stat");
+		return EXIT_FAILURE;
+	}
+
+	/* Convert hex characters to dec number */
+	errno = 0;
+	if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
+		if (errno != 0)
+			perror("sscanf");
+		else
+			fprintf(stderr, "No matching characters\n");
+
+		return EXIT_FAILURE;
+	}
+
+	vmlinux_size = (uint64_t)sb.st_size;
+	vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
+
+	/*
+	 * Align with 16 bytes: "greater than that used for any standard data
+	 * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
+	 */
+
+	vmlinuz_load_addr += (16 - vmlinux_size % 16);
+
+	printf("0x%llx\n", vmlinuz_load_addr);
+
+	return EXIT_SUCCESS;
+}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/dbg.c linux-2.6.27.6.yaffs/arch/mips/boot/compressed/dbg.c
--- linux-2.6.27.6/arch/mips/boot/compressed/dbg.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/dbg.c	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,37 @@
+/*
+ * MIPS-specific debug support for pre-boot environment
+ *
+ * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
+ * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
+ * need to implement your own putc().
+ */
+#include <linux/compiler.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+void __weak putc(char c)
+{
+}
+
+void puts(const char *s)
+{
+	char c;
+	while ((c = *s++) != '\0') {
+		putc(c);
+		if (c == '\n')
+			putc('\r');
+	}
+}
+
+void puthex(unsigned long long val)
+{
+
+	unsigned char buf[10];
+	int i;
+	for (i = 7; i >= 0; i--) {
+		buf[i] = "0123456789ABCDEF"[val & 0x0F];
+		val >>= 4;
+	}
+	buf[8] = '\0';
+	puts(buf);
+}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/decompress.c linux-2.6.27.6.yaffs/arch/mips/boot/compressed/decompress.c
--- linux-2.6.27.6/arch/mips/boot/compressed/decompress.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/decompress.c	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <asm/addrspace.h>
+
+/*
+ * These two variables specify the free mem region
+ * that can be used for temporary malloc area
+ */
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
+
+/* The linker tells us where the image is. */
+extern unsigned char __image_begin, __image_end;
+
+/* debug interfaces  */
+extern void puts(const char *s);
+extern void puthex(unsigned long long val);
+
+void error(char *x)
+{
+	puts("\n\n");
+	puts(x);
+	puts("\n\n -- System halted");
+
+	while (1)
+		;	/* Halt */
+}
+
+/* activate the code for pre-boot environment */
+#define STATIC static
+
+#ifdef CONFIG_KERNEL_GZIP
+void *memcpy(void *dest, const void *src, size_t n)
+{
+	int i;
+	const char *s = src;
+	char *d = dest;
+
+	for (i = 0; i < n; i++)
+		d[i] = s[i];
+	return dest;
+}
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_BZIP2
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+#include "../../../../lib/decompress_bunzip2.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZMA
+#include "../../../../lib/decompress_unlzma.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZO
+#include "../../../../lib/decompress_unlzo.c"
+#endif
+
+void decompress_kernel(unsigned long boot_heap_start)
+{
+	unsigned long zimage_start, zimage_size;
+
+	zimage_start = (unsigned long)(&__image_begin);
+	zimage_size = (unsigned long)(&__image_end) -
+	    (unsigned long)(&__image_begin);
+
+	puts("zimage at:     ");
+	puthex(zimage_start);
+	puts(" ");
+	puthex(zimage_size + zimage_start);
+	puts("\n");
+
+	/* This area are prepared for mallocing when decompressing */
+	free_mem_ptr = boot_heap_start;
+	free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
+
+	/* Display standard Linux/MIPS boot prompt */
+	puts("Uncompressing Linux at load address ");
+	puthex(VMLINUX_LOAD_ADDRESS_ULL);
+	puts("\n");
+
+	/* Decompress the kernel with according algorithm */
+	decompress((char *)zimage_start, zimage_size, 0, 0,
+		   (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
+
+	/* FIXME: should we flush cache here? */
+	puts("Now, booting the kernel...\n");
+}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/dummy.c linux-2.6.27.6.yaffs/arch/mips/boot/compressed/dummy.c
--- linux-2.6.27.6/arch/mips/boot/compressed/dummy.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/dummy.c	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,4 @@
+int main(void)
+{
+	return 0;
+}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/head.S linux-2.6.27.6.yaffs/arch/mips/boot/compressed/head.S
--- linux-2.6.27.6/arch/mips/boot/compressed/head.S	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/head.S	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf Electronics
+ * Written by Ralf Baechle and Andreas Busse
+ * Copyright (C) 1995 - 1999 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Modified for DECStation and hence R3000 support by Paul M. Antoine
+ * Further modifications by David S. Miller and Harald Koerfgen
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+	.set noreorder
+	.cprestore
+	LEAF(start)
+start:
+	/* Save boot rom start args */
+	move	s0, a0
+	move	s1, a1
+	move	s2, a2
+	move	s3, a3
+
+	/* Clear BSS */
+	PTR_LA	a0, _edata
+	PTR_LA	a2, _end
+1:	sw	zero, 0(a0)
+	bne	a2, a0, 1b
+	 addiu	a0, a0, 4
+
+	PTR_LA	a0, (.heap)          /* heap address */
+	PTR_LA  sp, (.stack + 8192)  /* stack address */
+
+	PTR_LA	ra, 2f
+	PTR_LA	k0, decompress_kernel
+	jr	k0
+	 nop
+2:
+	move	a0, s0
+	move	a1, s1
+	move	a2, s2
+	move	a3, s3
+	PTR_LI	k0, KERNEL_ENTRY
+	jr	k0
+	 nop
+3:
+	b	3b
+	 nop
+	END(start)
+
+	.comm .heap,BOOT_HEAP_SIZE,4
+	.comm .stack,4096*2,4
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/ld.script linux-2.6.27.6.yaffs/arch/mips/boot/compressed/ld.script
--- linux-2.6.27.6/arch/mips/boot/compressed/ld.script	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/ld.script	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,50 @@
+/*
+ * ld.script for compressed kernel support of MIPS
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin <wuzhanjing@gmail.com>
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
+ */
+
+OUTPUT_ARCH(mips)
+ENTRY(start)
+SECTIONS
+{
+	/* Text and read-only data */
+	/* . = VMLINUZ_LOAD_ADDRESS; */
+	.text : {
+		*(.text)
+		*(.rodata)
+	}
+	/* End of text section */
+
+	/* Writable data */
+	.data : {
+		*(.data)
+		/* Put the compressed image here */
+		__image_begin = .;
+		*(.image)
+		__image_end = .;
+		CONSTRUCTORS
+	}
+	. = ALIGN(16);
+	_edata = .;
+	/* End of data section */
+
+	/* BSS */
+	.bss : {
+		*(.bss)
+	}
+	. = ALIGN(16);
+	_end = .;
+
+	/* Sections to be discarded */
+	/DISCARD/ : {
+		*(.MIPS.options)
+		*(.options)
+		*(.pdr)
+		*(.reginfo)
+		*(.comment)
+		*(.note)
+	}
+}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/Makefile linux-2.6.27.6.yaffs/arch/mips/boot/compressed/Makefile
--- linux-2.6.27.6/arch/mips/boot/compressed/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/Makefile	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,108 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.
+#
+# Adapted for MIPS Pete Popov, Dan Malek
+#
+# Copyright (C) 1994 by Linus Torvalds
+# Adapted for PowerPC by Gary Thomas
+# modified by Cort (cort@cs.nmt.edu)
+#
+# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
+# Author: Wu Zhangjin <wuzhangjin@gmail.com>
+#
+
+# set the default size of the mallocing area for decompressing
+BOOT_HEAP_SIZE := 0x400000
+
+# Disable Function Tracer
+KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
+
+KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
+	-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
+
+KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
+	-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
+	-DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
+
+targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
+
+# decompressor objects (linked with vmlinuz)
+vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+
+ifdef CONFIG_DEBUG_ZBOOT
+vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY)		   += $(obj)/uart-alchemy.o
+endif
+
+targets += vmlinux.bin
+OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
+	$(call if_changed,objcopy)
+
+tool_$(CONFIG_KERNEL_GZIP)    = gzip
+tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
+tool_$(CONFIG_KERNEL_LZMA)    = lzma
+tool_$(CONFIG_KERNEL_LZO)     = lzo
+
+targets += vmlinux.bin.z
+$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
+	$(call if_changed,$(tool_y))
+
+targets += piggy.o
+OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
+                        --set-section-flags=.image=contents,alloc,load,readonly,data
+$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
+	$(call if_changed,objcopy)
+
+# Calculate the load address of the compressed kernel image
+hostprogs-y := calc_vmlinuz_load_addr
+
+VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
+		$(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
+
+vmlinuzobjs-y += $(obj)/piggy.o
+
+quiet_cmd_zld = LD      $@
+      cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
+quiet_cmd_strip = STRIP   $@
+      cmd_strip = $(STRIP) -s $@
+vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
+	$(call cmd,zld)
+	$(call cmd,strip)
+
+#
+# Some DECstations need all possible sections of an ECOFF executable
+#
+ifdef CONFIG_MACH_DECSTATION
+  e2eflag := -a
+endif
+
+# elf2ecoff can only handle 32bit image
+hostprogs-y += ../elf2ecoff
+
+ifdef CONFIG_32BIT
+	VMLINUZ = vmlinuz
+else
+	VMLINUZ = vmlinuz.32
+endif
+
+quiet_cmd_32 = OBJCOPY $@
+      cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+vmlinuz.32: vmlinuz
+	$(call cmd,32)
+
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
+vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
+	$(call cmd,ecoff)
+
+OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
+vmlinuz.bin: vmlinuz
+	$(call cmd,objcopy)
+
+OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
+vmlinuz.srec: vmlinuz
+	$(call cmd,objcopy)
+
+clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/uart-16550.c linux-2.6.27.6.yaffs/arch/mips/boot/compressed/uart-16550.c
--- linux-2.6.27.6/arch/mips/boot/compressed/uart-16550.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/uart-16550.c	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,43 @@
+/*
+ * 16550 compatible uart based serial debug support for zboot
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <linux/init.h>
+
+#include <asm/addrspace.h>
+
+#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
+#define UART_BASE 0x1fd003f8
+#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
+#endif
+
+#ifdef CONFIG_AR7
+#include <ar7.h>
+#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
+#endif
+
+#ifndef PORT
+#error please define the serial port address for your own machine
+#endif
+
+static inline unsigned int serial_in(int offset)
+{
+	return *((char *)PORT(offset));
+}
+
+static inline void serial_out(int offset, int value)
+{
+	*((char *)PORT(offset)) = value;
+}
+
+void putc(char c)
+{
+	int timeout = 1024;
+
+	while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
+		;
+
+	serial_out(UART_TX, c);
+}
diff -uNra linux-2.6.27.6/arch/mips/boot/compressed/uart-alchemy.c linux-2.6.27.6.yaffs/arch/mips/boot/compressed/uart-alchemy.c
--- linux-2.6.27.6/arch/mips/boot/compressed/uart-alchemy.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/boot/compressed/uart-alchemy.c	2011-05-16 21:56:25.000000000 +0800
@@ -0,0 +1,7 @@
+#include <asm/mach-au1x00/au1000.h>
+
+void putc(char c)
+{
+	/* all current (Jan. 2010) in-kernel boards */
+	alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff -uNra linux-2.6.27.6/arch/mips/include/asm/lemote/pci.h linux-2.6.27.6.yaffs/arch/mips/include/asm/lemote/pci.h
--- linux-2.6.27.6/arch/mips/include/asm/lemote/pci.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/include/asm/lemote/pci.h	2011-05-08 18:02:21.000000000 +0800
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General
+ * Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be
+ * useful, but WITHOUT ANY WARRANTY; without even the implied
+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ * PURPOSE.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
+ */
+
+#ifndef _LEMOTE_PCI_H_
+#define _LEMOTE_PCI_H_
+
+#define LEMOTE_IO_PORT_BASE         CKSEG1ADDR(0xbfd00000)
+
+#endif /* !_LEMOTE_PCI_H_ */
diff -uNra linux-2.6.27.6/arch/mips/Kconfig linux-2.6.27.6.yaffs/arch/mips/Kconfig
--- linux-2.6.27.6/arch/mips/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/Kconfig	2011-05-16 21:43:08.000000000 +0800
@@ -6,7 +6,6 @@
 	select HAVE_ARCH_KGDB
 	# Horrible source of confusion.  Die, die, die ...
 	select EMBEDDED
-	select RTC_LIB
 
 mainmenu "Linux/MIPS Kernel Configuration"
 
@@ -169,6 +168,7 @@
 	select I8259
 	select ISA
 	select IRQ_CPU
+	select I8253
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -181,6 +181,32 @@
 	  Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
 	  an FPGA northbridge
 
+config LEMOTE_FULONG2F
+	bool "Lemote LOONGSON2F Fulong mini-PC"
+	select ARCH_SPARSEMEM_ENABLE
+	select CEVT_R4K
+	select CSRC_R4K
+	select SYS_HAS_CPU_LOONGSON2
+	select DMA_NONCOHERENT
+ 	select BOOT_ELF32
+ 	select BOARD_SCACHE
+ 	select HAVE_STD_PC_SERIAL_PORT
+	select HW_HAS_PCI
+	select I8259
+	select ISA
+	select IRQ_CPU
+	select I8253
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_HAS_EARLY_PRINTK
+	select GENERIC_HARDIRQS_NO__DO_IRQ
+	select GENERIC_ISA_DMA_SUPPORT_BROKEN
+	select CPU_HAS_WB
+	help
+	  Lemote Fulong mini-PC board based on the Chinese Loongson-2F CPU
+
 config MIPS_MALTA
 	bool "MIPS Malta board"
 	select ARCH_MAY_HAVE_PC_FDC
@@ -1857,6 +1883,12 @@
 
 	  If unsure, say Y. Only embedded should say N here.
 
+config SYS_SUPPORTS_ZBOOT
+	bool "support compress vmlinuz"
+
+config KERNEL_GZIP
+	bool "USE GZIP"
+
 endmenu
 
 config RWSEM_GENERIC_SPINLOCK
diff -uNra linux-2.6.27.6/arch/mips/kernel/8250-platform.c linux-2.6.27.6.yaffs/arch/mips/kernel/8250-platform.c
--- linux-2.6.27.6/arch/mips/kernel/8250-platform.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/8250-platform.c	2011-05-08 18:02:21.000000000 +0800
@@ -20,10 +20,24 @@
 }
 
 static struct plat_serial8250_port uart8250_data[] = {
+#ifdef CONFIG_LEMOTE_FULONG2F
+#if 1 //for fl
+	PORT(0x2F8, 3),
+#else
+	{.membase = (void*)(0xffffffffbff003f8),
+	.irq = 19,
+	.uartclk = 3686400,
+	.iotype = UPIO_MEM,
+	.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST ,
+	.regshift = 0,
+	},
+#endif
+#else
 	PORT(0x3F8, 4),
 	PORT(0x2F8, 3),
 	PORT(0x3E8, 4),
 	PORT(0x2E8, 3),
+#endif
 	{ },
 };
 
diff -uNra linux-2.6.27.6/arch/mips/kernel/early_printk.c linux-2.6.27.6.yaffs/arch/mips/kernel/early_printk.c
--- linux-2.6.27.6/arch/mips/kernel/early_printk.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/early_printk.c	2011-05-11 18:36:09.000000000 +0800
@@ -17,12 +17,14 @@
 static void __init
 early_console_write(struct console *con, const char *s, unsigned n)
 {
+#if 0 //mj del for topstar nouart
 	while (n-- && *s) {
 		if (*s == '\n')
 			prom_putchar('\r');
 		prom_putchar(*s);
 		s++;
 	}
+#endif
 }
 
 static struct console early_console __initdata = {
diff -uNra linux-2.6.27.6/arch/mips/kernel/i8259.c linux-2.6.27.6.yaffs/arch/mips/kernel/i8259.c
--- linux-2.6.27.6/arch/mips/kernel/i8259.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/i8259.c	2011-05-08 18:02:21.000000000 +0800
@@ -53,7 +53,7 @@
 /*
  * This contains the irq mask for both 8259A irq controllers,
  */
-static unsigned int cached_irq_mask = 0xffff;
+unsigned int cached_irq_mask = 0xffff;
 
 #define cached_master_mask	(cached_irq_mask)
 #define cached_slave_mask	(cached_irq_mask >> 8)
@@ -175,11 +175,15 @@
 	if (irq & 8) {
 		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
 		outb(cached_slave_mask, PIC_SLAVE_IMR);
+		inb(PIC_SLAVE_IMR);	
 		outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
+		inb(PIC_SLAVE_CMD);
 		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
+		inb(PIC_MASTER_CMD);
 	} else {
 		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
 		outb(cached_master_mask, PIC_MASTER_IMR);
+		inb(PIC_MASTER_IMR);
 		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
 	}
 	smtc_im_ack_irq(irq);
@@ -203,8 +207,8 @@
 		 * At this point we can be sure the IRQ is spurious,
 		 * lets ACK and report it. [once per IRQ]
 		 */
-		if (!(spurious_irq_mask & irqmask)) {
-			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
+		if (!(spurious_irq_mask & irqmask) || 1) {
+			printk("spurious 8259A interrupt: IRQ%d.\n", irq);
 			spurious_irq_mask |= irqmask;
 		}
 		atomic_inc(&irq_err_count);
diff -uNra linux-2.6.27.6/arch/mips/kernel/Makefile linux-2.6.27.6.yaffs/arch/mips/kernel/Makefile
--- linux-2.6.27.6/arch/mips/kernel/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/Makefile	2011-05-26 19:59:34.000000000 +0800
@@ -86,6 +86,6 @@
 
 CFLAGS_cpu-bugs64.o	= $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
 
-obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
+#obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
 EXTRA_CFLAGS += -Werror
diff -uNra linux-2.6.27.6/arch/mips/kernel/rtc.c linux-2.6.27.6.yaffs/arch/mips/kernel/rtc.c
--- linux-2.6.27.6/arch/mips/kernel/rtc.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/rtc.c	2011-05-08 18:02:21.000000000 +0800
@@ -0,0 +1,232 @@
+/*
+ * RTC related functions
+ */
+#include <linux/acpi.h>
+#include <linux/bcd.h>
+#include <linux/mc146818rtc.h>
+#include <linux/platform_device.h>
+#include <linux/pnp.h>
+
+#include <asm/time.h>
+
+#ifdef CONFIG_X86_32
+/*
+ * This is a special lock that is owned by the CPU and holds the index
+ * register we are working with.  It is required for NMI access to the
+ * CMOS/RTC registers.  See include/asm-i386/mc146818rtc.h for details.
+ */
+volatile unsigned long cmos_lock = 0;
+EXPORT_SYMBOL(cmos_lock);
+#endif
+
+/* For two digit years assume time is always after that */
+#define CMOS_YEARS_OFFS 2000
+
+#if 0
+DEFINE_SPINLOCK(rtc_lock);
+EXPORT_SYMBOL(rtc_lock);
+#else
+extern spinlock_t rtc_lock;
+#endif
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be
+ * called 500 ms after the second nowtime has started, because when
+ * nowtime is written into the registers of the CMOS clock, it will
+ * jump to the next second precisely 500 ms later. Check the Motorola
+ * MC146818A or Dallas DS12887 data sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ *      sets the minutes. Usually you'll only notice that after reboot!
+ */
+int mach_set_rtc_mmss(unsigned long nowtime)
+{
+	int retval = 0;
+	int real_seconds, real_minutes, cmos_minutes;
+	unsigned char save_control, save_freq_select;
+
+	 /* tell the clock it's being set */
+	save_control = CMOS_READ(RTC_CONTROL);
+	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
+
+	/* stop and reset prescaler */
+	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
+	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+
+	cmos_minutes = CMOS_READ(RTC_MINUTES);
+	if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
+		BCD_TO_BIN(cmos_minutes);
+
+	/*
+	 * since we're only adjusting minutes and seconds,
+	 * don't interfere with hour overflow. This avoids
+	 * messing with unknown time zones but requires your
+	 * RTC not to be off by more than 15 minutes
+	 */
+	real_seconds = nowtime % 60;
+	real_minutes = nowtime / 60;
+	/* correct for half hour time zone */
+	if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
+		real_minutes += 30;
+	real_minutes %= 60;
+
+	if (abs(real_minutes - cmos_minutes) < 30) {
+		if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+			BIN_TO_BCD(real_seconds);
+			BIN_TO_BCD(real_minutes);
+		}
+		CMOS_WRITE(real_seconds,RTC_SECONDS);
+		CMOS_WRITE(real_minutes,RTC_MINUTES);
+	} else {
+		printk(KERN_WARNING
+		       "set_rtc_mmss: can't update from %d to %d\n",
+		       cmos_minutes, real_minutes);
+		retval = -1;
+	}
+
+	/* The following flags have to be released exactly in this order,
+	 * otherwise the DS12887 (popular MC146818A clone with integrated
+	 * battery and quartz) will not reset the oscillator and will not
+	 * update precisely 500 ms later. You won't find this mentioned in
+	 * the Dallas Semiconductor data sheets, but who believes data
+	 * sheets anyway ...                           -- Markus Kuhn
+	 */
+	CMOS_WRITE(save_control, RTC_CONTROL);
+	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+
+	return retval;
+}
+
+unsigned long mach_get_cmos_time(void)
+{
+	unsigned int status, year, mon, day, hour, min, sec, century = 0;
+
+	/*
+	 * If UIP is clear, then we have >= 244 microseconds before
+	 * RTC registers will be updated.  Spec sheet says that this
+	 * is the reliable way to read RTC - registers. If UIP is set
+	 * then the register access might be invalid.
+	 */
+	while ((CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
+		cpu_relax();
+
+	sec = CMOS_READ(RTC_SECONDS);
+	min = CMOS_READ(RTC_MINUTES);
+	hour = CMOS_READ(RTC_HOURS);
+	day = CMOS_READ(RTC_DAY_OF_MONTH);
+	mon = CMOS_READ(RTC_MONTH);
+	year = CMOS_READ(RTC_YEAR);
+
+#ifdef CONFIG_ACPI
+	if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
+	    acpi_gbl_FADT.century)
+		century = CMOS_READ(acpi_gbl_FADT.century);
+#endif
+
+	status = CMOS_READ(RTC_CONTROL);
+	WARN_ON_ONCE(RTC_ALWAYS_BCD && (status & RTC_DM_BINARY));
+
+	if (RTC_ALWAYS_BCD || !(status & RTC_DM_BINARY)) {
+		BCD_TO_BIN(sec);
+		BCD_TO_BIN(min);
+		BCD_TO_BIN(hour);
+		BCD_TO_BIN(day);
+		BCD_TO_BIN(mon);
+		BCD_TO_BIN(year);
+	}
+
+	if (century) {
+		BCD_TO_BIN(century);
+		year += century * 100;
+		printk(KERN_INFO "Extended CMOS year: %d\n", century * 100);
+	} else
+		year += CMOS_YEARS_OFFS;
+
+	return mktime(year, mon, day, hour, min, sec);
+}
+
+/* Routines for accessing the CMOS RAM/RTC. */
+unsigned char rtc_cmos_read(unsigned char addr)
+{
+	unsigned char val;
+
+	lock_cmos_prefix(addr);
+	outb(addr, RTC_PORT(0));
+	val = inb(RTC_PORT(1));
+	lock_cmos_suffix(addr);
+	return val;
+}
+EXPORT_SYMBOL(rtc_cmos_read);
+
+void rtc_cmos_write(unsigned char val, unsigned char addr)
+{
+	lock_cmos_prefix(addr);
+	outb(addr, RTC_PORT(0));
+	outb(val, RTC_PORT(1));
+	lock_cmos_suffix(addr);
+}
+EXPORT_SYMBOL(rtc_cmos_write);
+
+static int set_rtc_mmss(unsigned long nowtime)
+{
+	int retval;
+	unsigned long flags;
+
+	spin_lock_irqsave(&rtc_lock, flags);
+	retval = set_wallclock(nowtime);
+	spin_unlock_irqrestore(&rtc_lock, flags);
+
+	return retval;
+}
+
+/* not static: needed by APM */
+#if 0
+unsigned long read_persistent_clock(void)
+{
+	unsigned long retval, flags;
+
+	spin_lock_irqsave(&rtc_lock, flags);
+	retval = get_wallclock();
+	spin_unlock_irqrestore(&rtc_lock, flags);
+
+	return retval;
+}
+#endif
+
+int update_persistent_clock(struct timespec now)
+{
+	return set_rtc_mmss(now.tv_sec);
+}
+
+
+static struct resource rtc_resources[] = {
+	[0] = {
+		.start	= RTC_PORT(0),
+		.end	= RTC_PORT(1),
+		.flags	= IORESOURCE_IO,
+	},
+	[1] = {
+		.start	= RTC_IRQ,
+		.end	= RTC_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	}
+};
+
+static struct platform_device rtc_device = {
+	.name		= "rtc_cmos",
+	.id		= -1,
+	.resource	= rtc_resources,
+	.num_resources	= ARRAY_SIZE(rtc_resources),
+};
+
+static __init int add_rtc_cmos(void)
+{
+#ifdef CONFIG_PNP
+	if (!pnp_platform_devices)
+		platform_device_register(&rtc_device);
+#else
+	platform_device_register(&rtc_device);
+#endif /* CONFIG_PNP */
+	return 0;
+}
+device_initcall(add_rtc_cmos);
diff -uNra linux-2.6.27.6/arch/mips/kernel/time.c linux-2.6.27.6.yaffs/arch/mips/kernel/time.c
--- linux-2.6.27.6/arch/mips/kernel/time.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/time.c	2011-05-08 18:02:21.000000000 +0800
@@ -44,7 +44,7 @@
 	return rtc_mips_set_time(nowtime);
 }
 
-int update_persistent_clock(struct timespec now)
+int __weak update_persistent_clock(struct timespec now)
 {
 	return rtc_mips_set_mmss(now.tv_sec);
 }
diff -uNra linux-2.6.27.6/arch/mips/kernel/vmlinux.lds linux-2.6.27.6.yaffs/arch/mips/kernel/vmlinux.lds
--- linux-2.6.27.6/arch/mips/kernel/vmlinux.lds	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/kernel/vmlinux.lds	2011-06-21 14:33:11.000000000 +0800
@@ -0,0 +1,215 @@
+/*
+ * Automatically generated C config: don't edit
+ * Linux kernel version: 2.6.27.6
+ * Tue Jun 21 14:32:52 2011
+ */
+/*
+ * DO NOT MODIFY.
+ *
+ * This file was generated by Kbuild
+ *
+ */
+/* MIPS pt_regs offsets. */
+/* MIPS task_struct offsets. */
+/* MIPS thread_info offsets. */
+/* MIPS specific thread_struct offsets. */
+/* Size of struct page */
+/* Linux mm_struct offsets. */
+/* Linux sigcontext offsets. */
+/* Linux 32-bit sigcontext offsets. */
+/* Linux signal numbers. */
+/* Linux irq_cpustat_t offsets. */
+/* Align . to a 8 byte boundary equals to maximum function alignment. */
+/* The actual configuration determine if the init/exit sections
+ * are handled as text/data or they can be discarded (which
+ * often happens at runtime)
+ */
+/* .data section */
+/* RODATA provided for backward compatibility.
+ * All archs are supposed to use RO_DATA() */
+/* .text section. Map to function alignment to avoid address changes
+ * during second ld run in second ld pass when generating System.map */
+/* sched.text is aling to function alignment to secure we have same
+ * address even at second ld pass when generating System.map */
+/* spinlock.text is aling to function alignment to secure we have same
+ * address even at second ld pass when generating System.map */
+/* Section used for early init (in .S files) */
+/* init and exit section handling */
+  /* DWARF debug sections.
+		Symbols in the DWARF debugging sections are relative to
+		the beginning of the section so we begin them at 0.  */
+  /* Stabs debugging sections.  */
+OUTPUT_ARCH(mips)
+ENTRY(kernel_entry)
+PHDRS {
+ text PT_LOAD FLAGS(7); /* RWX */
+ note PT_NOTE FLAGS(4); /* R__ */
+}
+jiffies = jiffies_64;
+SECTIONS
+{
+ . = 0xffffffff80200000;
+ /* read-only */
+ _text = .; /* Text and read-only data */
+ .text : {
+  . = ALIGN(8); *(.text.hot) *(.text) *(.ref.text) *(.text.init.refok) *(.exit.text.refok) *(.devinit.text) *(.devexit.text) *(.text.unlikely)
+  . = ALIGN(8); __sched_text_start = .; *(.sched.text) __sched_text_end = .;
+  . = ALIGN(8); __lock_text_start = .; *(.spinlock.text) __lock_text_end = .;
+  . = ALIGN(8); __kprobes_text_start = .; *(.kprobes.text) __kprobes_text_end = .;
+  *(.text.*)
+  *(.fixup)
+  *(.gnu.warning)
+ } :text = 0
+ _etext = .; /* End of text section */
+ /* Exception table */
+ . = ALIGN(16);
+ __ex_table : {
+  __start___ex_table = .;
+  *(__ex_table)
+  __stop___ex_table = .;
+ }
+ /* Exception table for data bus errors */
+ __dbe_table : {
+  __start___dbe_table = .;
+  *(__dbe_table)
+  __stop___dbe_table = .;
+ }
+ .notes : AT(ADDR(.notes) - 0) { __start_notes = .; *(.note.*) __stop_notes = .; } :text :note
+ .dummy : { *(.dummy) } :text
+ . = ALIGN((4096)); .rodata : AT(ADDR(.rodata) - 0) { __start_rodata = .; *(.rodata) *(.rodata.*) *(__vermagic) *(__markers_strings) } .rodata1 : AT(ADDR(.rodata1) - 0) { *(.rodata1) } .pci_fixup : AT(ADDR(.pci_fixup) - 0) { __start_pci_fixups_early = .; *(.pci_fixup_early) __end_pci_fixups_early = .; __start_pci_fixups_header = .; *(.pci_fixup_header) __end_pci_fixups_header = .; __start_pci_fixups_final = .; *(.pci_fixup_final) __end_pci_fixups_final = .; __start_pci_fixups_enable = .; *(.pci_fixup_enable) __end_pci_fixups_enable = .; __start_pci_fixups_resume = .; *(.pci_fixup_resume) __end_pci_fixups_resume = .; __start_pci_fixups_resume_early = .; *(.pci_fixup_resume_early) __end_pci_fixups_resume_early = .; __start_pci_fixups_suspend = .; *(.pci_fixup_suspend) __end_pci_fixups_suspend = .; } .builtin_fw : AT(ADDR(.builtin_fw) - 0) { __start_builtin_fw = .; *(.builtin_fw) __end_builtin_fw = .; } .rio_route : AT(ADDR(.rio_route) - 0) { __start_rio_route_ops = .; *(.rio_route_ops) __end_rio_route_ops = .; } __ksymtab : AT(ADDR(__ksymtab) - 0) { __start___ksymtab = .; *(__ksymtab) __stop___ksymtab = .; } __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - 0) { __start___ksymtab_gpl = .; *(__ksymtab_gpl) __stop___ksymtab_gpl = .; } __ksymtab_unused : AT(ADDR(__ksymtab_unused) - 0) { __start___ksymtab_unused = .; *(__ksymtab_unused) __stop___ksymtab_unused = .; } __ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - 0) { __start___ksymtab_unused_gpl = .; *(__ksymtab_unused_gpl) __stop___ksymtab_unused_gpl = .; } __ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - 0) { __start___ksymtab_gpl_future = .; *(__ksymtab_gpl_future) __stop___ksymtab_gpl_future = .; } __kcrctab : AT(ADDR(__kcrctab) - 0) { __start___kcrctab = .; *(__kcrctab) __stop___kcrctab = .; } __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - 0) { __start___kcrctab_gpl = .; *(__kcrctab_gpl) __stop___kcrctab_gpl = .; } __kcrctab_unused : AT(ADDR(__kcrctab_unused) - 0) { __start___kcrctab_unused = .; *(__kcrctab_unused) __stop___kcrctab_unused = .; } __kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - 0) { __start___kcrctab_unused_gpl = .; *(__kcrctab_unused_gpl) __stop___kcrctab_unused_gpl = .; } __kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - 0) { __start___kcrctab_gpl_future = .; *(__kcrctab_gpl_future) __stop___kcrctab_gpl_future = .; } __ksymtab_strings : AT(ADDR(__ksymtab_strings) - 0) { *(__ksymtab_strings) } __init_rodata : AT(ADDR(__init_rodata) - 0) { *(.ref.rodata) *(.devinit.rodata) *(.devexit.rodata) } __param : AT(ADDR(__param) - 0) { __start___param = .; *(__param) __stop___param = .; . = ALIGN((4096)); __end_rodata = .; } . = ALIGN((4096));
+ /* writeable */
+ .data : { /* Data */
+  . = . + 0; /* for CONFIG_MAPPED_KERNEL */
+  /*
+		 * This ALIGN is needed as a workaround for a bug a
+		 * gcc bug upto 4.1 which limits the maximum alignment
+		 * to at most 32kB and results in the following
+		 * warning:
+		 *
+		 *  CC      arch/mips/kernel/init_task.o
+		 * arch/mips/kernel/init_task.c:30: warning: alignment
+		 * of ‘init_thread_union’ is greater than maximum
+		 * object file alignment.  Using 32768
+		 */
+  . = ALIGN(16384);
+  *(.data.init_task)
+  *(.data) *(.data.init.refok) *(.ref.data) *(.devinit.data) *(.devexit.data) . = ALIGN(8); __start___markers = .; *(__markers) __stop___markers = .;
+  CONSTRUCTORS
+ }
+ _gp = . + 0x8000;
+ .lit8 : {
+  *(.lit8)
+ }
+ .lit4 : {
+  *(.lit4)
+ }
+ /* We want the small data sections together, so single-instruction offsets
+	   can access them all, and initialized data all before uninitialized, so
+	   we can shorten the on-disk segment size.  */
+ .sdata : {
+  *(.sdata)
+ }
+ . = ALIGN(16384);
+ .data_nosave : {
+  __nosave_begin = .;
+  *(.data.nosave)
+ }
+ . = ALIGN(16384);
+ __nosave_end = .;
+ . = ALIGN(32);
+ .data.cacheline_aligned : {
+  *(.data.cacheline_aligned)
+ }
+ _edata = .; /* End of data section */
+ /* will be freed after init */
+ . = ALIGN(16384); /* Init code and data */
+ __init_begin = .;
+ .init.text : {
+  _sinittext = .;
+  *(.init.text) *(.cpuinit.text) *(.meminit.text)
+  _einittext = .;
+ }
+ .init.data : {
+  *(.init.data) *(.cpuinit.data) *(.cpuinit.rodata) *(.meminit.data) *(.meminit.rodata)
+ }
+ . = ALIGN(16);
+ .init.setup : {
+  __setup_start = .;
+  *(.init.setup)
+  __setup_end = .;
+ }
+ .initcall.init : {
+  __initcall_start = .;
+  *(.initcallearly.init) __early_initcall_end = .; *(.initcall0.init) *(.initcall0s.init) *(.initcall1.init) *(.initcall1s.init) *(.initcall2.init) *(.initcall2s.init) *(.initcall3.init) *(.initcall3s.init) *(.initcall4.init) *(.initcall4s.init) *(.initcall5.init) *(.initcall5s.init) *(.initcallrootfs.init) *(.initcall6.init) *(.initcall6s.init) *(.initcall7.init) *(.initcall7s.init)
+  __initcall_end = .;
+ }
+ .con_initcall.init : {
+  __con_initcall_start = .;
+  *(.con_initcall.init)
+  __con_initcall_end = .;
+ }
+ .security_initcall.init : AT(ADDR(.security_initcall.init) - 0) { __security_initcall_start = .; *(.security_initcall.init) __security_initcall_end = .; }
+ /* .exit.text is discarded at runtime, not link time, to deal with
+	 * references from .rodata
+	 */
+ .exit.text : {
+  *(.exit.text) *(.cpuexit.text) *(.memexit.text)
+ }
+ .exit.data : {
+  *(.exit.data) *(.cpuexit.data) *(.cpuexit.rodata) *(.memexit.data) *(.memexit.rodata)
+ }
+ . = ALIGN(16384);
+ .init.ramfs : {
+  __initramfs_start = .;
+  *(.init.ramfs)
+  __initramfs_end = .;
+ }
+ . = ALIGN(16384); __per_cpu_start = .; .data.percpu : AT(ADDR(.data.percpu) - 0) { *(.data.percpu) *(.data.percpu.shared_aligned) } __per_cpu_end = .;
+ . = ALIGN(16384);
+ __init_end = .;
+ /* freed after init ends here */
+ __bss_start = .; /* BSS */
+ .sbss : {
+  *(.sbss)
+  *(.scommon)
+ }
+ .bss : {
+  *(.bss)
+  *(COMMON)
+ }
+ __bss_stop = .;
+ _end = . ;
+ /* Sections to be discarded */
+ /DISCARD/ : {
+  *(.exitcall.exit)
+  /* ABI crap starts here */
+  *(.MIPS.options)
+  *(.options)
+  *(.pdr)
+  *(.reginfo)
+ }
+ /* These mark the ABI of the kernel for debuggers.  */
+ .mdebug.abi32 : {
+  KEEP(*(.mdebug.abi32))
+ }
+ .mdebug.abi64 : {
+  KEEP(*(.mdebug.abi64))
+ }
+ /* This is the MIPS specific mdebug section.  */
+ .mdebug : {
+  *(.mdebug)
+ }
+
+ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) }
+ .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) }
+
+ /* These must appear regardless of  .  */
+ .gptab.sdata : {
+  *(.gptab.data)
+  *(.gptab.sdata)
+ }
+ .gptab.sbss : {
+  *(.gptab.bss)
+  *(.gptab.sbss)
+ }
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2e/Makefile linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/Makefile
--- linux-2.6.27.6/arch/mips/lemote/lm2e/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/Makefile	2011-05-08 18:02:19.000000000 +0800
@@ -2,6 +2,6 @@
 # Makefile for Lemote Fulong mini-PC board.
 #
 
-obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o
+obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o mipsdha.o
 
 EXTRA_CFLAGS += -Werror
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2e/mipsdha.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/mipsdha.c
--- linux-2.6.27.6/arch/mips/lemote/lm2e/mipsdha.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/mipsdha.c	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+static ssize_t mipsdha_proc_read(struct file *file, char *buf, size_t len, loff_t *ppos);
+
+static ssize_t mipsdha_proc_write(struct file *file, const char *buf, size_t len, loff_t *ppos);
+
+
+static struct proc_dir_entry *mipsdha_proc_entry;
+
+#define INFO_SIZE 4096
+static char info_buf[INFO_SIZE];
+
+static struct file_operations mipsdha_fops =
+{
+    owner:	THIS_MODULE,
+    read:	mipsdha_proc_read,
+    write:	mipsdha_proc_write,
+};
+
+static enum {CMD_ERR, CMD_GIB, CMD_GPI} cmd;
+
+typedef struct pciinfo_s
+{
+  int		bus,card,func;
+  unsigned short command;
+  unsigned short vendor,device;
+  unsigned	base0,base1,base2,baserom;
+} pciinfo_t;
+
+
+extern struct proc_dir_entry proc_root;
+
+static int __init mipsdha_proc_init(void)
+{
+	mipsdha_proc_entry = create_proc_entry("mipsdha", S_IWUSR | S_IRUGO, &proc_root);
+	if (mipsdha_proc_entry == NULL) {
+		printk("MIPSDHA: register /proc/mipsdha failed!\n");
+		return 0;
+	}
+	
+	mipsdha_proc_entry->owner = THIS_MODULE;
+	mipsdha_proc_entry->proc_fops = &mipsdha_fops;
+
+	cmd=CMD_ERR;
+	return 0;
+}
+
+static ssize_t mipsdha_proc_write (struct file *file, const char *buf, size_t len, loff_t *ppos)
+{
+	char cmd_gib[]="GET IO BASE";
+	char cmd_gpi[]="GET PCI INFO";
+
+	if (len >= INFO_SIZE) return -ENOMEM;
+
+	if (copy_from_user(info_buf, buf, len)) return -EFAULT;
+	info_buf[len] = '\0';
+
+	if (strncmp(info_buf, cmd_gib, sizeof(cmd_gib)-1)==0) {
+		cmd = CMD_GIB;
+		return len;
+	} else if (strncmp(info_buf, cmd_gpi, sizeof(cmd_gpi)-1)==0) {
+		cmd = CMD_GPI;
+		return len;
+	} else {
+		return -EINVAL;
+	}
+}
+
+static ssize_t mipsdha_proc_read (struct file *file, char *buf, size_t len, loff_t *ppos)
+{
+	int info_cnt;
+	pciinfo_t *pciinfo;
+	struct pci_dev *dev = NULL;
+
+	switch (cmd) {
+		default:
+			printk("MIPSDHA: BUG found in function %s!(cmd=%d)\n", 
+					__FUNCTION__, cmd);
+			return -EINVAL;
+
+
+		case CMD_ERR:
+			return -EINVAL;
+
+
+		case CMD_GIB:
+			*(unsigned long *)info_buf = 
+				virt_to_phys((void *) mips_io_port_base);
+			info_cnt=sizeof(unsigned long);
+			break;
+
+
+		case CMD_GPI:
+			pciinfo = (pciinfo_t *) info_buf;
+			info_cnt = 0;
+			for_each_pci_dev(dev) {
+
+				if (info_cnt+sizeof(pciinfo_t)>INFO_SIZE) return -ENOMEM;
+
+				pciinfo->bus = dev->bus->number;
+				pciinfo->card = PCI_SLOT(dev->devfn);
+				pciinfo->func = PCI_FUNC(dev->devfn);
+
+				if (pci_read_config_word(dev, PCI_COMMAND, &pciinfo->command)
+						!= PCIBIOS_SUCCESSFUL) {
+					printk("MIPSDHA: BUG found in function %s!\n", 
+							__FUNCTION__);
+					pciinfo->command=0;
+				}
+
+				pciinfo->vendor = dev->vendor;
+				pciinfo->device = dev->device;
+
+				pciinfo->base0 = (dev->resource[0]).start;
+				pciinfo->base1 = (dev->resource[1]).start;
+				pciinfo->base2 = (dev->resource[2]).start;
+				pciinfo->baserom = (dev->resource[PCI_ROM_RESOURCE]).start;
+
+				pciinfo++;
+				info_cnt += sizeof(pciinfo_t);
+			}
+			break;
+	}
+
+	if (len < info_cnt) return -ENOMEM;
+	if (copy_to_user(buf, info_buf, info_cnt)) return -EFAULT;
+
+	return info_cnt;
+}
+
+__initcall(mipsdha_proc_init);
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2e/pci.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/pci.c
--- linux-2.6.27.6/arch/mips/lemote/lm2e/pci.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/pci.c	2011-05-08 18:02:19.000000000 +0800
@@ -30,6 +30,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <asm/mips-boards/bonito64.h>
+#include <asm/lemote/pci.h>
 
 extern struct pci_ops bonito64_pci_ops;
 
@@ -53,6 +54,7 @@
 	.mem_resource   = &loongson2e_pci_mem_resource,
 	.mem_offset     = 0x00000000UL,
 	.io_offset      = 0x00000000UL,
+	.io_map_base    = LEMOTE_IO_PORT_BASE,
 };
 
 static void __init ict_pcimap(void)
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2e/reset.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/reset.c
--- linux-2.6.27.6/arch/mips/lemote/lm2e/reset.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/reset.c	2011-10-27 10:28:55.000000000 +0800
@@ -23,9 +23,27 @@
 	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
 }
 
+
+static void delay(void)
+{
+	volatile int i;
+	for (i=0; i<0x10000; i++);
+}
 static void loongson2e_halt(void)
 {
-	while (1) ;
+#ifdef CONFIG_32BIT
+	*(unsigned short*)0xbfd0b000 = 0x8100;
+	delay();
+	*(unsigned short *)0xbfd0b004 = 0x2800;
+	delay();
+	*(unsigned int *)0xbfe00148 = 0x120002;
+#else
+	*(unsigned short *)0xffffffffbfd0b000 = 0x8100;
+	delay();
+	*(unsigned short *)0xffffffffbfd0b004 = 0x2800;
+	delay();
+	*(unsigned int *)0xffffffffbfe00148 = 0x120002;
+#endif
 }
 
 static void loongson2e_power_off(void)
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2e/setup.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/setup.c
--- linux-2.6.27.6/arch/mips/lemote/lm2e/setup.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2e/setup.c	2011-05-08 18:02:19.000000000 +0800
@@ -34,6 +34,7 @@
 #include <asm/mc146818-time.h>
 #include <asm/time.h>
 #include <asm/wbflush.h>
+#include <asm/lemote/pci.h>
 
 #ifdef CONFIG_VT
 #include <linux/console.h>
@@ -42,12 +43,6 @@
 
 extern void mips_reboot_setup(void);
 
-#ifdef CONFIG_64BIT
-#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
-#else
-#define PTR_PAD(p) (p)
-#endif
-
 unsigned long cpu_clock_freq;
 unsigned long bus_clock;
 unsigned int memsize;
@@ -80,7 +75,8 @@
 
 void __init plat_mem_setup(void)
 {
-	set_io_port_base(PTR_PAD(0xbfd00000));
+
+	set_io_port_base(LEMOTE_IO_PORT_BASE);
 
 	mips_reboot_setup();
 
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/bonito-irq.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/bonito-irq.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/bonito-irq.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/bonito-irq.c	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/io.h>
+
+#include <asm/mips-boards/bonito64.h>
+
+#define	bonito_irq_shutdown	bonito_irq_disable
+
+
+static inline void bonito_irq_enable(unsigned int irq)
+{
+	BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE));
+	(void)BONITO_INTENSET;
+	mmiowb();
+}
+
+static unsigned int bonito_irq_startup(unsigned int irq) 
+{
+	bonito_irq_enable(irq);
+	return 0;
+}
+
+static inline void bonito_irq_ack(unsigned int irq) 
+{
+	BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
+	(void)BONITO_INTENCLR;
+	mmiowb();
+}
+
+static inline void bonito_irq_end(unsigned int irq) 
+{
+	BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE ));
+	mmiowb();
+}
+
+static inline void bonito_irq_disable(unsigned int irq)
+{
+	BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
+	(void)BONITO_INTENCLR; 
+	mmiowb();
+}
+
+static struct irq_chip bonito_irq_type = {
+	.name	= "bonito_irq",
+	.startup = bonito_irq_startup,
+	.shutdown = bonito_irq_shutdown,
+	.enable = bonito_irq_enable,
+	.disable = bonito_irq_disable,
+	.ack	= bonito_irq_ack,
+	.end    = bonito_irq_end,
+	.mask	= bonito_irq_disable,
+	.mask_ack = bonito_irq_disable,
+	.unmask	= bonito_irq_enable,
+};
+
+/* There is no need to handle the DMA IO problem on godson2f any more. */
+/*
+static struct irqaction dma_timeout_irqaction = {
+	.handler	= no_action,
+	.name		= "dma_timeout",
+};
+*/
+
+void bonito_irq_init(void)
+{
+	u32 i;
+
+	for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) {
+		set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
+	}
+
+	/* setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); */
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/cs5536.h linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/cs5536.h
--- linux-2.6.27.6/arch/mips/lemote/lm2f/cs5536.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/cs5536.h	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,578 @@
+/*
+ * cs5536.h
+ * 
+ * The include file of cs5536 sourthbridge define which is used in the pmon only.
+ * you can modify it or change it, please set the modify time and steps.
+ *
+ * Author : jlliu <liujl@lemote.com>
+ * Data : 07-6-27
+ */
+
+#ifndef	_CS5536_H
+#define	_CS5536_H
+
+/*************************************************************************/
+
+/*
+ * basic define
+ */
+#define	PCI_IO_BASE		0x1fd00000	//( < 0x1fe00000)
+#define	PCI_IO_BASE_VA		0xbfd00000
+#define	PCI_MEM_BASE		0x10000000	//( < 0x1c000000 )
+#define	PCI_MEM_BASE_VA		0xb0000000
+
+/*
+ * MSR module base
+ */ 
+#define	CS5536_SB_MSR_BASE		(0x00000000)
+#define	CS5536_GLIU_MSR_BASE		(0x10000000)
+#define	CS5536_ILLEGAL_MSR_BASE		(0x20000000)
+#define	CS5536_USB_MSR_BASE		(0x40000000)
+#define	CS5536_IDE_MSR_BASE		(0x60000000)
+#define	CS5536_DIVIL_MSR_BASE		(0x80000000)
+#define	CS5536_ACC_MSR_BASE		(0xa0000000)
+#define	CS5536_UNUSED_MSR_BASE		(0xc0000000)
+#define	CS5536_GLCP_MSR_BASE		(0xe0000000)
+
+#define	SB_MSR_REG(offset)	(CS5536_SB_MSR_BASE	| offset)
+#define	GLIU_MSR_REG(offset)	(CS5536_GLIU_MSR_BASE	| offset)
+#define	ILLEGAL_MSR_REG(offset)	(CS5536_ILLEGAL_MSR_BASE| offset)
+#define	USB_MSR_REG(offset)	(CS5536_USB_MSR_BASE	| offset)
+#define	IDE_MSR_REG(offset)	(CS5536_IDE_MSR_BASE	| offset)
+#define	DIVIL_MSR_REG(offset)	(CS5536_DIVIL_MSR_BASE	| offset)
+#define	ACC_MSR_REG(offset)	(CS5536_ACC_MSR_BASE	| offset)
+#define	UNUSED_MSR_REG(offset)	(CS5536_UNUSED_MSR_BASE	| offset)
+#define	GLCP_MSR_REG(offset)	(CS5536_GLCP_MSR_BASE	| offset)
+
+/*
+ * BAR SPACE OF VIRTUAL PCI : range for pci probe use, length is the actual size. 
+ */
+// IO space for all DIVIL modules
+#define	CS5536_IRQ_RANGE		0xffffffe0	// USERD FOR PCI PROBE
+#define	CS5536_IRQ_LENGTH		0x20		// THE REGS ACTUAL LENGTH
+#define	CS5536_SMB_RANGE		0xfffffff8
+#define	CS5536_SMB_LENGTH		0x08
+#define	CS5536_GPIO_RANGE		0xffffff00
+#define	CS5536_GPIO_LENGTH		0x100
+#define	CS5536_MFGPT_RANGE		0xffffffc0
+#define	CS5536_MFGPT_LENGTH		0x40
+#define	CS5536_ACPI_RANGE		0xffffffe0
+#define	CS5536_ACPI_LENGTH		0x20
+#define	CS5536_PMS_RANGE		0xffffff80
+#define	CS5536_PMS_LENGTH		0x80
+// MEM space for 4KB nand flash; IO space for 16B nor flash.
+#ifdef	CS5536_USE_NOR_FLASH
+#define	CS5536_FLSH0_RANGE	0xfffffff0
+#define	CS5536_FLSH0_LENGTH	0x10
+#define	CS5536_FLSH1_RANGE	0xfffffff0
+#define	CS5536_FLSH1_LENGTH	0x10
+#define	CS5536_FLSH2_RANGE	0xfffffff0
+#define	CS5536_FLSH2_LENGTH	0x10
+#define	CS5536_FLSH3_RANGE	0xfffffff0
+#define	CS5536_FLSH3_LENGTH	0x10
+#else
+#define	CS5536_FLSH0_RANGE	0xfffff000
+#define	CS5536_FLSH0_LENGTH	0x1000
+#define	CS5536_FLSH1_RANGE	0xfffff000
+#define	CS5536_FLSH1_LENGTH	0x1000
+#define	CS5536_FLSH2_RANGE	0xfffff000
+#define	CS5536_FLSH2_LENGTH	0x1000
+#define	CS5536_FLSH3_RANGE	0xfffff000
+#define	CS5536_FLSH3_LENGTH	0x1000
+#endif
+// IO space for IDE
+#define	CS5536_IDE_RANGE	0xfffffff0
+#define	CS5536_IDE_LENGTH	0x10
+// IO space for ACC
+#define	CS5536_ACC_RANGE	0xffffff80
+#define	CS5536_ACC_LENGTH	0x80
+// MEM space for ALL USB modules
+//#define	CS5536_OHCI_RANGE	0xfffffff0
+#define	CS5536_OHCI_RANGE	0xfffff000
+#define	CS5536_OHCI_LENGTH	0x1000
+//#define	CS5536_EHCI_RANGE	0xfffffff0
+#define	CS5536_EHCI_RANGE	0xfffff000
+#define	CS5536_EHCI_LENGTH	0x1000
+#define	CS5536_UDC_RANGE	0xffffe000
+#define	CS5536_UDC_LENGTH	0x2000
+#define	CS5536_OTG_RANGE	0xfffff000
+#define	CS5536_OTG_LENGTH	0x1000
+
+/*
+ * PCI MSR ACCESS
+ */
+#define	PCI_MSR_CTRL		0xF0
+#define	PCI_MSR_ADDR		0xF4
+#define	PCI_MSR_DATA_LO		0xF8
+#define	PCI_MSR_DATA_HI		0xFC
+
+/******************************* MSR *********************************************/
+
+/*
+ * GLIU STANDARD MSR
+ */
+#define	GLIU_CAP		0x00
+#define	GLIU_CONFIG		0x01
+#define	GLIU_SMI		0x02
+#define	GLIU_ERROR		0x03
+#define	GLIU_PM			0x04
+#define	GLIU_DIAG		0x05
+
+/*
+ * GLIU SPEC. MSR
+ */
+#define	GLIU_P2D_BM0		0x20 
+#define	GLIU_P2D_BM1		0x21 
+#define	GLIU_P2D_BM2		0x22 
+#define	GLIU_P2D_BMK0		0x23
+#define	GLIU_P2D_BMK1		0x24
+#define	GLIU_P2D_BM3		0x25 
+#define	GLIU_P2D_BM4		0x26 
+#define	GLIU_COH		0x80
+#define	GLIU_PAE		0x81	
+#define	GLIU_ARB		0x82
+#define	GLIU_ASMI		0x83
+#define	GLIU_AERR		0x84
+#define	GLIU_DEBUG		0x85
+#define	GLIU_PHY_CAP		0x86
+#define	GLIU_NOUT_RESP		0x87
+#define	GLIU_NOUT_WDATA		0x88
+#define	GLIU_WHOAMI		0x8B
+#define	GLIU_SLV_DIS		0x8C
+#define	GLIU_IOD_BM0		0xE0
+#define	GLIU_IOD_BM1		0xE1
+#define	GLIU_IOD_BM2		0xE2
+#define	GLIU_IOD_BM3		0xE3
+#define	GLIU_IOD_BM4		0xE4
+#define	GLIU_IOD_BM5		0xE5
+#define	GLIU_IOD_BM6		0xE6
+#define	GLIU_IOD_BM7		0xE7
+#define	GLIU_IOD_BM8		0xE8
+#define	GLIU_IOD_BM9		0xE9
+#define	GLIU_IOD_SC0		0xEA
+#define	GLIU_IOD_SC1		0xEB
+#define	GLIU_IOD_SC2		0xEC
+#define	GLIU_IOD_SC3		0xED
+#define	GLIU_IOD_SC4		0xEE
+#define	GLIU_IOD_SC5		0xEF
+#define	GLIU_IOD_SC6		0xF0
+#define	GLIU_IOD_SC7		0xF1
+
+/*
+ * SB STANDARD
+ */
+#define	SB_CAP		0x00
+#define	SB_CONFIG	0x01
+#define	SB_SMI		0x02
+#define	SB_ERROR	0x03
+#define	SB_MAR_ERR_EN		0x00000001
+#define	SB_TAR_ERR_EN		0x00000002
+#define	SB_RSVD_BIT1		0x00000004
+#define	SB_EXCEP_ERR_EN		0x00000008
+#define	SB_SYSE_ERR_EN		0x00000010
+#define	SB_PARE_ERR_EN		0x00000020
+#define	SB_TAS_ERR_EN		0x00000040
+#define	SB_MAR_ERR_FLAG		0x00010000
+#define	SB_TAR_ERR_FLAG		0x00020000
+#define	SB_RSVD_BIT2		0x00040000
+#define	SB_EXCEP_ERR_FLAG	0x00080000
+#define	SB_SYSE_ERR_FLAG	0x00100000
+#define	SB_PARE_ERR_FLAG	0x00200000
+#define	SB_TAS_ERR_FLAG		0x00400000
+#define	SB_PM		0x04
+#define	SB_DIAG		0x05
+
+/*
+ * SB SPEC.
+ */
+#define	SB_CTRL		0x10
+#define	SB_R0		0x20
+#define	SB_R1		0x21
+#define	SB_R2		0x22
+#define	SB_R3		0x23
+#define	SB_R4		0x24
+#define	SB_R5		0x25
+#define	SB_R6		0x26
+#define	SB_R7		0x27
+#define	SB_R8		0x28
+#define	SB_R9		0x29
+#define	SB_R10		0x2A
+#define	SB_R11		0x2B
+#define	SB_R12		0x2C
+#define	SB_R13		0x2D
+#define	SB_R14		0x2E
+#define	SB_R15		0x2F
+
+/*
+ * GLCP STANDARD
+ */
+#define	GLCP_CAP		0x00
+#define	GLCP_CONFIG		0x01
+#define	GLCP_SMI		0x02
+#define	GLCP_ERROR		0x03
+#define	GLCP_PM			0x04
+#define	GLCP_DIAG		0x05
+
+/*
+ * GLCP SPEC. 
+ */
+#define	GLCP_CLK_DIS_DELAY	0x08
+#define	GLCP_PM_CLK_DISABLE	0x09
+#define	GLCP_GLB_PM		0x0B
+#define	GLCP_DBG_OUT		0x0C
+#define	GLCP_RSVD1		0x0D
+#define	GLCP_SOFT_COM		0x0E
+#define	SOFT_BAR_SMB_FLAG		0x00000001
+#define	SOFT_BAR_GPIO_FLAG		0x00000002
+#define	SOFT_BAR_MFGPT_FLAG		0x00000004
+#define	SOFT_BAR_IRQ_FLAG		0x00000008
+#define	SOFT_BAR_PMS_FLAG		0x00000010
+#define	SOFT_BAR_ACPI_FLAG		0x00000020
+#define	SOFT_BAR_FLSH0_FLAG		0x00000040
+#define	SOFT_BAR_FLSH1_FLAG		0x00000080
+#define	SOFT_BAR_FLSH2_FLAG		0x00000100
+#define	SOFT_BAR_FLSH3_FLAG		0x00000200
+#define	SOFT_BAR_IDE_FLAG		0x00000400
+#define	SOFT_BAR_ACC_FLAG		0x00000800
+#define	SOFT_BAR_OHCI_FLAG		0x00001000
+#define	SOFT_BAR_EHCI_FLAG		0x00002000
+#define	SOFT_BAR_UDC_FLAG		0x00004000
+#define	SOFT_BAR_OTG_FLAG		0x00008000
+#define	GLCP_RSVD2		0x0F
+#define	GLCP_CLK_OFF		0x10
+#define	GLCP_CLK_ACTIVE		0x11
+#define	GLCP_CLK_DISABLE	0x12
+#define	GLCP_CLK4ACK		0x13
+#define	GLCP_SYS_RST		0x14
+#define	GLCP_RSVD3		0x15
+#define	GLCP_DBG_CLK_CTRL	0x16
+#define	GLCP_CHIP_REV_ID	0x17
+
+/*
+ * DIVIL STANDARD
+ */
+#define	DIVIL_CAP		0x00
+#define	DIVIL_CONFIG		0x01
+#define	DIVIL_SMI		0x02
+#define	DIVIL_ERROR		0x03
+#define	DIVIL_PM		0x04
+#define	DIVIL_DIAG		0x05
+
+/*
+ * DIVIL SPEC. 
+ */
+#define	DIVIL_LBAR_IRQ		0x08
+#define	DIVIL_LBAR_KEL		0x09
+#define	DIVIL_LBAR_SMB		0x0B
+#define	DIVIL_LBAR_GPIO		0x0C
+#define	DIVIL_LBAR_MFGPT	0x0D
+#define	DIVIL_LBAR_ACPI		0x0E
+#define	DIVIL_LBAR_PMS		0x0F
+#define	DIVIL_LBAR_FLSH0	0x10
+#define	DIVIL_LBAR_FLSH1	0x11
+#define	DIVIL_LBAR_FLSH2	0x12
+#define	DIVIL_LBAR_FLSH3	0x13
+#define	DIVIL_LEG_IO		0x14
+#define	DIVIL_BALL_OPTS		0x15
+#define	DIVIL_SOFT_IRQ		0x16
+#define	DIVIL_SOFT_RESET	0x17
+// NOR FLASH
+#define	NORF_CTRL		0x18
+#define	NORF_T01		0x19
+#define	NORF_T23		0x1A
+// NAND FLASH
+#define	NANDF_DATA		0x1B
+#define	NANDF_CTRL		0x1C
+#define	NANDF_RSVD		0x1D
+// KEL Keyboard Emulation Logic
+#define	KEL_CTRL		0x1F
+// PIC
+#define	PIC_YSEL_LOW		0x20
+#define	PIC_YSEL_LOW_USB_SHIFT		8
+#define	PIC_YSEL_LOW_ACC_SHIFT		16
+#define	PIC_YSEL_LOW_FLASH_SHIFT	24
+#define	PIC_YSEL_HIGH		0x21
+#define	PIC_ZSEL_LOW		0x22
+#define	PIC_ZSEL_HIGH		0x23
+#define	PIC_IRQM_PRIM		0x24
+#define	PIC_IRQM_LPC		0x25
+#define	PIC_XIRR_STS_LOW	0x26
+#define	PIC_XIRR_STS_HIGH	0x27
+#define	PCI_SHDW		0x34
+// MFGPT
+#define	MFGPT_IRQ		0x28
+#define	MFGPT_NR		0x29
+#define	MFGPT_RSVD		0x2A
+#define	MFGPT_SETUP		0x2B
+// FLOPPY
+#define	FLPY_3F2_SHDW		0x30
+#define	FLPY_3F7_SHDW		0x31
+#define	FLPY_372_SHDW		0x32
+#define	FLPY_377_SHDW		0x33
+// PIT
+#define	PIT_SHDW		0x36
+#define	PIT_CNTRL		0x37
+// UART
+#define	UART1_MOD		0x38
+#define	UART1_DONG		0x39
+#define	UART1_CONF		0x3A
+#define	UART1_RSVD		0x3B
+#define	UART2_MOD		0x3C
+#define	UART2_DONG		0x3D
+#define	UART2_CONF		0x3E
+#define	UART2_RSVD		0x3F
+// DMA
+#define	DIVIL_AC_DMA		0x1E
+#define	DMA_MAP			0x40
+#define	DMA_SHDW_CH0		0x41
+#define	DMA_SHDW_CH1		0x42
+#define	DMA_SHDW_CH2		0x43
+#define	DMA_SHDW_CH3		0x44
+#define	DMA_SHDW_CH4		0x45
+#define	DMA_SHDW_CH5		0x46
+#define	DMA_SHDW_CH6		0x47
+#define	DMA_SHDW_CH7		0x48
+#define	DMA_MSK_SHDW		0x49
+// LPC
+#define	LPC_EADDR		0x4C
+#define	LPC_ESTAT		0x4D
+#define	LPC_SIRQ		0x4E
+#define	LPC_RSVD		0x4F
+// PMC
+#define	PMC_LTMR		0x50
+#define	PMC_RSVD		0x51
+// RTC
+#define	RTC_RAM_LOCK		0x54
+#define	RTC_DOMA_OFFSET		0x55
+#define	RTC_MONA_OFFSET		0x56
+#define	RTC_CEN_OFFSET		0x57
+
+/*
+ * IDE STANDARD 
+ */
+#define	IDE_CAP		0x00
+#define	IDE_CONFIG	0x01
+#define	IDE_SMI		0x02
+#define	IDE_ERROR	0x03
+#define	IDE_PM		0x04
+#define	IDE_DIAG	0x05
+
+/*
+ * IDE SPEC. 
+ */
+#define	IDE_IO_BAR	0x08
+#define	IDE_CFG		0x10
+#define	IDE_DTC		0x12
+#define	IDE_CAST	0x13
+#define	IDE_ETC		0x14
+#define	IDE_INTERNAL_PM	0x15
+
+/*
+ * ACC STANDARD
+ */
+#define	ACC_CAP		0x00
+#define	ACC_CONFIG	0x01
+#define	ACC_SMI		0x02
+#define	ACC_ERROR	0x03
+#define	ACC_PM		0x04
+#define	ACC_DIAG	0x05
+
+/*
+ * USB STANDARD
+ */
+#define	USB_CAP		0x00
+#define	USB_CONFIG	0x01
+#define	USB_SMI		0x02
+#define	USB_ERROR	0x03
+#define	USB_PM		0x04
+#define	USB_DIAG	0x05
+
+/*
+ * USB SPEC.
+ */
+#define	USB_OHCI	0x08
+#define	USB_EHCI	0x09
+#define	USB_UDC		0x0A
+#define	USB_OTG		0x0B
+
+/********************************** NATIVE ****************************************/
+// IDE NATIVE registers
+#define	IDE_BM_CMD	0x00
+#define	IDE_BM_STS	0x02
+#define	IDE_BM_PRD	0x04
+
+// OHCI native registers
+#define	OHCI_REVISION		0x00
+#define	OHCI_CONTROL		0x04
+#define	OHCI_COMMAND_STATUS	0x08
+#define	OHCI_INT_STATUS		0x0C
+#define	OHCI_INT_ENABLE		0x10
+#define	OHCI_INT_DISABLE	0x14
+#define	OHCI_HCCA		0x18
+#define	OHCI_PERI_CUR_ED	0x1C
+#define	OHCI_CTRL_HEAD_ED	0x20
+#define	OHCI_CTRL_CUR_ED	0x24
+#define	OHCI_BULK_HEAD_ED	0x28
+#define	OHCI_BULK_CUR_ED	0x2C
+#define	OHCI_DONE_HEAD		0x30
+#define	OHCI_FM_INTERVAL	0x34
+#define	OHCI_FM_REMAINING	0x38
+#define	OHCI_FM_NUMBER		0x3C
+#define	OHCI_PERI_START		0x40
+#define	OHCI_LS_THRESHOLD	0x44
+#define	OHCI_RH_DESCRIPTORA	0x48
+#define	OHCI_RH_DESCRIPTORB	0x4C
+#define	OHCI_RH_STATUS		0x50
+#define	OHCI_RH_PORT_STATUS1	0x54
+#define	OHCI_RH_PORT_STATUS2	0x58
+#define	OHCI_RH_PORT_STATUS3	0x5C
+#define	OHCI_RH_PORT_STATUS4	0x60
+
+// KEL : MEM SPACE; REG :32BITS WIDTH
+#define	KEL_HCE_CTRL	0x100
+#define	KEL_HCE_IN	0x104
+#define	KEL_HCE_OUT	0x108
+#define	KEL_HCE_STS	0x10C
+#define	KEL_PORTA	0x92	//8bits
+// PIC : I/O SPACE; REG : 8BITS
+#define	PIC_ICW1_MASTER	0x20
+#define	PIC_ICW1_SLAVE	0xA0
+#define	PIC_ICW2_MASTER	0x21
+#define	PIC_ICW2_SLAVE	0xA1
+#define	PIC_ICW3_MASTER	0x21
+#define	PIC_ICW3_SLAVE	0xA1
+#define	PIC_ICW4_MASTER	0x21
+#define	PIC_ICW4_SLAVE	0xA1
+#define	PIC_OCW1_MASTER	0x21
+#define	PIC_OCW1_SLAVE	0xA1
+#define	PIC_OCW2_MASTER	0x20
+#define	PIC_OCW2_SLAVE	0xA0
+#define	PIC_OCW3_MASTER	0x20
+#define	PIC_OCW3_SLAVE	0xA0
+#define	PIC_IRR_MASTER	0x20
+#define	PIC_IRR_SLAVE	0xA0
+#define	PIC_ISR_MASTER	0x20
+#define	PIC_ISR_SLAVE	0xA0
+#define	PIC_INT_SEL1	0x4D0
+#define	PIC_INT_SEL2	0x4D1
+// GPIO : I/O SPACE; REG : 32BITS
+#define	GPIOL_OUT_VAL		0x00
+#define	GPIOL_OUT_EN		0x04
+#define	GPIOL_OUT_OD_EN		0x08
+#define	GPIOL_OUT_INVRT_EN	0x0c
+#define	GPIOL_OUT_AUX1_SEL	0x10
+#define	GPIOL_OUT_AUX2_SEL	0x14
+#define	GPIOL_PU_EN		0x18
+#define	GPIOL_PD_EN		0x1c
+#define	GPIOL_IN_EN		0x20
+#define	GPIOL_IN_INVRT_EN	0x24
+#define	GPIOL_IN_FLTR_EN	0x28
+#define	GPIOL_IN_EVNTCNT_EN	0x2c
+#define	GPIOL_IN_READBACK	0x30
+#define	GPIOL_IN_AUX1_SEL	0x34
+#define	GPIOL_EVNT_EN		0x38
+#define	GPIOL_LOCK_EN		0x3c
+#define	GPIOL_IN_POSEDGE_EN	0x40
+#define	GPIOL_IN_NEGEDGE_EN	0x44
+#define	GPIOL_IN_POSEDGE_STS	0x48
+#define	GPIOL_IN_NEGEDGE_STS	0x4c
+#define	GPIOH_OUT_VAL		0x80
+#define	GPIOH_OUT_EN		0x84
+#define	GPIOH_OUT_OD_EN		0x88
+#define	GPIOH_OUT_INVRT_EN	0x8c
+#define	GPIOH_OUT_AUX1_SEL	0x90
+#define	GPIOH_OUT_AUX2_SEL	0x94
+#define	GPIOH_PU_EN		0x98
+#define	GPIOH_PD_EN		0x9c
+#define	GPIOH_IN_EN		0xA0
+#define	GPIOH_IN_INVRT_EN	0xA4
+#define	GPIOH_IN_FLTR_EN	0xA8
+#define	GPIOH_IN_EVNTCNT_EN	0xAc
+#define	GPIOH_IN_READBACK	0xB0
+#define	GPIOH_IN_AUX1_SEL	0xB4
+#define	GPIOH_EVNT_EN		0xB8
+#define	GPIOH_LOCK_EN		0xBc
+#define	GPIOH_IN_POSEDGE_EN	0xC0
+#define	GPIOH_IN_NEGEDGE_EN	0xC4
+#define	GPIOH_IN_POSEDGE_STS	0xC8
+#define	GPIOH_IN_NEGEDGE_STS	0xCC
+// SMB : I/O SPACE, REG : 8BITS WIDTH
+#define	SMB_SDA				0x00
+#define	SMB_STS				0x01
+#define	SMB_STS_SLVSTP		(1 << 7)
+#define	SMB_STS_SDAST		(1 << 6)
+#define	SMB_STS_BER		(1 << 5)
+#define	SMB_STS_NEGACK		(1 << 4)
+#define	SMB_STS_STASTR		(1 << 3)
+#define	SMB_STS_NMATCH		(1 << 2)
+#define	SMB_STS_MASTER		(1 << 1)
+#define	SMB_STS_XMIT		(1 << 0)
+#define	SMB_CTRL_STS			0x02
+#define	SMB_CSTS_TGSTL		(1 << 5)
+#define	SMB_CSTS_TSDA		(1 << 4)
+#define	SMB_CSTS_GCMTCH		(1 << 3)
+#define	SMB_CSTS_MATCH		(1 << 2)
+#define	SMB_CSTS_BB		(1 << 1)
+#define	SMB_CSTS_BUSY		(1 << 0)
+#define	SMB_CTRL1			0x03
+#define	SMB_CTRL1_STASTRE	(1 << 7)
+#define	SMB_CTRL1_NMINTE	(1 << 6)
+#define	SMB_CTRL1_GCMEN		(1 << 5)
+#define	SMB_CTRL1_ACK		(1 << 4)
+#define	SMB_CTRL1_RSVD		(1 << 3)
+#define	SMB_CTRL1_INTEN		(1 << 2)
+#define	SMB_CTRL1_STOP		(1 << 1)
+#define	SMB_CTRL1_START		(1 << 0)
+#define	SMB_ADDR			0x04
+#define	SMB_ADDR_SAEN		(1 << 7)
+#define	SMB_CONTROLLER_ADDR	(0xef << 0)
+#define	SMB_CTRL2			0x05
+#define	SMB_FREQ		(0x20 << 1)	//(0x7f << 1)
+#define	SMB_ENABLE		(0x01 << 0)
+#define	SMB_CTRL3			0x06
+
+/*********************************** LEGACY I/O *******************************/
+
+/*
+ * LEGACY I/O SPACE BASE
+ */
+#define	CS5536_LEGACY_BASE_ADDR		(PCI_IO_BASE_VA | 0x0000)
+
+/*
+ * IDE LEGACY REG : legacy IO address is 0x170~0x177 and 0x376 (0x1f0~0x1f7 and 0x3f6)
+ * all registers are 16bits except the IDE_LEGACY_DATA reg
+ * some registers are read only and the 
+ */
+#define	PRI_IDE_LEGACY_REG(offset) 	(CS5536_LEGACY_BASE_ADDR | 0x1f0 | offset)
+#define	SEC_IDE_LEGACY_REG(offset)	(CS5536_LEGACY_BASE_ADDR | 0x170 | offset)
+
+#define	IDE_LEGACY_DATA		0x00 // RW
+#define	IDE_LEGACY_ERROR	0x01 // RO
+#define	IDE_LEGACY_FEATURE	0x01 // WO
+#define	IDE_LEGACY_SECTOR_COUNT	0x02 // RW
+#define	IDE_LEGACY_SECTOR_NUM	0x03 // RW
+#define	IDE_LEGACY_CYL_LO	0x04 // RW
+#define	IDE_LEGACY_CYL_HI	0x05 // RW
+#define	IDE_LEGACY_HEAD		0x06 // RW
+#define	IDE_LEGACY_HEAD_DRV		(1 << 4)
+#define	IDE_LEGACY_HEAD_LBA		(1 << 6)
+#define	IDE_LEGACY_HEAD_IBM		(1 << 7 | 1 << 5)
+#define	IDE_LEGACY_STATUS	0x07 // RO
+#define IDE_LEGACY_STATUS_ERR		(1 << 0)
+#define	IDE_LEGACY_STATUS_IDX		(1 << 1)
+#define IDE_LEGACY_STATUS_CORR		(1 << 2)
+#define	IDE_LEGACY_STATUS_DRQ		(1 << 3)
+#define	IDE_LEGACY_STATUS_DSC 		(1 << 4)
+#define	IDE_LEGACY_STATUS_DWF		(1 << 5)
+#define	IDE_LEGACY_STATUS_DRDY		(1 << 6)
+#define	IDE_LEGACY_STATUS_BUSY		(1 << 7)
+#define	IDE_LEGACY_COMMAND	0x07 // WO
+#define	IDE_LEGACY_ASTATUS	0x206 // RO
+#define	IDE_LEGACY_CTRL		0x206 // WO
+#define	IDE_LEGACY_CTRL_IDS	0x02
+#define	IDE_LEGACY_CTRL_RST	0x04
+#define	IDE_LEGACY_CTRL_4BIT	0x08
+
+/**********************************************************************************/
+
+#endif	/* _CS5536_H */
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/cs5536_pci.h linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/cs5536_pci.h
--- linux-2.6.27.6/arch/mips/lemote/lm2f/cs5536_pci.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/cs5536_pci.h	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,181 @@
+/*
+ * cs5536_vsm.h
+ * the definition file of cs5536 Virtual Support Module(VSM).
+ * pci configuration space can be accessed through the VSM, so
+ * there is no need the MSR read/write now, except the spec. MSR
+ * registers which are not implemented yet.
+ *
+ * Author : jlliu <liujl@lemote.com>
+ * Date : 07-07-04
+ *
+ */
+
+#ifndef	_CS5536_PCI_H
+#define	_CS5536_PCI_H
+
+/**********************************************************************/
+
+//#define	TEST_CS5536_USE_FLASH
+//#ifdef	TEST_CS5536_USE_FLASH
+//#define	TEST_CS5536_USE_NOR_FLASH
+//#endif
+#define		TEST_CS5536_USE_EHCI
+#define	TEST_CS5536_USE_UDC
+#define	TEST_CS5536_USE_OTG
+
+/**********************************************************************/
+
+#define	PCI_SPECIAL_SHUTDOWN	1
+#define	CS5536_FLASH_INTR	6
+#define	CS5536_ACC_INTR		9
+#define	CS5536_IDE_INTR		14
+#define	CS5536_USB_INTR		11
+#define	CS5536_UART1_INTR	4
+#define	CS5536_UART2_INTR	3
+
+/************************* PCI BUS DEVICE FUNCTION ********************/
+
+/*
+ * PCI bus device function
+ */
+#define	PCI_BUS_CS5536		0
+#define	PCI_IDSEL_CS5536	14
+#define	PCI_CFG_BASE		0x02000000
+
+#define	CS5536_ISA_FUNC		0
+#define	CS5536_FLASH_FUNC	1
+#define	CS5536_IDE_FUNC		2
+#define	CS5536_ACC_FUNC		3
+#define	CS5536_OHCI_FUNC	4
+#define	CS5536_EHCI_FUNC	5
+#define	CS5536_UDC_FUNC		6
+#define	CS5536_OTG_FUNC		7
+#define	CS5536_FUNC_START	0
+#define	CS5536_FUNC_END		7
+#define	CS5536_FUNC_COUNT	(CS5536_FUNC_END - CS5536_FUNC_START + 1)
+
+/***************************** STANDARD PCI-2.2 EXPANSION ***********************/
+
+/*
+ * PCI configuration space
+ * we have to virtualize the PCI configure space head, so we should
+ * define the necessary IDs and some others.
+ */
+/* VENDOR ID */ 
+#define	CS5536_VENDOR_ID	0x1022
+
+/* DEVICE ID */
+#define	CS5536_ISA_DEVICE_ID		0x2090
+#define	CS5536_FLASH_DEVICE_ID		0x2091
+#define	CS5536_IDE_DEVICE_ID		0x209a
+#define	CS5536_ACC_DEVICE_ID		0x2093
+#define	CS5536_OHCI_DEVICE_ID		0x2094
+#define	CS5536_EHCI_DEVICE_ID		0x2095
+#define	CS5536_UDC_DEVICE_ID		0x2096
+#define	CS5536_OTG_DEVICE_ID		0x2097
+
+/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
+#define	CS5536_ISA_CLASS_CODE		0x060100
+#define	CS5536_FLASH_CLASS_CODE		0x050100
+#define CS5536_IDE_CLASS_CODE		0x010180
+#define	CS5536_ACC_CLASS_CODE		0x040100
+#define	CS5536_OHCI_CLASS_CODE		0x0C0310
+#define	CS5536_EHCI_CLASS_CODE		0x0C0320
+#define	CS5536_UDC_CLASS_CODE		0x0C03FE
+#define	CS5536_OTG_CLASS_CODE		0x0C0380
+
+/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
+#define	PCI_NONE_BIST			0x00	//RO not implemented yet.
+#define	PCI_BRIDGE_HEADER_TYPE		0x80	//RO
+#define	PCI_NORMAL_HEADER_TYPE		0x00
+#define	PCI_NORMAL_LATENCY_TIMER	0x00
+#define	PCI_NORMAL_CACHE_LINE_SIZE	0x08	//RW
+
+/* BAR */
+#define	PCI_BAR0_REG			0x10
+#define	PCI_BAR1_REG			0x14
+#define	PCI_BAR2_REG			0x18
+#define	PCI_BAR3_REG			0x1c
+#define	PCI_BAR4_REG			0x20
+#define	PCI_BAR5_REG			0x24
+#define	PCI_BAR_COUNT			6
+#define	PCI_BAR_RANGE_MASK		0xFFFFFFFF
+
+/* CARDBUS CIS POINTER */
+#define	PCI_CARDBUS_CIS_POINTER		0x00000000
+
+/* SUBSYSTEM VENDOR ID  */
+#define	CS5536_SUB_VENDOR_ID		CS5536_VENDOR_ID
+
+/* SUBSYSTEM ID */
+#define	CS5536_ISA_SUB_ID		CS5536_ISA_DEVICE_ID
+#define	CS5536_FLASH_SUB_ID		CS5536_FLASH_DEVICE_ID
+#define	CS5536_IDE_SUB_ID		CS5536_IDE_DEVICE_ID
+#define	CS5536_ACC_SUB_ID		CS5536_ACC_DEVICE_ID
+#define	CS5536_OHCI_SUB_ID		CS5536_OHCI_DEVICE_ID
+#define	CS5536_EHCI_SUB_ID		CS5536_EHCI_DEVICE_ID
+#define	CS5536_UDC_SUB_ID		CS5536_UDC_DEVICE_ID
+#define	CS5536_OTG_SUB_ID		CS5536_OTG_DEVICE_ID
+
+/* EXPANSION ROM BAR */
+#define	PCI_EXPANSION_ROM_BAR		0x00000000
+
+/* CAPABILITIES POINTER */
+#define	PCI_CAPLIST_POINTER		0x00000000
+#define PCI_CAPLIST_USB_POINTER		0x40
+/* INTERRUPT */
+#define	PCI_MAX_LATENCY			0x40
+#define	PCI_MIN_GRANT			0x00
+#define	PCI_DEFAULT_PIN			0x01
+
+/**************************** EXPANSION PCI REG **************************************/
+
+/*
+ * ISA EXPANSION
+ */
+#define	PCI_UART1_INT_REG 	0x50
+#define PCI_UART2_INT_REG	0x54
+#define	PCI_ISA_FIXUP_REG	0x58
+
+/*
+ * FLASH EXPANSION
+ */
+#define	PCI_FLASH_INT_REG		0x50
+#define	PCI_NOR_FLASH_CTRL_REG		0x40
+#define	PCI_NOR_FLASH_T01_REG		0x44
+#define	PCI_NOR_FLASH_T23_REG		0x48
+#define	PCI_NAND_FLASH_TDATA_REG	0x60
+#define	PCI_NAND_FLASH_TCTRL_REG	0x64
+#define	PCI_NAND_FLASH_RSVD_REG		0x68
+#define	PCI_FLASH_SELECT_REG		0x70
+
+/*
+ * IDE EXPANSION
+ */ 
+#define	PCI_IDE_CFG_REG		0x40
+#define	CS5536_IDE_FLASH_SIGNATURE	0xDEADBEEF
+#define	PCI_IDE_DTC_REG		0x48
+#define	PCI_IDE_CAST_REG	0x4C
+#define	PCI_IDE_ETC_REG		0x50
+#define	PCI_IDE_PM_REG		0x54
+#define	PCI_IDE_INT_REG		0x60
+
+/*
+ * ACC EXPANSION
+ */
+#define	PCI_ACC_INT_REG		0x50
+
+/*
+ * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
+ */
+#define	PCI_OHCI_PM_REG		0x40
+#define	PCI_OHCI_INT_REG	0x50
+
+/*
+ * EHCI EXPANSION
+ */
+#define	PCI_EHCI_LEGSMIEN_REG	0x50
+#define	PCI_EHCI_LEGSMISTS_REG	0x54
+#define	PCI_EHCI_FLADJ_REG	0x60
+
+#endif /* _CS5536_PCI_H_ */
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/cs5536_vsm.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/cs5536_vsm.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/cs5536_vsm.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/cs5536_vsm.c	2011-05-08 18:02:18.000000000 +0800
@@ -0,0 +1,2294 @@
+/*
+ * pci_machdep_cs5536.c  
+ * 	the Virtual Support Module(VSM) for virtulize the PCI configure  
+ * 	space. so user can access the PCI configure space directly as
+ *	a normal multi-function PCI device which following the PCI-2.2 spec.
+ *
+ * Author : jlliu <liujl@lemote.com>
+ * Date : 07-07-05
+ *
+ */
+#include <linux/types.h>
+
+#include "cs5536.h"
+#include "cs5536_pci.h"
+#include "pcireg.h"
+
+extern void _wrmsr(u32 reg, u32 hi, u32 lo);
+extern void _rdmsr(u32 reg, u32 *hi, u32 *lo);
+
+/******************************INTERNAL USED FUNCTIONS***********************************/
+
+/*
+ * divil_lbar_enable_disable : enable/disable the divil module bar space.
+ * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
+ * and the RCONFx(0~5) reg to use the modules.
+ */
+static void divil_lbar_enable_disable(int enable)
+{
+	u32 hi, lo;
+	
+	/* 
+	 * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
+	 */
+	
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_PMS), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_PMS), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_ACPI), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_ACPI), hi, lo);
+	
+	/*
+	 * RCONF0 is reserved to the DIVIL IRQ mdoule
+	 */
+#if	0	
+	_rdmsr(SB_MSR_REG(SB_R1), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R1), hi, lo);
+	
+	_rdmsr(SB_MSR_REG(SB_R2), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R2), hi, lo);
+
+	_rdmsr(SB_MSR_REG(SB_R3), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R3), hi, lo);
+	
+	_rdmsr(SB_MSR_REG(SB_R4), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R4), hi, lo);
+
+	_rdmsr(SB_MSR_REG(SB_R5), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R5), hi, lo);
+#endif	
+	return;
+}
+
+#ifdef	TEST_CS5536_USE_FLASH
+/*
+ * flash_lbar_enable_disable : enable or disable the region of flashs(NOR or NAND)
+ * the same as the DIVIL other modules above, two groups of regs should be modified
+ * here to control the region. DIVIL flash LBAR and the RCONFx(6~9 reserved).
+ */
+static void flash_lbar_enable_disable(int enable)
+{
+	u32 hi, lo;
+	
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH1), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH1), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH2), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH2), hi, lo);
+
+	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH3), &hi, &lo);
+	if(enable)
+		hi |= 0x01;
+	else
+		hi &= ~0x01;
+	_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH3), hi, lo);
+
+	_rdmsr(SB_MSR_REG(SB_R6), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R6), hi, lo);
+	
+	_rdmsr(SB_MSR_REG(SB_R7), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R7), hi, lo);
+	
+	_rdmsr(SB_MSR_REG(SB_R8), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R8), hi, lo);
+
+	_rdmsr(SB_MSR_REG(SB_R9), &hi, &lo);
+	if(enable)
+		lo |= 0x01;
+	else
+		lo &= ~0x01;
+	_wrmsr(SB_MSR_REG(SB_R9), hi, lo);
+	
+	return;
+}
+#endif
+
+
+/**********************************MODULES*********************************************/
+
+/*
+ * isa_write : isa write transfering.
+ * WE assume that the ISA is not the BUS MASTER.!!!
+ */
+/* FAST BACK TO BACK '1' for BUS MASTER '0' for BUS SALVE */
+/* COMMAND :
+ * 	bit0 : IO SPACE ENABLE
+ *	bit1 : MEMORY SPACE ENABLE(ignore)
+ *	bit2 : BUS MASTER ENABLE(ignore)
+ *	bit3 : SPECIAL CYCLE(ignore)? default is ignored.
+ *	bit4 : MEMORY WRITE and INVALIDATE(ignore)
+ *	bit5 : VGA PALETTE(ignore)
+ *	bit6 : PARITY ERROR(ignore)? : default is ignored.
+ *	bit7 : WAIT CYCLE CONTROL(ignore)
+ *	bit8 : SYSTEM ERROR(ignore)
+ *	bit9 : FAST BACK TO BACK(ignore)
+ *	bit10-bit15 : RESERVED
+ * STATUS :
+ *	bit0-bit3 : RESERVED
+ *	bit4 : CAPABILITY LIST(ignore)
+ *	bit5 : 66MHZ CAPABLE
+ *	bit6 : RESERVED
+ *	bit7 : FAST BACK TO BACK(ignore)
+ *	bit8 : DATA PARITY ERROR DETECED(ignore)
+ *	bit9-bit10 : DEVSEL TIMING(ALL MEDIUM)
+ *	bit11: SIGNALED TARGET ABORT
+ *	bit12: RECEIVED TARGET ABORT
+ *	bit13: RECEIVED MASTER ABORT
+ *	bit14: SIGNALED SYSTEM ERROR
+ *	bit15: DETECTED PARITY ERROR
+ */
+static void pci_isa_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+	u32 temp;
+
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// command
+			if( value & PCI_COMMAND_IO_ENABLE ){
+				divil_lbar_enable_disable(1);
+			}else{
+				divil_lbar_enable_disable(0);
+			}
+#if	0
+			/* PER response enable or disable. */
+			if( value & PCI_COMMAND_PARITY_ENABLE ){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				lo |= SB_PARE_ERR_EN;
+				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);			
+			}else{
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				lo &= ~SB_PARE_ERR_EN;
+				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);			
+			}
+#endif
+			// status
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			temp = lo & 0x0000ffff;
+			if( (value & PCI_STATUS_TARGET_TARGET_ABORT) && 
+				(lo & SB_TAS_ERR_EN) ){
+				temp |= SB_TAS_ERR_FLAG;
+			}
+			if( (value & PCI_STATUS_MASTER_TARGET_ABORT) &&
+				(lo & SB_TAR_ERR_EN) ){
+				temp |= SB_TAR_ERR_FLAG;
+			}
+			if( (value & PCI_STATUS_MASTER_ABORT) &&
+				(lo & SB_MAR_ERR_EN) ){
+				temp |= SB_MAR_ERR_FLAG;
+			}
+			if( (value & PCI_STATUS_PARITY_DETECT) &&
+				(lo & SB_PARE_ERR_EN) ){
+				temp |= SB_PARE_ERR_FLAG; 
+			}
+			lo = temp;
+			_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+			break;
+		case PCI_BHLC_REG :
+			value &= 0x0000ff00;
+			_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+			hi &= 0xffffff00;
+			hi |= (value >> 8);
+			_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_SMB_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// SMB NATIVE IO space has 8bytes
+				hi = 0x0000f001;
+				lo = value & 0x0000fff8;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
+				
+				// RCONFx is 4bytes in units for IO space.
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_SMB_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R0), hi, lo);
+			}
+			break;
+		case PCI_BAR1_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_GPIO_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// GPIO NATIVE reg is 256bytes
+				hi = 0x0000f001;
+				lo = value & 0x0000ff00;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), hi, lo);
+
+				// RCONFx is 4bytes in units for IO space
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_GPIO_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R1), hi, lo);
+			}
+			break;
+		case PCI_BAR2_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_MFGPT_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// MFGPT NATIVE reg is 64bytes
+				hi = 0x0000f001;
+				lo = value & 0x0000ffc0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), hi, lo);
+
+				// RCONFx is 4bytes in units for IO space
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_MFGPT_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R2), hi, lo);
+			}
+			break;
+		case PCI_BAR3_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_IRQ_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// IRQ NATIVE reg is 32bytes
+				hi = 0x0000f001;
+				lo = value & 0x0000ffc0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_IRQ), hi, lo);
+
+				// RCONFx is 4bytes in units for IO space
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_IRQ_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R3), hi, lo);
+			}
+			break;
+		case PCI_BAR4_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_PMS_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// PMS NATIVE reg is 128bytes
+				hi = 0x0000f001;
+				lo = value & 0x0000ff80;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_PMS), hi, lo);
+
+				// RCONFx is 4bytes in units for IO space.
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_PMS_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R4), hi, lo);
+			}
+			break;
+		case PCI_BAR5_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_ACPI_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// ACPI NATIVE reg is 32bytes
+				hi = 0x0000f001;
+				lo = value & 0x0000ffe0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_ACPI), hi, lo);
+				
+				// RCONFx is 4bytes in units for IO space.
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_ACPI_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R5), hi, lo);
+			}
+			break;
+		case PCI_UART1_INT_REG :
+			if(value){
+			/* enable uart1 interrupt in PIC */	
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+				lo &= ~(0xf << 24);
+				lo |= (CS5536_UART1_INTR << 24);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+			}else{
+			/* disable uart1 interrupt in PIC */
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+				lo &= ~(0xf << 24);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+			}
+			break;
+		case PCI_UART2_INT_REG :
+			if(value){
+			/* enable uart2 interrupt in PIC */	
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+				lo &= ~(0xf << 28);
+				lo |= (CS5536_UART2_INTR << 28);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+			}else{
+			/* disable uart2 interrupt in PIC */
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+				lo &= ~(0xf << 28);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+			}
+			break;
+		case PCI_ISA_FIXUP_REG :
+			if(value){
+				/* enable the TARGET ABORT/MASTER ABORT etc. */
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				lo |= 0x00000063;
+				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+			}
+
+		default :
+			/* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
+			break;			
+	}
+	
+	return;
+}
+
+/*
+ * isa_read : isa read transfering.
+ * we assume that the ISA is not the BUS MASTER. 
+ */
+ 
+ /* COMMAND :
+ * 	bit0 : IO SPACE ENABLE
+ *	bit1 : MEMORY SPACE ENABLE(ignore)
+ *	bit2 : BUS MASTER ENABLE(ignore)
+ *	bit3 : SPECIAL CYCLE(ignore)? default is ignored.
+ *	bit4 : MEMORY WRITE and INVALIDATE(ignore)
+ *	bit5 : VGA PALETTE(ignore)
+ *	bit6 : PARITY ERROR(ignore)? : default is ignored.
+ *	bit7 : WAIT CYCLE CONTROL(ignore)
+ *	bit8 : SYSTEM ERROR(ignore)
+ *	bit9 : FAST BACK TO BACK(ignore)
+ *	bit10-bit15 : RESERVED
+ * STATUS :
+ *	bit0-bit3 : RESERVED
+ *	bit4 : CAPABILITY LIST(ignore)
+ *	bit5 : 66MHZ CAPABLE
+ *	bit6 : RESERVED
+ *	bit7 : FAST BACK TO BACK(ignore)
+ *	bit8 : DATA PARITY ERROR DETECED(ignore)?
+ *	bit9-bit10 : DEVSEL TIMING(ALL MEDIUM)
+ *	bit11: SIGNALED TARGET ABORT
+ *	bit12: RECEIVED TARGET ABORT
+ *	bit13: RECEIVED MASTER ABORT
+ *	bit14: SIGNALED SYSTEM ERROR
+ *	bit15: DETECTED PARITY ERROR(?)
+ */
+
+static u32 pci_isa_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_ISA_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			// we just check the first LBAR for the IO enable bit,
+			// maybe we should changed later.
+			_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
+			if(hi & 0x01){
+				conf_data |= PCI_COMMAND_IO_ENABLE;
+			}
+			//conf_data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
+#if	0
+			conf_data |= PCI_COMMAND_SPECIAL_ENABLE;
+#endif
+#if	0
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_EN){
+				conf_data |= PCI_COMMAND_PARITY_ENABLE;
+			}else{
+				conf_data &= ~PCI_COMMAND_PARITY_ENABLE;
+			}
+#endif
+			// STATUS	
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+#if	1
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+#endif
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_TAS_ERR_FLAG)
+				conf_data |= PCI_STATUS_TARGET_TARGET_ABORT;
+			if(lo & SB_TAR_ERR_FLAG)
+				conf_data |= PCI_STATUS_MASTER_TARGET_ABORT;
+			if(lo & SB_MAR_ERR_FLAG)
+				conf_data |= PCI_STATUS_MASTER_ABORT;
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_DETECT;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_ISA_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+			hi &= 0x000000f8;
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_BRIDGE_HEADER_TYPE << 16) |
+				(hi << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		/*
+		 * we only use the LBAR of DIVIL, no RCONF used. 
+		 * all of them are IO space.
+		 */
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_SMB_FLAG){
+				conf_data = CS5536_SMB_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_SMB_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
+				conf_data = lo & 0x0000fff8;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR1_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_GPIO_FLAG){
+				conf_data = CS5536_GPIO_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_GPIO_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
+				conf_data = lo & 0x0000ff00;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR2_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_MFGPT_FLAG){
+				conf_data = CS5536_MFGPT_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_MFGPT_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &hi, &lo);
+				conf_data = lo & 0x0000ffc0;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+#if	1
+		case PCI_BAR3_REG :
+			conf_data = 0;
+			break;
+#else
+		case PCI_BAR3_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_IRQ_FLAG){
+				conf_data = CS5536_IRQ_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_IRQ_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_IRQ), &hi, &lo);
+				conf_data = lo & 0x0000ffc0;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+#endif
+		case PCI_BAR4_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_PMS_FLAG){
+				conf_data = CS5536_PMS_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_PMS_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_PMS), &hi, &lo);
+				conf_data = lo & 0x0000ff80;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR5_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_ACPI_FLAG){
+				conf_data = CS5536_ACPI_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_ACPI_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_ACPI), &hi, &lo);
+				conf_data = lo & 0x0000ffe0;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_ISA_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(0x00 << 8) | 0x00;
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+	
+	return conf_data;
+}
+
+#ifdef	TEST_CS5536_USE_FLASH
+
+#ifndef	TEST_CS5536_USE_NOR_FLASH	/* for nand flash */
+static void pci_flash_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// command
+			if( value & PCI_COMMAND_MEM_ENABLE ){
+				flash_lbar_enable_disable(1);
+			}else{
+				flash_lbar_enable_disable(0);
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				// make the flag for reading the bar length.
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH0_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				// mem space nand flash native reg base addr
+				hi = 0xfffff007;
+				lo = value & 0xfffff000;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), hi, lo);
+	
+				// RCONFx is 4KB in units for mem space.
+				hi = ((value & 0xfffff000) << 12) | ( (CS5536_FLSH0_LENGTH & 0xfffff000) - (1 << 12) ) | 0x00;
+				lo = ((value & 0xfffff000) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R6), hi, lo);			
+			}
+			break;
+		case PCI_BAR1_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH1_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				// mem space nand flash native reg base addr
+				hi = 0xfffff007;
+				lo = value & 0xfffff000;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH1), hi, lo);
+	
+				// RCONFx is 4KB in units for mem space.
+				hi = ((value & 0xfffff000) << 12) | ( (CS5536_FLSH1_LENGTH & 0xfffff000) - (1 << 12) ) | 0x00;
+				lo = ((value & 0xfffff000) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R7), hi, lo);
+			}
+			break;
+		case PCI_BAR2_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH2_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				// mem space nand flash native reg base addr
+				hi = 0xfffff007;
+				lo = value & 0xfffff000;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH2), hi, lo);
+	
+				// RCONFx is 4KB in units for mem space.
+				hi = ((value & 0xfffff000) << 12) | ( (CS5536_FLSH2_LENGTH & 0xfffff000) - (1 << 12) ) | 0x00;
+				lo = ((value & 0xfffff000) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R8), hi, lo);
+			}
+			break;		
+		case PCI_BAR3_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH3_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				// mem space nand flash native reg base addr
+				hi = 0xfffff007;
+				lo = value & 0xfffff000;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH3), hi, lo);
+	
+				// RCONFx is 4KB in units for mem space.
+				hi = ((value & 0xfffff000) << 12) | ( (CS5536_FLSH3_LENGTH & 0xfffff000)- (1 << 12) ) | 0x00;
+				lo = ((value & 0xfffff000) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R9), hi, lo);
+			}
+			break;
+		case PCI_FLASH_INT_REG :
+			if(value){
+			/* enable all the flash interrupt in PIC */	
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << PIC_YSEL_LOW_FLASH_SHIFT);
+				lo |= (CS5536_FLASH_INTR << PIC_YSEL_LOW_FLASH_SHIFT);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}else{
+			/* disable all the flash interrupt in PIC */
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << PIC_YSEL_LOW_FLASH_SHIFT);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}
+			break;
+		case PCI_NAND_FLASH_TDATA_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(DIVIL_MSR_REG(NANDF_DATA), hi, lo);
+			break;
+		case PCI_NAND_FLASH_TCTRL_REG :
+			hi = 0;
+			lo = value & 0x00000fff;
+			_wrmsr(DIVIL_MSR_REG(NANDF_CTRL), hi, lo);
+			break;
+		case PCI_NAND_FLASH_RSVD_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(DIVIL_MSR_REG(NANDF_RSVD), hi, lo);
+			break;
+		case PCI_FLASH_SELECT_REG :
+			if(value == CS5536_IDE_FLASH_SIGNATURE){
+				_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
+				lo &= ~0x01;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
+			}
+			break;
+		default :
+			break;
+	}
+	
+	return;
+}
+
+static u32 pci_flash_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_FLASH_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			// we just read one lbar for returning.
+			_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo);
+			if(hi & 0x01)
+				conf_data |= PCI_COMMAND_MEM_ENABLE;
+			//STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(DIVIL_MSR_REG(DIVIL_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_FLASH_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(PCI_NORMAL_LATENCY_TIMER << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH0_FLAG){
+				conf_data = CS5536_FLSH0_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH0_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo);
+				conf_data = lo;
+				conf_data &= ~0x0f;
+			}
+			break;
+		case PCI_BAR1_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH1_FLAG){
+				conf_data = CS5536_FLSH1_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH1_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH1), &hi, &lo);
+				conf_data = lo;
+				conf_data &= ~0x0f;
+			}
+			break;
+		case PCI_BAR2_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH2_FLAG){
+				conf_data = CS5536_FLSH2_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH2_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH2), &hi, &lo);
+				conf_data = lo;
+				conf_data &= ~0x0f;
+			}
+			break;
+		case PCI_BAR3_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH3_FLAG){
+				conf_data = CS5536_FLSH3_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH3_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH3), &hi, &lo);
+				conf_data = lo;
+				conf_data &= ~0x0f;
+			}
+			break;	
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_FLASH_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_FLASH_INTR);
+			break;
+		case PCI_NAND_FLASH_TDATA_REG :
+			_rdmsr(DIVIL_MSR_REG(NANDF_DATA), &hi, &lo);
+			conf_data = lo;
+			break;
+		case PCI_NAND_FLASH_TCTRL_REG :
+			_rdmsr(DIVIL_MSR_REG(NANDF_CTRL), &hi, &lo);
+			conf_data = lo & 0x00000fff;
+			break;
+		case PCI_NAND_FLASH_RSVD_REG :
+			_rdmsr(DIVIL_MSR_REG(NANDF_RSVD), &hi, &lo);
+			conf_data = lo;
+			break;
+		case PCI_FLASH_SELECT_REG :
+			_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
+			conf_data = lo & 0x01;
+			break;
+
+		}
+	return 0;
+}
+
+#else /* nor flash */
+
+static void pci_flash_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// command
+			if( value & PCI_COMMAND_IO_ENABLE ){
+				flash_lbar_enable_disable(1);
+			}else{
+				flash_lbar_enable_disable(0);
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH0_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// IO space of 16bytes nor flash
+				hi = 0x0000fff1;
+				lo = value & 0x0000fff0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), hi, lo);
+	
+				// RCONFx used for 16bytes reserved.
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_FLSH0_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R6), hi, lo);
+			}
+			break;
+		case PCI_BAR1_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH1_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// IO space of 16bytes nor flash
+				hi = 0x0000fff1;
+				lo = value & 0x0000fff0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH1), hi, lo);
+	
+				// RCONFx used for 16bytes reserved.
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_FLSH1_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R7), hi, lo);			
+			}
+			break;
+		case PCI_BAR2_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH2_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				hi = 0x0000fff1;
+				lo = value & 0x0000fff0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH2), hi, lo);
+	
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_FLSH2_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R8), hi, lo);				
+			}
+			break;		
+		case PCI_BAR3_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_FLSH3_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				// 16bytes for nor flash
+				hi = 0x0000fff1;
+				lo = value & 0x0000fff0;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH3), hi, lo);
+	
+				// 16bytes of IO space of RCONFx region.
+				hi = ((value & 0x000ffffc) << 12) | ((CS5536_FLSH3_LENGTH - 4) << 12) | 0x01;
+				lo = ((value & 0x000ffffc) << 12) | 0x01;
+				_wrmsr(SB_MSR_REG(SB_R9), hi, lo);	
+			}
+			break;
+			
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_FLASH_INTR);
+			break;
+		case PCI_FLASH_INT_REG :
+			if(value){
+			/* enable all the flash interrupt in PIC */	
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << PIC_YSEL_LOW_FLASH_SHIFT);
+				lo |= (CS5536_FLASH_INTR << PIC_YSEL_LOW_FLASH_SHIFT);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}else{
+			/* disable all the flash interrupt in PIC */
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << PIC_YSEL_LOW_FLASH_SHIFT);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}
+			break;
+		case PCI_NOR_FLASH_CTRL_REG :
+			hi = 0;
+			lo = value & 0x000000ff;
+			_wrmsr(DIVIL_MSR_REG(NORF_CTRL), hi, lo);
+			break;
+		case PCI_NOR_FLASH_T01_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(DIVIL_MSR_REG(NORF_T01), hi, lo);
+			break;
+		case PCI_NOR_FLASH_T23_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(DIVIL_MSR_REG(NORF_T23), hi, lo);
+			break;
+		case PCI_FLASH_SELECT_REG :
+			if(value == CS5536_IDE_FLASH_SIGNATURE){
+				_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
+				lo &= ~0x01;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
+			}
+			break;
+
+		default :
+			break;			
+	}
+	
+	return;
+}
+
+static u32 pci_flash_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_FLASH_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			// we just check one flash bar for returning.
+			_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo);
+			if(hi & 0x01)
+				conf_data |= PCI_COMMAND_IO_ENABLE;
+			//STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(DIVIL_MSR_REG(DIVIL_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_FLASH_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(PCI_NORMAL_LATENCY_TIMER << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH0_FLAG){
+				conf_data = CS5536_FLSH0_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH0_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo);
+				conf_data = lo & 0x0000ffff;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR1_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH1_FLAG){
+				conf_data = CS5536_FLSH1_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH1_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH1), &hi, &lo);
+				conf_data = lo & 0x0000ffff;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR2_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH2_FLAG){
+				conf_data = CS5536_FLSH2_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH2_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH2), &hi, &lo);
+				conf_data = lo & 0x0000ffff;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR3_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_FLSH3_FLAG){
+				conf_data = CS5536_FLSH3_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_FLSH3_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH3), &hi, &lo);
+				conf_data = lo & 0x0000ffff;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;	
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_FLASH_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_FLASH_INTR);
+			break;
+		case PCI_NOR_FLASH_CTRL_REG :
+			_rdmsr(DIVIL_MSR_REG(NORF_CTRL), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			break;
+		case PCI_NOR_FLASH_T01_REG :
+			_rdmsr(DIVIL_MSR_REG(NORF_T01), &hi, &lo);
+			conf_data = lo;
+			break;
+		case PCI_NOR_FLASH_T23_REG :
+			_rdmsr(DIVIL_MSR_REG(NORF_T23), &hi, &lo);
+			conf_data = lo;
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+	return conf_data;
+}
+#endif  /* TEST_CS5536_USE_NOR_FLASH */
+
+#else	/* TEST_CS5536_USE_FLASH */
+
+static void pci_flash_write_reg(int reg, u32 value)
+{
+	return;
+}
+
+static u32 pci_flash_read_reg(int reg)
+{
+	return 0xffffffff;
+}
+
+#endif	/* TEST_CS5536_USE_FLASH */
+
+/*
+ * ide_write : ide write transfering
+ */
+static void pci_ide_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// COMMAND
+			if(value & PCI_COMMAND_MASTER_ENABLE){
+				_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+				lo |= (0x03 << 4);
+				_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);			
+			}else{
+				_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+				lo &= ~(0x03 << 4);
+				_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);	
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BHLC_REG :
+			value &= 0x0000ff00;
+			_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+			hi &= 0xffffff00;
+			hi |= (value >> 8);
+			_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
+			break;
+		case PCI_BAR4_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_IDE_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if(value & 0x01){
+				hi = 0x00000000;
+				//lo = ((value & 0x0fffffff) << 4) | 0x001;
+				lo = (value & 0xfffffff0) | 0x1;
+				_wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
+
+				value &= 0xfffffffc;
+				hi = 0x60000000 | ((value & 0x000ff000) >> 12);
+				lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
+				_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
+	   		}
+			break;
+		case PCI_IDE_CFG_REG :
+			if(value == CS5536_IDE_FLASH_SIGNATURE){
+				_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
+				lo |= 0x01;
+				_wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
+			}else{
+				hi = 0;
+				lo = value;
+				_wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);			
+			}
+			break;
+		case PCI_IDE_DTC_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
+			break;
+		case PCI_IDE_CAST_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
+			break;
+		case PCI_IDE_ETC_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
+			break;
+		case PCI_IDE_PM_REG :
+			hi = 0;
+			lo = value;
+			_wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
+			break;
+		default :
+			break;			
+	}
+	
+	return;
+}
+
+/*
+ * ide_read : ide read tranfering.
+ */
+static u32 pci_ide_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_IDE_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
+			if(lo & 0xfffffff0)
+				conf_data |= PCI_COMMAND_IO_ENABLE;
+			_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+			if( (lo & 0x30) == 0x30 )
+				conf_data |= PCI_COMMAND_MASTER_ENABLE;
+			/* conf_data |= PCI_COMMAND_BACKTOBACK_ENABLE??? HOW TO GET..*/
+			//STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_IDE_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+			hi &= 0x000000f8;
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(hi << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			conf_data = 0x00000000;
+			break;
+		case PCI_BAR1_REG :
+			conf_data = 0x00000000;
+			break;
+		case PCI_BAR2_REG :
+			conf_data = 0x00000000;
+			break;
+		case PCI_BAR3_REG :
+			conf_data = 0x00000000;
+			break;
+		case PCI_BAR4_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_IDE_FLAG){
+				conf_data = CS5536_IDE_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_IDE_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
+				//conf_data = lo >> 4;
+				conf_data = lo & 0xfffffff0;
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR5_REG :
+			conf_data = 0x00000000;
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_IDE_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_IDE_INTR);
+			break;
+		case PCI_IDE_CFG_REG :
+			_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
+			conf_data = lo;
+			break;
+		case PCI_IDE_DTC_REG :
+			_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
+			conf_data = lo;
+			break;
+		case PCI_IDE_CAST_REG :
+			_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
+			conf_data = lo;
+			break;
+		case PCI_IDE_ETC_REG :
+			_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
+			conf_data = lo;
+		case PCI_IDE_PM_REG :
+			_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
+			conf_data = lo;
+			break;
+			
+		default :
+			conf_data = 0;
+			break;
+	}
+
+	return conf_data;
+}
+
+static void pci_acc_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// COMMAND
+			if(value & PCI_COMMAND_MASTER_ENABLE){
+				_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+				lo |= (0x03 << 8);
+				_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);			
+			}else{
+				_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+				lo &= ~(0x03 << 8);
+				_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);	
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_ACC_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( value & 0x01 ){
+				value &= 0xfffffffc;
+				hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
+				lo = 0x000fff80 | ((value & 0x00000fff) << 20);
+				_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
+			}
+			break;
+		case PCI_ACC_INT_REG :
+			if(value){
+			/* enable all the acc interrupt in PIC */	
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
+				lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}else{
+			/* disable all the usb interrupt in PIC */
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}
+			break;
+		default :
+			break;			
+	}
+
+	return;
+}
+
+static u32 pci_acc_read_reg(int reg)
+{
+	u32 hi, lo;
+	u32 conf_data;
+
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_ACC_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			
+			conf_data = 0;
+			// COMMAND
+			_rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
+			if( ( (lo & 0xfff00000) || (hi & 0x000000ff) ) 
+					&& ((hi & 0xf0000000) == 0xa0000000) )
+				conf_data |= PCI_COMMAND_IO_ENABLE;
+			_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+			if( (lo & 0x300) == 0x300 )
+				conf_data |= PCI_COMMAND_MASTER_ENABLE;
+			/* conf_data |= PCI_COMMAND_BACKTOBACK_ENABLE??? HOW TO GET..*/
+			//STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_ACC_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(PCI_NORMAL_LATENCY_TIMER << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_ACC_FLAG){
+				conf_data = CS5536_ACC_RANGE | PCI_MAPREG_TYPE_IO;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_ACC_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
+				conf_data = (hi & 0x000000ff) << 12;
+				conf_data |= (lo & 0xfff00000) >> 20; 
+				conf_data |= 0x01;
+				conf_data &= ~0x02;
+			}
+			break;
+		case PCI_BAR1_REG :
+			conf_data = 0x000000;
+			break;		
+		case PCI_BAR2_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR3_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR4_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR5_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_ACC_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_USB_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_ACC_INTR);
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+
+	return conf_data;
+}
+
+
+/*
+ * ohci_write : ohci write tranfering.
+ */
+static void pci_ohci_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// COMMAND
+			if(value & PCI_COMMAND_MASTER_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+				hi |= (1 << 2);
+				_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+				hi &= ~(1 << 2);
+				_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+			}
+			if(value & PCI_COMMAND_MEM_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+				hi |= (1 << 1);
+				_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+				hi &= ~(1 << 1);
+				_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);				
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_OHCI_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+				//lo = (value & 0xffffff00) << 8;
+				lo = value;
+				_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+				
+				value &= 0xfffffff0;
+				hi = 0x40000000 | ((value & 0xff000000) >> 24);
+				lo = 0x000fffff | ((value & 0x00fff000) << 8);
+				_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
+			}
+			break;
+		case PCI_INTERRUPT_REG :
+			value &= 0x000000ff;
+			break;
+		case PCI_OHCI_PM_REG :
+			break;
+		case PCI_OHCI_INT_REG :
+			if(value){
+			/* enable all the usb interrupt in PIC */	
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << 8);
+				lo |= (CS5536_USB_INTR << 8);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}else{
+			/* disable all the usb interrupt in PIC */
+				_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+				lo &= ~(0xf << 8);
+				_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+			}
+			break;
+		default :
+			break;			
+	}
+	
+	return;
+}
+
+/*
+ * ohci_read : ohci read transfering.
+ */
+static u32 pci_ohci_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_OHCI_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+			if(hi & 0x04)
+				conf_data |= PCI_COMMAND_MASTER_ENABLE;
+			if(hi & 0x02)
+				conf_data |= PCI_COMMAND_MEM_ENABLE;
+			// STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(0x00 << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_OHCI_FLAG){
+				conf_data = CS5536_OHCI_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_OHCI_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+				//conf_data = lo >> 8;
+				conf_data = lo & 0xffffff00;
+				conf_data &= ~0x0000000f; // 32bit mem
+			}
+			break;
+		case PCI_BAR1_REG :
+			conf_data = 0x000000;
+			break;		
+		case PCI_BAR2_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR3_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR4_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR5_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_OHCI_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_USB_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_USB_INTR);
+			break;
+		case PCI_OHCI_PM_REG :
+			conf_data = 0;
+			break;
+		case PCI_OHCI_INT_REG :
+			_rdmsr(DIVIL_MSR_REG(0x20), &hi, &lo);
+			if((lo & 0x00000f00) == 11)
+				conf_data = 1;
+			else
+				conf_data = 0;
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+
+	return conf_data;
+}
+
+#ifdef	TEST_CS5536_USE_EHCI
+static void pci_ehci_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// COMMAND
+			if(value & PCI_COMMAND_MASTER_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+				hi |= (1 << 2);
+				_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+				hi &= ~(1 << 2);
+				_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+			}
+			if(value & PCI_COMMAND_MEM_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+				hi |= (1 << 1);
+				_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+				hi &= ~(1 << 1);
+				_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);				
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_EHCI_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+				lo = value;
+				_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+				
+				value &= 0xfffffff0;
+				hi = 0x40000000 | ((value & 0xff000000) >> 24);
+				lo = 0x000fffff | ((value & 0x00fff000) << 8);
+				_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
+			}
+			break;
+		case PCI_EHCI_LEGSMIEN_REG :
+			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+			hi &= 0x003f0000;
+			hi |= (value & 0x3f) << 16;
+			_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+			break;
+		case PCI_EHCI_FLADJ_REG :
+			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+			hi &= ~0x00003f00;
+			hi |= value & 0x00003f00;
+			_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+			break;
+		default :
+			break;			
+	}
+	
+	return;
+}
+
+static u32 pci_ehci_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_EHCI_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+			if(hi & 0x04)
+				conf_data |= PCI_COMMAND_MASTER_ENABLE;
+			if(hi & 0x02)
+				conf_data |= PCI_COMMAND_MEM_ENABLE;
+			// STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(PCI_NORMAL_LATENCY_TIMER << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_EHCI_FLAG){
+				conf_data = CS5536_EHCI_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_EHCI_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+				conf_data = lo & 0xfffff000;
+			}
+			break;
+		case PCI_BAR1_REG :
+			conf_data = 0x000000;
+			break;		
+		case PCI_BAR2_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR3_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR4_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR5_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_EHCI_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_USB_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_USB_INTR);
+			break;
+		case PCI_EHCI_LEGSMIEN_REG :
+			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+			conf_data = (hi & 0x003f0000) >> 16;
+			break;
+		case PCI_EHCI_LEGSMISTS_REG :
+			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+			conf_data = (hi & 0x3f000000) >> 24;
+			break;
+		case PCI_EHCI_FLADJ_REG :
+			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+			conf_data = hi & 0x00003f00;
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+
+	return conf_data;
+}
+#else
+static void pci_ehci_write_reg(int reg, u32 value)
+{
+	return;
+}
+
+static u32 pci_ehci_read_reg(int reg)
+{
+	return  0xffffffff;
+}
+
+
+#endif
+
+#ifdef	TEST_CS5536_USE_UDC
+static void pci_udc_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// COMMAND
+			if(value & PCI_COMMAND_MASTER_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+				hi |= (1 << 2);
+				_wrmsr(USB_MSR_REG(USB_UDC), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+				hi &= ~(1 << 2);
+				_wrmsr(USB_MSR_REG(USB_UDC), hi, lo);
+			}
+			if(value & PCI_COMMAND_MEM_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+				hi |= (1 << 1);
+				_wrmsr(USB_MSR_REG(USB_UDC), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+				hi &= ~(1 << 1);
+				_wrmsr(USB_MSR_REG(USB_UDC), hi, lo);				
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_UDC_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+				lo = value;
+				_wrmsr(USB_MSR_REG(USB_UDC), hi, lo);
+				
+				value &= 0xfffffff0;
+				hi = 0x40000000 | ((value & 0xff000000) >> 24);
+				lo = 0x000fffff | ((value & 0x00fff000) << 8);
+				_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM0), hi, lo);
+			}
+			break;
+		default :
+			break;			
+	}
+	
+	return;
+}
+
+static u32 pci_udc_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_UDC_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+			if(hi & 0x04)
+				conf_data |= PCI_COMMAND_MASTER_ENABLE;
+			if(hi & 0x02)
+				conf_data |= PCI_COMMAND_MEM_ENABLE;
+			// STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_UDC_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(0x00 << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_UDC_FLAG){
+				conf_data = CS5536_UDC_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_UDC_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo);
+				conf_data = lo & 0xfffff000;
+				conf_data &= ~0x0000000f; // 32bit mem
+			}
+			break;
+		case PCI_BAR1_REG :
+			conf_data = 0x000000;
+			break;		
+		case PCI_BAR2_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR3_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR4_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR5_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_UDC_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_USB_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_USB_INTR);
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+
+	return conf_data;
+}
+
+#else	/* TEST_CS5536_USE_UDC */
+
+static void pci_udc_write_reg(int reg, u32 value)
+{
+	return;
+}
+
+static u32 pci_udc_read_reg(int reg)
+{
+	return  0xffffffff;
+}
+
+#endif	/* TEST_CS5536_USE_UDC */
+
+
+#ifdef	TEST_CS5536_USE_OTG
+static void pci_otg_write_reg(int reg, u32 value)
+{
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_COMMAND_STATUS_REG :
+			// COMMAND
+			if(value & PCI_COMMAND_MEM_ENABLE){
+				_rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo);
+				hi |= (1 << 1);
+				_wrmsr(USB_MSR_REG(USB_OTG), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo);
+				hi &= ~(1 << 1);
+				_wrmsr(USB_MSR_REG(USB_OTG), hi, lo);				
+			}
+			// STATUS
+			if(value & PCI_STATUS_PARITY_ERROR){
+				_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+				if(lo & SB_PARE_ERR_FLAG){
+					lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+					_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+				}				
+			}
+			break;
+		case PCI_BAR0_REG :
+			if(value == PCI_BAR_RANGE_MASK){
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo |= SOFT_BAR_OTG_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else if( (value & 0x01) == 0x00 ){
+				_rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo);
+				lo = value & 0xffffff00;
+				_wrmsr(USB_MSR_REG(USB_OTG), hi, lo);
+				
+				value &= 0xfffffff0;
+				hi = 0x40000000 | ((value & 0xff000000) >> 24);
+				lo = 0x000fffff | ((value & 0x00fff000) << 8);
+				_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM1), hi, lo);
+			}
+			break;
+		default :
+			break;			
+	}
+	
+	return;
+}
+
+static u32 pci_otg_read_reg(int reg)
+{
+	u32 conf_data;
+	u32 hi, lo;
+	
+	switch(reg){
+		case PCI_ID_REG :
+			conf_data = (CS5536_OTG_DEVICE_ID << 16 | CS5536_VENDOR_ID);
+			break;
+		case PCI_COMMAND_STATUS_REG :
+			conf_data = 0;
+			// COMMAND
+			_rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo);
+			if(hi & 0x02)
+				conf_data |= PCI_COMMAND_MEM_ENABLE;
+			// STATUS
+			conf_data |= PCI_STATUS_66MHZ_SUPPORT;
+			conf_data |= PCI_STATUS_BACKTOBACK_SUPPORT;
+			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+			if(lo & SB_PARE_ERR_FLAG)
+				conf_data |= PCI_STATUS_PARITY_ERROR;
+			conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+			break;
+		case PCI_CLASS_REG :
+			_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+			conf_data = lo & 0x000000ff;
+			conf_data |= (CS5536_OTG_CLASS_CODE << 8);
+			break;
+		case PCI_BHLC_REG :
+			conf_data = (PCI_NONE_BIST << 24) | (PCI_NORMAL_HEADER_TYPE << 16) |
+				(0x00 << 8) | PCI_NORMAL_CACHE_LINE_SIZE;
+			break;
+		case PCI_BAR0_REG :
+			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+			if(lo & SOFT_BAR_OTG_FLAG){
+				conf_data = CS5536_OTG_RANGE | PCI_MAPREG_TYPE_MEM;
+				_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+				lo &= ~SOFT_BAR_OTG_FLAG;
+				_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+			}else{
+				_rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo);
+				conf_data = lo & 0xffffff00;
+				conf_data &= ~0x0000000f;
+			}
+			break;
+		case PCI_BAR1_REG :
+			conf_data = 0x000000;
+			break;		
+		case PCI_BAR2_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR3_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR4_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_BAR5_REG :
+			conf_data = 0x000000;
+			break;
+		case PCI_CARDBUS_CIS_REG :
+			conf_data = PCI_CARDBUS_CIS_POINTER;
+			break;
+		case PCI_SUBSYS_ID_REG :
+			conf_data = (CS5536_OTG_SUB_ID << 16) | CS5536_SUB_VENDOR_ID;
+			break;
+		case PCI_MAPREG_ROM :
+			conf_data = PCI_EXPANSION_ROM_BAR;
+			break;
+		case PCI_CAPLISTPTR_REG :
+			conf_data = PCI_CAPLIST_USB_POINTER;
+			break;
+		case PCI_INTERRUPT_REG :
+			conf_data = (PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | 
+				(PCI_DEFAULT_PIN << 8) | (CS5536_USB_INTR);
+			break;
+		default :
+			conf_data = 0;
+			break;
+	}
+
+	return conf_data;
+}
+
+#else	/* TEST_CS5536_USE_OTG */
+
+static void pci_otg_write_reg(int reg, u32 value)
+{
+	return;
+}
+
+static u32 pci_otg_read_reg(int reg)
+{
+	return 0xffffffff;
+}
+
+#endif	/* TEST_CS5536_USE_OTG */
+
+/*******************************************************************************/
+
+/*
+ * writen : write to PCI config space and transfer it to MSR write.
+ */
+void cs5536_pci_conf_write4(int function, int reg, u32 value)
+{
+	/* some basic checking. */
+	if( (function < CS5536_FUNC_START) || (function > CS5536_FUNC_END) ){
+		return;
+	}
+	if( (reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0) ){
+		return;
+	}
+	
+	switch(function){
+		case CS5536_ISA_FUNC :
+			pci_isa_write_reg(reg, value);		
+			break;
+
+		case CS5536_FLASH_FUNC :
+			pci_flash_write_reg(reg, value);
+			break;
+		
+		case CS5536_IDE_FUNC :
+			pci_ide_write_reg(reg, value);
+			break;
+
+		case CS5536_ACC_FUNC :
+			pci_acc_write_reg(reg, value);
+			break;
+
+		case CS5536_OHCI_FUNC :
+			pci_ohci_write_reg(reg, value);
+			break;
+
+		case CS5536_EHCI_FUNC :
+			pci_ehci_write_reg(reg, value);
+			break;
+
+		case CS5536_UDC_FUNC :
+			pci_udc_write_reg(reg, value);
+			break;
+
+		case CS5536_OTG_FUNC :
+			pci_otg_write_reg(reg, value);
+			break;
+		
+		default :
+			break;
+	}
+	
+	return;
+}
+
+/*
+ * readn : read PCI config space and transfer it to MSR access.
+ */
+u32 cs5536_pci_conf_read4(int function, int reg)
+{
+	u32 data = 0;
+
+	/* some basic checking. */
+	if( (function < CS5536_FUNC_START) || (function > CS5536_FUNC_END) ){
+		return 0;
+	}
+	if( (reg < 0) || ((reg & 0x03) != 0) ){
+		return 0;
+	}
+	if( reg > 0x100 )
+		return 0xffffffff;
+	
+	switch(function){
+		case CS5536_ISA_FUNC :
+			data = pci_isa_read_reg(reg);
+			break;
+
+		case CS5536_FLASH_FUNC :
+			data = pci_flash_read_reg(reg);
+			break;
+		
+		case CS5536_IDE_FUNC :
+			data = pci_ide_read_reg(reg);
+			break;
+
+		case CS5536_ACC_FUNC :
+			data = pci_acc_read_reg(reg);
+			break;
+
+		case CS5536_OHCI_FUNC :
+			data = pci_ohci_read_reg(reg);
+			break;
+
+		case CS5536_EHCI_FUNC :
+			data = pci_ehci_read_reg(reg);
+			break;
+
+		case CS5536_UDC_FUNC :
+			data = pci_udc_read_reg(reg);
+			break;
+
+		case CS5536_OTG_FUNC :
+			data = pci_otg_read_reg(reg);
+			break;
+		
+		default :
+			break;
+	
+	}
+	
+	return data;
+}
+
+/**************************************************************************/
+
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/dbg_io.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/dbg_io.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/dbg_io.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/dbg_io.c	2011-05-08 18:02:18.000000000 +0800
@@ -0,0 +1,183 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <asm/types.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <asm/serial.h>		/* For the serial port location and base baud */
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* ----------------------------------------------------- */
+
+//#define	USE_LOONGSON2F_UART
+#ifdef	USE_LOONGSON2F_UART
+
+/* === CONFIG === */
+#ifdef CONFIG_64BIT
+#define         BASE                    (0xffffffffbff003f8)
+#else
+#define         BASE                    (0xbff003f8)
+#endif
+
+#else	/* USE_CS5536_UART1/2 */
+
+#ifdef CONFIG_64BIT
+#define         BASE                    0xffffffffbfd003f8
+#else
+#define         BASE                    0xbfd003f8
+#endif
+
+#endif	/* end of USE_LOONGSON2F_UART */
+
+#define         MAX_BAUD                BASE_BAUD
+/* === END OF CONFIG === */
+
+#define         REG_OFFSET              1
+
+/* register offset */
+#define         OFS_RCV_BUFFER          0
+#define         OFS_TRANS_HOLD          0
+#define         OFS_SEND_BUFFER         0
+#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
+#define         OFS_INTR_ID             (2*REG_OFFSET)
+#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
+#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
+#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
+#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
+#define         OFS_LINE_STATUS         (5*REG_OFFSET)
+#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
+#define         OFS_RS232_INPUT         (6*REG_OFFSET)
+#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
+
+#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
+#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
+
+/* memory-mapped read/write of the port */
+#define         UART16550_READ(y)    (*((volatile u8*)(0xffffffffbe000000 + y)))
+#define         UART16550_WRITE(y, z)  ((*((volatile u8*)(0xffffffffbe000000 + y))) = z)
+
+void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+	/* set up buad rate */
+	{
+		u32 divisor;
+
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+static int remoteDebugInitialized = 0;
+
+u8 getDebugChar(void)
+{
+	if (!remoteDebugInitialized) {
+		remoteDebugInitialized = 1;
+		debugInit(UART16550_BAUD_115200,
+			  UART16550_DATA_8BIT,
+			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+	}
+
+	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ;
+	return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+int putDebugChar(u8 byte)
+{
+	if (!remoteDebugInitialized) {
+		remoteDebugInitialized = 1;
+		/*
+		   debugInit(UART16550_BAUD_115200,
+		   UART16550_DATA_8BIT,
+		   UART16550_PARITY_NONE, UART16550_STOP_1BIT); */
+	}
+
+	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ;
+	UART16550_WRITE(OFS_SEND_BUFFER, byte);
+	return 1;
+}
+
+extern void prom_putchar(char c);
+
+void prom_printf(char *fmt, ...)
+{
+	va_list args;
+	char ppbuf[1024];
+	char *bptr;
+
+	va_start(args, fmt);
+	vsprintf(ppbuf, fmt, args);
+
+	bptr = ppbuf;
+
+	while (*bptr != 0) {
+		if (*bptr == '\n')
+			prom_putchar('\r');
+
+		prom_putchar(*bptr++);
+	}
+	va_end(args);
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/irq.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/irq.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/irq.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/irq.c	2011-05-27 16:42:39.000000000 +0800
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+#include <asm/delay.h>
+#include <asm/mips-boards/bonito64.h>
+
+#define	BONITO_INT_BIT_GPIO0		(1 << 0)
+#define	BONITO_INT_BIT_GPIO1		(1 << 1)
+#define	BONITO_INT_BIT_GPIO2		(1 << 2)
+#define	BONITO_INT_BIT_GPIO3		(1 << 3)
+#define	BONITO_INT_BIT_PCI_INTA		(1 << 4)
+#define	BONITO_INT_BIT_PCI_INTB		(1 << 5)
+#define	BONITO_INT_BIT_PCI_INTC		(1 << 6)
+#define	BONITO_INT_BIT_PCI_INTD		(1 << 7)
+#define	BONITO_INT_BIT_PCI_PERR		(1 << 8)
+#define	BONITO_INT_BIT_PCI_SERR		(1 << 9)
+#define	BONITO_INT_BIT_DDR		(1 << 10)
+#define	BONITO_INT_BIT_INT0		(1 << 11)
+#define	BONITO_INT_BIT_INT1		(1 << 12)
+#define	BONITO_INT_BIT_INT2		(1 << 13)
+#define	BONITO_INT_BIT_INT3		(1 << 14)
+
+#define	BONITO_INT_TIMER_OFF		7
+#define	BONITO_INT_BONITO_OFF		6
+#define	BONITO_INT_UART_OFF			3
+#define	BONITO_INT_I8259_OFF		2
+
+/****************************************************************/
+
+static void godson2f_timer_dispatch(void)
+{
+	/* place the godson2f timer interrupt on 23 */
+	do_IRQ(MIPS_CPU_IRQ_BASE + BONITO_INT_TIMER_OFF);
+	return;
+}
+
+static void godson2f_bonito_dispatch(void)
+{
+	int int_status;
+	int i = 0;
+
+	/* place the other interrupt on bit6 for bonito, inclding PCI and so on */
+	int_status = BONITO_INTISR & BONITO_INTEN;
+	
+	for(i = 0; (i < 10) && int_status; i++){
+		if(int_status & (1 << i)){
+			if(i == 10)
+				printk("ddr int.\n");
+#if 0
+			if(int_status & 0x00000004)
+				printk("cpu gpio int %08x\n",int_status);
+			if(int_status & 0x000000ff)
+#endif
+				do_IRQ(BONITO_IRQ_BASE + i);
+			int_status &= ~(1 << i);
+		}
+	}
+	
+	return;
+}
+
+static void godson2f_int3_dispatch(void)
+{
+	do_IRQ(21);
+	
+	return;
+}
+
+static void godson2f_int2_dispatch(void)
+{
+	do_IRQ(20);
+	
+	return;
+}
+
+static void godson2f_int0_dispatch(void)
+{
+		do_IRQ(18);
+}
+static void godson2f_int1_dispatch(void)
+{
+	/* place the godson2f uart interrupt on int1 */
+	//do_IRQ(MIPS_CPU_IRQ_BASE + BONITO_INT_UART_OFF);
+//	int_status = BONITO_INTISR & BONITO_INTEN;
+//	if(int_status & BONITO_INT_BIT_INT1)
+	do_IRQ(19);
+}
+
+static void i8259_irqdispatch(void)
+{
+	int irq, isr;
+	extern unsigned int cached_irq_mask;
+
+	if((BONITO_INTISR & BONITO_INTEN) & BONITO_INT_BIT_INT0) {
+
+		isr = inb(0x20) | (inb(0xa0) << 8);
+		isr &= ~0x4; // irq2 for cascade
+		isr &= ~cached_irq_mask;
+		irq = ffs(isr) - 1;
+
+		if(irq >= 0) {
+			do_IRQ(irq);
+		} else {
+			spurious_interrupt();
+		}
+	}
+}
+
+static void godson2f_steer1_dispatch(void)
+{
+	printk(KERN_INFO "godson2f steer1 is not used yet.\n");
+	return;
+}
+
+static void godson2f_steer0_dispatch(void)
+{
+	printk(KERN_INFO "godson2f steer0 is not used yet.\n");
+	return;
+}
+
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+		//printk(">>>>check your mother board.%08x,%08x\n",read_c0_cause(),read_c0_status());
+
+	if(pending & CAUSEF_IP7){
+		godson2f_timer_dispatch();
+	}else if(pending & CAUSEF_IP6){ /*nb*/
+#ifdef CONFIG_PROFILING
+		do_IRQ(MIPS_CPU_IRQ_BASE + 6);
+#endif
+		godson2f_bonito_dispatch();
+	}else if(pending & CAUSEF_IP5){
+		godson2f_int3_dispatch();
+	}else if(pending & CAUSEF_IP4){
+		godson2f_int2_dispatch();
+	}else if(pending & CAUSEF_IP3){ /*cpu uart*/
+		godson2f_int1_dispatch();
+	}else if(pending & CAUSEF_IP2){ /*sb*/
+		godson2f_int0_dispatch();
+		//i8259_irqdispatch();
+	}else if(pending & CAUSEF_IP1){
+		godson2f_steer1_dispatch();
+	}else if(pending & CAUSEF_IP0){
+		godson2f_steer0_dispatch();
+	}else{
+		spurious_interrupt();
+	}
+	return;
+}
+
+static struct irqaction cascade_irqaction = {
+	.handler = no_action,
+	.mask = CPU_MASK_NONE,
+	.name = "cascade",
+};
+
+irqreturn_t ip6_action(int cpl, void *dev_id, struct pt_regs *regs)
+{
+	return IRQ_HANDLED;
+}
+
+static struct irqaction ip6_irqaction = {
+	.handler = ip6_action,
+	.mask = CPU_MASK_NONE,
+	.name = "cascade",
+	.flags = IRQF_SHARED,
+};
+
+
+void __init arch_init_irq(void)
+{
+	extern void bonito_irq_init(void);
+
+	/*
+	 * Clear all of the interrupts while we change the able around a bit.
+	 * int-handler is not on bootstrap
+	 */
+	clear_c0_status(ST0_IM | ST0_BEV);
+	local_irq_disable();
+	
+#if	0
+	/* most bonito irq should be level triggered */
+	BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR
+	    | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
+#endif
+
+	/* setup cs5536 as high level */
+//	BONITO_INTEDGE |= (1 << 11 | 1 << 12);
+	BONITO_INTPOL  = (1 << 11 | 1 << 12 | 1 << 13 | 1 << 14 | 1 << 0| 1 << 1| 1 << 2);
+//	BONITO_INTEDGE &= ~(1 << 11 | 1 << 12);
+//	BONITO_INTEDGE |= (1 << 11 | 1 << 12);
+
+	/* no steer */
+	BONITO_INTSTEER = 0;
+	/*
+	 * Mask out all interrupt by writing "1" to all bit position in
+	 * the interrupt reset reg.
+	 */
+	BONITO_INTENCLR = ~0;
+
+	/* init all controller
+	 *   0-15         ------> i8259 interrupt
+	 *   16-23        ------> mips cpu interrupt
+	 *   32-63        ------> bonito irq
+	 */
+	
+	/* Sets the first-level interrupt dispatcher. */
+	mips_cpu_irq_init();
+
+	init_i8259_irqs();
+	bonito_irq_init();
+	
+	/* setup bonito interrupt */
+	//setup_irq(MIPS_CPU_IRQ_BASE + BONITO_INT_BONITO_OFF, &cascade_irqaction);
+#ifdef CONFIG_PROFILING
+	setup_irq(MIPS_CPU_IRQ_BASE + BONITO_INT_BONITO_OFF, &ip6_irqaction);
+	setup_irq(MIPS_CPU_IRQ_BASE + 2, &ip6_irqaction);
+#else
+	setup_irq(MIPS_CPU_IRQ_BASE + BONITO_INT_BONITO_OFF, &cascade_irqaction);
+#endif
+//printk("MIPS_CPU_IRQ_BASE:%d\n",MIPS_CPU_IRQ_BASE);
+//printk("cpu gpio:%08x,%08x\n",*(unsigned int *)0xffffffffbfe00120,*(unsigned int *)0xffffffffbfe0011c);
+	/* 8259 irq at IP2 */
+//	setup_irq(MIPS_CPU_IRQ_BASE + BONITO_INT_I8259_OFF, &cascade_irqaction);
+
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/Makefile linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/Makefile
--- linux-2.6.27.6/arch/mips/lemote/lm2f/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/Makefile	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,7 @@
+#
+# Makefile for ICT CAS godsonev2e board.
+#
+
+obj-y	+= setup.o prom.o reset.o irq.o pci.o bonito-irq.o mipsdha.o dbg_io.o mem.o
+
+EXTRA_AFLAGS := $(CFLAGS)
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/mem.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/mem.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/mem.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/mem.c	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,23 @@
+/*
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/fs.h>
+#include <linux/fcntl.h>
+#include <linux/mm.h>
+
+/* override of arch/mips/mm/cache.c: __uncached_access */
+int __uncached_access(struct file *file, unsigned long addr)
+{
+	if (file->f_flags & O_SYNC)
+		return 1;
+
+	/*
+	 * On the Lemote Loongson 2e system, the peripheral registers
+	 * reside between 0x1000:0000 and 0x2000:0000.
+	 */
+	return addr >= __pa(high_memory) ||
+		((addr >= 0x10000000) && (addr < 0x80000000));
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/mipsdha.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/mipsdha.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/mipsdha.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/mipsdha.c	2011-05-08 18:02:18.000000000 +0800
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+static ssize_t mipsdha_proc_read(struct file *file, char *buf, size_t len, loff_t *ppos);
+
+static ssize_t mipsdha_proc_write(struct file *file, const char *buf, size_t len, loff_t *ppos);
+
+
+static struct proc_dir_entry *mipsdha_proc_entry;
+
+#define INFO_SIZE 4096
+static char info_buf[INFO_SIZE];
+
+static struct file_operations mipsdha_fops =
+{
+    owner:	THIS_MODULE,
+    read:	mipsdha_proc_read,
+    write:	mipsdha_proc_write,
+};
+
+static enum {CMD_ERR, CMD_GIB, CMD_GPI} cmd;
+
+typedef struct pciinfo_s
+{
+  int		bus,card,func;
+  unsigned short command;
+  unsigned short vendor,device;
+  unsigned	base0,base1,base2,baserom;
+} pciinfo_t;
+
+
+extern struct proc_dir_entry proc_root;
+
+static int __init mipsdha_proc_init(void)
+{
+	mipsdha_proc_entry = create_proc_entry("mipsdha", S_IWUSR | S_IRUGO, &proc_root);
+	if (mipsdha_proc_entry == NULL) {
+		printk("MIPSDHA: register /proc/mipsdha failed!\n");
+		return 0;
+	}
+	
+	mipsdha_proc_entry->owner = THIS_MODULE;
+	mipsdha_proc_entry->proc_fops = &mipsdha_fops;
+
+	cmd=CMD_ERR;
+	return 0;
+}
+
+static ssize_t mipsdha_proc_write (struct file *file, const char *buf, size_t len, loff_t *ppos)
+{
+	char cmd_gib[]="GET IO BASE";
+	char cmd_gpi[]="GET PCI INFO";
+
+	if (len >= INFO_SIZE) return -ENOMEM;
+
+	if (copy_from_user(info_buf, buf, len)) return -EFAULT;
+	info_buf[len] = '\0';
+
+	if (strncmp(info_buf, cmd_gib, sizeof(cmd_gib)-1)==0) {
+		cmd = CMD_GIB;
+		return len;
+	} else if (strncmp(info_buf, cmd_gpi, sizeof(cmd_gpi)-1)==0) {
+		cmd = CMD_GPI;
+		return len;
+	} else {
+		return -EINVAL;
+	}
+}
+
+static ssize_t mipsdha_proc_read (struct file *file, char *buf, size_t len, loff_t *ppos)
+{
+	int info_cnt;
+	pciinfo_t *pciinfo;
+	struct pci_dev *dev = NULL;
+
+	switch (cmd) {
+		default:
+			printk("MIPSDHA: BUG found in function %s!(cmd=%d)\n", 
+					__FUNCTION__, cmd);
+			return -EINVAL;
+
+
+		case CMD_ERR:
+			return -EINVAL;
+
+
+		case CMD_GIB:
+			*(unsigned long *)info_buf = 
+				virt_to_phys((void *) mips_io_port_base);
+			info_cnt=sizeof(unsigned long);
+			break;
+
+
+		case CMD_GPI:
+			pciinfo = (pciinfo_t *) info_buf;
+			info_cnt = 0;
+			for_each_pci_dev(dev) {
+
+				if (info_cnt+sizeof(pciinfo_t)>INFO_SIZE) return -ENOMEM;
+
+				pciinfo->bus = dev->bus->number;
+				pciinfo->card = PCI_SLOT(dev->devfn);
+				pciinfo->func = PCI_FUNC(dev->devfn);
+
+				if (pci_read_config_word(dev, PCI_COMMAND, &pciinfo->command)
+						!= PCIBIOS_SUCCESSFUL) {
+					printk("MIPSDHA: BUG found in function %s!\n", 
+							__FUNCTION__);
+					pciinfo->command=0;
+				}
+
+				pciinfo->vendor = dev->vendor;
+				pciinfo->device = dev->device;
+
+				pciinfo->base0 = (dev->resource[0]).start;
+				pciinfo->base1 = (dev->resource[1]).start;
+				pciinfo->base2 = (dev->resource[2]).start;
+				pciinfo->baserom = (dev->resource[PCI_ROM_RESOURCE]).start;
+
+				pciinfo++;
+				info_cnt += sizeof(pciinfo_t);
+			}
+			break;
+	}
+
+	if (len < info_cnt) return -ENOMEM;
+	if (copy_to_user(buf, info_buf, info_cnt)) return -EFAULT;
+
+	return info_cnt;
+}
+
+__initcall(mipsdha_proc_init);
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/pci.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/pci.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/pci.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/pci.c	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,88 @@
+/*
+ * pci.c
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+extern struct pci_ops loongson2f_pci_pci_ops;
+/* if you want to expand the pci memory space, you should config 64bits kernel too. */
+
+static struct resource loongson2f_pci_mem_resource = {
+	.name   = "LOONGSON2E PCI MEM",
+	.start  = 0x14000000UL,
+	.end    = 0x1fffffffUL,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct resource loongson2f_pci_io_resource = {
+	.name   = "LOONGSON2E PCI IO MEM",
+	.start  = 0x00004000UL,
+	.end    = 0x0000ffffUL,
+	.flags  = IORESOURCE_IO,
+};
+
+
+static struct pci_controller  loongson2f_pci_controller = {
+	.pci_ops        = &loongson2f_pci_pci_ops,
+	.io_resource    = &loongson2f_pci_io_resource,
+	.mem_resource   = &loongson2f_pci_mem_resource,
+	.mem_offset     = 0x00000000UL,
+	.io_offset      = 0x00000000UL,
+};
+
+static int __init pcibios_init(void)
+{
+	extern int pci_probe_only;
+	pci_probe_only = 0;
+
+#ifdef CONFIG_TRACE_BOOT
+	printk(KERN_INFO"arch_initcall:pcibios_init\n");
+	printk(KERN_INFO"register_pci_controller : %x\n",&loongson2f_pci_controller);
+#endif
+	
+#ifdef	CONFIG_64BIT
+	loongson2f_pci_mem_resource.start	= 0x50000000UL; 
+	loongson2f_pci_mem_resource.end		= 0x7fffffffUL;
+	__asm__(".set mips3\n"
+	            "dli $2,0x900000003ff00000\n"
+				"li $3,0x40000000\n"
+				"sd $3,0x18($2)\n"
+				"or $3,1\n"
+				"sd $3,0x58($2)\n"
+				"dli $3,0xffffffffc0000000\n"
+				"sd $3,0x38($2)\n"
+				".set mips0\n"
+				:::"$2","$3","memory"
+			   );
+#endif
+	register_pci_controller(&loongson2f_pci_controller);
+	return 0;
+}
+
+arch_initcall(pcibios_init);
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/pcireg.h linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/pcireg.h
--- linux-2.6.27.6/arch/mips/lemote/lm2f/pcireg.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/pcireg.h	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,503 @@
+/*	$OpenBSD: pcireg.h,v 1.17 2001/05/08 19:47:43 mickey Exp $	*/
+/*	$NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1995, 1996 Christopher G. Demetriou.  All rights reserved.
+ * Copyright (c) 1994, 1996 Charles Hannum.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Charles Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_PCIREG_H_
+#define	_DEV_PCI_PCIREG_H_
+
+
+/*
+ * Standardized PCI configuration information
+ *
+ * XXX This is not complete.
+ */
+
+/*
+ * Device identification register; contains a vendor ID and a device ID.
+ */
+#define	PCI_ID_REG			0x00
+
+typedef u_int16_t pci_vendor_id_t;
+typedef u_int16_t pci_product_id_t;
+
+#define	PCI_VENDOR_SHIFT			0
+#define	PCI_VENDOR_MASK				0xffff
+#define	PCI_VENDOR(id) \
+	    (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
+
+#define	PCI_PRODUCT_SHIFT			16
+#define	PCI_PRODUCT_MASK			0xffff
+#define	PCI_PRODUCT(id) \
+	    (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
+
+/*
+ * Command and status register.
+ */
+#define	PCI_COMMAND_STATUS_REG			0x04
+
+#define	PCI_COMMAND_IO_ENABLE			0x00000001
+#define	PCI_COMMAND_MEM_ENABLE			0x00000002
+#define	PCI_COMMAND_MASTER_ENABLE		0x00000004
+#define	PCI_COMMAND_SPECIAL_ENABLE		0x00000008
+#define	PCI_COMMAND_INVALIDATE_ENABLE		0x00000010
+#define	PCI_COMMAND_PALETTE_ENABLE		0x00000020
+#define	PCI_COMMAND_PARITY_ENABLE		0x00000040
+#define	PCI_COMMAND_STEPPING_ENABLE		0x00000080
+#define	PCI_COMMAND_SERR_ENABLE			0x00000100
+#define	PCI_COMMAND_BACKTOBACK_ENABLE		0x00000200
+
+#define	PCI_STATUS_CAPLIST_SUPPORT		0x00100000
+#define	PCI_STATUS_66MHZ_SUPPORT		0x00200000
+#define	PCI_STATUS_UDF_SUPPORT			0x00400000
+#define	PCI_STATUS_BACKTOBACK_SUPPORT		0x00800000
+#define	PCI_STATUS_PARITY_ERROR			0x01000000
+#define	PCI_STATUS_DEVSEL_FAST			0x00000000
+#define	PCI_STATUS_DEVSEL_MEDIUM		0x02000000
+#define	PCI_STATUS_DEVSEL_SLOW			0x04000000
+#define	PCI_STATUS_DEVSEL_MASK			0x06000000
+#define	PCI_STATUS_TARGET_TARGET_ABORT		0x08000000
+#define	PCI_STATUS_MASTER_TARGET_ABORT		0x10000000
+#define	PCI_STATUS_MASTER_ABORT			0x20000000
+#define	PCI_STATUS_SPECIAL_ERROR		0x40000000
+#define	PCI_STATUS_PARITY_DETECT		0x80000000
+
+/*
+ * PCI Class and Revision Register; defines type and revision of device.
+ */
+#define	PCI_CLASS_REG			0x08
+
+typedef u_int8_t pci_class_t;
+typedef u_int8_t pci_subclass_t;
+typedef u_int8_t pci_interface_t;
+typedef u_int8_t pci_revision_t;
+
+#define	PCI_CLASS_SHIFT				24
+#define	PCI_CLASS_MASK				0xff
+#define	PCI_CLASS(cr) \
+	    (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
+
+#define	PCI_SUBCLASS_SHIFT			16
+#define	PCI_SUBCLASS_MASK			0xff
+#define	PCI_SUBCLASS(cr) \
+	    (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
+
+#define PCI_ISCLASS(what, class, subclass) \
+	(((what) & 0xffff0000) == (class << 24 | subclass << 16))
+
+#define	PCI_INTERFACE_SHIFT			8
+#define	PCI_INTERFACE_MASK			0xff
+#define	PCI_INTERFACE(cr) \
+	    (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
+
+#define	PCI_REVISION_SHIFT			0
+#define	PCI_REVISION_MASK			0xff
+#define	PCI_REVISION(cr) \
+	    (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
+
+/* base classes */
+#define	PCI_CLASS_PREHISTORIC			0x00
+#define	PCI_CLASS_MASS_STORAGE			0x01
+#define	PCI_CLASS_NETWORK			0x02
+#define	PCI_CLASS_DISPLAY			0x03
+#define	PCI_CLASS_MULTIMEDIA			0x04
+#define	PCI_CLASS_MEMORY			0x05
+#define	PCI_CLASS_BRIDGE			0x06
+#define	PCI_CLASS_COMMUNICATIONS		0x07
+#define	PCI_CLASS_SYSTEM			0x08
+#define	PCI_CLASS_INPUT				0x09
+#define	PCI_CLASS_DOCK				0x0a
+#define	PCI_CLASS_PROCESSOR			0x0b
+#define	PCI_CLASS_SERIALBUS			0x0c
+#define	PCI_CLASS_WIRELESS			0x0d
+#define	PCI_CLASS_I2O				0x0e
+#define	PCI_CLASS_SATCOM			0x0f
+#define	PCI_CLASS_CRYPTO			0x10
+#define	PCI_CLASS_DASP				0x11
+#define	PCI_CLASS_UNDEFINED			0xff
+
+/* 0x00 prehistoric subclasses */
+#define	PCI_SUBCLASS_PREHISTORIC_MISC		0x00
+#define	PCI_SUBCLASS_PREHISTORIC_VGA		0x01
+
+/* 0x01 mass storage subclasses */
+#define	PCI_SUBCLASS_MASS_STORAGE_SCSI		0x00
+#define	PCI_SUBCLASS_MASS_STORAGE_IDE		0x01
+#define	PCI_SUBCLASS_MASS_STORAGE_FLOPPY	0x02
+#define	PCI_SUBCLASS_MASS_STORAGE_IPI		0x03
+#define	PCI_SUBCLASS_MASS_STORAGE_RAID		0x04
+#define	PCI_SUBCLASS_MASS_STORAGE_ATA		0x05
+#define	PCI_SUBCLASS_MASS_STORAGE_MISC		0x80
+
+/* 0x02 network subclasses */
+#define	PCI_SUBCLASS_NETWORK_ETHERNET		0x00
+#define	PCI_SUBCLASS_NETWORK_TOKENRING		0x01
+#define	PCI_SUBCLASS_NETWORK_FDDI		0x02
+#define	PCI_SUBCLASS_NETWORK_ATM		0x03
+#define	PCI_SUBCLASS_NETWORK_ISDN		0x04
+#define	PCI_SUBCLASS_NETWORK_WORLDFIP		0x05
+#define	PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP	0x06
+#define	PCI_SUBCLASS_NETWORK_MISC		0x80
+
+/* 0x03 display subclasses */
+#define	PCI_SUBCLASS_DISPLAY_VGA		0x00
+#define	PCI_SUBCLASS_DISPLAY_XGA		0x01
+#define	PCI_SUBCLASS_DISPLAY_3D			0x02
+#define	PCI_SUBCLASS_DISPLAY_MISC		0x80
+
+/* 0x04 multimedia subclasses */
+#define	PCI_SUBCLASS_MULTIMEDIA_VIDEO		0x00
+#define	PCI_SUBCLASS_MULTIMEDIA_AUDIO		0x01
+#define	PCI_SUBCLASS_MULTIMEDIA_TELEPHONY	0x02
+#define	PCI_SUBCLASS_MULTIMEDIA_MISC		0x80
+
+/* 0x05 memory subclasses */
+#define	PCI_SUBCLASS_MEMORY_RAM			0x00
+#define	PCI_SUBCLASS_MEMORY_FLASH		0x01
+#define	PCI_SUBCLASS_MEMORY_MISC		0x80
+
+/* 0x06 bridge subclasses */
+#define	PCI_SUBCLASS_BRIDGE_HOST		0x00
+#define	PCI_SUBCLASS_BRIDGE_ISA			0x01
+#define	PCI_SUBCLASS_BRIDGE_EISA		0x02
+#define	PCI_SUBCLASS_BRIDGE_MC			0x03
+#define	PCI_SUBCLASS_BRIDGE_PCI			0x04
+#define	PCI_SUBCLASS_BRIDGE_PCMCIA		0x05
+#define	PCI_SUBCLASS_BRIDGE_NUBUS		0x06
+#define	PCI_SUBCLASS_BRIDGE_CARDBUS		0x07
+#define	PCI_SUBCLASS_BRIDGE_RACEWAY		0x08
+#define	PCI_SUBCLASS_BRIDGE_STPCI		0x09
+#define	PCI_SUBCLASS_BRIDGE_INFINIBAND		0x0a
+#define	PCI_SUBCLASS_BRIDGE_MISC		0x80
+
+/* 0x07 communications subclasses */
+#define	PCI_SUBCLASS_COMMUNICATIONS_SERIAL	0x00
+#define	PCI_SUBCLASS_COMMUNICATIONS_PARALLEL	0x01
+#define	PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL	0x02
+#define	PCI_SUBCLASS_COMMUNICATIONS_MODEM	0x03
+#define	PCI_SUBCLASS_COMMUNICATIONS_MISC	0x80
+
+/* 0x08 system subclasses */
+#define	PCI_SUBCLASS_SYSTEM_PIC			0x00
+#define	PCI_SUBCLASS_SYSTEM_DMA			0x01
+#define	PCI_SUBCLASS_SYSTEM_TIMER		0x02
+#define	PCI_SUBCLASS_SYSTEM_RTC			0x03
+#define	PCI_SUBCLASS_SYSTEM_PCIHOTPLUG		0x04
+#define	PCI_SUBCLASS_SYSTEM_MISC		0x80
+
+/* 0x09 input subclasses */
+#define	PCI_SUBCLASS_INPUT_KEYBOARD		0x00
+#define	PCI_SUBCLASS_INPUT_DIGITIZER		0x01
+#define	PCI_SUBCLASS_INPUT_MOUSE		0x02
+#define	PCI_SUBCLASS_INPUT_SCANNER		0x03
+#define	PCI_SUBCLASS_INPUT_GAMEPORT		0x04
+#define	PCI_SUBCLASS_INPUT_MISC			0x80
+
+/* 0x0a dock subclasses */
+#define	PCI_SUBCLASS_DOCK_GENERIC		0x00
+#define	PCI_SUBCLASS_DOCK_MISC			0x80
+
+/* 0x0b processor subclasses */
+#define	PCI_SUBCLASS_PROCESSOR_386		0x00
+#define	PCI_SUBCLASS_PROCESSOR_486		0x01
+#define	PCI_SUBCLASS_PROCESSOR_PENTIUM		0x02
+#define	PCI_SUBCLASS_PROCESSOR_ALPHA		0x10
+#define	PCI_SUBCLASS_PROCESSOR_POWERPC		0x20
+#define	PCI_SUBCLASS_PROCESSOR_MIPS		0x30
+#define	PCI_SUBCLASS_PROCESSOR_COPROC		0x40
+
+/* 0x0c serial bus subclasses */
+#define	PCI_SUBCLASS_SERIALBUS_FIREWIRE		0x00
+#define	PCI_SUBCLASS_SERIALBUS_ACCESS		0x01
+#define	PCI_SUBCLASS_SERIALBUS_SSA		0x02
+#define	PCI_SUBCLASS_SERIALBUS_USB		0x03
+#define	PCI_SUBCLASS_SERIALBUS_FIBER		0x04
+#define	PCI_SUBCLASS_SERIALBUS_SMBUS		0x05
+#define	PCI_SUBCLASS_SERIALBUS_INFINIBAND	0x06
+#define	PCI_SUBCLASS_SERIALBUS_IPMI		0x07
+#define	PCI_SUBCLASS_SERIALBUS_SERCOS		0x08
+#define	PCI_SUBCLASS_SERIALBUS_CANBUS		0x09
+
+/* 0x0d wireless subclasses */
+#define	PCI_SUBCLASS_WIRELESS_IRDA		0x00
+#define	PCI_SUBCLASS_WIRELESS_CONSUMERIR	0x01
+#define	PCI_SUBCLASS_WIRELESS_RF		0x10
+#define	PCI_SUBCLASS_WIRELESS_MISC		0x80
+
+/* 0x0e I2O (Intelligent I/O) subclasses */
+#define	PCI_SUBCLASS_I2O_STANDARD		0x00
+
+/* 0x0f satellite communication subclasses */
+/*	PCI_SUBCLASS_SATCOM_???			0x00    / * XXX ??? */
+#define	PCI_SUBCLASS_SATCOM_TV			0x01
+#define	PCI_SUBCLASS_SATCOM_AUDIO		0x02
+#define	PCI_SUBCLASS_SATCOM_VOICE		0x03
+#define	PCI_SUBCLASS_SATCOM_DATA		0x04
+
+/* 0x10 encryption/decryption subclasses */
+#define	PCI_SUBCLASS_CRYPTO_NETCOMP		0x00
+#define	PCI_SUBCLASS_CRYPTO_ENTERTAINMENT	0x10
+#define	PCI_SUBCLASS_CRYPTO_MISC		0x80
+
+/* 0x11 data acquisition and signal processing subclasses */
+#define	PCI_SUBCLASS_DASP_DPIO			0x00
+#define	PCI_SUBCLASS_DASP_TIMEFREQ		0x01
+#define	PCI_SUBCLASS_DASP_MISC			0x80
+
+/*
+ * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
+ */
+#define	PCI_BHLC_REG			0x0c
+
+#define	PCI_BIST_SHIFT				24
+#define	PCI_BIST_MASK				0xff
+#define	PCI_BIST(bhlcr) \
+	    (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
+
+#define	PCI_HDRTYPE_SHIFT			16
+#define	PCI_HDRTYPE_MASK			0xff
+#define	PCI_HDRTYPE(bhlcr) \
+	    (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
+
+#define PCI_HDRTYPE_TYPE(bhlcr) \
+	    (PCI_HDRTYPE(bhlcr) & 0x7f)
+#define	PCI_HDRTYPE_MULTIFN(bhlcr) \
+	    ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
+
+#define	PCI_LATTIMER_SHIFT			8
+#define	PCI_LATTIMER_MASK			0xff
+#define	PCI_LATTIMER(bhlcr) \
+	    (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
+
+#define	PCI_CACHELINE_SHIFT			0
+#define	PCI_CACHELINE_MASK			0xff
+#define	PCI_CACHELINE(bhlcr) \
+	    (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
+
+/* config registers for header type 0 devices */
+
+#define PCI_MAPS	0x10
+#define PCI_CARDBUSCIS	0x28
+#define PCI_SUBVEND_0	0x2c
+#define PCI_SUBDEV_0	0x2e
+#define PCI_INTLINE	0x3c
+#define PCI_INTPIN	0x3d
+#define PCI_MINGNT	0x3e
+#define PCI_MAXLAT	0x3f
+
+/* config registers for header type 1 devices */
+
+#define PCI_SECSTAT_1	0 /**/
+
+#define PCI_PRIBUS_1	0x18
+#define PCI_SECBUS_1	0x19
+#define PCI_SUBBUS_1	0x1a
+#define PCI_SECLAT_1	0x1b
+
+#define PCI_IOBASEL_1	0x1c
+#define PCI_IOLIMITL_1	0x1d
+#define PCI_IOBASEH_1	0x30 /**/
+#define PCI_IOLIMITH_1	0x32 /**/ 
+
+#define PCI_MEMBASE_1	0x20
+#define PCI_MEMLIMIT_1	0x22
+
+#define PCI_PMBASEL_1	0x24
+#define PCI_PMLIMITL_1	0x26
+#define PCI_PMBASEH_1	0 /**/
+#define PCI_PMLIMITH_1	0 /**/
+
+#define PCI_BRIDGECTL_1 0 /**/
+
+#define PCI_SUBVEND_1	0x34
+#define PCI_SUBDEV_1	0x36
+
+/* config registers for header type 2 devices */
+
+#define PCI_SECSTAT_2	0x16
+
+#define PCI_PRIBUS_2	0x18
+#define PCI_SECBUS_2	0x19
+#define PCI_SUBBUS_2	0x1a
+#define PCI_SECLAT_2	0x1b
+
+#define PCI_MEMBASE0_2	0x1c
+#define PCI_MEMLIMIT0_2 0x20
+#define PCI_MEMBASE1_2	0x24
+#define PCI_MEMLIMIT1_2 0x28
+#define PCI_IOBASE0_2	0x2c
+#define PCI_IOLIMIT0_2	0x30
+#define PCI_IOBASE1_2	0x34
+#define PCI_IOLIMIT1_2	0x38
+
+#define PCI_BRIDGECTL_2 0x3e
+
+#define PCI_SUBVEND_2	0x40
+#define PCI_SUBDEV_2	0x42
+
+#define PCI_PCCARDIF_2	0x44
+
+/*
+ * Mapping registers
+ */
+#define	PCI_MAPREG_START		0x10
+#define	PCI_MAPREG_END			0x28
+#define	PCI_MAPREG_ROM			0x30
+#define	PCI_MAPREG_PPB_END		0x18
+#define	PCI_MAPREG_PCB_END		0x14
+
+#define	PCI_MAPREG_TYPE(mr)						\
+	    ((mr) & PCI_MAPREG_TYPE_MASK)
+#define	PCI_MAPREG_TYPE_MASK			0x00000001
+
+#define	PCI_MAPREG_TYPE_MEM			0x00000000
+#define	PCI_MAPREG_TYPE_IO			0x00000001
+#define	PCI_MAPREG_TYPE_ROM			0x00000001
+
+#define	PCI_MAPREG_MEM_TYPE(mr)						\
+	    ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
+#define	PCI_MAPREG_MEM_TYPE_MASK		0x00000006
+
+#define	PCI_MAPREG_MEM_TYPE_32BIT		0x00000000
+#define	PCI_MAPREG_MEM_TYPE_32BIT_1M		0x00000002
+#define	PCI_MAPREG_MEM_TYPE_64BIT		0x00000004
+
+#define	PCI_MAPREG_MEM_CACHEABLE(mr)					\
+	    (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0)
+#define	PCI_MAPREG_MEM_CACHEABLE_MASK		0x00000008
+
+#define	PCI_MAPREG_MEM_PREFETCHABLE(mr)					\
+	    (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
+#define	PCI_MAPREG_MEM_PREFETCHABLE_MASK	0x00000008
+
+#define	PCI_MAPREG_MEM_ADDR(mr)						\
+	    ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
+#define	PCI_MAPREG_MEM_SIZE(mr)						\
+	    (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
+#define	PCI_MAPREG_MEM_ADDR_MASK		0xfffffff0
+
+#define	PCI_MAPREG_MEM64_ADDR(mr)					\
+	    ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
+#define	PCI_MAPREG_MEM64_SIZE(mr)					\
+	    (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
+#define	PCI_MAPREG_MEM64_ADDR_MASK		0xfffffffffffffff0
+
+#define	PCI_MAPREG_IO_ADDR(mr)						\
+	    ((mr) & PCI_MAPREG_IO_ADDR_MASK)
+#define	PCI_MAPREG_IO_SIZE(mr)						\
+	    (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
+#define	PCI_MAPREG_IO_ADDR_MASK			0xfffffffe
+
+#define	PCI_MAPREG_ROM_ADDR(mr)						\
+	    ((mr) & PCI_MAPREG_ROM_ADDR_MASK)
+#define	PCI_MAPREG_ROM_SIZE(mr)						\
+	    (PCI_MAPREG_ROM_ADDR(mr) & -PCI_MAPREG_ROM_ADDR(mr))
+#define	PCI_MAPREG_ROM_ADDR_MASK		0xfffff800
+
+/*
+ * Cardbus CIS pointer (PCI rev. 2.1)
+ */
+#define PCI_CARDBUS_CIS_REG 0x28
+
+/*
+ * Subsystem identification register; contains a vendor ID and a device ID.
+ * Types/macros for PCI_ID_REG apply.
+ * (PCI rev. 2.1)
+ */
+#define PCI_SUBSYS_ID_REG 0x2c
+
+/*
+ * capabilities link list (PCI rev. 2.2)
+ */
+#define PCI_CAPLISTPTR_REG		0x34
+#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
+#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
+#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
+
+#define PCI_CAP_REESSERVED	0x00
+#define PCI_CAP_PWRMGMT		0x01
+#define PCI_CAP_AGP		0x02
+#define PCI_CAP_VPD		0x03
+#define PCI_CAP_SLOTID		0x04
+#define PCI_CAP_MBI		0x05
+#define PCI_CAP_CPCI_HOTSWAP	0x06
+#define PCI_CAP_PCIX		0x07
+#define PCI_CAP_LDT		0x08
+#define PCI_CAP_VENDSPEC	0x09
+#define PCI_CAP_DEBUGPORT	0x0a
+#define PCI_CAP_CPCI_RSRCCTL	0x0b
+#define PCI_CAP_HOTPLUG		0x0c
+
+/*
+ * Power Management Control Status Register; access via capability pointer.
+ */
+#define PCI_PMCSR_STATE_MASK	0x03
+#define PCI_PMCSR_STATE_D0	0x00
+#define PCI_PMCSR_STATE_D1	0x01
+#define PCI_PMCSR_STATE_D2	0x02
+#define PCI_PMCSR_STATE_D3	0x03
+
+/*
+ * Interrupt Configuration Register; contains interrupt pin and line.
+ */
+#define	PCI_INTERRUPT_REG		0x3c
+
+typedef u_int8_t pci_intr_pin_t;
+typedef u_int8_t pci_intr_line_t;
+
+#define	PCI_INTERRUPT_PIN_SHIFT			8
+#define	PCI_INTERRUPT_PIN_MASK			0xff
+#define	PCI_INTERRUPT_PIN(icr) \
+	    (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
+
+#define	PCI_INTERRUPT_LINE_SHIFT		0
+#define	PCI_INTERRUPT_LINE_MASK			0xff
+#define	PCI_INTERRUPT_LINE(icr) \
+	    (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
+
+#define	PCI_MIN_GNT_SHIFT			16
+#define	PCI_MIN_GNT_MASK			0xff
+#define	PCI_MIN_GNT(icr) \
+	    (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
+
+#define	PCI_MAX_LAT_SHIFT			24
+#define	PCI_MAX_LAT_MASK			0xff
+#define	PCI_MAX_LAT(icr) \
+	    (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
+
+#define	PCI_INTERRUPT_PIN_NONE			0x00
+#define	PCI_INTERRUPT_PIN_A			0x01
+#define	PCI_INTERRUPT_PIN_B			0x02
+#define	PCI_INTERRUPT_PIN_C			0x03
+#define	PCI_INTERRUPT_PIN_D			0x04
+#define	PCI_INTERRUPT_PIN_MAX			0x04
+
+#endif /* _DEV_PCI_PCIREG_H_ */
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/prom.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/prom.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/prom.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/prom.c	2011-05-08 18:02:19.000000000 +0800
@@ -0,0 +1,110 @@
+/*
+ * Based on Ocelot Linux port, which is
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * Copyright 2003 ICT CAS
+ * Author: Michael Guo <guoyi@ict.ac.cn>
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+
+extern unsigned long bus_clock;
+extern unsigned long cpu_clock_freq;
+extern unsigned int memsize, highmemsize;
+extern int putDebugChar(unsigned char byte);
+
+static int argc;
+/* pmon passes arguments in 32bit pointers */
+static int *arg;
+static int *env;
+
+const char *get_system_type(void)
+{
+	return "lemote-fulong";
+}
+
+void __init prom_init_cmdline(void)
+{
+	int i;
+	long l;
+
+	/* arg[0] is "g", the rest is boot parameters */
+	arcs_cmdline[0] = '\0';
+	for (i = 1; i < argc; i++) {
+		l = (long)arg[i];
+		if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
+		    >= sizeof(arcs_cmdline))
+			break;
+		strcat(arcs_cmdline, ((char *)l));
+		strcat(arcs_cmdline, " ");
+	}
+}
+
+void __init prom_init(void)
+{
+	long l;
+	argc = fw_arg0;
+	arg = (int *)fw_arg1;
+	env = (int *)fw_arg2;
+
+	prom_init_cmdline();
+
+	if ((strstr(arcs_cmdline, "console=")) == NULL)
+		strcat(arcs_cmdline, " console=ttyS0,115200");
+	if ((strstr(arcs_cmdline, "root=")) == NULL)
+		strcat(arcs_cmdline, " root=/dev/hda1");
+	if ((strstr(arcs_cmdline, "ide_core.ignore_cable=")) == NULL)
+		strcat(arcs_cmdline, " ide_core.ignore_cable=0");
+	if ((strstr(arcs_cmdline, "uca=")) == NULL)
+		strcat(arcs_cmdline, " uca=0x50000000,0x1000000");
+
+	l = (long)*env;
+	while (l != 0) {
+		if (strncmp("busclock", (char *)l, strlen("busclock")) == 0) {
+			bus_clock = simple_strtol((char *)l + strlen("busclock="),
+					NULL, 10);
+		}
+		if (strncmp("cpuclock", (char *)l, strlen("cpuclock")) == 0) {
+			cpu_clock_freq = simple_strtol((char *)l + strlen("cpuclock="),
+					NULL, 10);
+		}
+		if (strncmp("memsize", (char *)l, strlen("memsize")) == 0) {
+			memsize = simple_strtol((char *)l + strlen("memsize="),
+						NULL, 10);
+		}
+		if (strncmp("highmemsize", (char *)l, strlen("highmemsize")) == 0) {
+			highmemsize = simple_strtol((char *)l + strlen("highmemsize="),
+					  NULL, 10);
+		}
+		env++;
+		l = (long)*env;
+	}
+	if (memsize == 0)
+		memsize = 256;
+
+	printk("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n",
+	       bus_clock, cpu_clock_freq, memsize, highmemsize);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void prom_putchar(char c)
+{
+	putDebugChar(c);
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/reset.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/reset.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/reset.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/reset.c	2011-10-28 16:28:21.000000000 +0800
@@ -0,0 +1,145 @@
+/*
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ */
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/pm.h>
+#include <linux/delay.h>
+extern void _wrmsr(u32 reg, u32 hi, u32 lo);
+extern void _rdmsr(u32 reg, u32 *hi, u32 *lo);
+void prom_printf(char *fmt, ...);
+static void loongson2e_restart(char *command)
+{
+#ifdef CONFIG_LEMOTE_FULONG2F
+	*(volatile unsigned long *)0xffffffffbfe00120 &= ~(1 << 3);
+	*(volatile unsigned long *)0xffffffffbfe0011c &= ~(1 << 3);
+/*	u32 hi, lo;
+	_rdmsr(0xe0000014, &hi, &lo);
+	lo |= 0x00000001;
+	_wrmsr(0xe0000014, hi, lo);*/
+#else
+
+#ifdef CONFIG_32BIT
+	*(unsigned long *)0xbfe00120 &= ~(1 << 3);
+	*(unsigned long *)0xbfe0011c &= ~(1 << 3);
+#else
+	*(volatile unsigned long *)0xffffffffbfe00120 &= ~(1 << 3);
+	*(volatile unsigned long *)0xffffffffbfe0011c &= ~(1 << 3);
+#endif
+#endif
+	printk("Hard reset not take effect!!\n");
+	__asm__ __volatile__ (
+					".long 0x3c02bfc0\n"
+					".long 0x00400008\n"
+					:::"v0"
+					);
+}
+
+void sm501_date_gpio(unsigned int gpio, unsigned char mode); 
+void sm501_dir_gpio(unsigned int gpio, unsigned char mode); 
+
+static void delay(void)
+{
+	volatile int i;
+	for (i=0; i<0x10000; i++);
+}
+static void loongson2e_halt(void)
+{
+	int i,j; //add by zhao
+
+#if 0
+	volatile int *gpio_date = 0xffffffffb6010004;
+	volatile int *gpio_dir = 0xffffffffb601000c;
+	int tmp;
+	prom_printf("-----test\n");
+	tmp = *gpio_dir;
+	prom_printf("--1---tmpdir:%08x\n",tmp);
+	*gpio_dir = tmp|1<<22;
+	prom_printf("--2---tmpdir:%08x\n",*gpio_dir);
+	tmp = *gpio_date;
+	prom_printf("--3---tmpdir:%08x\n",tmp);
+	*gpio_date = tmp& ~(1<<22);
+	prom_printf("--4---tmpdir:%08x\n",*gpio_date);
+#endif
+
+   sm501_dir_gpio(1,1);
+   sm501_date_gpio(1,0);
+
+/*****************add by zhao*************************/
+	for(i = 0; i < 1000; i++)
+	{
+	for(j = 0; j < 1000; j++)
+			;
+	}
+	delay();
+  sm501_date_gpio(1,1);
+/*****************************************************/
+  //sm501_dir_gpio(54,1);
+//sm501_date_gpio(54,0);
+#if 0
+#ifdef CONFIG_LEMOTE_FULONG2F
+#ifdef CONFIG_32BIT
+	u32 base;
+#else
+	u64 base;
+#endif
+	u32 hi, lo, val;
+	
+	_rdmsr(0x8000000c, &hi, &lo);
+#ifdef CONFIG_32BIT
+	base = (lo & 0xff00) | 0xbfd00000;
+#else
+	base = (lo & 0xff00) | 0xffffffffbfd00000ULL;
+#endif
+	val = *(volatile unsigned int *)(base + 0x04);
+	val = (val & ~(1 << (16 + 13))) | (1 << 13);
+	delay();
+	*(__volatile__ u32 *)(base + 0x04) = val;
+	delay();
+	val = (val & ~(1 << (13))) | (1 << (16 + 13));
+	delay();
+	*(__volatile__ u32 *)(base + 0x00) = val;
+	delay();
+#else
+#ifdef CONFIG_32BIT
+	*(unsigned short*)0xbfd0b000 = 0x8100;
+	delay();
+	*(unsigned short *)0xbfd0b004 = 0x2800;
+	delay();
+	*(unsigned int *)0xbfe00148 = 0x120002;
+#else
+	*(unsigned short *)0xffffffffbfd0b000 = 0x8100;
+	delay();
+	*(unsigned short *)0xffffffffbfd0b004 = 0x2800;
+	delay();
+	*(unsigned int *)0xffffffffbfe00148 = 0x120002;
+#endif
+#endif
+#endif
+
+}
+
+static void loongson2e_power_off(void)
+{
+	loongson2e_halt();
+}
+
+void mips_reboot_setup(void)
+{
+	_machine_restart = loongson2e_restart;
+	_machine_halt = loongson2e_halt;
+	pm_power_off = loongson2e_power_off;
+}
diff -uNra linux-2.6.27.6/arch/mips/lemote/lm2f/setup.c linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/setup.c
--- linux-2.6.27.6/arch/mips/lemote/lm2f/setup.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/lemote/lm2f/setup.c	2011-05-08 18:02:18.000000000 +0800
@@ -0,0 +1,126 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * setup.c - board dependent boot routines
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/bootmem.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mc146818-time.h>
+#include <asm/time.h>
+#include <asm/wbflush.h>
+
+#ifdef CONFIG_VT
+#include <linux/console.h>
+#include <linux/screen_info.h>
+#endif
+
+extern void mips_reboot_setup(void);
+
+#ifdef CONFIG_64BIT
+#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
+#else
+#define PTR_PAD(p) (p)
+#endif
+
+unsigned long cpu_clock_freq;
+unsigned long bus_clock;
+unsigned int memsize;
+unsigned int highmemsize = 0;
+
+void __init plat_time_init(void)
+{
+	/* setup mips r4k timer */
+	mips_hpt_frequency = cpu_clock_freq / 2;
+}
+
+unsigned long read_persistent_clock(void)
+{
+	return mc146818_get_cmos_time();
+}
+
+void (*__wbflush)(void);
+EXPORT_SYMBOL(__wbflush);
+
+static void wbflush_loongson2f(void)
+{
+	asm(".set\tpush\n\t"
+	    ".set\tnoreorder\n\t"
+	    ".set mips3\n\t"
+	    "sync\n\t"
+	    "nop\n\t"
+	    ".set\tpop\n\t"
+	    ".set mips0\n\t");
+}
+
+void __init plat_mem_setup(void)
+{
+	set_io_port_base(PTR_PAD(0xbfd00000));
+
+	mips_reboot_setup();
+
+	__wbflush = wbflush_loongson2f;
+
+	add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+#ifdef CONFIG_64BIT
+	__asm__(
+		".set mips3\n"			
+		"dli $2, 0x900000003ff00000\n"
+		"dli $3, 0x0000000080000000\n"
+		"sd  $3, 0x10($2)\n"
+		"sd  $0, 0x50($2)\n"
+		"dli $3, 0xffffffff80000000\n"
+		"sd  $3, 0x30($2)\n"
+		".set mips0\n"
+		:::"$2","$3","memory");
+	if (highmemsize > 0) {
+		add_memory_region(0x90000000, highmemsize << 20, BOOT_MEM_RAM);
+	}
+#endif
+
+#ifdef CONFIG_VT
+#if defined(CONFIG_VGA_CONSOLE)
+	conswitchp = &vga_con;
+
+	screen_info = (struct screen_info) {
+		0, 25,		/* orig-x, orig-y */
+		    0,		/* unused */
+		    0,		/* orig-video-page */
+		    0,		/* orig-video-mode */
+		    80,		/* orig-video-cols */
+		    0, 0, 0,	/* ega_ax, ega_bx, ega_cx */
+		    25,		/* orig-video-lines */
+		    VIDEO_TYPE_VGAC,	/* orig-video-isVGA */
+		    16		/* orig-video-points */
+	};
+#elif defined(CONFIG_DUMMY_CONSOLE)
+	conswitchp = &dummy_con;
+#endif
+#endif
+
+}
diff -uNra linux-2.6.27.6/arch/mips/Makefile linux-2.6.27.6.yaffs/arch/mips/Makefile
--- linux-2.6.27.6/arch/mips/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/Makefile	2011-05-16 21:44:13.000000000 +0800
@@ -68,6 +68,7 @@
 
 all-$(CONFIG_BOOT_ELF32)	:= $(vmlinux-32)
 all-$(CONFIG_BOOT_ELF64)	:= $(vmlinux-64)
+all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
 
 #
 # GCC uses -G 0 -mabicalls -fpic as default.  We don't want PIC in the kernel
@@ -119,7 +120,9 @@
 cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2)	+= -Wa,--trap
+cflags-$(CONFIG_LEMOTE_FULONG) += -march=loongson2e -fprefetch-loop-arrays
+cflags-$(CONFIG_LEMOTE_FULONG2F) += -march=loongson2f -fprefetch-loop-arrays
 cflags-$(CONFIG_CPU_MIPS32_R1)	+= $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
 			-Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)	+= $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -304,6 +307,14 @@
 load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000
 cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote
 
+# lemote loongson2f fulong mini-PC board
+#
+core-$(CONFIG_LEMOTE_FULONG2F) +=arch/mips/lemote/lm2f/
+load-$(CONFIG_LEMOTE_FULONG2F) +=0xffffffff80200000
+cflags-$(CONFIG_LEMOTE_FULONG2F) += -Iinclude/asm-mips/mach-lemote
+#
+
+
 #
 # MIPS Malta board
 #
@@ -685,6 +696,12 @@
 CLEAN_FILES += vmlinux.ecoff \
 	       vmlinux.srec
 
+# boot/compressed
+vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
+	$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
+	    VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
+
+
 archprepare:
 ifdef CONFIG_MIPS32_N32
 	@echo '  Checking missing-syscalls for N32'
@@ -697,6 +714,7 @@
 
 archclean:
 	@$(MAKE) $(clean)=arch/mips/boot
+	@$(MAKE) $(clean)=arch/mips/boot/compressed
 	@$(MAKE) $(clean)=arch/mips/lasat
 
 define archhelp
diff -uNra linux-2.6.27.6/arch/mips/mm/dma-default.c linux-2.6.27.6.yaffs/arch/mips/mm/dma-default.c
--- linux-2.6.27.6/arch/mips/mm/dma-default.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/mm/dma-default.c	2011-05-08 18:02:22.000000000 +0800
@@ -40,6 +40,12 @@
 	       current_cpu_type() == CPU_R12000);
 }
 
+static inline int cpu_is_noncoherent_loongson(struct device *dev)
+{
+	return !plat_device_is_coherent(dev) &&
+			(current_cpu_data.cputype == CPU_LOONGSON2);
+}
+
 static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
 {
 	/* ignore region specifiers */
@@ -166,7 +172,7 @@
 void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 	enum dma_data_direction direction)
 {
-	if (cpu_is_noncoherent_r10000(dev))
+	if (cpu_is_noncoherent_r10000(dev) || cpu_is_noncoherent_loongson(dev))
 		__dma_sync(dma_addr_to_virt(dma_addr), size,
 		           direction);
 
@@ -257,7 +263,7 @@
 {
 	BUG_ON(direction == DMA_NONE);
 
-	if (cpu_is_noncoherent_r10000(dev)) {
+	if (cpu_is_noncoherent_r10000(dev) || cpu_is_noncoherent_loongson(dev)) {
 		unsigned long addr;
 
 		addr = dma_addr_to_virt(dma_handle);
diff -uNra linux-2.6.27.6/arch/mips/oprofile/common.c linux-2.6.27.6.yaffs/arch/mips/oprofile/common.c
--- linux-2.6.27.6/arch/mips/oprofile/common.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/oprofile/common.c	2011-05-19 16:21:40.000000000 +0800
@@ -16,6 +16,7 @@
 
 extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak));
 extern struct op_mips_model op_model_rm9000_ops __attribute__((weak));
+extern struct op_mips_model op_model_loongson2_ops __attribute__((weak));
 
 static struct op_mips_model *model;
 
@@ -93,6 +94,11 @@
 	case CPU_RM9000:
 		lmodel = &op_model_rm9000_ops;
 		break;
+	case CPU_LOONGSON2:
+		lmodel = &op_model_loongson2_ops;
+		break;
+
+
 	};
 
 	if (!lmodel)
diff -uNra linux-2.6.27.6/arch/mips/oprofile/loongson.h linux-2.6.27.6.yaffs/arch/mips/oprofile/loongson.h
--- linux-2.6.27.6/arch/mips/oprofile/loongson.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/oprofile/loongson.h	2011-05-27 16:29:13.000000000 +0800
@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
+#define __ASM_MACH_LOONGSON_LOONGSON_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+
+/* loongson internal northbridge initialization */
+extern void bonito_irq_init(void);
+
+/* machine-specific reboot/halt operation */
+extern void mach_prepare_reboot(void);
+extern void mach_prepare_shutdown(void);
+
+/* environment arguments from bootloader */
+extern unsigned long cpu_clock_freq;
+extern unsigned long memsize, highmemsize;
+
+/* loongson-specific command line, env and memory initialization */
+extern void __init prom_init_memory(void);
+extern void __init prom_init_cmdline(void);
+extern void __init prom_init_machtype(void);
+extern void __init prom_init_env(void);
+#ifdef CONFIG_LOONGSON_UART_BASE
+extern unsigned long _loongson_uart_base, loongson_uart_base;
+extern void prom_init_loongson_uart_base(void);
+#endif
+
+static inline void prom_init_uart_base(void)
+{
+#ifdef CONFIG_LOONGSON_UART_BASE
+	prom_init_loongson_uart_base();
+#endif
+}
+
+/* irq operation functions */
+extern void bonito_irqdispatch(void);
+extern void __init bonito_irq_init(void);
+extern void __init mach_init_irq(void);
+extern void mach_irq_dispatch(unsigned int pending);
+extern int mach_i8259_irq(void);
+
+/* We need this in some places... */
+#define delay()	({		\
+	int x;				\
+	for (x = 0; x < 100000; x++)	\
+		__asm__ __volatile__(""); \
+})
+
+#define LOONGSON_REG(x) \
+	(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON_IRQ_BASE	32
+#define LOONGSON2_PERFCNT_IRQ	(MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
+
+#include <linux/interrupt.h>
+static inline void do_perfcnt_IRQ(void)
+{
+#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
+	do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+}
+
+#define LOONGSON_FLASH_BASE	0x1c000000
+#define LOONGSON_FLASH_SIZE	0x02000000	/* 32M */
+#define LOONGSON_FLASH_TOP	(LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
+
+#define LOONGSON_LIO0_BASE	0x1e000000
+#define LOONGSON_LIO0_SIZE	0x01C00000	/* 28M */
+#define LOONGSON_LIO0_TOP	(LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
+
+#define LOONGSON_BOOT_BASE	0x1fc00000
+#define LOONGSON_BOOT_SIZE	0x00100000	/* 1M */
+#define LOONGSON_BOOT_TOP 	(LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
+#define LOONGSON_REG_BASE 	0x1fe00000
+#define LOONGSON_REG_SIZE 	0x00100000	/* 256Bytes + 256Bytes + ??? */
+#define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+
+#define LOONGSON_LIO1_BASE 	0x1ff00000
+#define LOONGSON_LIO1_SIZE 	0x00100000	/* 1M */
+#define LOONGSON_LIO1_TOP	(LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
+
+#define LOONGSON_PCILO0_BASE	0x10000000
+#define LOONGSON_PCILO1_BASE	0x14000000
+#define LOONGSON_PCILO2_BASE	0x18000000
+#define LOONGSON_PCILO_BASE	LOONGSON_PCILO0_BASE
+#define LOONGSON_PCILO_SIZE	0x0c000000	/* 64M * 3 */
+#define LOONGSON_PCILO_TOP	(LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
+
+#define LOONGSON_PCICFG_BASE	0x1fe80000
+#define LOONGSON_PCICFG_SIZE	0x00000800	/* 2K */
+#define LOONGSON_PCICFG_TOP	(LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
+#ifdef CONFIG_HT_PCI
+#define LOONGSON_PCIIO_BASE	0xefdfc000000
+#else
+#define LOONGSON_PCIIO_BASE	0x1fd00000
+#endif
+#define LOONGSON_PCIIO_SIZE	0x00100000	/* 1M */
+#define LOONGSON_PCIIO_TOP	(LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+
+/* Loongson3A HT Address cww */
+
+#define LOONGSON_HTIO_BASE	0x90000efdfc000000
+#define LOONGSON_HTIO_SIZE	0x00100000	/* 1M */
+
+/* Loongson3A UART Base cww */
+
+#ifdef CONFIG_CPU_UART
+#define LOONGSON_UART_BASE	0x1fe001e0	/* CPU UART */
+#else 
+#define LOONGSON_UART_BASE	0x1ff003f8	/* CPU LPC UART */
+#endif
+
+/* Loongson Register Bases */
+
+#define LOONGSON_PCICONFIGBASE	0x00
+#define LOONGSON_REGBASE	0x100
+
+/* PCI Configuration Registers */
+
+#define LOONGSON_PCI_REG(x)	LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
+#define LOONGSON_PCIDID		LOONGSON_PCI_REG(0x00)
+#define LOONGSON_PCICMD		LOONGSON_PCI_REG(0x04)
+#define LOONGSON_PCICLASS 	LOONGSON_PCI_REG(0x08)
+#define LOONGSON_PCILTIMER	LOONGSON_PCI_REG(0x0c)
+#define LOONGSON_PCIBASE0 	LOONGSON_PCI_REG(0x10)
+#define LOONGSON_PCIBASE1 	LOONGSON_PCI_REG(0x14)
+#define LOONGSON_PCIBASE2 	LOONGSON_PCI_REG(0x18)
+#define LOONGSON_PCIBASE3 	LOONGSON_PCI_REG(0x1c)
+#define LOONGSON_PCIBASE4 	LOONGSON_PCI_REG(0x20)
+#define LOONGSON_PCIEXPRBASE	LOONGSON_PCI_REG(0x30)
+#define LOONGSON_PCIINT		LOONGSON_PCI_REG(0x3c)
+
+#define LOONGSON_PCI_ISR4C	LOONGSON_PCI_REG(0x4c)
+
+#define LOONGSON_PCICMD_PERR_CLR	0x80000000
+#define LOONGSON_PCICMD_SERR_CLR	0x40000000
+#define LOONGSON_PCICMD_MABORT_CLR	0x20000000
+#define LOONGSON_PCICMD_MTABORT_CLR	0x10000000
+#define LOONGSON_PCICMD_TABORT_CLR	0x08000000
+#define LOONGSON_PCICMD_MPERR_CLR 	0x01000000
+#define LOONGSON_PCICMD_PERRRESPEN	0x00000040
+#define LOONGSON_PCICMD_ASTEPEN		0x00000080
+#define LOONGSON_PCICMD_SERREN		0x00000100
+#define LOONGSON_PCILTIMER_BUSLATENCY	0x0000ff00
+#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT	8
+
+/* Loongson h/w Configuration */
+
+#define LOONGSON_GENCFG_OFFSET		0x4
+#define LOONGSON_GENCFG	LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
+
+#define LOONGSON_GENCFG_DEBUGMODE	0x00000001
+#define LOONGSON_GENCFG_SNOOPEN		0x00000002
+#define LOONGSON_GENCFG_CPUSELFRESET	0x00000004
+
+#define LOONGSON_GENCFG_FORCE_IRQA	0x00000008
+#define LOONGSON_GENCFG_IRQA_ISOUT	0x00000010
+#define LOONGSON_GENCFG_IRQA_FROM_INT1	0x00000020
+#define LOONGSON_GENCFG_BYTESWAP	0x00000040
+
+#define LOONGSON_GENCFG_UNCACHED	0x00000080
+#define LOONGSON_GENCFG_PREFETCHEN	0x00000100
+#define LOONGSON_GENCFG_WBEHINDEN	0x00000200
+#define LOONGSON_GENCFG_CACHEALG	0x00000c00
+#define LOONGSON_GENCFG_CACHEALG_SHIFT	10
+#define LOONGSON_GENCFG_PCIQUEUE	0x00001000
+#define LOONGSON_GENCFG_CACHESTOP	0x00002000
+#define LOONGSON_GENCFG_MSTRBYTESWAP	0x00004000
+#define LOONGSON_GENCFG_BUSERREN	0x00008000
+#define LOONGSON_GENCFG_NORETRYTIMEOUT	0x00010000
+#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT	0x00020000
+
+/* PCI address map control */
+
+#define LOONGSON_PCIMAP			LOONGSON_REG(LOONGSON_REGBASE + 0x10)
+#define LOONGSON_PCIMEMBASECFG		LOONGSON_REG(LOONGSON_REGBASE + 0x14)
+#define LOONGSON_PCIMAP_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x18)
+
+/* GPIO Regs - r/w */
+
+#define LOONGSON_GPIODATA 		LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
+#define LOONGSON_GPIOIE			LOONGSON_REG(LOONGSON_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE		LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER 		LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL			LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET 		LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR 		LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN			LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR			LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
+/* ICU */
+#define LOONGSON_ICU_MBOXES		0x0000000f
+#define LOONGSON_ICU_MBOXES_SHIFT 	0
+#define LOONGSON_ICU_DMARDY		0x00000010
+#define LOONGSON_ICU_DMAEMPTY		0x00000020
+#define LOONGSON_ICU_COPYRDY		0x00000040
+#define LOONGSON_ICU_COPYEMPTY		0x00000080
+#define LOONGSON_ICU_COPYERR		0x00000100
+#define LOONGSON_ICU_PCIIRQ		0x00000200
+#define LOONGSON_ICU_MASTERERR		0x00000400
+#define LOONGSON_ICU_SYSTEMERR		0x00000800
+#define LOONGSON_ICU_DRAMPERR		0x00001000
+#define LOONGSON_ICU_RETRYERR		0x00002000
+#define LOONGSON_ICU_GPIOS		0x01ff0000
+#define LOONGSON_ICU_GPIOS_SHIFT		16
+#define LOONGSON_ICU_GPINS		0x7e000000
+#define LOONGSON_ICU_GPINS_SHIFT		25
+#define LOONGSON_ICU_MBOX(N)		(1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
+#define LOONGSON_ICU_GPIO(N)		(1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
+#define LOONGSON_ICU_GPIN(N)		(1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
+
+/* PCI prefetch window base & mask */
+
+#define LOONGSON_MEM_WIN_BASE_L 	LOONGSON_REG(LOONGSON_REGBASE + 0x40)
+#define LOONGSON_MEM_WIN_BASE_H 	LOONGSON_REG(LOONGSON_REGBASE + 0x44)
+#define LOONGSON_MEM_WIN_MASK_L 	LOONGSON_REG(LOONGSON_REGBASE + 0x48)
+#define LOONGSON_MEM_WIN_MASK_H 	LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
+
+/* PCI_Hit*_Sel_* */
+
+#define LOONGSON_PCI_HIT0_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x50)
+#define LOONGSON_PCI_HIT0_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x54)
+#define LOONGSON_PCI_HIT1_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x58)
+#define LOONGSON_PCI_HIT1_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
+#define LOONGSON_PCI_HIT2_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x60)
+#define LOONGSON_PCI_HIT2_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x64)
+
+/* PXArb Config & Status */
+
+#define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)
+#define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
+
+/* pcimap */
+
+#define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f
+#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT	0
+#define LOONGSON_PCIMAP_PCIMAP_LO1	0x00000fc0
+#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT	6
+#define LOONGSON_PCIMAP_PCIMAP_LO2	0x0003f000
+#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT	12
+#define LOONGSON_PCIMAP_PCIMAP_2	0x00040000
+#define LOONGSON_PCIMAP_WIN(WIN, ADDR)	\
+	((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
+#include <linux/cpufreq.h>
+extern void loongson2_cpu_wait(void);
+extern struct cpufreq_frequency_table loongson2_clockmod_table[];
+
+/* Chip Config */
+#define LOONGSON_CHIPCFG0		LOONGSON_REG(LOONGSON_REGBASE + 0x80)
+#endif
+
+/*
+ * address windows configuration module
+ *
+ * loongson2e do not have this module
+ */
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/* address window config module base address */
+#define LOONGSON_ADDRWINCFG_BASE		0x3ff00000ul
+#define LOONGSON_ADDRWINCFG_SIZE		0x180
+
+extern unsigned long _loongson_addrwincfg_base;
+#define LOONGSON_ADDRWINCFG(offset) \
+	(*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
+
+#define CPU_WIN0_BASE	LOONGSON_ADDRWINCFG(0x00)
+#define CPU_WIN1_BASE	LOONGSON_ADDRWINCFG(0x08)
+#define CPU_WIN2_BASE	LOONGSON_ADDRWINCFG(0x10)
+#define CPU_WIN3_BASE	LOONGSON_ADDRWINCFG(0x18)
+
+#define CPU_WIN0_MASK	LOONGSON_ADDRWINCFG(0x20)
+#define CPU_WIN1_MASK	LOONGSON_ADDRWINCFG(0x28)
+#define CPU_WIN2_MASK	LOONGSON_ADDRWINCFG(0x30)
+#define CPU_WIN3_MASK	LOONGSON_ADDRWINCFG(0x38)
+
+#define CPU_WIN0_MMAP	LOONGSON_ADDRWINCFG(0x40)
+#define CPU_WIN1_MMAP	LOONGSON_ADDRWINCFG(0x48)
+#define CPU_WIN2_MMAP	LOONGSON_ADDRWINCFG(0x50)
+#define CPU_WIN3_MMAP	LOONGSON_ADDRWINCFG(0x58)
+
+#define PCIDMA_WIN0_BASE	LOONGSON_ADDRWINCFG(0x60)
+#define PCIDMA_WIN1_BASE	LOONGSON_ADDRWINCFG(0x68)
+#define PCIDMA_WIN2_BASE	LOONGSON_ADDRWINCFG(0x70)
+#define PCIDMA_WIN3_BASE	LOONGSON_ADDRWINCFG(0x78)
+
+#define PCIDMA_WIN0_MASK	LOONGSON_ADDRWINCFG(0x80)
+#define PCIDMA_WIN1_MASK	LOONGSON_ADDRWINCFG(0x88)
+#define PCIDMA_WIN2_MASK	LOONGSON_ADDRWINCFG(0x90)
+#define PCIDMA_WIN3_MASK	LOONGSON_ADDRWINCFG(0x98)
+
+#define PCIDMA_WIN0_MMAP	LOONGSON_ADDRWINCFG(0xa0)
+#define PCIDMA_WIN1_MMAP	LOONGSON_ADDRWINCFG(0xa8)
+#define PCIDMA_WIN2_MMAP	LOONGSON_ADDRWINCFG(0xb0)
+#define PCIDMA_WIN3_MMAP	LOONGSON_ADDRWINCFG(0xb8)
+
+#define ADDRWIN_WIN0	0
+#define ADDRWIN_WIN1	1
+#define ADDRWIN_WIN2	2
+#define ADDRWIN_WIN3	3
+
+#define ADDRWIN_MAP_DST_DDR	0
+#define ADDRWIN_MAP_DST_PCI	1
+#define ADDRWIN_MAP_DST_LIO	1
+
+/*
+ * s: CPU, PCIDMA
+ * d: DDR, PCI, LIO
+ * win: 0, 1, 2, 3
+ * src: map source
+ * dst: map destination
+ * size: ~mask + 1
+ */
+#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
+	s##_WIN##w##_BASE = (src); \
+	s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
+	s##_WIN##w##_MASK = ~(size-1); \
+} while (0)
+
+#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
+	LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
+#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
+	LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
+#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
+	LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
+
+#endif	/* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
+#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff -uNra linux-2.6.27.6/arch/mips/oprofile/Makefile linux-2.6.27.6.yaffs/arch/mips/oprofile/Makefile
--- linux-2.6.27.6/arch/mips/oprofile/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/oprofile/Makefile	2011-05-19 16:22:09.000000000 +0800
@@ -15,3 +15,4 @@
 oprofile-$(CONFIG_CPU_R10000)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_SB1)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_RM9000)		+= op_model_rm9000.o
+oprofile-$(CONFIG_CPU_LOONGSON2)  	+= op_model_loongson2.o
diff -uNra linux-2.6.27.6/arch/mips/oprofile/op_model_loongson2.c linux-2.6.27.6.yaffs/arch/mips/oprofile/op_model_loongson2.c
--- linux-2.6.27.6/arch/mips/oprofile/op_model_loongson2.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/oprofile/op_model_loongson2.c	2011-05-27 16:28:46.000000000 +0800
@@ -0,0 +1,161 @@
+/*
+ * Loongson2 performance counter driver for oprofile
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Yanhua <yanh@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+
+#include "loongson.h"			/* LOONGSON2_PERFCNT_IRQ */
+#include "op_impl.h"
+
+#define LOONGSON2_CPU_TYPE	"mips/godson2"
+
+#define LOONGSON2_PERFCNT_OVERFLOW		(1ULL   << 31)
+
+#define LOONGSON2_PERFCTRL_EXL			(1UL	<<  0)
+#define LOONGSON2_PERFCTRL_KERNEL		(1UL    <<  1)
+#define LOONGSON2_PERFCTRL_SUPERVISOR		(1UL    <<  2)
+#define LOONGSON2_PERFCTRL_USER			(1UL    <<  3)
+#define LOONGSON2_PERFCTRL_ENABLE		(1UL    <<  4)
+#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
+	(((event) & 0x0f) << ((idx) ? 9 : 5))
+
+#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
+#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
+#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
+#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
+
+static struct loongson2_register_config {
+	unsigned int ctrl;
+	unsigned long long reset_counter1;
+	unsigned long long reset_counter2;
+	int cnt1_enabled, cnt2_enabled;
+} reg;
+
+static char *oprofid = "LoongsonPerf";
+static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
+
+static void reset_counters(void *arg)
+{
+	write_c0_perfctrl(0);
+	write_c0_perfcnt(0);
+}
+
+static void loongson2_reg_setup(struct op_counter_config *cfg)
+{
+	unsigned int ctrl = 0;
+
+	reg.reset_counter1 = 0;
+	reg.reset_counter2 = 0;
+
+	/*
+	 * Compute the performance counter ctrl word.
+	 * For now, count kernel and user mode.
+	 */
+	if (cfg[0].enabled) {
+		ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
+		reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
+	}
+
+	if (cfg[1].enabled) {
+		ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
+		reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
+	}
+
+	if (cfg[0].enabled || cfg[1].enabled) {
+		ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE;
+		if (cfg[0].kernel || cfg[1].kernel)
+			ctrl |= LOONGSON2_PERFCTRL_KERNEL;
+		if (cfg[0].user || cfg[1].user)
+			ctrl |= LOONGSON2_PERFCTRL_USER;
+	}
+
+	reg.ctrl = ctrl;
+
+	reg.cnt1_enabled = cfg[0].enabled;
+	reg.cnt2_enabled = cfg[1].enabled;
+}
+
+static void loongson2_cpu_setup(void *args)
+{
+	write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1);
+}
+
+static void loongson2_cpu_start(void *args)
+{
+	/* Start all counters on current CPU */
+	if (reg.cnt1_enabled || reg.cnt2_enabled)
+		write_c0_perfctrl(reg.ctrl);
+}
+
+static void loongson2_cpu_stop(void *args)
+{
+	/* Stop all counters on current CPU */
+	write_c0_perfctrl(0);
+	memset(&reg, 0, sizeof(reg));
+}
+
+static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
+{
+	uint64_t counter, counter1, counter2;
+	struct pt_regs *regs = get_irq_regs();
+	int enabled;
+
+	/* Check whether the irq belongs to me */
+	enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
+	if (!enabled)
+		return IRQ_NONE;
+	enabled = reg.cnt1_enabled | reg.cnt2_enabled;
+	if (!enabled)
+		return IRQ_NONE;
+
+	counter = read_c0_perfcnt();
+	counter1 = counter & 0xffffffff;
+	counter2 = counter >> 32;
+
+	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
+		if (reg.cnt1_enabled)
+			oprofile_add_sample(regs, 0);
+		counter1 = reg.reset_counter1;
+	}
+	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
+		if (reg.cnt2_enabled)
+			oprofile_add_sample(regs, 1);
+		counter2 = reg.reset_counter2;
+	}
+
+	write_c0_perfcnt((counter2 << 32) | counter1);
+
+	return IRQ_HANDLED;
+}
+
+static int __init loongson2_init(void)
+{
+	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
+			   IRQF_SHARED, "Perfcounter", oprofid);
+}
+
+static void loongson2_exit(void)
+{
+	reset_counters(NULL);
+	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
+}
+
+struct op_mips_model op_model_loongson2_ops = {
+	.reg_setup = loongson2_reg_setup,
+	.cpu_setup = loongson2_cpu_setup,
+	.init = loongson2_init,
+	.exit = loongson2_exit,
+	.cpu_start = loongson2_cpu_start,
+	.cpu_stop = loongson2_cpu_stop,
+	.cpu_type = LOONGSON2_CPU_TYPE,
+	.num_counters = 2
+};
diff -uNra linux-2.6.27.6/arch/mips/pci/fixup-lm2f.c linux-2.6.27.6.yaffs/arch/mips/pci/fixup-lm2f.c
--- linux-2.6.27.6/arch/mips/pci/fixup-lm2f.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/pci/fixup-lm2f.c	2011-05-08 18:02:22.000000000 +0800
@@ -0,0 +1,293 @@
+/*
+ * fixup-lm2f.c
+ *
+ * Copyright (C) 2004 ICT CAS
+ * Author: Li xiaoyu, ICT CAS
+ *   lixy@ict.ac.cn
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/mips-boards/bonito64.h>
+
+/* PCI interrupt pins */
+/* These should not be changed, or you should consider godson2f interrupt register and
+ * your pci card dispatch
+ */
+#define PCIA		4
+#define PCIB		5
+#define PCIC		6
+#define PCID		7
+
+/* all the pci device has the PCIA pin, check the datasheet. */
+#if 0
+static char irq_tab[][5] __initdata = {
+	/*      INTA    INTB    INTC    INTD */
+	{0,	0,	0,	0,	0 },	/*  11: Unused */
+	{0,	0,	0,	0,	0 },	/*  12: Unused */
+	{0,	0,	0,	0,	0 },	/*  13: Unused */
+	{0,	0,	0,	0,	0 },	/*  14: Unused */
+	{0,	0,	0,	0,	0 },	/*  15: Unused */
+	{0,	0,	0,	0,	0 },	/*  16: Unused */
+	{0,	PCIA,	0,	0,	0 },	/*  17: RTL8110-0 */
+	{0,	PCIB,	0,	0,	0 },	/*  18: RTL8110-1 */
+	{0,	PCIC,	0,	0,	0 },	/*  19: SiI3114 */
+	{0,	0,	0,	0,	0 },	/*  20: Unused */
+	{0,	PCIA,	PCIB,	PCIC,	PCID },	/*  21: PCI-SLOT */
+	{0,	0,	0,	0,	0 },	/*  22: Unused */
+	{0,	PCID,	0,	0,	0 },	/*  23: Unused */
+	{0,	0,	0,	0,	0 },	/*  24: Unused */
+	{0,	0,	0,	0,	0 },	/*  25: Unused */
+	{0,	0,	0,	0,	0 },	/*  26: Unused */
+	{0,	0,	0,	0,	0 },	/*  27: Unused */
+};
+#endif
+static char irq_tab[][5] __initdata = {
+	/*      INTA    INTB    INTC    INTD */
+	{0,	0,	0,	0,	0 },	/*  11: Unused */
+	{0,	0,	0,	0,	0 },	/*  12  */
+	{0,	0,	0,	0,	0 },	/*  13:  */
+	{0,	0,	0,	0,	0 },	/*  14:  */
+	{0,	0,	0,	0,	0 },	/*  15: Unused */
+	{0,	0,	0,	0,	0 },	/*  16:  */
+	{0,	0,	0,	0,	0 },	/*  17: Unused */
+	{0,	0,	0,	0,	0 },	/*  18: Unused */
+	{0,	0,	0,	0,	0 },	/*  19: Unused */
+	{0,	0,	0,	0,	0 },	/*  20: Unused */
+	{0,	0,	0,	0,	0 },	/*  21: Unused */
+	{0,	0,	0,	0,	0 },	/*  22: Unused */
+	{0,	PCID,	0,	0,	0 },	/*  23: ATP8620 */
+	{0,	PCIB,	PCIC,	PCID,	PCIA },	/*  24: PCI-SLOT */
+	{0,	PCIA,	0,	0,	0 },	/*  25: SM502 */
+	{0,	PCIB,	PCIC,	PCIA,	0 },	/*  26: USB */
+	{0,	PCIC,	0,	0,	0 },	/*  27: RTL8100 */
+};
+int __init pcibios_map_irq( struct pci_dev *dev, u8 slot, u8 pin)
+{
+	unsigned int virq;
+#if 0
+	if(PCI_SLOT(dev->devfn) == (17 - 11) ){		/* RTL8110SC_0 */
+		dev->irq = BONITO_IRQ_BASE + 25 + 1;
+		(void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+		return dev->irq;
+	}else if(PCI_SLOT(dev->devfn) == (18 - 11)){	/* RTL8110SC_1 */
+		dev->irq = BONITO_IRQ_BASE + 25 + 2;
+		(void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+		return dev->irq;
+	}else if(PCI_SLOT(dev->devfn) == (19 - 11)){	/* SiI3114 */
+		dev->irq = BONITO_IRQ_BASE + 25 + 3;
+		(void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+		return dev->irq;
+	//}
+	//else if(PCI_SLOT(dev->devfn) == (21 - 11)){	/* PCI SLOT */
+	//	dev->irq = BONITO_IRQ_BASE + 25 + 4;
+	//	(void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+	//	return dev->irq;
+	}else 
+#endif
+
+	if( PCI_SLOT(dev->devfn) < 32 ){
+		virq = irq_tab[slot][pin];
+		printk("slot: %d, pin: %d, irq: %d\n", slot, pin, virq+BONITO_IRQ_BASE);
+		dev->irq = virq + BONITO_IRQ_BASE;
+		if(virq != 0){
+			(void)pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+			return dev->irq;
+		}else
+			return 0;
+	}/*else if( PCI_SLOT(dev->devfn) == 14){	// cs5536
+		switch(PCI_FUNC(dev->devfn)){
+			case 2 :
+				pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
+				return 14;	// for IDE
+			case 3 :
+				pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 9);
+				return 9;	// for AUDIO
+			case 4 :		// for OHCI
+			case 5 :		// for EHCI
+			case 6 :		// for UDC
+			case 7 :		// for OTG
+				pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
+				return 11;	
+		}
+		return dev->irq;
+	}*/
+	else{
+		printk(" strange pci slot number.\n");
+		return 0;
+	}
+/* if(slot >=14 && slot <=16) { 
+	dev->irq = P6032INT_IRQA +(((slot-14)+ (pin-1))&3);
+	(void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+	return dev->irq;
+	}
+	else 
+	return 0;*/
+
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+	return 0;
+}
+
+#ifndef	TEST_NO_CS5536
+/* CS5536 SPEC. fixup */
+static void __init loongson2e_cs5536_isa_fixup(struct pci_dev *pdev)
+{
+	/* the uart1 and uart2 interrupt in PIC is enabled as default */
+	pci_write_config_dword(pdev, 0x50, 1);
+	pci_write_config_dword(pdev, 0x54, 1);
+	/* enable the pci MASTER ABORT/ TARGET ABORT etc. */
+	pci_write_config_dword(pdev, 0x58, 1);
+	return;
+}
+
+
+static void __init loongson2e_cs5536_ide_fixup(struct pci_dev *pdev)
+{
+	/* setting the mutex pin as IDE function */
+	/* the IDE interrupt in PIC is enabled as default */
+	pci_write_config_dword(pdev, 0x40, 0xDEADBEEF);
+	return;
+}
+
+static void __init loongson2e_cs5536_acc_fixup(struct pci_dev *pdev)
+{
+	u8 val;
+
+	/* enable the AUDIO interrupt in PIC  */
+	pci_write_config_dword(pdev, 0x50, 1);
+
+#if 1
+	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
+	printk("cs5536 acc latency %x\n", val);
+	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
+#endif
+	return;
+}
+
+static void __init loongson2e_cs5536_ohci_fixup(struct pci_dev *pdev)
+{
+	/* enable the OHCI interrupt in PIC */
+	/* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
+	pci_write_config_dword(pdev, 0x50, 1);
+	return;
+}
+
+static void __init loongson2e_cs5536_ehci_fixup(struct pci_dev *pdev)
+{
+	/* setting the USB2.0 micro frame length */
+	pci_write_config_dword(pdev, 0x60, 0x2000);
+	return;
+}
+#endif	/* TEST_NO_CS5536 */
+
+static void __init loongson2e_fixup_pcimap(struct pci_dev *pdev)
+{
+	static int first = 1;
+	u32 tmp;
+
+	(void)pdev;
+	if (first)
+		first = 0;
+	else
+		return;
+
+	/* local to PCI mapping: [256M,512M] -> [256M,512M]; differ from pmon */
+	/*
+	 *       cpu address space [256M,448M] is window for accessing pci space
+	 *       we set pcimap_lo[0,1,2] to map it to pci space [256M,448M]
+	 *        pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0
+	 */
+	/* 1,00 0110 ,0001 01,00 0000 */
+	BONITO_PCIMAP = 0x46140;
+	//1, 00 0010, 0000,01, 00 0000
+	//BONITO_PCIMAP = 0x42040;
+
+	/*
+	 * PCI to local mapping: [2G,2G+256M] -> [0,256M]
+	 */
+#if	1	// for LOONGSON2F
+	BONITO_PCIBASE0 = 0x80000000;
+	BONITO_PCIBASE1 = 0x00000000;
+	BONITO(BONITO_REGBASE + 0x50) = 0x8000000c;
+	BONITO(BONITO_REGBASE + 0x54) = 0xffffffff;
+#else		// for LOONGSON2E
+	BONITO_PCIBASE0 = 0x80000000;
+	BONITO_PCIBASE1 = 0x00800000;
+	BONITO_PCIBASE2 = 0x90000000;
+#endif
+#if 0
+	/*set pci 2G -> DDR 0 ,window size 2G*/
+		asm(".set mips3;dli $2,0x900000003ff00000;li $3,0x80000000;sd $3,0x60($2);sd $0,0xa0($2);dli $3,0xffffffff80000000;    sd $3,0x80($2);.set mips0" :::"$2","$3");
+		/*
+		* PCI to local mapping: [8M,16M] -> [8M,16M]
+		  250 ____ */
+	BONITO_PCI_REG(0x18) = 0x00800000;
+	BONITO_PCI_REG(0x1c) = 0x0;
+	BONITO(BONITO_REGBASE + 0x58) = 0xff80000c;
+	BONITO(BONITO_REGBASE + 0x5c) = 0xffffffff;
+	
+	/*set pci 8-16M -> DDR 8-16M ,window size 8M*/
+	asm(".set mips3;dli $2,0x900000003ff00000;li $3,0x800000;sd $3,0x68($2);sd $3,0xa8($2);dli $3,0xffffffffff800000;sd     $3,0x88($2);.set mips0" :::"$2","$3");
+	
+	/* if needed then enable io cache for mem 0*/
+	if (BONITO_PCIMEMBASECFG & BONITO_PCIMEMBASECFG_MEMBASE0_CACHED)
+	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG_MEMBASE0_CACHED;
+	else
+	BONITO_PCIMEMBASECFG = 0x0;
+
+#endif
+#if 1
+#ifdef CONFIG_64BIT
+	*(volatile u32*)0xffffffffbfe0004c = 0xd2000001;
+/*
+	tmp = *(volatile u32*)0xffffffffbfe00058ULL;
+	tmp &= ~0x0000ff00;
+	tmp |= 0x0000ff80;
+	*(volatile u32*)0xffffffffbfe00058 = tmp;
+*/
+#else
+	 *(volatile u32*)0xbfe0004c = 0xd2000001;
+#endif
+#endif
+}
+
+#ifndef	TEST_NO_CS5536
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 
+			 loongson2e_cs5536_isa_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC, 
+			 loongson2e_cs5536_ohci_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC, 
+			 loongson2e_cs5536_ehci_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO, 
+			 loongson2e_cs5536_acc_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, 
+			 loongson2e_cs5536_ide_fixup);
+#endif	/* TEST_NO_CS5536 */
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, loongson2e_fixup_pcimap);
diff -uNra linux-2.6.27.6/arch/mips/pci/Makefile linux-2.6.27.6.yaffs/arch/mips/pci/Makefile
--- linux-2.6.27.6/arch/mips/pci/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/pci/Makefile	2011-05-08 18:02:23.000000000 +0800
@@ -27,6 +27,7 @@
 obj-$(CONFIG_SOC_AU1550)	+= fixup-au1000.o ops-au1000.o
 obj-$(CONFIG_SOC_PNX8550)	+= fixup-pnx8550.o ops-pnx8550.o
 obj-$(CONFIG_LEMOTE_FULONG)	+= fixup-lm2e.o ops-bonito64.o
+obj-$(CONFIG_LEMOTE_FULONG2F)	+= fixup-lm2f.o ops-loongson2f.o
 obj-$(CONFIG_MIPS_MALTA)	+= fixup-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
diff -uNra linux-2.6.27.6/arch/mips/pci/ops-loongson2f.c linux-2.6.27.6.yaffs/arch/mips/pci/ops-loongson2f.c
--- linux-2.6.27.6/arch/mips/pci/ops-loongson2f.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/pci/ops-loongson2f.c	2011-05-08 18:02:23.000000000 +0800
@@ -0,0 +1,202 @@
+/*
+ * ops-lm2f.c
+ *
+ * Copyright (C) 2004 ICT CAS
+ * Author: Li xiaoyu, ICT CAS
+ *   lixy@ict.ac.cn
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+
+#include <asm/mips-boards/bonito64.h>
+
+#define	PCI_OPS_CS5536_IDSEL	14
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+extern void	cs5536_pci_conf_write4(int function, int reg, u32 value);
+extern u32	cs5536_pci_conf_read4(int function, int reg);
+
+static inline void bflush(void)
+{
+	/* flush Bonito register writes */
+	(void)BONITO_PCICMD;
+}
+
+static int lm2f_pci_config_access(unsigned char access_type,
+				  struct pci_bus *bus, unsigned int devfn,
+				  int where, u32 *data)
+{
+	u32 busnum = bus->number;
+	u32 addr, type;
+	void *addrp;
+	int device = PCI_SLOT(devfn);
+	int function = PCI_FUNC(devfn);
+	int reg = where & ~3;
+#if 0 	
+	/************************************************************************/
+	/* CS5536 PCI ACCESS ROUTINE :						*/
+	/*	Note the functions circle call :				*/
+	/* lm2e_pci_config_access()--->cs5536_pci_conf_read/write4()--->	*/
+	/* _rdmsr/_wrmsr()--->lm2e_pci_config_access()				*/
+	/************************************************************************/
+	if( (busnum == 0) && (device == PCI_OPS_CS5536_IDSEL) && (reg < 0xF0) ){
+		switch(access_type){
+			case PCI_ACCESS_READ :
+				*data = cs5536_pci_conf_read4(function, reg);
+				break;
+			case PCI_ACCESS_WRITE :
+				cs5536_pci_conf_write4(function, reg, *data);
+				break;
+		}
+		return 0;
+	}
+#endif	
+	if (busnum == 0) {
+		/* Type 0 configuration on onboard PCI bus */
+		if (device > 20 || function > 7) {
+			*data = -1;	/* device out of range */
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+		addr = (1 << (device + 11)) | (function << 8) | reg;
+		type = 0;
+	} else {
+		/* Type 1 configuration on offboard PCI bus */
+		if (device > 31 || function > 7) {
+			*data = -1;	/* device out of range */
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+		type = 0x10000;
+	}
+
+	/* clear aborts */
+	BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR;
+
+	BONITO_PCIMAP_CFG = (addr >> 16) | type;
+	bflush();
+
+	addrp = (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (addr & 0xffff));
+	if (access_type == PCI_ACCESS_WRITE) {
+		*(volatile unsigned int *)addrp = cpu_to_le32(*data);
+	} else {
+		*data = le32_to_cpu(*(volatile unsigned int *)addrp);
+	}
+
+	/* Detect Master/Target abort */
+	if (BONITO_PCICMD & (BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR)) {
+		BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR;
+		*data = -1;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+
+}
+
+static int lm2f_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 * val)
+{
+	u32 data = 0;
+
+	int ret = lm2f_pci_config_access(PCI_ACCESS_READ,
+			bus, devfn, where, &data);
+
+	if (ret != PCIBIOS_SUCCESSFUL)
+		return ret;
+
+	if (size == 1)
+		*val = (data >> ((where & 3) << 3)) & 0xff;
+	else if (size == 2)
+		*val = (data >> ((where & 3) << 3)) & 0xffff;
+	else
+		*val = data;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int lm2f_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+				  int where, int size, u32 val)
+{
+	u32 data = 0;
+	int ret;
+
+	if (size == 4)
+		data = val;
+	else {
+		ret = lm2f_pci_config_access(PCI_ACCESS_READ,
+				bus, devfn, where, &data);
+		if (ret != PCIBIOS_SUCCESSFUL)
+			return ret;
+
+		if (size == 1)
+			data = (data & ~(0xff << ((where & 3) << 3))) |
+			    (val << ((where & 3) << 3));
+		else if (size == 2)
+			data = (data & ~(0xffff << ((where & 3) << 3))) |
+			    (val << ((where & 3) << 3));
+	}
+
+	ret = lm2f_pci_config_access(PCI_ACCESS_WRITE,
+			bus, devfn, where, &data);
+	if (ret != PCIBIOS_SUCCESSFUL)
+		return ret;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+void _rdmsr(u32 msr, u32 *hi, u32 *lo)
+{
+	struct pci_bus bus = {
+		.number = 0
+	};
+	u32 devfn = PCI_DEVFN(14, 0);
+	lm2f_pci_pcibios_write(&bus, devfn, 0xf4, 4, msr);
+	lm2f_pci_pcibios_read(&bus, devfn, 0xf8, 4, lo);
+	lm2f_pci_pcibios_read(&bus, devfn, 0xfc, 4, hi);
+	//printk("rdmsr msr %x, lo %x, hi %x\n", msr, *lo, *hi);
+}
+
+void _wrmsr(u32 msr, u32 hi, u32 lo)
+{
+	struct pci_bus bus = {
+		.number = 0
+	};
+	u32 devfn = PCI_DEVFN(14, 0);
+	lm2f_pci_pcibios_write(&bus, devfn, 0xf4, 4, msr);
+	lm2f_pci_pcibios_write(&bus, devfn, 0xf8, 4, lo);
+	lm2f_pci_pcibios_write(&bus, devfn, 0xfc, 4, hi);
+	//printk("wrmsr msr %x, lo %x, hi %x\n", msr, lo, hi); 
+}
+
+struct pci_ops loongson2f_pci_pci_ops = {
+	.read = lm2f_pci_pcibios_read,
+	.write = lm2f_pci_pcibios_write
+};
diff -uNra linux-2.6.27.6/arch/mips/pci/pci.c.21 linux-2.6.27.6.yaffs/arch/mips/pci/pci.c.21
--- linux-2.6.27.6/arch/mips/pci/pci.c.21	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/arch/mips/pci/pci.c.21	2011-05-08 18:02:23.000000000 +0800
@@ -0,0 +1,340 @@
+/*
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
+ */
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+/*
+ * Indicate whether we respect the PCI setup left by the firmware.
+ *
+ * Make this long-lived  so that we know when shutting down
+ * whether we probed only or not.
+ */
+int pci_probe_only;
+
+#define PCI_ASSIGN_ALL_BUSSES	1
+
+unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
+
+/*
+ * The PCI controller list.
+ */
+
+struct pci_controller *hose_head, **hose_tail = &hose_head;
+struct pci_controller *pci_isa_hose;
+
+unsigned long PCIBIOS_MIN_IO	= 0x0000;
+unsigned long PCIBIOS_MIN_MEM	= 0;
+
+/*
+ * We need to avoid collisions with `mirrored' VGA ports
+ * and other strange ISA hardware, so we always want the
+ * addresses to be allocated in the 0x000-0x0ff region
+ * modulo 0x400.
+ *
+ * Why? Because some silly external IO cards only decode
+ * the low 10 bits of the IO address. The 0x00-0xff region
+ * is reserved for motherboard devices that decode all 16
+ * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
+ * but we want to try to avoid allocating at 0x2900-0x2bff
+ * which might have be mirrored at 0x0100-0x03ff..
+ */
+void
+pcibios_align_resource(void *data, struct resource *res,
+		       resource_size_t size, resource_size_t align)
+{
+	struct pci_dev *dev = data;
+	struct pci_controller *hose = dev->sysdata;
+	resource_size_t start = res->start;
+
+	if (res->flags & IORESOURCE_IO) {
+		/* Make sure we start at our min on all hoses */
+		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
+			start = PCIBIOS_MIN_IO + hose->io_resource->start;
+
+		/*
+		 * Put everything into 0x00-0xff region modulo 0x400
+		 */
+		if (start & 0x300)
+			start = (start + 0x3ff) & ~0x3ff;
+	} else if (res->flags & IORESOURCE_MEM) {
+		/* Make sure we start at our min on all hoses */
+		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
+			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
+	}
+
+	res->start = start;
+}
+
+void __init register_pci_controller(struct pci_controller *hose)
+{
+	*hose_tail = hose;
+	hose_tail = &hose->next;
+
+	/*
+	 * Do not panic here but later - this might hapen before console init.
+	 */
+	if (!hose->io_map_base) {
+		printk(KERN_WARNING
+		       "registering PCI controller with io_map_base unset\n");
+	}
+}
+
+/* Most MIPS systems have straight-forward swizzling needs.  */
+
+static inline u8 bridge_swizzle(u8 pin, u8 slot)
+{
+	return (((pin - 1) + slot) % 4) + 1;
+}
+
+static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
+{
+	u8 pin = *pinp;
+
+	while (dev->bus->parent) {
+		pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
+		/* Move up the chain of bridges. */
+		dev = dev->bus->self;
+        }
+	*pinp = pin;
+
+	/* The slot is the slot of the last bridge. */
+	return PCI_SLOT(dev->devfn);
+}
+
+int mips_system_has_legacy_ide;
+
+EXPORT_SYMBOL_GPL(mips_system_has_legacy_ide);
+
+static int __init pcibios_init(void)
+{
+	struct pci_controller *hose;
+	struct pci_bus *bus;
+	struct pci_dev *dev;
+	int next_busno;
+	int need_domain_info = 0;
+
+	/* Scan all of the recorded PCI controllers.  */
+	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
+
+		if (request_resource(&iomem_resource, hose->mem_resource) < 0)
+			goto out;
+		if (request_resource(&ioport_resource, hose->io_resource) < 0)
+			goto out_free_mem_resource;
+
+		if (!hose->iommu)
+			PCI_DMA_BUS_IS_PHYS = 1;
+
+		if (hose->get_busno && pci_probe_only)
+			next_busno = (*hose->get_busno)();
+
+		bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
+		hose->bus = bus;
+		hose->need_domain_info = need_domain_info;
+		if (bus) {
+			next_busno = bus->subordinate + 1;
+			/* Don't allow 8-bit bus number overflow inside the hose -
+			   reserve some space for bridges. */
+			if (next_busno > 224) {
+				next_busno = 0;
+				need_domain_info = 1;
+			}
+		}
+		continue;
+
+out_free_mem_resource:
+		release_resource(hose->mem_resource);
+
+out:
+		printk(KERN_WARNING
+		       "Skipping PCI bus scan due to resource conflict\n");
+	}
+
+	if (!pci_probe_only)
+		pci_assign_unassigned_resources();
+	pci_fixup_irqs(common_swizzle, pcibios_map_irq);
+
+	if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
+	    (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
+		pci_dev_put(dev);
+
+		mips_system_has_legacy_ide = 1;
+	}
+
+	return 0;
+}
+
+subsys_initcall(pcibios_init);
+
+static int pcibios_enable_resources(struct pci_dev *dev, int mask)
+{
+	u16 cmd, old_cmd;
+	int idx;
+	struct resource *r;
+
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	old_cmd = cmd;
+	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
+		/* Only set up the requested stuff */
+		if (!(mask & (1<<idx)))
+			continue;
+
+		r = &dev->resource[idx];
+		if (!r->start && r->end) {
+			printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
+			return -EINVAL;
+		}
+		if (r->flags & IORESOURCE_IO)
+			cmd |= PCI_COMMAND_IO;
+		if (r->flags & IORESOURCE_MEM)
+			cmd |= PCI_COMMAND_MEMORY;
+	}
+	if (dev->resource[PCI_ROM_RESOURCE].start)
+		cmd |= PCI_COMMAND_MEMORY;
+	if (cmd != old_cmd) {
+		printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
+		pci_write_config_word(dev, PCI_COMMAND, cmd);
+	}
+	return 0;
+}
+
+/*
+ *  If we set up a device for bus mastering, we need to check the latency
+ *  timer as certain crappy BIOSes forget to set it properly.
+ */
+unsigned int pcibios_max_latency = 255;
+
+void pcibios_set_master(struct pci_dev *dev)
+{
+	u8 lat;
+	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
+	if (lat < 16)
+		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
+	else if (lat > pcibios_max_latency)
+		lat = pcibios_max_latency;
+	else
+		return;
+	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
+	       pci_name(dev), lat);
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+}
+
+unsigned int pcibios_assign_all_busses(void)
+{
+	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
+}
+
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+	int err;
+
+	if ((err = pcibios_enable_resources(dev, mask)) < 0)
+		return err;
+
+	return pcibios_plat_dev_init(dev);
+}
+
+static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
+	struct pci_bus *bus)
+{
+	/* Update device resources.  */
+	struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
+	unsigned long offset = 0;
+	int i;
+
+	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+		if (!dev->resource[i].start)
+			continue;
+		if (dev->resource[i].flags & IORESOURCE_IO)
+			offset = hose->io_offset;
+		else if (dev->resource[i].flags & IORESOURCE_MEM)
+			offset = hose->mem_offset;
+
+		dev->resource[i].start += offset;
+		dev->resource[i].end += offset;
+	}
+}
+
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+{
+	/* Propagate hose info into the subordinate devices.  */
+
+	struct pci_controller *hose = bus->sysdata;
+	struct list_head *ln;
+	struct pci_dev *dev = bus->self;
+
+	if (!dev) {
+		bus->resource[0] = hose->io_resource;
+		bus->resource[1] = hose->mem_resource;
+	} else if (pci_probe_only &&
+		   (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
+		pci_read_bridge_bases(bus);
+		pcibios_fixup_device_resources(dev, bus);
+	}
+
+	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
+		struct pci_dev *dev = pci_dev_b(ln);
+
+		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
+			pcibios_fixup_device_resources(dev, bus);
+	}
+}
+
+void __init
+pcibios_update_irq(struct pci_dev *dev, int irq)
+{
+	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
+}
+
+void __devinit
+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+			 struct resource *res)
+{
+	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
+	unsigned long offset = 0;
+
+	if (res->flags & IORESOURCE_IO)
+		offset = hose->io_offset;
+	else if (res->flags & IORESOURCE_MEM)
+		offset = hose->mem_offset;
+
+	region->start = res->start - offset;
+	region->end = res->end - offset;
+}
+
+void __devinit
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region)
+{
+	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
+	unsigned long offset = 0;
+
+	if (res->flags & IORESOURCE_IO)
+		offset = hose->io_offset;
+	else if (res->flags & IORESOURCE_MEM)
+		offset = hose->mem_offset;
+
+	res->start = region->start + offset;
+	res->end = region->end + offset;
+}
+
+#ifdef CONFIG_HOTPLUG
+EXPORT_SYMBOL(pcibios_resource_to_bus);
+EXPORT_SYMBOL(pcibios_bus_to_resource);
+EXPORT_SYMBOL(PCIBIOS_MIN_IO);
+EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
+#endif
+
+char *pcibios_setup(char *str)
+{
+	return str;
+}
diff -uNra linux-2.6.27.6/block/ioctl.c linux-2.6.27.6.yaffs/block/ioctl.c
--- linux-2.6.27.6/block/ioctl.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/block/ioctl.c	2011-05-08 18:01:05.000000000 +0800
@@ -19,6 +19,8 @@
 	int i;
 	int err;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if (!capable(CAP_SYS_ADMIN))
 		return -EACCES;
 	if (copy_from_user(&a, arg, sizeof(struct blkpg_ioctl_arg)))
@@ -142,6 +144,8 @@
 	struct backing_dev_info *bdi;
 	int ret, n;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	switch (cmd) {
 	case BLKRAGET:
 	case BLKFRAGET:
@@ -204,6 +208,9 @@
 			struct gendisk *disk, unsigned cmd, unsigned long arg)
 {
 	int ret;
+
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if (disk->fops->unlocked_ioctl)
 		return disk->fops->unlocked_ioctl(file, cmd, arg);
 
@@ -229,6 +236,8 @@
 	struct gendisk *disk = bdev->bd_disk;
 	int ret, n;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	switch(cmd) {
 	case BLKFLSBUF:
 		if (!capable(CAP_SYS_ADMIN))
diff -uNra linux-2.6.27.6/block/scsi_ioctl.c linux-2.6.27.6.yaffs/block/scsi_ioctl.c
--- linux-2.6.27.6/block/scsi_ioctl.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/block/scsi_ioctl.c	2011-05-08 18:01:06.000000000 +0800
@@ -268,6 +268,8 @@
 	char sense[SCSI_SENSE_BUFFERSIZE];
 	struct bio *bio;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if (hdr->interface_id != 'S')
 		return -EINVAL;
 	if (hdr->cmd_len > BLK_MAX_CDB)
@@ -386,6 +388,8 @@
 	unsigned int in_len, out_len, bytes, opcode, cmdlen;
 	char *buffer = NULL, sense[SCSI_SENSE_BUFFERSIZE];
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if (!sic)
 		return -EINVAL;
 
@@ -525,6 +529,8 @@
 {
 	int err;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if (!q || blk_get_queue(q))
 		return -ENXIO;
 
diff -uNra linux-2.6.27.6/.config linux-2.6.27.6.yaffs/.config
--- linux-2.6.27.6/.config	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config	2012-03-14 10:55:17.000000000 +0800
@@ -0,0 +1,1965 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed Mar 14 10:55:17 2012
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="~/ramfs/cww.cpio.gz"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_VEGAS=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_SX8=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_BLK_DEV_HD=y
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_STRADIS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=y
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=m
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/config.0420 linux-2.6.27.6.yaffs/config.0420
--- linux-2.6.27.6/config.0420	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/config.0420	2011-05-08 18:01:40.000000000 +0800
@@ -0,0 +1,2107 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Sun Dec  5 17:14:23 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
+# CONFIG_PARPORT_PC_PCMCIA is not set
+# CONFIG_PARPORT_GSC is not set
+CONFIG_PARPORT_AX88796=y
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_NET_POCKET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/config.0706 linux-2.6.27.6.yaffs/config.0706
--- linux-2.6.27.6/config.0706	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/config.0706	2011-07-06 08:53:13.000000000 +0800
@@ -0,0 +1,1881 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Tue May 31 11:28:22 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_VEGAS=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=m
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.bak linux-2.6.27.6.yaffs/.config.bak
--- linux-2.6.27.6/.config.bak	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.bak	2011-05-08 18:02:44.000000000 +0800
@@ -0,0 +1,2035 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed Sep  8 16:06:57 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_PANTHERLORD_FF=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=y
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/config.bak linux-2.6.27.6.yaffs/config.bak
--- linux-2.6.27.6/config.bak	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/config.bak	2011-05-08 18:01:36.000000000 +0800
@@ -0,0 +1,2034 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Fri Oct  8 16:34:14 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_PANTHERLORD_FF=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/config.bak.11.23 linux-2.6.27.6.yaffs/config.bak.11.23
--- linux-2.6.27.6/config.bak.11.23	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/config.bak.11.23	2011-05-08 18:01:03.000000000 +0800
@@ -0,0 +1,2053 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed Nov 17 11:08:26 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
+# CONFIG_PARPORT_PC_PCMCIA is not set
+# CONFIG_PARPORT_GSC is not set
+CONFIG_PARPORT_AX88796=y
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_NET_POCKET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_PANTHERLORD_FF=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/config.bak.11.24.nand linux-2.6.27.6.yaffs/config.bak.11.24.nand
--- linux-2.6.27.6/config.bak.11.24.nand	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/config.bak.11.24.nand	2011-05-08 18:01:06.000000000 +0800
@@ -0,0 +1,2088 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed Nov 24 13:14:11 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
+# CONFIG_PARPORT_PC_PCMCIA is not set
+# CONFIG_PARPORT_GSC is not set
+CONFIG_PARPORT_AX88796=y
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_NET_POCKET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_PANTHERLORD_FF=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/config.beforezxf linux-2.6.27.6.yaffs/config.beforezxf
--- linux-2.6.27.6/config.beforezxf	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/config.beforezxf	2011-10-18 10:15:36.000000000 +0800
@@ -0,0 +1,1963 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Mon Oct 17 18:41:26 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_VEGAS=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_SX8=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_BLK_DEV_HD=y
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_STRADIS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=y
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=m
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.haveuart linux-2.6.27.6.yaffs/.config.haveuart
--- linux-2.6.27.6/.config.haveuart	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.haveuart	2011-05-11 18:31:13.000000000 +0800
@@ -0,0 +1,2112 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Sun May  8 18:10:39 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
+# CONFIG_PARPORT_PC_PCMCIA is not set
+# CONFIG_PARPORT_GSC is not set
+CONFIG_PARPORT_AX88796=y
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_NET_POCKET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.nouart linux-2.6.27.6.yaffs/.config.nouart
--- linux-2.6.27.6/.config.nouart	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.nouart	2011-05-16 11:07:27.000000000 +0800
@@ -0,0 +1,2094 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed May 11 18:34:02 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
+# CONFIG_PARPORT_PC_PCMCIA is not set
+# CONFIG_PARPORT_GSC is not set
+CONFIG_PARPORT_AX88796=y
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_NET_POCKET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.old linux-2.6.27.6.yaffs/.config.old
--- linux-2.6.27.6/.config.old	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.old	2012-03-14 10:53:29.000000000 +0800
@@ -0,0 +1,1965 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed Mar 14 10:53:29 2012
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../ramdisk.gz"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_VEGAS=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_SX8=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_BLK_DEV_HD=y
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_STRADIS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=y
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=m
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.oprofilebad linux-2.6.27.6.yaffs/.config.oprofilebad
--- linux-2.6.27.6/.config.oprofilebad	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.oprofilebad	2011-05-19 21:47:00.000000000 +0800
@@ -0,0 +1,1805 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed May 18 09:16:39 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+# CONFIG_NF_NAT_IRC is not set
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+CONFIG_X25=m
+CONFIG_LAPB=m
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_PROC_FS is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+# CONFIG_SSB_PCIHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+# CONFIG_JFFS2_SUMMARY is not set
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=m
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.rtcok linux-2.6.27.6.yaffs/.config.rtcok
--- linux-2.6.27.6/.config.rtcok	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.rtcok	2011-05-08 18:01:39.000000000 +0800
@@ -0,0 +1,2034 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Tue Oct 19 11:26:41 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_BRIDGE_EBT_ULOG=y
+CONFIG_BRIDGE_EBT_NFLOG=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=y
+# CONFIG_AF_RXRPC_DEBUG is not set
+CONFIG_RXKAD=m
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+# CONFIG_NL80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+CONFIG_SCSI_ACARD=y
+CONFIG_SCSI_ACARD_ATP8620=y
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+CONFIG_ATA_GENERIC=y
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLHC=m
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_PANTHERLORD_FF=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIFS_POSIX is not set
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=y
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=y
+CONFIG_AFS_FS=y
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/.config.yun linux-2.6.27.6.yaffs/.config.yun
--- linux-2.6.27.6/.config.yun	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.config.yun	2011-05-31 11:37:13.000000000 +0800
@@ -0,0 +1,1881 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Tue May 31 11:28:22 2011
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LEMOTE_FULONG2F=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+
+#
+# CPU selection
+#
+CONFIG_CPU_LOONGSON2=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-loongson-2f"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_ISA=y
+CONFIG_MMU=y
+CONFIG_I8253=y
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_VEGAS=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+CONFIG_IPX=y
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=y
+CONFIG_DEV_APPLETALK=y
+# CONFIG_COPS is not set
+# CONFIG_IPDDP is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+CONFIG_SSFDC=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_TOPSTAR=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG=y
+
+#
+# Protocols
+#
+CONFIG_ISAPNP=y
+# CONFIG_PNPACPI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SCSI_SAS_ATA is not set
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_REALTEK_PHY=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_NET_PCMCIA is not set
+CONFIG_WAN=y
+# CONFIG_HDLC is not set
+# CONFIG_DLCI is not set
+# CONFIG_WAN_ROUTER_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_MOUSE_BCM5974=y
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SMIVGX_SERIAL_SECOND is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+# CONFIG_SSB_PCMCIAHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SILICONMOTION is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_MIPS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SM501_SOC=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_PHIDGET=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_USB_PHIDGETSERVO=y
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_UIO=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_SMX=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=y
+CONFIG_EFS_FS=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPCSEC_GSS_SPKM3=m
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -uNra linux-2.6.27.6/cscope.files linux-2.6.27.6.yaffs/cscope.files
diff -uNra linux-2.6.27.6/drivers/cdrom/cdrom.c linux-2.6.27.6.yaffs/drivers/cdrom/cdrom.c
--- linux-2.6.27.6/drivers/cdrom/cdrom.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/cdrom/cdrom.c	2011-05-08 18:00:27.000000000 +0800
@@ -2669,6 +2669,8 @@
 	int ret;
 	struct gendisk *disk = ip->i_bdev->bd_disk;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	/*
 	 * Try the generic SCSI command ioctl's first.
 	 */
@@ -2793,6 +2795,8 @@
 	unsigned char buffer[32];
 	int ret = 0;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	memset(&cgc, 0, sizeof(cgc));
 
 	/* build a unified command and queue it through
diff -uNra linux-2.6.27.6/drivers/char/mem.c linux-2.6.27.6.yaffs/drivers/char/mem.c
--- linux-2.6.27.6/drivers/char/mem.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/char/mem.c	2011-05-08 18:00:43.000000000 +0800
@@ -35,6 +35,8 @@
 # include <linux/efi.h>
 #endif
 
+unsigned int uca =1;
+unsigned long fb_start = 0xffffffffUL, fb_end = 0xffffffffUL;
 /*
  * Architectures vary in how they handle caching for addresses
  * outside of main memory.
@@ -61,6 +63,12 @@
 	 */
 	if (file->f_flags & O_SYNC)
 		return 1;
+#if defined(CONFIG_CPU_LOONGSON2) && defined(CONFIG_64BIT)
+       return (addr >= __pa(high_memory)) || ((addr >=0x10000000) && (addr < 0x80000000));
+#else
+         return addr >= __pa(high_memory);
+#endif
+
 	return addr >= __pa(high_memory);
 #endif
 }
@@ -354,6 +362,13 @@
 						 size,
 						 vma->vm_page_prot);
 
+	if (uca) {
+		unsigned offset = vma->vm_pgoff << PAGE_SHIFT;
+		if (offset >= fb_start && offset < fb_end){
+			vma->vm_page_prot = __pgprot((pgprot_val(vma->vm_page_prot)&~_CACHE_MASK)|_CACHE_UNCACHED_ACCELERATED);
+		}
+	}
+
 	vma->vm_ops = &mmap_mem_ops;
 
 	/* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
@@ -1000,3 +1015,59 @@
 }
 
 fs_initcall(chr_dev_init);
+
+/*setup for godson uncache acceleration*/
+
+#include <linux/pci.h>
+#ifndef pci_for_each_dev
+#define pci_for_each_dev for_each_pci_dev
+#endif
+static int __init find_vga_mem_init(void)
+{
+       struct pci_dev *dev = 0;
+       struct resource *r;
+       int idx;
+       printk("begin to find the vga mem range\n");
+       if(!uca)return 0;
+       pci_for_each_dev(dev) {
+               //if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA){
+               if ((dev->class >> 8) == 0x0380){
+                       for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
+                               r = &dev->resource[idx];
+                               if (!r->start && r->end) {
+                                       continue;
+                               }
+                               if (r->flags & IORESOURCE_IO)
+                                       continue;
+                               if (r->flags & IORESOURCE_MEM){
+                                       fb_start = r->start;
+                                       fb_end  = r->end;
+                                       printk("find the frame buffer:start=%lx,end=%lx\n", fb_start, fb_end);
+                                       return 0;
+                               }
+                       }
+
+               }
+       }
+       printk("<0>can not find vga device\n");
+       return 0;
+}
+
+late_initcall(find_vga_mem_init);
+
+static int __init uca_setup(char *str)
+{
+       char tmp[100], *end;
+
+       uca = 1;
+       strncpy(tmp, str, 100);
+       fb_start = simple_strtoul(tmp, &end, 16);
+       if (end && *end) {
+                       end ++;
+                       fb_end = fb_start + simple_strtoul(end, NULL, 16) ;
+       }
+
+       return 0;
+}
+
+__setup("uca=", uca_setup);
diff -uNra linux-2.6.27.6/drivers/char/rtc.c linux-2.6.27.6.yaffs/drivers/char/rtc.c
--- linux-2.6.27.6/drivers/char/rtc.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/char/rtc.c	2011-05-08 18:00:44.000000000 +0800
@@ -100,6 +100,7 @@
 #undef	RTC_IRQ
 #endif
 
+#undef	RTC_IRQ
 #ifdef RTC_IRQ
 static int rtc_has_irq = 1;
 #endif
@@ -257,7 +258,9 @@
 	} else {
 		rtc_irq_data |= (CMOS_READ(RTC_INTR_FLAGS) & 0xF0);
 	}
-
+#if defined(CONFIG_LEMOTE_FULONG2F) /* FIXUP_CS5536_RTC */
+	(void)CMOS_READ(RTC_VALID);
+#endif
 	if (rtc_status & RTC_TIMER_ON)
 		mod_timer(&rtc_irq_timer, jiffies + HZ/rtc_freq + 2*HZ/100);
 
@@ -397,6 +400,7 @@
 #endif
 }
 
+extern int rtc_mytest();
 static int rtc_do_ioctl(unsigned int cmd, unsigned long arg, int kernel)
 {
 	struct rtc_time wtime;
@@ -515,6 +519,7 @@
 			 * so that we will get proper value in RTC_ALM_READ
 			 */
 		}
+#if 0 //mj_rtc
 		if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) ||
 							RTC_ALWAYS_BCD) {
 			if (sec < 60)
@@ -532,6 +537,7 @@
 			else
 				hrs = 0xff;
 		}
+#endif 
 		CMOS_WRITE(hrs, RTC_HOURS_ALARM);
 		CMOS_WRITE(min, RTC_MINUTES_ALARM);
 		CMOS_WRITE(sec, RTC_SECONDS_ALARM);
@@ -541,6 +547,7 @@
 	}
 	case RTC_RD_TIME:	/* Read the time/date from RTC	*/
 	{
+		//rtc_mytest();
 		memset(&wtime, 0, sizeof(struct rtc_time));
 		rtc_get_rtc_time(&wtime);
 		break;
@@ -555,6 +562,7 @@
 		unsigned int real_yrs;
 #endif
 
+		//rtc_mytest();
 		if (!capable(CAP_SYS_TIME))
 			return -EACCES;
 
@@ -611,7 +619,7 @@
 		}
 		if (yrs >= 100)
 			yrs -= 100;
-
+#if 0 //mj_rtc
 		if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
 		    || RTC_ALWAYS_BCD) {
 			BIN_TO_BCD(sec);
@@ -621,7 +629,7 @@
 			BIN_TO_BCD(mon);
 			BIN_TO_BCD(yrs);
 		}
-
+#endif
 		save_control = CMOS_READ(RTC_CONTROL);
 		CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
 		save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
@@ -641,6 +649,7 @@
 		CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
 
 		spin_unlock_irq(&rtc_lock);
+		//rtc_mytest();
 		return 0;
 	}
 #ifdef RTC_IRQ
@@ -962,7 +971,28 @@
 	else
 		release_mem_region(RTC_PORT(0), rtc_size);
 }
+int rtc_mytest()
+{
+	unsigned int year1, mon, day, hour, min, sec;
+	unsigned long flags;
+
+	spin_lock_irqsave(&rtc_lock, flags);
+
+	printk("sec %d, min %d,hour %d,day %d,mon %d, year1 %d\n",RTC_SECONDS,RTC_MINUTES,RTC_HOURS,RTC_DAY_OF_MONTH,RTC_MONTH,RTC_YEAR);
+	do {
+		sec = CMOS_READ(RTC_SECONDS);
+		min = CMOS_READ(RTC_MINUTES);
+		hour = CMOS_READ(RTC_HOURS);
+		day = CMOS_READ(RTC_DAY_OF_MONTH);
+		mon = CMOS_READ(RTC_MONTH);
+		year1 = CMOS_READ(RTC_YEAR);
+	} while (sec != CMOS_READ(RTC_SECONDS));
+	printk("sec %d, min %d,hour %d,day %d,mon %d, year1 %d\n",sec,min,hour,day,mon,year1);
+
+	spin_unlock_irqrestore(&rtc_lock, flags);
+	return 0;
 
+}
 static int __init rtc_init(void)
 {
 #ifdef CONFIG_PROC_FS
@@ -981,7 +1011,7 @@
 	irq_handler_t rtc_int_handler_ptr;
 #endif
 #endif
-
+   //rtc_mytest();
 #ifdef CONFIG_SPARC32
 	for_each_ebus(ebus) {
 		for_each_ebusdev(edev, ebus) {
@@ -1093,10 +1123,10 @@
 	year = CMOS_READ(RTC_YEAR);
 	ctrl = CMOS_READ(RTC_CONTROL);
 	spin_unlock_irq(&rtc_lock);
-
+#if 0 //mj_rtc
 	if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
 		BCD_TO_BIN(year);       /* This should never happen... */
-
+#endif
 	if (year < 20) {
 		epoch = 2000;
 		guess = "SRM (post-2000)";
@@ -1346,7 +1376,7 @@
 #endif
 	ctrl = CMOS_READ(RTC_CONTROL);
 	spin_unlock_irqrestore(&rtc_lock, flags);
-
+#if 0 //mj_rtc
 	if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 		BCD_TO_BIN(rtc_tm->tm_sec);
 		BCD_TO_BIN(rtc_tm->tm_min);
@@ -1356,7 +1386,7 @@
 		BCD_TO_BIN(rtc_tm->tm_year);
 		BCD_TO_BIN(rtc_tm->tm_wday);
 	}
-
+#endif 
 #ifdef CONFIG_MACH_DECSTATION
 	rtc_tm->tm_year += real_year - 72;
 #endif
diff -uNra linux-2.6.27.6/drivers/char/tty_io.c linux-2.6.27.6.yaffs/drivers/char/tty_io.c
--- linux-2.6.27.6/drivers/char/tty_io.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/char/tty_io.c	2011-05-08 18:00:42.000000000 +0800
@@ -2180,16 +2180,20 @@
 
 	nonseekable_open(inode, filp);
 
+	//printk("tty open start----------------0\n");
 retry_open:
 	noctty = filp->f_flags & O_NOCTTY;
 	index  = -1;
 	retval = 0;
 
 	mutex_lock(&tty_mutex);
+	//printk("tty open start----------------1\n");
 
 	if (device == MKDEV(TTYAUX_MAJOR, 0)) {
+	//printk("++++++++++++++++++++++++++++++\n");
 		tty = get_current_tty();
 		if (!tty) {
+	//printk("++++++++++++++++++++++++++++++1\n");
 			mutex_unlock(&tty_mutex);
 			return -ENXIO;
 		}
@@ -2214,6 +2218,7 @@
 			/* Don't let /dev/console block */
 			filp->f_flags |= O_NONBLOCK;
 			noctty = 1;
+	//printk("tty open start----------------4\n");
 			goto got_driver;
 		}
 		mutex_unlock(&tty_mutex);
@@ -2240,6 +2245,7 @@
 #ifdef TTY_DEBUG_HANGUP
 	printk(KERN_DEBUG "opening %s...", tty->name);
 #endif
+	//printk("opening %s...\n", tty->name);
 	if (!retval) {
 		if (tty->ops->open)
 			retval = tty->ops->open(tty, filp);
@@ -2280,6 +2286,7 @@
 		__proc_set_tty(current, tty);
 	spin_unlock_irq(&current->sighand->siglock);
 	mutex_unlock(&tty_mutex);
+	//printk("tty open finish----------------\n");
 	return 0;
 }
 
@@ -3093,24 +3100,35 @@
 	struct tty_ldisc *ld;
 	int retval = -ENOIOCTLCMD;
 
+	//printk("tty_compat_ioctl--------------1\n");
+
 	if (tty_paranoia_check(tty, inode, "tty_ioctl"))
 		return -EINVAL;
 
+//	printk("tty_compat_ioctl--------------2\n");
 	if (tty->ops->compat_ioctl) {
+//	printk("tty_compat_ioctl--------------3\n");
 		retval = (tty->ops->compat_ioctl)(tty, file, cmd, arg);
+//	printk("tty_compat_ioctl--------------4\n");
 		if (retval != -ENOIOCTLCMD)
 			return retval;
 	}
 
+//	printk("tty_compat_ioctl--------------5\n");
 	ld = tty_ldisc_ref_wait(tty);
-	if (ld->ops->compat_ioctl)
+//	printk("tty_compat_ioctl--------------6\n");
+	if (ld->ops->compat_ioctl){
+//		printk("tty_compat_ioctl--------------7\n");
 		retval = ld->ops->compat_ioctl(tty, file, cmd, arg);
+//		printk("tty_compat_ioctl--------------8\n");
+	}
+	//	printk("tty_compat_ioctl--------------9\n");
 	tty_ldisc_deref(ld);
 
+//	printk("tty_compat_ioctl--------------10\n");
 	return retval;
 }
 #endif
-
 /*
  * This implements the "Secure Attention Key" ---  the idea is to
  * prevent trojan horses by killing all processes associated with this
diff -uNra linux-2.6.27.6/drivers/char/vt_ioctl.c linux-2.6.27.6.yaffs/drivers/char/vt_ioctl.c
--- linux-2.6.27.6/drivers/char/vt_ioctl.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/char/vt_ioctl.c	2011-05-08 18:00:43.000000000 +0800
@@ -165,6 +165,7 @@
 	struct kbkeycode tmp;
 	int kc = 0;
 
+//	printk("---1----%s----------\n",__func__);
 	if (copy_from_user(&tmp, user_kbkc, sizeof(struct kbkeycode)))
 		return -EFAULT;
 	switch (cmd) {
@@ -375,6 +376,7 @@
 	int i, perm;
 	int ret = 0;
 
+//	printk("---1----%s----------\n",__func__);
 	console = vc->vc_num;
 
 	lock_kernel();
@@ -585,7 +587,10 @@
 	case KDSETKEYCODE:
 		if(!capable(CAP_SYS_TTY_CONFIG))
 			perm = 0;
+//	printk("---2----%s----------\n",__func__);
 		ret = do_kbkeycode_ioctl(cmd, up, perm);
+
+//	printk("---3----%s----------\n",__func__);
 		break;
 
 	case KDGKBENT:
diff -uNra linux-2.6.27.6/drivers/gpu/drm/ati_pcigart.c linux-2.6.27.6.yaffs/drivers/gpu/drm/ati_pcigart.c
--- linux-2.6.27.6/drivers/gpu/drm/ati_pcigart.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/gpu/drm/ati_pcigart.c	2011-05-08 18:00:37.000000000 +0800
@@ -126,9 +126,11 @@
 			  (unsigned long long)bus_address,
 			  (unsigned long)address);
 	}
-
+#ifdef CONFIG_CPU_LOONGSON2
+	pci_gart = (u32 *) UNCAC_ADDR(address);
+#else
 	pci_gart = (u32 *) address;
-
+#endif
 	max_pages = (gart_info->table_size / sizeof(u32));
 	pages = (entry->pages <= max_pages)
 	    ? entry->pages : max_pages;
diff -uNra linux-2.6.27.6/drivers/gpu/drm/drm_bufs.c linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_bufs.c
--- linux-2.6.27.6/drivers/gpu/drm/drm_bufs.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_bufs.c	2011-05-08 18:00:36.000000000 +0800
@@ -88,6 +88,10 @@
 					 0, DRM_MAP_HASH_OFFSET >> PAGE_SHIFT);
 }
 
+#ifdef CONFIG_CPU_LOONGSON2
+extern void *vmalloc_user_uncached(unsigned long size);
+#endif
+
 /**
  * Ioctl to specify a range of memory that is available for mapping by a non-root process.
  *
@@ -141,7 +145,7 @@
 	switch (map->type) {
 	case _DRM_REGISTERS:
 	case _DRM_FRAME_BUFFER:
-#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__)
+#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__mips__)
 		if (map->offset + (map->size-1) < map->offset ||
 		    map->offset < virt_to_phys(high_memory)) {
 			drm_free(map, sizeof(*map), DRM_MEM_MAPS);
@@ -200,7 +204,11 @@
 			*maplist = list;
 			return 0;
 		}
+#ifdef CONFIG_CPU_LOONGSON2
+		map->handle = vmalloc_user_uncached(map->size);
+#else
 		map->handle = vmalloc_user(map->size);
+#endif
 		DRM_DEBUG("%lu %d %p\n",
 			  map->size, drm_order(map->size), map->handle);
 		if (!map->handle) {
diff -uNra linux-2.6.27.6/drivers/gpu/drm/drm_pci.c linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_pci.c
--- linux-2.6.27.6/drivers/gpu/drm/drm_pci.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_pci.c	2011-05-08 18:00:37.000000000 +0800
@@ -113,7 +113,11 @@
 	/* Reserve */
 	for (addr = (unsigned long)dmah->vaddr, sz = size;
 	     sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
+#ifdef CONFIG_CPU_LOONGSON2
+		SetPageReserved(virt_to_page(CAC_ADDR(addr)));
+#else
 		SetPageReserved(virt_to_page(addr));
+#endif
 	}
 
 	return dmah;
@@ -147,7 +151,11 @@
 		/* Unreserve */
 		for (addr = (unsigned long)dmah->vaddr, sz = dmah->size;
 		     sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
+#ifdef CONFIG_CPU_LOONGSON2			
+			ClearPageReserved(virt_to_page(CAC_ADDR(addr)));
+#else			
 			ClearPageReserved(virt_to_page(addr));
+#endif
 		}
 		dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
 				  dmah->busaddr);
diff -uNra linux-2.6.27.6/drivers/gpu/drm/drm_scatter.c linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_scatter.c
--- linux-2.6.27.6/drivers/gpu/drm/drm_scatter.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_scatter.c	2011-05-08 18:00:37.000000000 +0800
@@ -40,6 +40,9 @@
 {
 #if defined(__powerpc__) && defined(CONFIG_NOT_COHERENT_CACHE)
 	return __vmalloc(size, GFP_KERNEL, PAGE_KERNEL | _PAGE_NO_CACHE);
+#elseif defined(CONFIG_CPU_LOONGSON2)
+	return __vmalloc(size, GFP_KERNEL, PAGE_KERNEL | _PAGE_NO_CACHE);
+//        return __vmalloc(size, GFP_KERNEL, pgprot_noncached(PAGE_KERNEL));
 #else
 	return vmalloc_32(size);
 #endif
diff -uNra linux-2.6.27.6/drivers/gpu/drm/drm_vm.c linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_vm.c
--- linux-2.6.27.6/drivers/gpu/drm/drm_vm.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/gpu/drm/drm_vm.c	2011-05-08 18:00:37.000000000 +0800
@@ -299,7 +299,11 @@
 
 	offset = (unsigned long)vmf->virtual_address - vma->vm_start;	/* vm_[pg]off[set] should be 0 */
 	page_nr = offset >> PAGE_SHIFT; /* page_nr could just be vmf->pgoff */
+#ifdef CONFIG_CPU_LOONGSON2
+	page = virt_to_page(CAC_ADDR(dma->pagelist[page_nr] + (offset & (~PAGE_MASK))));
+#else
 	page = virt_to_page((dma->pagelist[page_nr] + (offset & (~PAGE_MASK))));
+#endif
 
 	get_page(page);
 	vmf->page = page;
@@ -498,6 +502,10 @@
 			      (__pte(pgprot_val(vma->vm_page_prot)))));
 #endif
 	}
+	
+#ifdef CONFIG_CPU_LOONGSON2
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
 
 	vma->vm_ops = &drm_vm_dma_ops;
 
@@ -614,6 +622,9 @@
 		offset = dev->driver->get_reg_ofs(dev);
 		vma->vm_flags |= VM_IO;	/* not in core dump */
 		vma->vm_page_prot = drm_io_prot(map->type, vma);
+#if  defined(CONFIG_CPU_LOONGSON2)
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
 		if (io_remap_pfn_range(vma, vma->vm_start,
 				       (map->offset + offset) >> PAGE_SHIFT,
 				       vma->vm_end - vma->vm_start,
@@ -628,13 +639,23 @@
 	case _DRM_CONSISTENT:
 		/* Consistent memory is really like shared memory. But
 		 * it's allocated in a different way, so avoid fault */
+#ifdef CONFIG_CPU_LOONGSON2
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
 		if (remap_pfn_range(vma, vma->vm_start,
+#ifdef CONFIG_CPU_LOONGSON2
+		page_to_pfn(virt_to_page(CAC_ADDR(map->handle))),
+#else
 		    page_to_pfn(virt_to_page(map->handle)),
+#endif
 		    vma->vm_end - vma->vm_start, vma->vm_page_prot))
 			return -EAGAIN;
 		vma->vm_page_prot = drm_dma_prot(map->type, vma);
 	/* fall through to _DRM_SHM */
 	case _DRM_SHM:
+#ifdef CONFIG_CPU_LOONGSON2
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
 		vma->vm_ops = &drm_vm_shm_ops;
 		vma->vm_private_data = (void *)map;
 		/* Don't let this area swap.  Change when
@@ -642,6 +663,9 @@
 		vma->vm_flags |= VM_RESERVED;
 		break;
 	case _DRM_SCATTER_GATHER:
+#ifdef CONFIG_CPU_LOONGSON2
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
 		vma->vm_ops = &drm_vm_sg_ops;
 		vma->vm_private_data = (void *)map;
 		vma->vm_flags |= VM_RESERVED;
diff -uNra linux-2.6.27.6/drivers/gpu/drm/radeon/radeon_cp.c linux-2.6.27.6.yaffs/drivers/gpu/drm/radeon/radeon_cp.c
--- linux-2.6.27.6/drivers/gpu/drm/radeon/radeon_cp.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/gpu/drm/radeon/radeon_cp.c	2011-05-08 18:00:37.000000000 +0800
@@ -1750,9 +1750,15 @@
 		return ret;
 
 	dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
+#ifdef CONFIG_LEMOTE_FULONG
+	ret = drm_addmap(dev, dev_priv->fb_aper_offset,
+			 0x1000000, _DRM_FRAME_BUFFER,
+			 _DRM_WRITE_COMBINING, &map);
+#else
 	ret = drm_addmap(dev, dev_priv->fb_aper_offset,
 			 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
 			 _DRM_WRITE_COMBINING, &map);
+#endif
 	if (ret != 0)
 		return ret;
 
diff -uNra linux-2.6.27.6/drivers/hid/hid-core.c linux-2.6.27.6.yaffs/drivers/hid/hid-core.c
--- linux-2.6.27.6/drivers/hid/hid-core.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/hid/hid-core.c	2011-05-08 18:00:15.000000000 +0800
@@ -44,6 +44,7 @@
 
 #ifdef CONFIG_HID_DEBUG
 int hid_debug = 0;
+//int hid_debug = 1;
 module_param_named(debug, hid_debug, int, 0600);
 MODULE_PARM_DESC(debug, "HID debugging (0=off, 1=probing info, 2=continuous data dumping)");
 EXPORT_SYMBOL_GPL(hid_debug);
@@ -472,6 +473,7 @@
  * Process a main item.
  */
 
+void prom_printf();
 static int hid_parser_main(struct hid_parser *parser, struct hid_item *item)
 {
 	__u32 data;
@@ -479,6 +481,8 @@
 
 	data = item_udata(item);
 
+//	printk("---1----%s----------\n",__func__);
+//	prom_printf("---1----%s----------\n",__func__);
 	switch (item->tag) {
 		case HID_MAIN_ITEM_TAG_BEGIN_COLLECTION:
 			ret = open_collection(parser, data & 0xff);
@@ -948,10 +952,13 @@
 
 int hid_input_report(struct hid_device *hid, int type, u8 *data, int size, int interrupt)
 {
+
 	struct hid_report_enum *report_enum = hid->report_enum + type;
 	struct hid_report *report;
 	int n, rsize, i;
 
+//	printk("---1----%s----------\n",__func__);
+//	prom_printf("---1----%s----------\n",__func__);
 	if (!hid)
 		return -ENODEV;
 
@@ -970,8 +977,14 @@
 
 	/* dump the report */
 	dbg_hid("report %d (size %u) = ", n, size);
+//	printk("----------------------------------\n");
+#if 0 //mj
 	for (i = 0; i < size; i++)
+	{
 		dbg_hid_line(" %02x", data[i]);
+		printk(" %02x", data[i]);
+	}
+#endif
 	dbg_hid_line("\n");
 
 	if (!(report = report_enum->report_id_hash[n])) {
@@ -1000,7 +1013,11 @@
 		hid_input_field(hid, report->field[n], data, interrupt);
 
 	if (hid->claimed & HID_CLAIMED_INPUT)
+	{
+//	printk("---2----%s----------\n",__func__);
+//	prom_printf("---2----%s----------\n",__func__);
 		hidinput_report_event(hid, report);
+	}
 
 	return 0;
 }
diff -uNra linux-2.6.27.6/drivers/hid/hid-input.c linux-2.6.27.6.yaffs/drivers/hid/hid-input.c
--- linux-2.6.27.6/drivers/hid/hid-input.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/hid/hid-input.c	2011-05-08 18:00:15.000000000 +0800
@@ -167,6 +167,7 @@
 {
 	struct hidinput_key_translation *trans;
 
+//	printk("-------%s----------\n",__func__);
 	/* Look for the translation */
 	for (trans = table; trans->from; trans++)
 		if (trans->from == from)
@@ -180,6 +181,7 @@
 {
 	struct hidinput_key_translation *trans;
 
+//	printk("-------%s----------\n",__func__);
 	if (usage->code == KEY_FN) {
 		if (value) hid->quirks |=  HID_QUIRK_APPLE_FN_ON;
 		else       hid->quirks &= ~HID_QUIRK_APPLE_FN_ON;
@@ -282,6 +284,7 @@
 
 static inline int match_scancode(int code, int scancode)
 {
+//	printk("-------%s----------\n",__func__);
 	if (scancode == 0)
 		return 1;
 	return ((code & (HID_USAGE_PAGE | HID_USAGE)) == scancode);
@@ -289,11 +292,13 @@
 
 static inline int match_keycode(int code, int keycode)
 {
+//	printk("-------%s----------\n",__func__);
 	if (keycode == 0)
 		return 1;
 	return (code == keycode);
 }
 
+void prom_printf();
 static struct hid_usage *hidinput_find_key(struct hid_device *hid,
 		int scancode, int keycode)
 {
@@ -301,6 +306,7 @@
 	struct hid_report *report;
 	struct hid_usage *usage;
 
+//	printk("-------%s----------\n",__func__);
 	for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) {
 		list_for_each_entry(report, &hid->report_enum[k].report_list, list) {
 			for (i = 0; i < report->maxfield; i++) {
@@ -309,7 +315,11 @@
 					if (usage->type == EV_KEY &&
 						match_scancode(usage->hid, scancode) &&
 						match_keycode(usage->code, keycode))
+					{
+//	prom_printf("-------mj hidkbd- find------------\n");
+//	printk("-------mj hidkbd---find----------\n");
 						return usage;
+					}
 				}
 			}
 		}
@@ -323,6 +333,8 @@
 	struct hid_device *hid = input_get_drvdata(dev);
 	struct hid_usage *usage;
 
+//	prom_printf("-------mj hidkbd-------------\n");
+//	printk("-------mj hidkbd-------------\n");
 	usage = hidinput_find_key(hid, scancode, 0);
 	if (usage) {
 		*keycode = usage->code;
@@ -364,11 +376,14 @@
 static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_field *field,
 				     struct hid_usage *usage)
 {
+
 	struct input_dev *input = hidinput->input;
 	struct hid_device *device = input_get_drvdata(input);
 	int max = 0, code, ret;
 	unsigned long *bit = NULL;
 
+//	printk("-------%s----------\n",__func__);
+//	prom_printf("-------%s----------\n",__func__);
 	field->hidinput = hidinput;
 
 	dbg_hid("Mapping: ");
@@ -850,6 +865,7 @@
 	struct input_dev *input;
 	unsigned *quirks = &hid->quirks;
 
+//	printk("-------%s----------\n",__func__);
 	if (!field->hidinput)
 		return;
 
@@ -935,6 +951,8 @@
 {
 	struct hid_input *hidinput;
 
+//	printk("-------%s----------\n",__func__);
+//	prom_printf("-------%s----------\n",__func__);
 	list_for_each_entry(hidinput, &hid->inputs, list)
 		input_sync(hidinput->input);
 }
@@ -988,6 +1006,7 @@
 	if (hid->quirks & HID_QUIRK_IGNORE_HIDINPUT)
 		return -1;
 
+	printk("-------%s----------\n",__func__);
 	INIT_LIST_HEAD(&hid->inputs);
 
 	for (i = 0; i < hid->maxcollection; i++)
@@ -1058,6 +1077,7 @@
 	if (hidinput && input_register_device(hidinput->input))
 		goto out_cleanup;
 
+	printk("----2---%s----------\n",__func__);
 	return 0;
 
 out_cleanup:
diff -uNra linux-2.6.27.6/drivers/hid/hid-input-quirks.c linux-2.6.27.6.yaffs/drivers/hid/hid-input-quirks.c
--- linux-2.6.27.6/drivers/hid/hid-input-quirks.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/hid/hid-input-quirks.c	2011-05-08 18:00:16.000000000 +0800
@@ -394,7 +394,10 @@
 	while (hid_input_blacklist[i].quirk) {
 		if (hid_input_blacklist[i].idVendor == device->vendor &&
 				hid_input_blacklist[i].idProduct == device->product)
+		{
+//			printk("------mj hid quirks-----------------\n");
 			return hid_input_blacklist[i].quirk(usage, input, bit, max);
+		}
 		i++;
 	}
 	return 0;
diff -uNra linux-2.6.27.6/drivers/hid/usbhid/hid-core.c linux-2.6.27.6.yaffs/drivers/hid/usbhid/hid-core.c
--- linux-2.6.27.6/drivers/hid/usbhid/hid-core.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/hid/usbhid/hid-core.c	2011-05-08 18:00:15.000000000 +0800
@@ -190,14 +190,19 @@
  * Input interrupt completion handler.
  */
 
+void prom_printf();
 static void hid_irq_in(struct urb *urb)
 {
 	struct hid_device	*hid = urb->context;
 	struct usbhid_device 	*usbhid = hid->driver_data;
 	int			status;
 
+//	printk("--->>>>----%s----------\n",__func__);
+//	prom_printf("---1----%s----------\n",__func__);
 	switch (urb->status) {
 		case 0:			/* success */
+//	printk("---2----%s----------\n",__func__);
+//	prom_printf("---2----%s----------\n",__func__);
 			usbhid->retry_delay = 0;
 			hid_input_report(urb->context, HID_INPUT_REPORT,
 					 urb->transfer_buffer,
@@ -235,6 +240,7 @@
 			hid_io_error(hid);
 		}
 	}
+//	printk("---<<<----%s----------\n",__func__);
 }
 
 static int hid_submit_out(struct hid_device *hid)
@@ -700,7 +706,6 @@
 
 	kfree(buf);
 }
-
 static struct hid_device *usb_hid_configure(struct usb_interface *intf)
 {
 	struct usb_host_interface *interface = intf->cur_altsetting;
@@ -713,6 +718,8 @@
 	int n, len;
 	struct usbhid_device *usbhid;
 
+//	printk("---1----%s----------\n",__func__);
+//	prom_printf("---1----%s----------\n",__func__);
 	quirks = usbhid_lookup_quirk(le16_to_cpu(dev->descriptor.idVendor),
 			le16_to_cpu(dev->descriptor.idProduct));
 
@@ -849,6 +856,9 @@
 			if (!(usbhid->urbin = usb_alloc_urb(0, GFP_KERNEL)))
 				goto fail;
 			pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress);
+
+//	printk("---2----%s----------\n",__func__);
+//	prom_printf("---2----%s----------\n",__func__);
 			usb_fill_int_urb(usbhid->urbin, dev, pipe, usbhid->inbuf, insize,
 					 hid_irq_in, hid, interval);
 			usbhid->urbin->transfer_dma = usbhid->inbuf_dma;
diff -uNra linux-2.6.27.6/drivers/input/input.c linux-2.6.27.6.yaffs/drivers/input/input.c
--- linux-2.6.27.6/drivers/input/input.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/input/input.c	2011-05-08 18:00:23.000000000 +0800
@@ -77,13 +77,20 @@
 
 	handle = rcu_dereference(dev->grab);
 	if (handle)
+	{//printk("---1----%s-,key :---%08x--set:%08x-:--\n",__func__,handle,(int)handle->handler->event);
 		handle->handler->event(handle, type, code, value);
+	}
 	else
 		list_for_each_entry_rcu(handle, &dev->h_list, d_node)
 			if (handle->open)
+			{
 				handle->handler->event(handle,
+
 							type, code, value);
+//	printk("---2----%s-,key :---%08x--set:%08x-:--\n",__func__,handle,(int)handle->handler->event);
+			}
 	rcu_read_unlock();
+//	printk("---1----%s-,key :---%08x--set:%08x-:--\n",__func__,handle,(int)handle->handler->event);
 }
 
 /*
@@ -98,11 +105,13 @@
 
 	spin_lock_irqsave(&dev->event_lock, flags);
 
+//	printk("---1----%s-,key :---%08x--set:%08x-:get:%08x--\n",__func__,dev->repeat_key,dev->setkeycode,dev->getkeycode);
 	if (test_bit(dev->repeat_key, dev->key) &&
 	    is_event_supported(dev->repeat_key, dev->keybit, KEY_MAX)) {
 
 		input_pass_event(dev, EV_KEY, dev->repeat_key, 2);
 
+//	printk("---2----%s-,code :--------\n",__func__);
 		if (dev->sync) {
 			/*
 			 * Only send SYN_REPORT if we are not in a middle
@@ -110,6 +119,7 @@
 			 * Otherwise assume that the driver will send
 			 * SYN_REPORT once it's done.
 			 */
+//	printk("---3----%s-,code :--------\n",__func__);
 			input_pass_event(dev, EV_SYN, SYN_REPORT, 1);
 		}
 
@@ -126,6 +136,7 @@
 	if (test_bit(EV_REP, dev->evbit) &&
 	    dev->rep[REP_PERIOD] && dev->rep[REP_DELAY] &&
 	    dev->timer.data) {
+//	printk("---1----%s-,code :%08x--------\n",__func__,code);
 		dev->repeat_key = code;
 		mod_timer(&dev->timer,
 			  jiffies + msecs_to_jiffies(dev->rep[REP_DELAY]));
@@ -142,6 +153,7 @@
 {
 	int disposition = INPUT_IGNORE_EVENT;
 
+//	printk("---1----%s-type:%08x-,code :%08x,value :%08x--------\n",__func__,type,code,value);
 	switch (type) {
 
 	case EV_SYN:
@@ -166,6 +178,7 @@
 			if (value != 2) {
 				__change_bit(code, dev->key);
 				if (value)
+//	printk("---1----%s-type:%08x-,code :%08x,value :%08x--------\n",__func__,type,code,value);
 					input_start_autorepeat(dev, code);
 			}
 
@@ -243,13 +256,21 @@
 	}
 
 	if (disposition != INPUT_IGNORE_EVENT && type != EV_SYN)
+	{
 		dev->sync = 0;
-
+//	printk("---2----%s----------\n",__func__);
+	}
 	if ((disposition & INPUT_PASS_TO_DEVICE) && dev->event)
+	{
 		dev->event(dev, type, code, value);
+//	printk("---3----%s----------\n",__func__);
+	}
 
 	if (disposition & INPUT_PASS_TO_HANDLERS)
+	{
 		input_pass_event(dev, type, code, value);
+//	printk("---4----%s----------\n",__func__);
+	}
 }
 
 /**
@@ -268,13 +289,16 @@
 {
 	unsigned long flags;
 
+//	printk("---1----%s----------\n",__func__);
 	if (is_event_supported(type, dev->evbit, EV_MAX)) {
 
+//	printk("---2----%s----------\n",__func__);
 		spin_lock_irqsave(&dev->event_lock, flags);
 		add_input_randomness(type, code, value);
 		input_handle_event(dev, type, code, value);
 		spin_unlock_irqrestore(&dev->event_lock, flags);
 	}
+//	printk("---3----%s----------\n",__func__);
 }
 EXPORT_SYMBOL(input_event);
 
@@ -596,6 +620,8 @@
  */
 int input_get_keycode(struct input_dev *dev, int scancode, int *keycode)
 {
+
+//	printk("---1----%s----------\n",__func__);
 	if (scancode < 0)
 		return -EINVAL;
 
@@ -1612,7 +1638,8 @@
 	}
 	old_fops = file->f_op;
 	file->f_op = new_fops;
-
+//	printk("-------inde-%08x----------\n",new_fops->open);
+//	printk();
 	err = new_fops->open(inode, file);
 
 	if (err) {
diff -uNra linux-2.6.27.6/drivers/input/input-polldev.c linux-2.6.27.6.yaffs/drivers/input/input-polldev.c
--- linux-2.6.27.6/drivers/input/input-polldev.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/input/input-polldev.c	2011-05-08 18:00:20.000000000 +0800
@@ -25,6 +25,7 @@
 {
 	int retval;
 
+//	printk("->>>--1----%s----------\n",__func__);
 	retval = mutex_lock_interruptible(&polldev_mutex);
 	if (retval)
 		return retval;
@@ -43,6 +44,7 @@
 
  out:
 	mutex_unlock(&polldev_mutex);
+//	printk("---<<<----%s----------\n",__func__);
 	return retval;
 }
 
diff -uNra linux-2.6.27.6/drivers/input/keyboard/atkbd.c linux-2.6.27.6.yaffs/drivers/input/keyboard/atkbd.c
--- linux-2.6.27.6/drivers/input/keyboard/atkbd.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/input/keyboard/atkbd.c	2011-05-08 18:00:22.000000000 +0800
@@ -30,6 +30,7 @@
 #include <linux/dmi.h>
 
 #define DRIVER_DESC	"AT and PS/2 keyboard driver"
+void prom_printf(char *fmt, ...);
 
 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
 MODULE_DESCRIPTION(DRIVER_DESC);
@@ -332,6 +333,9 @@
  */
 static unsigned int atkbd_compat_scancode(struct atkbd *atkbd, unsigned int code)
 {
+
+//	prom_printf("------->>>>>>>>------%s-------\n",__func__);   //mj
+//	printk("------->>>>>>>>------%s-------\n",__func__);   //mj
 	if (atkbd->set == 3) {
 		if (atkbd->emul == 1)
 			code |= 0x100;
@@ -359,6 +363,8 @@
 	int value;
 	unsigned short keycode;
 
+//	prom_printf("--------%s------------\n",__func__); //mj
+//	printk("--------%s------------\n",__func__); //mj
 #ifdef ATKBD_DEBUG
 	printk(KERN_DEBUG "atkbd.c: Received %02x flags %02x\n", data, flags);
 #endif
diff -uNra linux-2.6.27.6/drivers/input/serio/i8042.c linux-2.6.27.6.yaffs/drivers/input/serio/i8042.c
--- linux-2.6.27.6/drivers/input/serio/i8042.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/input/serio/i8042.c	2011-05-08 18:00:21.000000000 +0800
@@ -23,6 +23,7 @@
 
 #include <asm/io.h>
 
+void prom_printf(char *fmt, ...);
 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
 MODULE_LICENSE("GPL");
@@ -311,6 +312,8 @@
 	unsigned int port_no;
 	int ret = 1;
 
+	prom_printf("------->>>>>>>>------%s-------\n",__func__);   //mj
+	printk("------->>>>>>>>------%s-------\n",__func__);   //mj
 	spin_lock_irqsave(&i8042_lock, flags);
 	str = i8042_read_status();
 	if (unlikely(~str & I8042_STR_OBF)) {
diff -uNra linux-2.6.27.6/drivers/mfd/i2c-sm502.c linux-2.6.27.6.yaffs/drivers/mfd/i2c-sm502.c
--- linux-2.6.27.6/drivers/mfd/i2c-sm502.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mfd/i2c-sm502.c	2011-05-08 18:00:26.000000000 +0800
@@ -0,0 +1,441 @@
+#include <linux/io.h>
+#include <asm/types.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <asm/serial.h>		/* For the serial port location and base baud */
+#include <linux/pci.h>
+
+
+#define DEVBD2F_SM502 
+extern struct pci_ops * loongson2f_pci_pci_ops;
+
+static unsigned long read_mmio(int renew)
+{
+	struct pci_bus bus;
+	struct pci_dev dev;
+	u32 tmp;
+	unsigned long mmio;
+	static unsigned long maped_mmio=0;
+
+	bus.ops=&loongson2f_pci_pci_ops;
+	dev.bus=&bus;
+	bus.number=0x0;
+	dev.devfn=0x70;
+	pci_read_config_dword(&dev,0x14,&tmp);
+	mmio=(tmp&~0xf);
+	if(mmio<0x20000000){
+	if(mmio<0x10000000)mmio |=0x10000000;
+	//return (mmio+0x30000)|0xffffffffa0000000;
+	return (mmio)|0xffffffffa0000000;
+	}
+	//else if(!maped_mmio) maped_mmio = ioremap_nocache(mmio,1*1024*1024)+0x30000;
+	else if(!maped_mmio) maped_mmio = ioremap_nocache(mmio,1*1024*1024);
+
+	return maped_mmio;
+}
+
+#define I2C_SINGLE 0
+#define I2C_BLOCK 1
+#define I2C_SMB_BLOCK 2
+
+
+#define GPIO_DIR_REG 		(volatile unsigned int *)(read_mmio(0)+ 0x1000c)
+#define GPIO_DATA_REG		(volatile unsigned int *)(read_mmio(0) + 0x10004)
+#define G_OUTPUT			1
+#define G_INPUT				0
+#define GPIO_SDA_DIR_SHIFT	15
+#define	GPIO_SCL_DIR_SHIFT	14
+#define GPIO_SDA_DATA_SHIFT	15
+#define GPIO_SCL_DATA_SHIFT	14
+
+
+static void i2c_sleep(int ntime)
+{
+	int i,j = 0;
+	for(i = 0; i < 300 * ntime; i++)
+	{
+		j = i;
+		j += i;
+	}
+}
+
+void sda_dir(int ivalue)
+{
+	int tmp;
+	tmp = *GPIO_DIR_REG;
+	if(ivalue == 1)
+		*GPIO_DIR_REG = tmp | (0x1 << GPIO_SDA_DIR_SHIFT);
+	else
+		*GPIO_DIR_REG = tmp & (~(0x1 << GPIO_SDA_DIR_SHIFT));
+}
+void scl_dir(int ivalue)
+{
+	int tmp;
+	tmp = *GPIO_DIR_REG;
+	if(ivalue == 1)
+		*GPIO_DIR_REG = tmp | (0x1 << GPIO_SCL_DIR_SHIFT);
+	else
+		*GPIO_DIR_REG = tmp & (~(0x1 << GPIO_SCL_DIR_SHIFT));
+}
+
+void sda_bit(int ivalue)
+{
+	int tmp;
+	tmp = *GPIO_DATA_REG;
+	if(ivalue == 1)
+		*GPIO_DATA_REG = tmp | (0x1 << GPIO_SDA_DATA_SHIFT);
+	else
+		*GPIO_DATA_REG = tmp & (~(0x1 << GPIO_SDA_DATA_SHIFT));
+}
+
+void scl_bit(int ivalue)
+{
+	int tmp;
+	tmp = *GPIO_DATA_REG;
+	if(ivalue == 1)
+		*GPIO_DATA_REG = tmp | (0x1 << GPIO_SCL_DATA_SHIFT);
+	else
+		*GPIO_DATA_REG = tmp & (~(0x1 << GPIO_SCL_DATA_SHIFT));
+}
+
+static void i2c_start(void)
+{
+	sda_dir(G_OUTPUT);
+	scl_dir(G_OUTPUT);
+	scl_bit(0);
+	i2c_sleep(1);
+	sda_bit(1);
+	i2c_sleep(1);
+	scl_bit(1);
+	i2c_sleep(5);
+	sda_bit(0);
+	i2c_sleep(5);
+	scl_bit(0);
+	i2c_sleep(2);
+}
+static void i2c_stop(void)
+{
+	sda_dir(G_OUTPUT);
+	scl_dir(G_OUTPUT);
+	scl_bit(0);
+	i2c_sleep(1);
+	sda_bit(0);
+	i2c_sleep(1);
+	scl_bit(1);
+	i2c_sleep(5);
+	sda_bit(1);
+	i2c_sleep(5);
+	scl_bit(0);
+	i2c_sleep(2);
+}
+
+static void i2c_send_ack(int ack)
+{
+	sda_dir(G_OUTPUT);
+	sda_bit(ack);
+	i2c_sleep(3);
+	scl_bit(1);
+	i2c_sleep(5);
+	scl_bit(0);
+	i2c_sleep(2);
+}
+
+static char i2c_rec_ack()
+{
+    char res = 1;
+    int num = 10;
+	int tmp;
+    sda_dir(G_INPUT);
+    i2c_sleep(3);
+    scl_bit(1);
+    i2c_sleep(5);
+	tmp = ((*GPIO_DATA_REG) & (0x1 << GPIO_SDA_DATA_SHIFT));
+        //wait for a ack signal from slave
+
+     while(tmp)
+     {
+		i2c_sleep(1);
+        num--;
+        if(!num)
+        {
+			res = 0;
+            break;
+        }
+		tmp = ((*GPIO_DATA_REG) & (0x1 << GPIO_SDA_DATA_SHIFT));
+        }
+    scl_bit(0);
+    i2c_sleep(3);
+    return res;
+}
+
+static unsigned char i2c_rec()
+{
+	int i;
+	int tmp;
+	unsigned char or_char;
+	unsigned char value = 0x00;
+	sda_dir(G_INPUT);
+	for(i = 7;i >= 0;i--)
+	{
+		i2c_sleep(5);
+		scl_bit(1);
+		i2c_sleep(3);
+		tmp = ((*GPIO_DATA_REG) & (0x1 << GPIO_SDA_DATA_SHIFT));
+		if(tmp)
+			or_char = 0x1;
+		else
+			or_char = 0x0;
+		or_char <<= i;
+		value |= or_char;
+		i2c_sleep(3);
+		scl_bit(0);
+	}
+	return value;
+}
+
+static unsigned char i2c_send(unsigned char value)
+{
+	//we assume that now scl is 0
+	int i;
+	unsigned char and_char;
+	sda_dir(G_OUTPUT);
+	for(i = 7;i >= 0;i--)
+	{
+		and_char = value;
+		and_char >>= i;
+		and_char &= 0x1;
+		if(and_char)
+			sda_bit(1);
+		else
+			sda_bit(0);
+		i2c_sleep(1);
+		scl_bit(1);
+		i2c_sleep(5);
+		scl_bit(0);
+		i2c_sleep(1);
+	}
+	sda_bit(1);	
+	return 1;
+}
+
+unsigned char i2c_rec_s(unsigned char *addr,int addrlen,unsigned char reg,unsigned char* buf ,int count)
+{
+	int i;
+	int j;
+	unsigned char value;
+	//start signal
+	for(i = 0;i < count;i++)
+	{
+		i2c_start();
+		for(j = 0;j < addrlen;j++)
+		{
+		//write slave_addr
+		i2c_send(addr[j]);
+		if(!i2c_rec_ack())
+			return 0;
+		}
+
+		i2c_send(reg);
+		if(!i2c_rec_ack())
+			return 0;
+
+		//repeat start
+		i2c_start();
+		//write slave_addr+1
+		i2c_send(addr[0] | 0x1);
+		if(!i2c_rec_ack())
+			return 0;
+		//read data
+		buf[i] = i2c_rec();	
+//		i2c_send_ack(1);//***add in***//
+		i2c_stop();
+		reg++;
+	}
+	return count;
+}
+
+unsigned char i2c_send_s(unsigned char *addr,int addrlen,unsigned char reg,unsigned char * buf ,int count)
+{
+	int i;
+	int j;
+	for(i = 0;i < count;i++)
+	{	
+		i2c_start();	
+		for(j = 0;j < addrlen;j++)
+		{
+		//write slave_addr
+		i2c_send(addr[j]);
+		if(!i2c_rec_ack())
+			return 0;
+		}
+
+		i2c_send(reg);
+		if(!i2c_rec_ack())
+			return 0;
+
+		i2c_send(buf[i]);
+		if(!i2c_rec_ack())
+			return 0;
+		i2c_stop();
+		reg++;
+	}
+	return 1;
+}
+
+unsigned char i2c_rec_b(unsigned char *addr,int addrlen,unsigned char reg,unsigned char* buf ,int count)
+{
+	int i;
+	int j;
+	unsigned char value;
+	//start signal
+	i2c_start();
+	for(j = 0;j < addrlen;j++)
+	{
+		//write slave_addr
+		i2c_send(addr[j]);
+		if(!i2c_rec_ack())
+			return 0;
+	}
+
+	i2c_send(reg);
+	if(!i2c_rec_ack())
+		return 0;
+
+	//repeat start
+	i2c_start();
+	//write slave_addr+1
+	i2c_send(addr[0] | 0x1);
+	if(!i2c_rec_ack())
+		return 0;
+
+	for(i = 0;i < count;i++)
+	{
+		//read data
+		buf[i] = i2c_rec();	
+//		i2c_send_ack(1);//***add in***//
+		
+	}
+	i2c_stop();
+	return count;
+}
+unsigned char i2c_send_b(unsigned char *addr,int addrlen,unsigned char reg,unsigned char * buf ,int count)
+{
+	int i;
+	int j;
+	i2c_start();	
+	for(j = 0;j < addrlen;j++)
+	{
+		//write slave_addr
+		i2c_send(addr[j]);
+		if(!i2c_rec_ack())
+			return 0;
+	}
+
+	i2c_send(reg);
+	if(!i2c_rec_ack())
+		return 0;
+
+	for(i = 0;i < count;i++)
+	{
+		i2c_send(buf[i]);
+		if(!i2c_rec_ack())
+			return 0;
+	}
+	i2c_stop();
+	return count;
+}
+//----------------------
+/*
+ * 0 single:
+ * 1 smb block
+ */
+ static void * my_memset(void * s,int c, size_t count)
+	  {
+		char *xs = (char *) s;
+	
+		while (count--)
+			*xs++ = c;
+	
+				return s;
+			 }
+#if 1
+int tgt_i2cinit1()
+{
+	int tmp;
+	unsigned long mmio=read_mmio(0);
+    // mmio = sm50x_base_reg;
+		tmp = *(volatile long *)(mmio + 0x40);
+		*(volatile long *)(mmio + 0x40) = tmp | 0x40;
+		return 0;
+//		tgt_printf("clock enable bit 40 = %x\n", *(volatile int *)(mmio + 0x40));
+}
+void prom_printf(char *fmt, ...);
+int tgt_i2cinit()
+{
+#if 1
+	static int inited = 0;
+	unsigned long tmp;
+	unsigned long mmio=read_mmio(0);
+    
+	if(inited == 0 && (mmio & 0x80000000) )
+	{
+		//mmio = mmio | (0xb0000000);
+		tmp = *(volatile long *)(mmio + 0x40);
+		*(volatile long *)(mmio + 0x40) = tmp | 0x40;
+//		tgt_printf("clock enable bit 40 = %x\n", *(volatile int *)(mmio + 0x40));
+//	prom_printf("------1--inited:%d---\n",inited);
+		inited += 1;
+	}
+	else if (inited == 1 && !(mmio & 0x80000000) )
+	{
+		//mmio = mmio | (0xb0000000);
+		tmp = *(volatile long *)(mmio + 0x40);
+		*(volatile long *)(mmio + 0x40) = tmp | 0x40;
+//		tgt_printf("clock enable bit 40 = %x\n", *(volatile int *)(mmio + 0x40));
+//	prom_printf("------2--inited:%d---\n",inited);
+		inited += 1;
+
+	}
+#endif
+	return 0;
+}
+#endif
+int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count)
+{
+	int i;
+	tgt_i2cinit();
+//	prom_printf("------1--read_mmio:%08x---\n",read_mmio(0));
+	my_memset(buf,-1,count);
+//	prom_printf("------2-----\n");
+	switch(type)
+	{
+		case I2C_SINGLE:
+			return i2c_rec_s(addr,addrlen,reg,buf,count);
+		break;
+		case I2C_BLOCK:
+			return i2c_rec_b(addr,addrlen,reg,buf,count);
+		break;
+
+		default: return 0;break;
+	}
+	return 0;
+}
+
+int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count)
+{
+	tgt_i2cinit();
+	switch(type & 0xff)
+	{
+		case I2C_SINGLE:
+			i2c_send_s(addr,addrlen,reg,buf,count);
+		break;
+		case I2C_BLOCK:
+			return i2c_send_b(addr,addrlen,reg,buf,count);
+		break;
+		case I2C_SMB_BLOCK:
+		break;
+		default:return -1;break;
+	}
+	return -1;
+}
+
diff -uNra linux-2.6.27.6/drivers/mfd/oldsm501.c linux-2.6.27.6.yaffs/drivers/mfd/oldsm501.c
--- linux-2.6.27.6/drivers/mfd/oldsm501.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mfd/oldsm501.c	2011-05-08 18:00:26.000000000 +0800
@@ -0,0 +1,1742 @@
+/* linux/drivers/mfd/sm501.c
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	Vincent Sanders <vince@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * SM501 MFD driver
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/i2c-gpio.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501-regs.h>
+#include <linux/serial_8250.h>
+
+#include <asm/io.h>
+
+struct sm501_device {
+	struct list_head		list;
+	struct platform_device		pdev;
+};
+
+struct sm501_gpio;
+
+#ifdef CONFIG_MFD_SM501_GPIO
+#include <linux/gpio.h>
+
+struct sm501_gpio_chip {
+	struct gpio_chip	gpio;
+	struct sm501_gpio	*ourgpio;	/* to get back to parent. */
+	void __iomem		*regbase;
+};
+
+struct sm501_gpio {
+	struct sm501_gpio_chip	low;
+	struct sm501_gpio_chip	high;
+	spinlock_t		lock;
+
+	unsigned int		 registered : 1;
+	void __iomem		*regs;
+	struct resource		*regs_res;
+};
+#else
+struct sm501_gpio {
+	/* no gpio support, empty definition for sm501_devdata. */
+};
+#endif
+
+struct sm501_devdata {
+	spinlock_t			 reg_lock;
+	struct mutex			 clock_lock;
+	struct list_head		 devices;
+	struct sm501_gpio		 gpio;
+
+	struct device			*dev;
+	struct resource			*io_res;
+	struct resource			*mem_res;
+	struct resource			*regs_claim;
+	struct sm501_platdata		*platdata;
+
+
+	unsigned int			 in_suspend;
+	unsigned long			 pm_misc;
+
+	int				 unit_power[20];
+	unsigned int			 pdev_id;
+	unsigned int			 irq;
+	void __iomem			*regs;
+	unsigned int			 rev;
+};
+
+
+#define MHZ (1000 * 1000)
+
+#ifdef DEBUG
+static const unsigned int div_tab[] = {
+	[0]		= 1,
+	[1]		= 2,
+	[2]		= 4,
+	[3]		= 8,
+	[4]		= 16,
+	[5]		= 32,
+	[6]		= 64,
+	[7]		= 128,
+	[8]		= 3,
+	[9]		= 6,
+	[10]	        = 12,
+	[11]		= 24,
+	[12]		= 48,
+	[13]		= 96,
+	[14]		= 192,
+	[15]		= 384,
+	[16]		= 5,
+	[17]		= 10,
+	[18]		= 20,
+	[19]		= 40,
+	[20]		= 80,
+	[21]		= 160,
+	[22]		= 320,
+	[23]		= 604,
+};
+
+static unsigned long decode_div(unsigned long pll2, unsigned long val,
+				unsigned int lshft, unsigned int selbit,
+				unsigned long mask)
+{
+	if (val & selbit)
+		pll2 = 288 * MHZ;
+
+	return pll2 / div_tab[(val >> lshft) & mask];
+}
+
+#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
+
+/* sm501_dump_clk
+ *
+ * Print out the current clock configuration for the device
+*/
+
+static void sm501_dump_clk(struct sm501_devdata *sm)
+{
+	unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
+	unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
+	unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
+	unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
+	unsigned long sdclk0, sdclk1;
+	unsigned long pll2 = 0;
+
+	switch (misct & 0x30) {
+	case 0x00:
+		pll2 = 336 * MHZ;
+		break;
+	case 0x10:
+		pll2 = 288 * MHZ;
+		break;
+	case 0x20:
+		pll2 = 240 * MHZ;
+		break;
+	case 0x30:
+		pll2 = 192 * MHZ;
+		break;
+	}
+
+	sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
+	sdclk0 /= div_tab[((misct >> 8) & 0xf)];
+
+	sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
+	sdclk1 /= div_tab[((misct >> 16) & 0xf)];
+
+	dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
+		misct, pm0, pm1);
+
+	dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
+		fmt_freq(pll2), sdclk0, sdclk1);
+
+	dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
+
+	dev_dbg(sm->dev, "PM0[%c]: "
+		 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
+		 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
+		 (pmc & 3 ) == 0 ? '*' : '-',
+		 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
+		 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
+		 fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
+		 fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
+
+	dev_dbg(sm->dev, "PM1[%c]: "
+		"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
+		"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
+		(pmc & 3 ) == 1 ? '*' : '-',
+		fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
+		fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
+		fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
+		fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
+}
+
+static void sm501_dump_regs(struct sm501_devdata *sm)
+{
+	void __iomem *regs = sm->regs;
+
+	dev_info(sm->dev, "System Control   %08x\n",
+			readl(regs + SM501_SYSTEM_CONTROL));
+	dev_info(sm->dev, "Misc Control     %08x\n",
+			readl(regs + SM501_MISC_CONTROL));
+	dev_info(sm->dev, "GPIO Control Low %08x\n",
+			readl(regs + SM501_GPIO31_0_CONTROL));
+	dev_info(sm->dev, "GPIO Control Hi  %08x\n",
+			readl(regs + SM501_GPIO63_32_CONTROL));
+	dev_info(sm->dev, "DRAM Control     %08x\n",
+			readl(regs + SM501_DRAM_CONTROL));
+	dev_info(sm->dev, "Arbitration Ctrl %08x\n",
+			readl(regs + SM501_ARBTRTN_CONTROL));
+	dev_info(sm->dev, "Misc Timing      %08x\n",
+			readl(regs + SM501_MISC_TIMING));
+}
+
+static void sm501_dump_gate(struct sm501_devdata *sm)
+{
+	dev_info(sm->dev, "CurrentGate      %08x\n",
+			readl(sm->regs + SM501_CURRENT_GATE));
+	dev_info(sm->dev, "CurrentClock     %08x\n",
+			readl(sm->regs + SM501_CURRENT_CLOCK));
+	dev_info(sm->dev, "PowerModeControl %08x\n",
+			readl(sm->regs + SM501_POWER_MODE_CONTROL));
+}
+
+#else
+static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
+static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
+static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
+#endif
+
+/* sm501_sync_regs
+ *
+ * ensure the
+*/
+
+static void sm501_sync_regs(struct sm501_devdata *sm)
+{
+	readl(sm->regs);
+}
+
+static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
+{
+	/* during suspend/resume, we are currently not allowed to sleep,
+	 * so change to using mdelay() instead of msleep() if we
+	 * are in one of these paths */
+
+	if (sm->in_suspend)
+		mdelay(delay);
+	else
+		msleep(delay);
+}
+
+/* sm501_misc_control
+ *
+ * alters the miscellaneous control parameters
+*/
+
+int sm501_misc_control(struct device *dev,
+		       unsigned long set, unsigned long clear)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long misc;
+	unsigned long save;
+	unsigned long to;
+
+	spin_lock_irqsave(&sm->reg_lock, save);
+
+	misc = readl(sm->regs + SM501_MISC_CONTROL);
+	to = (misc & ~clear) | set;
+
+	if (to != misc) {
+		writel(to, sm->regs + SM501_MISC_CONTROL);
+		sm501_sync_regs(sm);
+
+		dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
+	}
+
+	spin_unlock_irqrestore(&sm->reg_lock, save);
+	return to;
+}
+
+EXPORT_SYMBOL_GPL(sm501_misc_control);
+
+/* sm501_modify_reg
+ *
+ * Modify a register in the SM501 which may be shared with other
+ * drivers.
+*/
+
+unsigned long sm501_modify_reg(struct device *dev,
+			       unsigned long reg,
+			       unsigned long set,
+			       unsigned long clear)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long data;
+	unsigned long save;
+
+	spin_lock_irqsave(&sm->reg_lock, save);
+
+	data = readl(sm->regs + reg);
+	data |= set;
+	data &= ~clear;
+
+	writel(data, sm->regs + reg);
+	sm501_sync_regs(sm);
+
+	spin_unlock_irqrestore(&sm->reg_lock, save);
+
+	return data;
+}
+
+EXPORT_SYMBOL_GPL(sm501_modify_reg);
+
+/* sm501_unit_power
+ *
+ * alters the power active gate to set specific units on or off
+ */
+
+int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long mode;
+	unsigned long gate;
+	unsigned long clock;
+
+	mutex_lock(&sm->clock_lock);
+
+	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
+	gate = readl(sm->regs + SM501_CURRENT_GATE);
+	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
+
+	mode &= 3;		/* get current power mode */
+
+	if (unit >= ARRAY_SIZE(sm->unit_power)) {
+		dev_err(dev, "%s: bad unit %d\n", __func__, unit);
+		goto already;
+	}
+
+	dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
+		sm->unit_power[unit], to);
+
+	if (to == 0 && sm->unit_power[unit] == 0) {
+		dev_err(sm->dev, "unit %d is already shutdown\n", unit);
+		goto already;
+	}
+
+	sm->unit_power[unit] += to ? 1 : -1;
+	to = sm->unit_power[unit] ? 1 : 0;
+
+	if (to) {
+		if (gate & (1 << unit))
+			goto already;
+		gate |= (1 << unit);
+	} else {
+		if (!(gate & (1 << unit)))
+			goto already;
+		gate &= ~(1 << unit);
+	}
+
+	switch (mode) {
+	case 1:
+		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
+		mode = 0;
+		break;
+	case 2:
+	case 0:
+		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
+		mode = 1;
+		break;
+
+	default:
+		return -1;
+	}
+
+	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
+	sm501_sync_regs(sm);
+
+	dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
+		gate, clock, mode);
+
+	sm501_mdelay(sm, 16);
+
+ already:
+	mutex_unlock(&sm->clock_lock);
+	return gate;
+}
+
+EXPORT_SYMBOL_GPL(sm501_unit_power);
+
+
+/* Perform a rounded division. */
+static long sm501fb_round_div(long num, long denom)
+{
+        /* n / d + 1 / 2 = (2n + d) / 2d */
+        return (2 * num + denom) / (2 * denom);
+}
+
+/* clock value structure. */
+struct sm501_clock {
+	unsigned long mclk;
+	int divider;
+	int shift;
+	unsigned int m, n, k;
+};
+
+/* sm501_calc_clock
+ *
+ * Calculates the nearest discrete clock frequency that
+ * can be achieved with the specified input clock.
+ *   the maximum divisor is 3 or 5
+ */
+
+static int sm501_calc_clock(unsigned long freq,
+			    struct sm501_clock *clock,
+			    int max_div,
+			    unsigned long mclk,
+			    long *best_diff)
+{
+	int ret = 0;
+	int divider;
+	int shift;
+	long diff;
+
+	/* try dividers 1 and 3 for CRT and for panel,
+	   try divider 5 for panel only.*/
+
+	for (divider = 1; divider <= max_div; divider += 2) {
+		/* try all 8 shift values.*/
+		for (shift = 0; shift < 8; shift++) {
+			/* Calculate difference to requested clock */
+			diff = sm501fb_round_div(mclk, divider << shift) - freq;
+			if (diff < 0)
+				diff = -diff;
+
+			/* If it is less than the current, use it */
+			if (diff < *best_diff) {
+				*best_diff = diff;
+
+				clock->mclk = mclk;
+				clock->divider = divider;
+				clock->shift = shift;
+				ret = 1;
+			}
+		}
+	}
+
+	return ret;
+}
+
+/* sm501_calc_pll
+ *
+ * Calculates the nearest discrete clock frequency that can be
+ * achieved using the programmable PLL.
+ *   the maximum divisor is 3 or 5
+ */
+
+static unsigned long sm501_calc_pll(unsigned long freq,
+					struct sm501_clock *clock,
+					int max_div)
+{
+	unsigned long mclk;
+	unsigned int m, n, k;
+	long best_diff = 999999999;
+
+	/*
+	 * The SM502 datasheet doesn't specify the min/max values for M and N.
+	 * N = 1 at least doesn't work in practice.
+	 */
+	for (m = 2; m <= 255; m++) {
+		for (n = 2; n <= 127; n++) {
+			for (k = 0; k <= 1; k++) {
+				mclk = (24000000UL * m / n) >> k;
+
+				if (sm501_calc_clock(freq, clock, max_div,
+						     mclk, &best_diff)) {
+					clock->m = m;
+					clock->n = n;
+					clock->k = k;
+				}
+			}
+		}
+	}
+
+	/* Return best clock. */
+	return clock->mclk / (clock->divider << clock->shift);
+}
+
+/* sm501_select_clock
+ *
+ * Calculates the nearest discrete clock frequency that can be
+ * achieved using the 288MHz and 336MHz PLLs.
+ *   the maximum divisor is 3 or 5
+ */
+
+static unsigned long sm501_select_clock(unsigned long freq,
+					struct sm501_clock *clock,
+					int max_div)
+{
+	unsigned long mclk;
+	long best_diff = 999999999;
+
+	/* Try 288MHz and 336MHz clocks. */
+	for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
+		sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
+	}
+
+	/* Return best clock. */
+	return clock->mclk / (clock->divider << clock->shift);
+}
+
+/* sm501_set_clock
+ *
+ * set one of the four clock sources to the closest available frequency to
+ *  the one specified
+*/
+
+unsigned long sm501_set_clock(struct device *dev,
+			      int clksrc,
+			      unsigned long req_freq)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
+	unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
+	unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
+	unsigned char reg;
+	unsigned int pll_reg = 0;
+	unsigned long sm501_freq; /* the actual frequency acheived */
+
+	struct sm501_clock to;
+
+	/* find achivable discrete frequency and setup register value
+	 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
+	 * has an extra bit for the divider */
+
+	switch (clksrc) {
+	case SM501_CLOCK_P2XCLK:
+		/* This clock is divided in half so to achive the
+		 * requested frequency the value must be multiplied by
+		 * 2. This clock also has an additional pre divisor */
+
+		if (sm->rev >= 0xC0) {
+			/* SM502 -> use the programmable PLL */
+			sm501_freq = (sm501_calc_pll(2 * req_freq,
+						     &to, 5) / 2);
+			reg = to.shift & 0x07;/* bottom 3 bits are shift */
+			if (to.divider == 3)
+				reg |= 0x08; /* /3 divider required */
+			else if (to.divider == 5)
+				reg |= 0x10; /* /5 divider required */
+			reg |= 0x40; /* select the programmable PLL */
+			pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
+		} else {
+			sm501_freq = (sm501_select_clock(2 * req_freq,
+							 &to, 5) / 2);
+			reg = to.shift & 0x07;/* bottom 3 bits are shift */
+			if (to.divider == 3)
+				reg |= 0x08; /* /3 divider required */
+			else if (to.divider == 5)
+				reg |= 0x10; /* /5 divider required */
+			if (to.mclk != 288000000)
+				reg |= 0x20; /* which mclk pll is source */
+		}
+		break;
+
+	case SM501_CLOCK_V2XCLK:
+		/* This clock is divided in half so to achive the
+		 * requested frequency the value must be multiplied by 2. */
+
+		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
+		reg=to.shift & 0x07;	/* bottom 3 bits are shift */
+		if (to.divider == 3)
+			reg |= 0x08;	/* /3 divider required */
+		if (to.mclk != 288000000)
+			reg |= 0x10;	/* which mclk pll is source */
+		break;
+
+	case SM501_CLOCK_MCLK:
+	case SM501_CLOCK_M1XCLK:
+		/* These clocks are the same and not further divided */
+
+		sm501_freq = sm501_select_clock( req_freq, &to, 3);
+		reg=to.shift & 0x07;	/* bottom 3 bits are shift */
+		if (to.divider == 3)
+			reg |= 0x08;	/* /3 divider required */
+		if (to.mclk != 288000000)
+			reg |= 0x10;	/* which mclk pll is source */
+		break;
+
+	default:
+		return 0; /* this is bad */
+	}
+
+	mutex_lock(&sm->clock_lock);
+
+	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
+	gate = readl(sm->regs + SM501_CURRENT_GATE);
+	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
+
+	clock = clock & ~(0xFF << clksrc);
+	clock |= reg<<clksrc;
+
+	mode &= 3;	/* find current mode */
+
+	switch (mode) {
+	case 1:
+		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
+		mode = 0;
+		break;
+	case 2:
+	case 0:
+		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
+		mode = 1;
+		break;
+
+	default:
+		mutex_unlock(&sm->clock_lock);
+		return -1;
+	}
+
+	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
+
+	if (pll_reg)
+		writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
+
+	sm501_sync_regs(sm);
+
+	dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
+		 gate, clock, mode);
+
+	sm501_mdelay(sm, 16);
+	mutex_unlock(&sm->clock_lock);
+
+	sm501_dump_clk(sm);
+
+	return sm501_freq;
+}
+
+EXPORT_SYMBOL_GPL(sm501_set_clock);
+
+/* sm501_find_clock
+ *
+ * finds the closest available frequency for a given clock
+*/
+
+unsigned long sm501_find_clock(struct device *dev,
+			       int clksrc,
+			       unsigned long req_freq)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long sm501_freq; /* the frequency achiveable by the 501 */
+	struct sm501_clock to;
+
+	switch (clksrc) {
+	case SM501_CLOCK_P2XCLK:
+		if (sm->rev >= 0xC0) {
+			/* SM502 -> use the programmable PLL */
+			sm501_freq = (sm501_calc_pll(2 * req_freq,
+						     &to, 5) / 2);
+		} else {
+			sm501_freq = (sm501_select_clock(2 * req_freq,
+							 &to, 5) / 2);
+		}
+		break;
+
+	case SM501_CLOCK_V2XCLK:
+		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
+		break;
+
+	case SM501_CLOCK_MCLK:
+	case SM501_CLOCK_M1XCLK:
+		sm501_freq = sm501_select_clock(req_freq, &to, 3);
+		break;
+
+	default:
+		sm501_freq = 0;		/* error */
+	}
+
+	return sm501_freq;
+}
+
+EXPORT_SYMBOL_GPL(sm501_find_clock);
+
+static struct sm501_device *to_sm_device(struct platform_device *pdev)
+{
+	return container_of(pdev, struct sm501_device, pdev);
+}
+
+/* sm501_device_release
+ *
+ * A release function for the platform devices we create to allow us to
+ * free any items we allocated
+*/
+
+static void sm501_device_release(struct device *dev)
+{
+	kfree(to_sm_device(to_platform_device(dev)));
+}
+
+/* sm501_create_subdev
+ *
+ * Create a skeleton platform device with resources for passing to a
+ * sub-driver
+*/
+
+static struct platform_device *
+sm501_create_subdev(struct sm501_devdata *sm, char *name,
+		    unsigned int res_count, unsigned int platform_data_size)
+{
+	struct sm501_device *smdev;
+
+	smdev = kzalloc(sizeof(struct sm501_device) +
+			(sizeof(struct resource) * res_count) +
+			platform_data_size, GFP_KERNEL);
+	if (!smdev)
+		return NULL;
+
+	smdev->pdev.dev.release = sm501_device_release;
+
+	smdev->pdev.name = name;
+	smdev->pdev.id = sm->pdev_id;
+	smdev->pdev.dev.parent = sm->dev;
+
+	if (res_count) {
+		smdev->pdev.resource = (struct resource *)(smdev+1);
+		smdev->pdev.num_resources = res_count;
+	}
+	if (platform_data_size)
+		smdev->pdev.dev.platform_data = (void *)(smdev+1);
+
+	return &smdev->pdev;
+}
+
+/* sm501_register_device
+ *
+ * Register a platform device created with sm501_create_subdev()
+*/
+
+static int sm501_register_device(struct sm501_devdata *sm,
+				 struct platform_device *pdev)
+{
+	struct sm501_device *smdev = to_sm_device(pdev);
+	int ptr;
+	int ret;
+
+	for (ptr = 0; ptr < pdev->num_resources; ptr++) {
+		printk("%s[%d] flags %08lx: %08llx..%08llx\n",
+		       pdev->name, ptr,
+		       pdev->resource[ptr].flags,
+		       (unsigned long long)pdev->resource[ptr].start,
+		       (unsigned long long)pdev->resource[ptr].end);
+	}
+
+	ret = platform_device_register(pdev);
+
+	if (ret >= 0) {
+		dev_dbg(sm->dev, "registered %s\n", pdev->name);
+		list_add_tail(&smdev->list, &sm->devices);
+	} else
+		dev_err(sm->dev, "error registering %s (%d)\n",
+			pdev->name, ret);
+
+	return ret;
+}
+
+/* sm501_create_subio
+ *
+ * Fill in an IO resource for a sub device
+*/
+
+static void sm501_create_subio(struct sm501_devdata *sm,
+			       struct resource *res,
+			       resource_size_t offs,
+			       resource_size_t size)
+{
+	res->flags = IORESOURCE_MEM;
+	res->parent = sm->io_res;
+	res->start = sm->io_res->start + offs;
+	res->end = res->start + size - 1;
+}
+
+/* sm501_create_mem
+ *
+ * Fill in an MEM resource for a sub device
+*/
+
+static void sm501_create_mem(struct sm501_devdata *sm,
+			     struct resource *res,
+			     resource_size_t *offs,
+			     resource_size_t size)
+{
+	*offs -= size;		/* adjust memory size */
+
+	res->flags = IORESOURCE_MEM;
+	res->parent = sm->mem_res;
+	res->start = sm->mem_res->start + *offs;
+	res->end = res->start + size - 1;
+}
+
+/* sm501_create_irq
+ *
+ * Fill in an IRQ resource for a sub device
+*/
+
+static void sm501_create_irq(struct sm501_devdata *sm,
+			     struct resource *res)
+{
+	res->flags = IORESOURCE_IRQ;
+	res->parent = NULL;
+	res->start = res->end = sm->irq;
+}
+
+static int sm501_register_usbhost(struct sm501_devdata *sm,
+				  resource_size_t *mem_avail)
+{
+	struct platform_device *pdev;
+
+	pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
+	if (!pdev)
+		return -ENOMEM;
+
+	sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
+	sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
+	sm501_create_irq(sm, &pdev->resource[2]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static void sm501_setup_uart_data(struct sm501_devdata *sm,
+				  struct plat_serial8250_port *uart_data,
+				  unsigned int offset)
+{
+	uart_data->membase = sm->regs + offset;
+	uart_data->mapbase = sm->io_res->start + offset;
+	uart_data->iotype = UPIO_MEM;
+	uart_data->irq = sm->irq;
+	uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
+	uart_data->regshift = 2;
+	uart_data->uartclk = (9600 * 16);
+}
+
+static int sm501_register_uart(struct sm501_devdata *sm, int devices)
+{
+	struct platform_device *pdev;
+	struct plat_serial8250_port *uart_data;
+
+	pdev = sm501_create_subdev(sm, "serial8250", 0,
+				   sizeof(struct plat_serial8250_port) * 3);
+	if (!pdev)
+		return -ENOMEM;
+
+	uart_data = pdev->dev.platform_data;
+
+	if (devices & SM501_USE_UART0) {
+		sm501_setup_uart_data(sm, uart_data++, 0x30000);
+		sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
+		sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
+		sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
+	}
+	if (devices & SM501_USE_UART1) {
+		sm501_setup_uart_data(sm, uart_data++, 0x30020);
+		sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
+		sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
+		sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
+	}
+
+	pdev->id = PLAT8250_DEV_SM501;
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_display(struct sm501_devdata *sm,
+				  resource_size_t *mem_avail)
+{
+	struct platform_device *pdev;
+
+	pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
+	if (!pdev)
+		return -ENOMEM;
+
+	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
+	sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
+	sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
+	sm501_create_irq(sm, &pdev->resource[3]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+#ifdef CONFIG_MFD_SM501_GPIO
+
+static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
+{
+	return container_of(gc, struct sm501_gpio_chip, gpio);
+}
+
+static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
+{
+	return container_of(gpio, struct sm501_devdata, gpio);
+}
+
+static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
+
+{
+	struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
+	unsigned long result;
+
+	result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
+	result >>= offset;
+
+	return result & 1UL;
+}
+
+static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+
+{
+	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
+	struct sm501_gpio *smgpio = smchip->ourgpio;
+	unsigned long bit = 1 << offset;
+	void __iomem *regs = smchip->regbase;
+	unsigned long save;
+	unsigned long val;
+
+	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
+		__func__, chip, offset);
+
+	spin_lock_irqsave(&smgpio->lock, save);
+
+	val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
+	if (value)
+		val |= bit;
+	writel(val, regs);
+
+	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
+	spin_unlock_irqrestore(&smgpio->lock, save);
+}
+
+static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
+{
+	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
+	struct sm501_gpio *smgpio = smchip->ourgpio;
+	void __iomem *regs = smchip->regbase;
+	unsigned long bit = 1 << offset;
+	unsigned long save;
+	unsigned long ddr;
+
+	dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
+		 __func__, chip, offset);
+
+	spin_lock_irqsave(&smgpio->lock, save);
+
+	ddr = readl(regs + SM501_GPIO_DDR_LOW);
+	writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
+
+	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
+	spin_unlock_irqrestore(&smgpio->lock, save);
+
+	return 0;
+}
+
+static int sm501_gpio_output(struct gpio_chip *chip,
+			     unsigned offset, int value)
+{
+	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
+	struct sm501_gpio *smgpio = smchip->ourgpio;
+	unsigned long bit = 1 << offset;
+	void __iomem *regs = smchip->regbase;
+	unsigned long save;
+	unsigned long val;
+	unsigned long ddr;
+
+	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
+		__func__, chip, offset, value);
+
+	spin_lock_irqsave(&smgpio->lock, save);
+
+	val = readl(regs + SM501_GPIO_DATA_LOW);
+	if (value)
+		val |= bit;
+	else
+		val &= ~bit;
+	writel(val, regs);
+
+	ddr = readl(regs + SM501_GPIO_DDR_LOW);
+	writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
+
+	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
+	writel(val, regs + SM501_GPIO_DATA_LOW);
+
+	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
+	spin_unlock_irqrestore(&smgpio->lock, save);
+
+	return 0;
+}
+
+static struct gpio_chip gpio_chip_template = {
+	.ngpio			= 32,
+	.direction_input	= sm501_gpio_input,
+	.direction_output	= sm501_gpio_output,
+	.set			= sm501_gpio_set,
+	.get			= sm501_gpio_get,
+};
+
+static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
+					      struct sm501_gpio *gpio,
+					      struct sm501_gpio_chip *chip)
+{
+	struct sm501_platdata *pdata = sm->platdata;
+	struct gpio_chip *gchip = &chip->gpio;
+	int base = pdata->gpio_base;
+
+	chip->gpio = gpio_chip_template;
+
+	if (chip == &gpio->high) {
+		if (base > 0)
+			base += 32;
+		chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
+		gchip->label  = "SM501-HIGH";
+	} else {
+		chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
+		gchip->label  = "SM501-LOW";
+	}
+
+	gchip->base   = base;
+	chip->ourgpio = gpio;
+
+	return gpiochip_add(gchip);
+}
+
+static int sm501_register_gpio(struct sm501_devdata *sm)
+{
+	struct sm501_gpio *gpio = &sm->gpio;
+	resource_size_t iobase = sm->io_res->start + SM501_GPIO;
+	int ret;
+	int tmp;
+
+	dev_dbg(sm->dev, "registering gpio block %08llx\n",
+		(unsigned long long)iobase);
+
+	spin_lock_init(&gpio->lock);
+
+	gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
+	if (gpio->regs_res == NULL) {
+		dev_err(sm->dev, "gpio: failed to request region\n");
+		return -ENXIO;
+	}
+
+	gpio->regs = ioremap(iobase, 0x20);
+	if (gpio->regs == NULL) {
+		dev_err(sm->dev, "gpio: failed to remap registers\n");
+		ret = -ENXIO;
+		goto err_claimed;
+	}
+
+	/* Register both our chips. */
+
+	ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
+	if (ret) {
+		dev_err(sm->dev, "failed to add low chip\n");
+		goto err_mapped;
+	}
+
+	ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
+	if (ret) {
+		dev_err(sm->dev, "failed to add high chip\n");
+		goto err_low_chip;
+	}
+
+	gpio->registered = 1;
+
+	return 0;
+
+ err_low_chip:
+	tmp = gpiochip_remove(&gpio->low.gpio);
+	if (tmp) {
+		dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
+		return ret;
+	}
+
+ err_mapped:
+	iounmap(gpio->regs);
+
+ err_claimed:
+	release_resource(gpio->regs_res);
+	kfree(gpio->regs_res);
+
+	return ret;
+}
+
+static void sm501_gpio_remove(struct sm501_devdata *sm)
+{
+	struct sm501_gpio *gpio = &sm->gpio;
+	int ret;
+
+	if (!sm->gpio.registered)
+		return;
+
+	ret = gpiochip_remove(&gpio->low.gpio);
+	if (ret)
+		dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
+
+	ret = gpiochip_remove(&gpio->high.gpio);
+	if (ret)
+		dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
+
+	iounmap(gpio->regs);
+	release_resource(gpio->regs_res);
+	kfree(gpio->regs_res);
+}
+
+static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
+{
+	struct sm501_gpio *gpio = &sm->gpio;
+	int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
+
+	return (pin % 32) + base;
+}
+
+static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
+{
+	return sm->gpio.registered;
+}
+#else
+static inline int sm501_register_gpio(struct sm501_devdata *sm)
+{
+	return 0;
+}
+
+static inline void sm501_gpio_remove(struct sm501_devdata *sm)
+{
+}
+
+static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
+{
+	return -1;
+}
+
+static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
+{
+	return 0;
+}
+#endif
+
+static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
+					    struct sm501_platdata_gpio_i2c *iic)
+{
+	struct i2c_gpio_platform_data *icd;
+	struct platform_device *pdev;
+
+	pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
+				   sizeof(struct i2c_gpio_platform_data));
+	if (!pdev)
+		return -ENOMEM;
+
+	icd = pdev->dev.platform_data;
+
+	/* We keep the pin_sda and pin_scl fields relative in case the
+	 * same platform data is passed to >1 SM501.
+	 */
+
+	icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
+	icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
+	icd->timeout = iic->timeout;
+	icd->udelay = iic->udelay;
+
+	/* note, we can't use either of the pin numbers, as the i2c-gpio
+	 * driver uses the platform.id field to generate the bus number
+	 * to register with the i2c core; The i2c core doesn't have enough
+	 * entries to deal with anything we currently use.
+	*/
+
+	pdev->id = iic->bus_num;
+
+	dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
+		 iic->bus_num,
+		 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
+				   struct sm501_platdata *pdata)
+{
+	struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
+	int index;
+	int ret;
+
+	for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
+		ret = sm501_register_gpio_i2c_instance(sm, iic);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+/* sm501_dbg_regs
+ *
+ * Debug attribute to attach to parent device to show core registers
+*/
+
+static ssize_t sm501_dbg_regs(struct device *dev,
+			      struct device_attribute *attr, char *buff)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev)	;
+	unsigned int reg;
+	char *ptr = buff;
+	int ret;
+
+	for (reg = 0x00; reg < 0x70; reg += 4) {
+		ret = sprintf(ptr, "%08x = %08x\n",
+			      reg, readl(sm->regs + reg));
+		ptr += ret;
+	}
+
+	return ptr - buff;
+}
+
+
+static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
+
+/* sm501_init_reg
+ *
+ * Helper function for the init code to setup a register
+ *
+ * clear the bits which are set in r->mask, and then set
+ * the bits set in r->set.
+*/
+
+static inline void sm501_init_reg(struct sm501_devdata *sm,
+				  unsigned long reg,
+				  struct sm501_reg_init *r)
+{
+	unsigned long tmp;
+
+	tmp = readl(sm->regs + reg);
+	tmp &= ~r->mask;
+	tmp |= r->set;
+	writel(tmp, sm->regs + reg);
+}
+
+/* sm501_init_regs
+ *
+ * Setup core register values
+*/
+
+static void sm501_init_regs(struct sm501_devdata *sm,
+			    struct sm501_initdata *init)
+{
+	sm501_misc_control(sm->dev,
+			   init->misc_control.set,
+			   init->misc_control.mask);
+
+	sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
+	sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
+	sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
+
+	if (init->m1xclk) {
+		dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
+		sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
+	}
+
+	if (init->mclk) {
+		dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
+		sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
+	}
+
+}
+
+/* Check the PLL sources for the M1CLK and M1XCLK
+ *
+ * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
+ * there is a risk (see errata AB-5) that the SM501 will cease proper
+ * function. If this happens, then it is likely the SM501 will
+ * hang the system.
+*/
+
+static int sm501_check_clocks(struct sm501_devdata *sm)
+{
+	unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
+	unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
+	unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
+
+	return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
+}
+
+static unsigned int sm501_mem_local[] = {
+	[0]	= 4*1024*1024,
+	[1]	= 8*1024*1024,
+	[2]	= 16*1024*1024,
+	[3]	= 32*1024*1024,
+	[4]	= 64*1024*1024,
+	[5]	= 2*1024*1024,
+};
+
+/* sm501_init_dev
+ *
+ * Common init code for an SM501
+*/
+
+static int sm501_init_dev(struct sm501_devdata *sm)
+{
+	struct sm501_initdata *idata;
+	struct sm501_platdata *pdata;
+	resource_size_t mem_avail;
+	unsigned long dramctrl;
+	unsigned long devid;
+	int ret;
+
+	mutex_init(&sm->clock_lock);
+	spin_lock_init(&sm->reg_lock);
+
+	INIT_LIST_HEAD(&sm->devices);
+
+	devid = readl(sm->regs + SM501_DEVICEID);
+
+	if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
+		dev_err(sm->dev, "incorrect device id %08lx\n", devid);
+		return -EINVAL;
+	}
+
+	/* disable irqs */
+	writel(0, sm->regs + SM501_IRQ_MASK);
+
+	dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
+	mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
+
+	dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
+		 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
+
+	sm->rev = devid & SM501_DEVICEID_REVMASK;
+
+	sm501_dump_gate(sm);
+
+	ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
+	if (ret)
+		dev_err(sm->dev, "failed to create debug regs file\n");
+
+	sm501_dump_clk(sm);
+
+	/* check to see if we have some device initialisation */
+
+	pdata = sm->platdata;
+	idata = pdata ? pdata->init : NULL;
+
+	if (idata) {
+		sm501_init_regs(sm, idata);
+
+		if (idata->devices & SM501_USE_USB_HOST)
+			sm501_register_usbhost(sm, &mem_avail);
+		if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
+			sm501_register_uart(sm, idata->devices);
+		if (idata->devices & SM501_USE_GPIO)
+			sm501_register_gpio(sm);
+	}
+
+	if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
+		if (!sm501_gpio_isregistered(sm))
+			dev_err(sm->dev, "no gpio available for i2c gpio.\n");
+		else
+			sm501_register_gpio_i2c(sm, pdata);
+	}
+
+	ret = sm501_check_clocks(sm);
+	if (ret) {
+		dev_err(sm->dev, "M1X and M clocks sourced from different "
+					"PLLs\n");
+		return -EINVAL;
+	}
+
+	/* always create a framebuffer */
+	sm501_register_display(sm, &mem_avail);
+
+	return 0;
+}
+
+static int sm501_plat_probe(struct platform_device *dev)
+{
+	struct sm501_devdata *sm;
+	int err;
+
+	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
+	if (sm == NULL) {
+		dev_err(&dev->dev, "no memory for device data\n");
+		err = -ENOMEM;
+		goto err1;
+	}
+
+	sm->dev = &dev->dev;
+	sm->pdev_id = dev->id;
+	sm->irq = platform_get_irq(dev, 0);
+	sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
+	sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	sm->platdata = dev->dev.platform_data;
+
+	if (sm->irq < 0) {
+		dev_err(&dev->dev, "failed to get irq resource\n");
+		err = sm->irq;
+		goto err_res;
+	}
+
+	if (sm->io_res == NULL || sm->mem_res == NULL) {
+		dev_err(&dev->dev, "failed to get IO resource\n");
+		err = -ENOENT;
+		goto err_res;
+	}
+
+	sm->regs_claim = request_mem_region(sm->io_res->start,
+					    0x100, "sm501");
+
+	if (sm->regs_claim == NULL) {
+		dev_err(&dev->dev, "cannot claim registers\n");
+		err= -EBUSY;
+		goto err_res;
+	}
+
+	platform_set_drvdata(dev, sm);
+
+	sm->regs = ioremap(sm->io_res->start,
+			   (sm->io_res->end - sm->io_res->start) - 1);
+
+	if (sm->regs == NULL) {
+		dev_err(&dev->dev, "cannot remap registers\n");
+		err = -EIO;
+		goto err_claim;
+	}
+
+	return sm501_init_dev(sm);
+
+ err_claim:
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+ err_res:
+	kfree(sm);
+ err1:
+	return err;
+
+}
+
+#ifdef CONFIG_PM
+
+/* power management support */
+
+static void sm501_set_power(struct sm501_devdata *sm, int on)
+{
+	struct sm501_platdata *pd = sm->platdata;
+
+	if (pd == NULL)
+		return;
+
+	if (pd->get_power) {
+		if (pd->get_power(sm->dev) == on) {
+			dev_dbg(sm->dev, "is already %d\n", on);
+			return;
+		}
+	}
+
+	if (pd->set_power) {
+		dev_dbg(sm->dev, "setting power to %d\n", on);
+
+		pd->set_power(sm->dev, on);
+		sm501_mdelay(sm, 10);
+	}
+}
+
+static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct sm501_devdata *sm = platform_get_drvdata(pdev);
+
+	sm->in_suspend = 1;
+	sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
+
+	sm501_dump_regs(sm);
+
+	if (sm->platdata) {
+		if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
+			sm501_set_power(sm, 0);
+	}
+
+	return 0;
+}
+
+static int sm501_plat_resume(struct platform_device *pdev)
+{
+	struct sm501_devdata *sm = platform_get_drvdata(pdev);
+
+	sm501_set_power(sm, 1);
+
+	sm501_dump_regs(sm);
+	sm501_dump_gate(sm);
+	sm501_dump_clk(sm);
+
+	/* check to see if we are in the same state as when suspended */
+
+	if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
+		dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
+		writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
+
+		/* our suspend causes the controller state to change,
+		 * either by something attempting setup, power loss,
+		 * or an external reset event on power change */
+
+		if (sm->platdata && sm->platdata->init) {
+			sm501_init_regs(sm, sm->platdata->init);
+		}
+	}
+
+	/* dump our state from resume */
+
+	sm501_dump_regs(sm);
+	sm501_dump_clk(sm);
+
+	sm->in_suspend = 0;
+
+	return 0;
+}
+#else
+#define sm501_plat_suspend NULL
+#define sm501_plat_resume NULL
+#endif
+
+/* Initialisation data for PCI devices */
+
+static struct sm501_initdata sm501_pci_initdata = {
+	.gpio_high	= {
+		.set	= 0x3F000000,		/* 24bit panel */
+		.mask	= 0x0,
+	},
+	.misc_timing	= {
+		.set	= 0x010100,		/* SDRAM timing */
+		.mask	= 0x1F1F00,
+	},
+	.misc_control	= {
+		.set	= SM501_MISC_PNL_24BIT,
+		.mask	= 0,
+	},
+
+	.devices	= SM501_USE_ALL,
+
+	/* Errata AB-3 says that 72MHz is the fastest available
+	 * for 33MHZ PCI with proper bus-mastering operation */
+
+	.mclk		= 72 * MHZ,
+	.m1xclk		= 144 * MHZ,
+};
+
+static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
+	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
+			   SM501FB_FLAG_USE_HWCURSOR |
+			   SM501FB_FLAG_USE_HWACCEL |
+			   SM501FB_FLAG_DISABLE_AT_EXIT),
+};
+
+static struct sm501_platdata_fb sm501_fb_pdata = {
+	.fb_route	= SM501_FB_OWN,
+	.fb_crt		= &sm501_pdata_fbsub,
+	.fb_pnl		= &sm501_pdata_fbsub,
+};
+
+static struct sm501_platdata sm501_pci_platdata = {
+	.init		= &sm501_pci_initdata,
+	.fb		= &sm501_fb_pdata,
+	.gpio_base	= -1,
+};
+
+static int sm501_pci_probe(struct pci_dev *dev,
+			   const struct pci_device_id *id)
+{
+	struct sm501_devdata *sm;
+	int err;
+
+	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
+	if (sm == NULL) {
+		dev_err(&dev->dev, "no memory for device data\n");
+		err = -ENOMEM;
+		goto err1;
+	}
+
+	/* set a default set of platform data */
+	dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
+
+	/* set a hopefully unique id for our child platform devices */
+	sm->pdev_id = 32 + dev->devfn;
+
+	pci_set_drvdata(dev, sm);
+
+	err = pci_enable_device(dev);
+	if (err) {
+		dev_err(&dev->dev, "cannot enable device\n");
+		goto err2;
+	}
+
+	sm->dev = &dev->dev;
+	sm->irq = dev->irq;
+
+#ifdef __BIG_ENDIAN
+	/* if the system is big-endian, we most probably have a
+	 * translation in the IO layer making the PCI bus little endian
+	 * so make the framebuffer swapped pixels */
+
+	sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
+#endif
+
+	/* check our resources */
+
+	if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
+		dev_err(&dev->dev, "region #0 is not memory?\n");
+		err = -EINVAL;
+		goto err3;
+	}
+
+	if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
+		dev_err(&dev->dev, "region #1 is not memory?\n");
+		err = -EINVAL;
+		goto err3;
+	}
+
+	/* make our resources ready for sharing */
+
+	sm->io_res = &dev->resource[1];
+	sm->mem_res = &dev->resource[0];
+
+	sm->regs_claim = request_mem_region(sm->io_res->start,
+					    0x100, "sm501");
+	if (sm->regs_claim == NULL) {
+		dev_err(&dev->dev, "cannot claim registers\n");
+		err= -EBUSY;
+		goto err3;
+	}
+
+	sm->regs = ioremap(pci_resource_start(dev, 1),
+			   pci_resource_len(dev, 1));
+
+	if (sm->regs == NULL) {
+		dev_err(&dev->dev, "cannot remap registers\n");
+		err = -EIO;
+		goto err4;
+	}
+
+	sm501_init_dev(sm);
+	return 0;
+
+ err4:
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+ err3:
+	pci_disable_device(dev);
+ err2:
+	pci_set_drvdata(dev, NULL);
+	kfree(sm);
+ err1:
+	return err;
+}
+
+static void sm501_remove_sub(struct sm501_devdata *sm,
+			     struct sm501_device *smdev)
+{
+	list_del(&smdev->list);
+	platform_device_unregister(&smdev->pdev);
+}
+
+static void sm501_dev_remove(struct sm501_devdata *sm)
+{
+	struct sm501_device *smdev, *tmp;
+
+	list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
+		sm501_remove_sub(sm, smdev);
+
+	device_remove_file(sm->dev, &dev_attr_dbg_regs);
+
+	sm501_gpio_remove(sm);
+}
+
+static void sm501_pci_remove(struct pci_dev *dev)
+{
+	struct sm501_devdata *sm = pci_get_drvdata(dev);
+
+	sm501_dev_remove(sm);
+	iounmap(sm->regs);
+
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+
+	pci_set_drvdata(dev, NULL);
+	pci_disable_device(dev);
+}
+
+static int sm501_plat_remove(struct platform_device *dev)
+{
+	struct sm501_devdata *sm = platform_get_drvdata(dev);
+
+	sm501_dev_remove(sm);
+	iounmap(sm->regs);
+
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+
+	return 0;
+}
+
+static struct pci_device_id sm501_pci_tbl[] = {
+	{ 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+	{ 0, },
+};
+
+MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
+
+static struct pci_driver sm501_pci_drv = {
+	.name		= "sm501",
+	.id_table	= sm501_pci_tbl,
+	.probe		= sm501_pci_probe,
+	.remove		= sm501_pci_remove,
+};
+
+MODULE_ALIAS("platform:sm501");
+
+static struct platform_driver sm501_plat_drv = {
+	.driver		= {
+		.name	= "sm501",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= sm501_plat_probe,
+	.remove		= sm501_plat_remove,
+	.suspend	= sm501_plat_suspend,
+	.resume		= sm501_plat_resume,
+};
+
+static int __init sm501_base_init(void)
+{
+	platform_driver_register(&sm501_plat_drv);
+	return pci_register_driver(&sm501_pci_drv);
+}
+
+static void __exit sm501_base_exit(void)
+{
+	platform_driver_unregister(&sm501_plat_drv);
+	pci_unregister_driver(&sm501_pci_drv);
+}
+
+module_init(sm501_base_init);
+module_exit(sm501_base_exit);
+
+MODULE_DESCRIPTION("SM501 Core Driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
+MODULE_LICENSE("GPL v2");
diff -uNra linux-2.6.27.6/drivers/mfd/sm501.bak.c linux-2.6.27.6.yaffs/drivers/mfd/sm501.bak.c
--- linux-2.6.27.6/drivers/mfd/sm501.bak.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mfd/sm501.bak.c	2011-05-08 18:00:26.000000000 +0800
@@ -0,0 +1,1399 @@
+/* linux/drivers/mfd/sm50x.c
+ *
+ * Copyright (C) 2010 SiliconMotion Inc.
+ * Copyright (c) 2006 Simtec Electronics
+ *
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	Vincent Sanders <vince@simtec.co.uk>
+ *	Boyod.yang,  <boyod.yang@siliconmotion.com.cn>
+ *    Teddy.wang,  <teddy.wang@siliconmotion.com>
+ *	
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 
+ * or later as published by the Free Software Foundation. 
+ *
+ * SM50x/SM107  MFD driver
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif
+#define SM501_CHAR_MAJOR 245
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+#include <linux/sm501-regs.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+static unsigned char __iomem *sm50x_base_reg = NULL;
+static unsigned char __iomem *sm50x_base_mem = NULL;
+resource_size_t sm50x_mem_size = 0;
+EXPORT_SYMBOL_GPL(sm50x_mem_size);
+
+static unsigned int sm501_mem_local[] = {
+	[0]	= 4*1024*1024,
+	[1]	= 8*1024*1024,
+	[2]	= 16*1024*1024,
+	[3]	= 32*1024*1024,
+	[4]	= 64*1024*1024,
+	[5]	= 2*1024*1024,
+};
+
+struct sm501_sub_device_list {
+	struct list_head		list;
+	struct platform_device		pdev;
+};
+
+struct sm501_devdata {
+	spinlock_t			 reg_lock;
+	struct mutex			 clock_lock;
+	struct list_head		 devices;
+
+	struct device			*dev;
+	struct resource			*io_res;
+	struct resource			*mem_res;
+	struct resource			*regs_claim;
+	struct resource			*mem_claim;
+	struct sm501_platdata		*platdata;
+
+	unsigned int			 in_suspend;
+	int				 unit_power[20];
+	unsigned int			 pdev_id;
+	u8					 chipRevID;
+	unsigned int			 irq;
+	void __iomem			*regs;
+	void __iomem			*fb_mem;
+
+	/* mtrr support */
+	int mtrr_reg;
+	u32 has_mtrr;
+};
+
+/* SmRead8()
+ * 
+ *    Read the 8-bit value, to the 8-bit register location
+ *    specified by nOffset
+ *
+*/
+unsigned long SmRead8(unsigned long nOffset)
+{
+    return readb(sm50x_base_reg + nOffset);
+}
+
+/* SmRead16()
+ * 
+ *    Read the 16-bit value, to the 16-bit register location
+ *    specified by nOffset
+ *
+*/
+unsigned long SmRead16(unsigned long nOffset)
+{
+    return readw(sm50x_base_reg + nOffset);
+}
+
+/* SmRead32()
+ * 
+ *    Read the 32-bit value, to the 32-bit register location
+ *    specified by nOffset
+ *
+*/
+unsigned long SmRead32(unsigned long nOffset)
+{
+    return readl(sm50x_base_reg + nOffset);
+}
+
+
+EXPORT_SYMBOL_GPL(SmRead8);
+EXPORT_SYMBOL_GPL(SmRead16);
+EXPORT_SYMBOL_GPL(SmRead32);
+
+/* SmWrite8()
+ * 
+ *    Write the 8-bit value, to the 8-bit register location
+ *    specified by nOffset
+ *
+*/
+void SmWrite8(unsigned long nOffset, unsigned long nData)
+{
+	writeb(nData,sm50x_base_reg + nOffset);
+}
+
+/* SmWrite16()
+ * 
+ *    Write the 16-bit value, to the 16-bit register location
+ *    specified by nOffset
+ *
+*/
+void SmWrite16(unsigned long nOffset, unsigned long nData)
+{
+	writew(nData,sm50x_base_reg + nOffset);
+}
+
+/* SmWrite32()
+ * 
+ *    Write the 32-bit value, to the 32-bit register location
+ *    specified by nOffset
+ *
+*/
+void SmWrite32(unsigned long nOffset, unsigned long nData)
+{
+	writel(nData,sm50x_base_reg + nOffset);
+}
+
+EXPORT_SYMBOL_GPL(SmWrite8);
+EXPORT_SYMBOL_GPL(SmWrite16);
+EXPORT_SYMBOL_GPL(SmWrite32);
+
+void SmMemset(unsigned long nOffset, unsigned char val, int count)
+{
+	memset((void __force *) (sm50x_base_reg + nOffset), val, count);
+}
+
+EXPORT_SYMBOL_GPL(SmMemset);
+
+static void sm501_sync_regs()
+{
+	SmRead32(0);
+}
+
+/* Perform a rounded division. */
+static long sm501fb_round_div(long num, long denom)
+{
+        /* n / d + 1 / 2 = (2n + d) / 2d */
+        return (2 * num + denom) / (2 * denom);
+}
+
+void sm501_configure_gpio(unsigned int gpio, unsigned char mode) 
+{ 
+    unsigned long conf; 
+    unsigned long reg; 
+    unsigned long offset = gpio; 
+ 
+    if (offset >= 32) { 
+        reg = SM501_GPIO63_32_CONTROL; 
+        offset = gpio - 32; 
+    } else 
+        reg = SM501_GPIO31_0_CONTROL; 
+ 
+    conf = readl(sm50x_base_reg + reg); 
+    conf &= ~(1 << offset); 
+    if (mode) 
+        conf |= (1 << offset); 
+    writel(conf, sm50x_base_reg + reg); 
+} 
+EXPORT_SYMBOL_GPL(sm501_configure_gpio);
+
+void sm501_date_gpio(unsigned int gpio, unsigned char mode) 
+{ 
+    unsigned long conf; 
+    unsigned long reg; 
+    unsigned long offset = gpio; 
+ 
+    if (offset >= 32) { 
+        reg = 0x10004; 
+        offset = gpio - 32; 
+    } else 
+        reg = 0x10000; 
+ 
+    conf = readl(sm50x_base_reg + reg); 
+    conf &= ~(1 << offset); 
+    if (mode) 
+        conf |= (1 << offset); 
+    writel(conf, sm50x_base_reg + reg); 
+} 
+EXPORT_SYMBOL_GPL(sm501_date_gpio);
+void sm501_dir_gpio(unsigned int gpio, unsigned char mode) 
+{ 
+    unsigned long conf; 
+    unsigned long reg; 
+    unsigned long offset = gpio; 
+ 
+    if (offset >= 32) { 
+        reg = 0x1000c; 
+        offset = gpio - 32; 
+    } else 
+        reg = 0x10008; 
+ 
+    conf = readl(sm50x_base_reg + reg); 
+    conf &= ~(1 << offset); 
+    if (mode) 
+        conf |= (1 << offset); 
+    writel(conf, sm50x_base_reg + reg); 
+} 
+EXPORT_SYMBOL_GPL(sm501_dir_gpio);
+
+/* clock value structure. */
+struct sm501_clock {
+	unsigned long mclk;
+	int divider;
+	int shift;
+
+	long multipleM;
+	int dividerN;
+	short divby2;
+};
+
+/* sm501_select_clock
+ *
+ * selects nearest discrete clock frequency the SM501 can achive
+ *   the maximum divisor is 3 or 5
+ */
+static unsigned long sm501_select_clock(unsigned long freq,
+					struct sm501_clock *clock,
+					int max_div)
+{
+	unsigned long mclk;
+	int divider;
+	int shift;
+	long diff;
+	long best_diff = 999999999;
+
+	/* Try 288MHz and 336MHz clocks. */
+	for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
+		/* try dividers 1 and 3 for CRT and for panel,
+		   try divider 5 for panel only.*/
+
+		for (divider = 1; divider <= max_div; divider += 2) {
+			/* try all 8 shift values.*/
+			for (shift = 0; shift < 8; shift++) {
+				/* Calculate difference to requested clock */
+				diff = sm501fb_round_div(mclk, divider << shift) - freq;
+				if (diff < 0)
+					diff = -diff;
+
+				/* If it is less than the current, use it */
+				if (diff < best_diff) {
+					best_diff = diff;
+
+					clock->mclk = mclk;
+					clock->divider = divider;
+					clock->shift = shift;
+				}
+			}
+		}
+	}
+
+	/* Return best clock. */
+	return clock->mclk / (clock->divider << clock->shift);
+}
+
+
+#ifdef CONFIG_MTRR
+
+/* sm501fb_set_mtrr
+ *
+ * mtrr support functions 
+*/
+
+void  sm501fb_set_mtrr(struct device *dev)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+
+	sm->mtrr_reg = mtrr_add(sm->mem_res->start,
+				   ((sm->mem_res->end - sm->mem_res->start) - 2*0x10000)-1, MTRR_TYPE_WRCOMB, 1);
+	if (sm->mtrr_reg < 0) {
+		dev_info(sm->dev,"unable to set MTRR\n");
+		return;
+	}
+	sm->has_mtrr = 1;
+}
+EXPORT_SYMBOL_GPL(sm501fb_set_mtrr);
+
+/* sm501fb_unset_mtrr
+ *
+ * mtrr support functions 
+*/
+
+void sm501fb_unset_mtrr(struct device *dev)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+
+  	if (sm->has_mtrr)
+  		mtrr_del(sm->mtrr_reg, sm->mem_res->start,
+			  ((sm->mem_res->end - sm->mem_res->start) - 2*0x10000)-1);
+}
+EXPORT_SYMBOL_GPL(sm501fb_unset_mtrr);
+
+#endif
+
+
+/* sm501_get_memory_size
+ *
+ * get memory size of sm501
+*/
+
+static resource_size_t sm501_get_memory_size()
+{
+	return sm501_mem_local[FIELD_GET(SmRead32(DRAM_CONTROL),DRAM_CONTROL,LOCAL_SIZE)];
+}
+
+/* sm501_set_clock
+ *
+ * set one of the four clock sources to the closest available frequency to
+ *  the one specified
+*/
+unsigned long sm501_set_clock(struct device *dev,
+			      int clksrc,
+			      unsigned long req_freq)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long mode = SmRead32(POWER_MODE_CTRL);
+	unsigned long clock = SmRead32(CURRENT_POWER_CLOCK);
+	unsigned char reg = 0;
+	unsigned long sm501_freq,pllclock; /* the actual frequency acheived */
+
+	struct sm501_clock to;
+
+	/* find achivable discrete frequency and setup register value
+	 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
+	 * has an extra bit for the divider */
+
+	switch (clksrc) {
+	case SM501_CLOCK_P2XCLK:
+		/* This clock is divided in half so to achive the
+		 * requested frequency the value must be multiplied by
+		 * 2. This clock also has an additional pre divisor */
+		if (sm->chipRevID < SM502_REV_ID){
+			sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
+			reg=to.shift & 0x07;/* bottom 3 bits are shift */
+			if (to.divider == 3)
+				reg |= 0x08; /* /3 divider required */
+			else if (to.divider == 5)
+				reg |= 0x10; /* /5 divider required */
+			if (to.mclk != 288000000)
+				reg |= 0x20; /* which mclk pll is source */
+		}else
+		{
+			/*For new PLL in SM502*/
+			to.multipleM = (2 * req_freq)/(1000*1000);
+			to.dividerN = 24;
+			to.divby2 = 0;
+
+			while (to.multipleM > 192){
+			to.multipleM /= 2;
+			to.dividerN /= 2;
+			}
+			sm501_freq = req_freq;
+		}
+		break;
+
+	case SM501_CLOCK_V2XCLK:
+		/* This clock is divided in half so to achive the
+		 * requested frequency the value must be multiplied by 2. */
+
+		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
+		reg=to.shift & 0x07;	/* bottom 3 bits are shift */
+		if (to.divider == 3)
+			reg |= 0x08;	/* /3 divider required */
+		if (to.mclk != 288000000)
+			reg |= 0x10;	/* which mclk pll is source */
+		break;
+
+	case SM501_CLOCK_MCLK:
+	case SM501_CLOCK_M1XCLK:
+		/* These clocks are the same and not further divided */
+
+		sm501_freq = sm501_select_clock( req_freq, &to, 3);
+		reg=to.shift & 0x07;	/* bottom 3 bits are shift */
+		if (to.divider == 3)
+			reg |= 0x08;	/* /3 divider required */
+		if (to.mclk != 288000000)
+			reg |= 0x10;	/* which mclk pll is source */
+		break;
+
+	default:
+		return 0; /* this is bad */
+	}
+
+	mutex_lock(&sm->clock_lock);
+
+	mode = SmRead32(POWER_MODE_CTRL);
+	clock = SmRead32(CURRENT_POWER_CLOCK);
+	
+	clock = clock & ~(0xFF << clksrc);
+	clock |= reg<<clksrc;
+
+		/*For new PLL in SM502*/
+	if ( (sm->chipRevID >= SM502_REV_ID)&& (clksrc==SM501_CLOCK_P2XCLK) ){
+
+		pllclock = SmRead32(CURRENT_POWER_PLLCLOCK);
+
+		pllclock &= FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, MULTIPLE_M)
+				  &  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, DIVIDE_N)
+				  &  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, DIVIDEBY2)
+					&  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, INPUT_SELECT)
+					  &  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, POWER);
+		
+		SmWrite32(CURRENT_POWER_PLLCLOCK,
+				  FIELD_VALUE(pllclock, CURRENT_POWER_PLLCLOCK, MULTIPLE_M, to.multipleM)|
+					  FIELD_VALUE(pllclock, CURRENT_POWER_PLLCLOCK, DIVIDE_N, to.dividerN)|
+				              FIELD_VALUE(pllclock, CURRENT_POWER_PLLCLOCK, DIVIDEBY2, to.divby2)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, POWER, ON)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, INPUT_SELECT,CRYSTAL)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, TEST_OUTPUT, DISABLE)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, TESTMODE, DISABLE));		
+
+		clock = (FIELD_SET(clock, CURRENT_POWER_CLOCK, PLLCLK_SELECT, ENABLE)|
+					FIELD_SET(clock, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 1)|
+					FIELD_SET(clock, CURRENT_POWER_CLOCK, P2XCLK_SHIFT, 0)  );
+		}	
+	
+	mode = FIELD_GET(mode, POWER_MODE_CTRL, MODE);	/* find current mode */
+
+	switch (mode) {
+	case 0:
+		SmWrite32(POWER_MODE0_CLOCK, clock);
+		mode = 0;
+		break;
+	case 1:
+		SmWrite32(POWER_MODE1_CLOCK, clock);
+		mode = 1;
+		break;
+
+	default:
+		mutex_unlock(&sm->clock_lock);
+		return -1;
+	}
+
+	sm501_sync_regs();
+
+	dev_info(sm->dev, "clock %08lx, mode %08lx\n",
+		  clock, mode);
+
+	msleep(16);
+	mutex_unlock(&sm->clock_lock);
+
+	return sm501_freq;
+}
+
+EXPORT_SYMBOL_GPL(sm501_set_clock);
+
+
+/* sm501_set_gate
+ *
+ * set one of the four gate sources to the closest available frequency to
+ *  the one specified
+*/
+
+void sm501_set_gate( unsigned long gate)
+{
+
+	unsigned long mode = SmRead32(POWER_MODE_CTRL);
+	mode = FIELD_GET(mode, POWER_MODE_CTRL, MODE);	
+
+	switch (mode) {
+	case 0:
+		SmWrite32(POWER_MODE0_GATE, gate);
+		break;
+	case 1:
+		SmWrite32(POWER_MODE1_GATE, gate);
+		break;
+	default:
+		return;
+	}
+
+	sm501_sync_regs();
+	msleep(16);
+}
+
+EXPORT_SYMBOL_GPL(sm501_set_gate);
+			      
+/* sm501_find_clock
+ *
+ * finds the closest available frequency for a given clock
+*/
+
+unsigned long sm501_find_clock(int clksrc,
+			       unsigned long req_freq)
+{
+	unsigned long sm501_freq; /* the frequency achiveable by the 501 */
+	struct sm501_clock to;
+
+	switch (clksrc) {
+	case SM501_CLOCK_P2XCLK:
+		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
+		break;
+
+	case SM501_CLOCK_V2XCLK:
+		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
+		break;
+
+	case SM501_CLOCK_MCLK:
+	case SM501_CLOCK_M1XCLK:
+		sm501_freq = sm501_select_clock(req_freq, &to, 3);
+		break;
+
+	default:
+		sm501_freq = 0;		/* error */
+	}
+
+	return sm501_freq;
+}
+
+EXPORT_SYMBOL_GPL(sm501_find_clock);
+
+static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
+{
+	/* during suspend/resume, we are currently not allowed to sleep,
+	 * so change to using mdelay() instead of msleep() if we
+	 * are in one of these paths */
+
+	if (sm->in_suspend)
+		mdelay(delay);
+	else
+		msleep(delay);
+}
+
+/* sm501_modify_reg
+ *
+ * Modify a register in the SM501 which may be shared with other
+ * drivers.
+*/
+unsigned long sm501_modify_reg(struct device *dev,
+			       unsigned long reg,
+			       unsigned long set,
+			       unsigned long clear)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long data;
+	unsigned long save;
+
+	spin_lock_irqsave(&sm->reg_lock, save);
+
+	data = readl(sm->regs + reg);
+	data |= set;
+	data &= ~clear;
+
+	writel(data, sm->regs + reg);
+	sm501_sync_regs(sm);
+
+	spin_unlock_irqrestore(&sm->reg_lock, save);
+
+	return data;
+}
+
+EXPORT_SYMBOL_GPL(sm501_modify_reg);
+
+/* sm501_unit_power
+ *
+ * alters the power active gate to set specific units on or off
+ */
+
+int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long mode;
+	unsigned long gate;
+	unsigned long clock;
+
+	mutex_lock(&sm->clock_lock);
+
+	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
+	gate = readl(sm->regs + SM501_CURRENT_GATE);
+	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
+
+	mode &= 3;		/* get current power mode */
+
+	if (unit >= ARRAY_SIZE(sm->unit_power)) {
+		dev_err(dev, "%s: bad unit %d\n", __func__, unit);
+		goto already;
+	}
+
+	dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
+		sm->unit_power[unit], to);
+
+	if (to == 0 && sm->unit_power[unit] == 0) {
+		dev_err(sm->dev, "unit %d is already shutdown\n", unit);
+		goto already;
+	}
+
+	sm->unit_power[unit] += to ? 1 : -1;
+	to = sm->unit_power[unit] ? 1 : 0;
+
+	if (to) {
+		if (gate & (1 << unit))
+			goto already;
+		gate |= (1 << unit);
+	} else {
+		if (!(gate & (1 << unit)))
+			goto already;
+		gate &= ~(1 << unit);
+	}
+
+	switch (mode) {
+	case 1:
+		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
+		mode = 0;
+		break;
+	case 2:
+	case 0:
+		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
+		mode = 1;
+		break;
+
+	default:
+		return -1;
+	}
+
+	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
+	sm501_sync_regs(sm);
+
+	dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
+		gate, clock, mode);
+
+	sm501_mdelay(sm, 16);
+
+ already:
+	mutex_unlock(&sm->clock_lock);
+	return gate;
+}
+
+EXPORT_SYMBOL_GPL(sm501_unit_power);
+
+
+/* sm501_dbg_regs
+ *
+ * Debug attribute to attach to parent device to show core registers
+*/
+
+static ssize_t sm50x_dbg_regs(struct device *dev,
+			      struct device_attribute *attr, char *buff)
+{
+	struct sm501_devdata *sm = dev_get_drvdata(dev)	;
+	unsigned long reg;
+	char *ptr = buff;
+	int ret;
+
+	for (reg = 0x00; reg < 0x70; reg += 4) {
+		ret = sprintf(ptr, "%08x = %08x\n", reg, SmRead32(reg));
+		ptr += ret;
+	}
+
+	return ptr - buff;
+}
+
+
+static DEVICE_ATTR(dbg_regs, 0666, sm50x_dbg_regs, NULL);
+
+
+static struct sm501_sub_device_list *get_sm_dev_list(struct platform_device *pdev)
+{
+	return container_of(pdev, struct sm501_sub_device_list, pdev);
+}
+
+/* sm501_devices_release
+ *
+ * A release function for the platform devices we create to allow us to
+ * free any items we allocated
+*/
+
+static void sm501_devices_release(struct device *dev)
+{
+	kfree(get_sm_dev_list(to_platform_device(dev)));
+}
+
+/* sm501_create_subdev
+ *
+ * Create a sub platform device with resources for passing to a
+ * sub-driver
+*/
+
+static struct platform_device *
+sm501_create_subdev(struct sm501_devdata *sm,
+		    char *name, unsigned int res_count)
+{
+	struct sm501_sub_device_list *smdevs;
+
+	smdevs = kzalloc(sizeof(struct sm501_sub_device_list) +
+			sizeof(struct resource) * res_count, GFP_KERNEL);
+	if (!smdevs)
+		return NULL;
+
+	smdevs->pdev.dev.release = sm501_devices_release;
+
+	smdevs->pdev.name = name;
+	smdevs->pdev.id = sm->pdev_id;
+	smdevs->pdev.resource = (struct resource *)(smdevs+1);
+	smdevs->pdev.num_resources = res_count;
+
+	smdevs->pdev.dev.parent = sm->dev;
+
+	return &smdevs->pdev;
+}
+
+/* sm501_register_device
+ *
+ * Register a platform device created with sm501_create_subdev()
+*/
+
+static int sm501_register_device(struct sm501_devdata *sm,
+				 struct platform_device *pdev)
+{
+	struct sm501_sub_device_list *smdevs = get_sm_dev_list(pdev);
+	int ptr;
+	int ret;
+
+	for (ptr = 0; ptr < pdev->num_resources; ptr++) {
+		printk("%s[%d] flags %08lx: %08llx..%08llx\n",
+		       pdev->name, ptr,
+		       pdev->resource[ptr].flags,
+		       (unsigned long long)pdev->resource[ptr].start,
+		       (unsigned long long)pdev->resource[ptr].end);
+	}
+
+	ret = platform_device_register(pdev);
+
+	if (ret >= 0) {
+		dev_dbg(sm->dev, "registered %s\n", pdev->name);
+		list_add_tail(&smdevs->list, &sm->devices);
+	} else
+		dev_err(sm->dev, "error registering %s (%d)\n",
+			pdev->name, ret);
+
+	return ret;
+}
+
+/* sm501_create_subio
+ *
+ * Fill in an IO resource for a sub device
+*/
+
+static void sm501_create_subio(struct sm501_devdata *sm,
+			       struct resource *res,
+			       resource_size_t offs,
+			       resource_size_t size)
+{
+	res->flags = IORESOURCE_MEM;
+	res->parent = sm->io_res;
+	res->start = sm->io_res->start + offs;
+	res->end = res->start + size - 1;
+}
+
+/* sm501_create_mem
+ *
+ * Fill in an MEM resource for a sub device
+*/
+
+static void sm501_create_mem(struct sm501_devdata *sm,
+			     struct resource *res,
+			     resource_size_t offs,
+			     resource_size_t size)
+{
+
+
+	res->flags = IORESOURCE_MEM;
+	res->parent = sm->mem_res;
+	res->start = sm->mem_res->start + offs;
+	res->end = res->start + size - 1;
+}
+
+/* sm501_create_irq
+ *
+ * Fill in an IRQ resource for a sub device
+*/
+
+static void sm501_create_irq(struct sm501_devdata *sm,
+			     struct resource *res)
+{
+	res->flags = IORESOURCE_IRQ;
+	res->parent = NULL;
+	res->start = res->end = sm->irq;
+}
+
+static int sm501_fill_usbdev(struct device *dev, struct platform_device *pdev)
+{
+	pdev->dev.power.power_state = PMSG_ON;
+	/*Add for usb dma mask*/
+	pdev->dev.coherent_dma_mask = ~0x0;
+	pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+}
+static int sm501_register_usbhost(struct sm501_devdata *sm, 
+				  struct device *dev)
+{
+	struct platform_device *pdev;
+	/*If the chip is SM107 just return without doing anything*/
+	if (sm50x_mem_size == 0x400000)
+		return 0;
+	
+	pdev = sm501_create_subdev(sm, "sm501-usb", 3);
+	if (!pdev)
+		return -ENOMEM;
+	sm501_fill_usbdev(dev, pdev);
+	sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
+	sm501_create_mem(sm, &pdev->resource[1], sm50x_mem_size-USB_DMA_BUFFER_SIZE, USB_DMA_BUFFER_SIZE);
+	sm501_create_irq(sm, &pdev->resource[2]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_display(struct sm501_devdata *sm)
+{
+	struct platform_device *pdev;
+	resource_size_t resource2Size;
+
+	pdev = sm501_create_subdev(sm, "sm501-fb", 4);
+	if (!pdev)
+		return -ENOMEM;
+
+	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
+	sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
+	sm501_create_mem(sm, &pdev->resource[2], 0, sm50x_mem_size-USB_DMA_BUFFER_SIZE);
+	sm501_create_irq(sm, &pdev->resource[3]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_i2c(struct sm501_devdata *sm)
+{
+	struct platform_device *pdev;
+	pdev = sm501_create_subdev(sm, "sm501-i2c", 1);
+	if (!pdev)
+		return -ENOMEM;
+	sm501_create_irq(sm, &pdev->resource[0]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_uart(struct sm501_devdata *sm)
+{
+	struct platform_device *pdev;
+	/*If the chip is SM107 just return without doing anything*/
+	if (sm50x_mem_size == 0x400000)
+		return 0;
+	
+	pdev = sm501_create_subdev(sm, "sm501-uart", 1);
+	if (!pdev)
+		return -ENOMEM;
+
+//	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
+	sm501_create_irq(sm, &pdev->resource[0]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_audio(struct sm501_devdata *sm)
+{
+	struct platform_device *pdev;
+
+	/*If the chip is SM107 just return without doing anything*/
+	if (sm50x_mem_size == 0x400000)
+		return 0;
+
+	pdev = sm501_create_subdev(sm, "sm501-audio", 1);
+	if (!pdev)
+		return -ENOMEM;
+	sm501_create_irq(sm, &pdev->resource[0]);
+
+	return sm501_register_device(sm, pdev);
+}
+
+static int sm501_register_gpio(struct sm501_devdata *sm)
+{
+    struct platform_device *pdev;
+ 
+    pdev = sm501_create_subdev(sm, "sm501-gpio", 4);
+    if (!pdev)
+        return -ENOMEM;
+ 
+    sm501_create_subio(sm, &pdev->resource[0], SM501_GPIO, 0x20);
+    return sm501_register_device(sm, pdev);
+}
+
+/* sm501_init_regs
+ *
+ * Setup core register values
+*/
+
+static void sm501_init_regs(struct sm501_devdata *sm,
+			    struct sm501_initdata *init)
+{
+	ulong RegValue;
+	/*Set the local memory number of banks according to the chip type*/
+	sm50x_mem_size = sm501_get_memory_size();
+
+	RegValue= SmRead32(DRAM_CONTROL);
+	if (sm50x_mem_size == 0x400000){
+		dev_info(sm->dev, "SM107 is detected.\n");
+		RegValue = FIELD_SET(RegValue, DRAM_CONTROL, LOCAL_BANKS, 2);
+	}
+	else	{
+		dev_info(sm->dev, "SM502 is detected.\n");
+		RegValue = FIELD_SET(RegValue, DRAM_CONTROL, LOCAL_BANKS, 4);
+	}
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON2
+	RegValue = FIELD_SET(RegValue, DRAM_CONTROL,LOCAL,RESET);
+#endif
+	SmWrite32(DRAM_CONTROL, RegValue);
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON2
+	RegValue = FIELD_SET(RegValue, DRAM_CONTROL,LOCAL,NORMAL);
+	SmWrite32(DRAM_CONTROL, RegValue);	
+#endif
+
+	RegValue = SmRead32(SYSTEM_CTRL);
+	SmWrite32(SYSTEM_CTRL, FIELD_SET(RegValue, SYSTEM_CTRL, PCI_BURST, ENABLE)|
+//			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_MASTER, START)|
+			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_BURST_READ, ENABLE)|
+			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_RETRY, ENABLE)|
+			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_CLOCK_RUN, ENABLE));
+	
+	RegValue = SmRead32(MISC_CTRL);
+	SmWrite32(MISC_CTRL, FIELD_SET(RegValue, MISC_CTRL, FPDATA, 24)|
+		FIELD_SET(RegValue, MISC_CTRL, BURST_LENGTH, 1));
+
+	RegValue = SmRead32(GPIO_CONTROL_HIGH);
+
+	SmWrite32(GPIO_CONTROL_HIGH, 
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 56, CRT0_ZVPORT8_PANEL0) |		
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 57, CRT1_ZVPORT9_PANEL1) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 58, CRT2_ZVPORT10_PANEL8) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 59, CRT3_ZVPORT11_PANEL9) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 60, CRT4_ZVPORT12_PANEL16) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 61, CRT5_ZVPORT13_PANEL17) );
+
+
+
+	if (init->mclk) {
+		dev_dbg(sm->dev, "setting MCLK to %ld\n", init->mclk);
+		sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
+	}
+
+	if (init->m1xclk) {
+		dev_dbg(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
+		sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
+	
+	}
+}
+
+/* sm501_init_dev
+ *
+ * Common init code for an SM501
+*/
+
+static int sm501_init_dev(struct sm501_devdata *sm, struct device *dev)
+{
+	int ret;
+	
+
+	mutex_init(&sm->clock_lock);
+	spin_lock_init(&sm->reg_lock);
+	INIT_LIST_HEAD(&sm->devices);
+	
+	sm50x_mem_size = sm501_get_memory_size();
+	
+	dev_info(sm->dev, "SM502/SM107 At %p: Version %08x, %ld Mb, IRQ %d\n",
+		 sm->regs, SmRead32( DEVICE_ID),(unsigned long)sm50x_mem_size >> 20, sm->irq);
+
+	dev_dbg(sm->dev, "CurrentGate      %08x\n", SmRead32(CURRENT_GATE));
+	dev_dbg(sm->dev, "CurrentClock     %08x\n", SmRead32(CURRENT_POWER_CLOCK));
+	dev_dbg(sm->dev, "PowerModeControl %08x\n", SmRead32(POWER_MODE_CTRL));
+
+	ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
+	if (ret)
+		dev_err(sm->dev, "failed to create debug regs file\n");
+
+
+	SmWrite32(ENDIAN_CONTROL,~0);
+
+	/* check to see if we have some device initialisation */
+
+	if (sm->platdata) {
+		struct sm501_platdata *pdata = sm->platdata;
+
+		if (pdata->init) {
+			sm501_init_regs(sm, sm->platdata->init);
+
+			if (pdata->init->devices & SM501_USE_FB)		
+			sm501_register_display(sm);
+
+			printk(KERN_INFO"devices is 0x%x\n", pdata->init->devices);
+			if (pdata->init->devices & SM501_USE_USB_HOST )
+				sm501_register_usbhost(sm, dev);
+			if (pdata->init->devices & SM501_USE_AC97)
+				sm501_register_audio(sm);
+			if ((pdata->init->devices & SM501_USE_UART0) ||
+				(pdata->init->devices & SM501_USE_UART1))
+				sm501_register_uart(sm);
+			if (pdata->init->devices & SM501_USE_GPIO)
+                sm501_register_gpio(sm);
+#if 0
+			if (pdata->init->devices & SM501_USE_I2C) {
+				printk("Using SM501 I2C module\n");
+				sm501_register_i2c(sm);
+			}
+#endif			
+		}
+	}
+
+	return 0;
+}
+
+static int sm501_plat_probe(struct platform_device *dev)
+{
+	struct sm501_devdata *sm;
+	int err;
+
+	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
+	if (sm == NULL) {
+		dev_err(&dev->dev, "no memory for device data\n");
+		err = -ENOMEM;
+		goto err1;
+	}
+
+	sm->dev = &dev->dev;
+	sm->pdev_id = dev->id;
+	sm->irq = platform_get_irq(dev, 0);
+	sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
+	sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	sm->platdata = dev->dev.platform_data;
+
+	if (sm->irq < 0) {
+		dev_err(&dev->dev, "failed to get irq resource\n");
+		err = sm->irq;
+		goto err_res;
+	}
+
+	if (sm->io_res == NULL || sm->mem_res == NULL) {
+		dev_err(&dev->dev, "failed to get IO resource\n");
+		err = -ENOENT;
+		goto err_res;
+	}
+
+	/* check register */
+	sm->regs_claim = request_mem_region(sm->io_res->start,
+					    0x100, "sm501");
+
+	if (sm->regs_claim == NULL) {
+		dev_err(&dev->dev, "cannot claim registers\n");
+		err= -EBUSY;
+		goto err_res;
+	}
+
+	platform_set_drvdata(dev, sm);
+
+	/* mapping register */
+	sm->regs = sm50x_base_reg = ioremap(sm->io_res->start,
+			   (sm->io_res->end - sm->io_res->start) - 1);
+
+	printk("---------sm50x_base_reg:%08x \n",sm50x_base_reg);
+	/*
+	 * By Belcon:
+	 * mapping framebuffer
+	 */
+//	sm->fb_mem = ioremap(sm->mem_res->start, sm50x_mem_size - 1);
+
+	if (sm->regs == NULL) {
+		dev_err(&dev->dev, "cannot remap registers\n");
+		err = -EIO;
+		goto err_claim;
+	}
+
+	sm->chipRevID = FIELD_GET(SmRead32(DEVICE_ID), DEVICE_ID, REVISION);
+	
+	return sm501_init_dev(sm, &dev->dev);
+
+ err_claim:
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+ err_res:
+	kfree(sm);
+ err1:
+	return err;
+
+}
+
+
+/* Initialisation data for graphic modules */
+static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
+	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
+			   SM501FB_FLAG_USE_HWCURSOR |
+			   SM501FB_FLAG_USE_HWACCEL |
+			   SM501FB_FLAG_DISABLE_AT_EXIT),
+};
+
+static struct sm501_platdata_fb sm501_fb_pdata = {
+	.fb_crt		= &sm501_pdata_fbsub,
+	.fb_pnl		= &sm501_pdata_fbsub,
+};
+
+/* Initialisation data for PCI devices */
+static struct sm501_initdata sm501_pci_initdata = {
+	.devices	= SM501_USE_ALL,	
+	.mclk		= 84 * MHZ,
+	//.m1xclk		= 144 * MHZ,
+	.m1xclk		= 112 * MHZ,
+};
+
+static struct sm501_platdata sm501_pci_platdata = {
+	.init		= &sm501_pci_initdata,
+	.fb		= &sm501_fb_pdata,
+	.gpio_base  = 0,
+};
+
+static int sm501_pci_probe(struct pci_dev *dev,
+			   const struct pci_device_id *id)
+{
+	struct sm501_devdata *sm;
+	int err;
+	unsigned long	mem_start, mem_end, mem_length;
+
+	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
+	if (sm == NULL) {
+		dev_err(&dev->dev, "no memory for device data\n");
+		err = -ENOMEM;
+		goto err1;
+	}
+
+	/* set a default set of platform data */
+	dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
+
+	/* set a hopefully unique id for our child platform devices */
+	sm->pdev_id = 32 + dev->devfn;
+
+	pci_set_drvdata(dev, sm);
+
+	err = pci_enable_device(dev);
+	if (err) {
+		dev_err(&dev->dev, "cannot enable device\n");
+		goto err2;
+	}
+
+	sm->dev = &dev->dev;
+	sm->irq = dev->irq;
+
+#ifdef __BIG_ENDIAN
+	/* if the system is big-endian, we most probably have a
+	 * translation in the IO layer making the PCI bus little endian
+	 * so make the framebuffer swapped pixels */
+	sm->platdata->init->flags |= SM501_FBPD_SWAP_FB_ENDIAN;
+	sm->platdata->fb->flags |= SM501_FBPD_SWAP_FB_ENDIAN;
+#endif
+
+	/* check our resources */
+
+	if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
+		dev_err(&dev->dev, "region #0 is not memory?\n");
+		err = -EINVAL;
+		goto err3;
+	}
+
+	if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
+		dev_err(&dev->dev, "region #1 is not memory?\n");
+		err = -EINVAL;
+		goto err3;
+	}
+
+	pci_read_config_byte(dev, PCI_REVISION_ID, &sm->chipRevID);
+
+	/* make our resources ready for sharing */
+
+	sm->io_res = &dev->resource[1];
+	sm->mem_res = &dev->resource[0];
+
+	/* check register */
+	sm->regs_claim = request_mem_region(sm->io_res->start,0x100, "sm501");
+	
+	if (sm->regs_claim == NULL) {
+		dev_err(&dev->dev, "cannot claim registers\n");
+		err= -EBUSY;
+		goto err3;
+	}
+
+	/* mapping register */
+	sm->regs = sm50x_base_reg = ioremap(pci_resource_start(dev, 1), pci_resource_len(dev, 1));
+	printk("--2-------sm50x_base_reg:%08x \n",sm50x_base_reg);
+	
+	if (sm->regs == NULL) {
+		dev_err(&dev->dev, "cannot remap registers\n");
+		err = -EIO;
+		goto err4;
+	}
+
+	mem_start = pci_resource_start(dev, 0);
+	mem_end = pci_resource_end(dev, 0);
+	mem_length = pci_resource_len(dev, 0);
+	sm501_init_dev(sm, &dev->dev);
+	
+	/*
+	 * By Belcon:
+	 * mapping framebuffer
+	 */
+	sm->fb_mem = sm50x_base_mem = ioremap(mem_start, mem_length);
+
+	return 0;
+
+ err4:
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+ err3:
+	pci_disable_device(dev);
+ err2:
+	pci_set_drvdata(dev, NULL);
+	kfree(sm);
+ err1:
+	return err;
+}
+
+static void sm501_remove_sub(struct sm501_devdata *sm,
+			     struct sm501_sub_device_list *smdevs)
+{
+	list_del(&smdevs->list);
+	platform_device_unregister(&smdevs->pdev);
+}
+
+static void sm501_dev_remove(struct sm501_devdata *sm)
+{
+	struct sm501_sub_device_list *smdevs, *tmp;
+
+	list_for_each_entry_safe(smdevs, tmp, &sm->devices, list)
+		sm501_remove_sub(sm, smdevs);
+
+	device_remove_file(sm->dev, &dev_attr_dbg_regs);
+}
+
+static void sm501_pci_remove(struct pci_dev *dev)
+{
+	struct sm501_devdata *sm = pci_get_drvdata(dev);
+
+	sm501_dev_remove(sm);
+	iounmap(sm->regs);
+	iounmap(sm->fb_mem );
+
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+
+
+	
+	pci_set_drvdata(dev, NULL);
+	pci_disable_device(dev);
+}
+
+static int sm501_plat_remove(struct platform_device *dev)
+{
+	struct sm501_devdata *sm = platform_get_drvdata(dev);
+
+	sm501_dev_remove(sm);
+	iounmap(sm->regs);
+
+	release_resource(sm->regs_claim);
+	kfree(sm->regs_claim);
+
+	return 0;
+}
+static int sm501_chr_open(struct inode *inode, struct file *flip)
+{
+	return 0;
+}
+static int sm501_chr_release(struct inode *inode, struct file *flip)
+{
+	return 0;
+}
+
+static int sm501_chr_ioctl(struct inode *inode, struct file *flip, u32 cmd, unsigned long arg)
+{
+	switch (cmd)
+	{
+		case SM501_IOCTL_SMREAD:
+		{
+			unsigned long value = 0;
+			unsigned long ret_value = 0;
+			PREGDATA pregdata;
+			copy_from_user(pregdata, (void *)arg, sizeof(PREGDATA));
+			pregdata->data = SmRead32(pregdata->address);
+			copy_to_user((void *)arg, pregdata, sizeof(PREGDATA));
+			break;
+		}
+		case SM501_IOCTL_SMWRITE:
+		{
+			PREGDATA pregdata;
+			copy_from_user(pregdata, (void *)arg, sizeof(PREGDATA));
+			SmWrite32(pregdata->address, pregdata->data);
+			break;
+		}
+		case SM501_GET_CURSOR:
+		{
+			PREGDATA pregdata;
+			copy_from_user(pregdata, (void *)arg, sizeof(PREGDATA));
+			pregdata->data = sm50x_base_mem + pregdata->address;
+			copy_to_user((void *)arg, pregdata, sizeof(PREGDATA));
+			break;
+		}
+		case SM501_SET_CURSOR:
+		{
+			PCURSORDATA pcursor_data;
+			copy_from_user(pcursor_data, (void *)arg, sizeof(PCURSORDATA));
+			memcpy(sm50x_base_mem + pcursor_data->address, pcursor_data->data, 64 * 16);
+			break;
+		}
+		default:
+		{
+			printk("No such command!\n");
+		}
+	}
+	return 0;
+}
+#include "i2c-sm502.c" //mj
+
+static struct file_operations sm501_chr_fops = {
+	.owner		= THIS_MODULE,
+	.open		= sm501_chr_open,
+	.release	= sm501_chr_release,
+	.ioctl		= sm501_chr_ioctl,
+};
+
+static struct pci_device_id sm501_pci_tbl[] = {
+	{ 0x126f, 0x501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+	{ 0, },
+};
+
+MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
+
+/*For PCI bus*/
+static struct pci_driver sm501_pci_drv = {
+	.name		= "sm501",
+	.id_table	= sm501_pci_tbl,
+	.probe		= sm501_pci_probe,
+	.remove		= sm501_pci_remove,
+};
+
+/*For Platform bus*/
+static struct platform_driver sm501_plat_drv = {
+	.driver		= {
+		.name	= "sm501",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= sm501_plat_probe,
+	.remove		= sm501_plat_remove,
+};
+
+static int __init sm501_base_init(void)
+{
+	platform_driver_register(&sm501_plat_drv);
+	register_chrdev(SM501_CHAR_MAJOR, "sm501", &sm501_chr_fops);
+	return pci_register_driver(&sm501_pci_drv);
+}
+
+static void __exit sm501_base_exit(void)
+{
+	platform_driver_unregister(&sm501_plat_drv);
+	unregister_chrdev(SM501_CHAR_MAJOR, "sm501");
+	pci_unregister_driver(&sm501_pci_drv);
+}
+
+module_init(sm501_base_init);
+module_exit(sm501_base_exit);
+
+MODULE_DESCRIPTION("SM50x/SM107 Core Driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders, Boyod Yang");
+MODULE_LICENSE("GPL v2");
diff -uNra linux-2.6.27.6/drivers/mfd/sm501.c linux-2.6.27.6.yaffs/drivers/mfd/sm501.c
--- linux-2.6.27.6/drivers/mfd/sm501.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mfd/sm501.c	2011-10-27 17:32:17.000000000 +0800
@@ -1,14 +1,18 @@
-/* linux/drivers/mfd/sm501.c
+/* linux/drivers/mfd/sm50x.c
+ *
+ * Copyright (C) 2010 SiliconMotion Inc.
+ * Copyright (c) 2006 Simtec Electronics
  *
- * Copyright (C) 2006 Simtec Electronics
  *	Ben Dooks <ben@simtec.co.uk>
  *	Vincent Sanders <vince@simtec.co.uk>
- *
+ *	Boyod.yang,  <boyod.yang@siliconmotion.com.cn>
+ *    Teddy.wang,  <teddy.wang@siliconmotion.com>
+ *	
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License version 2 
+ * or later as published by the Free Software Foundation. 
  *
- * SM501 MFD driver
+ * SM50x/SM107  MFD driver
 */
 
 #include <linux/kernel.h>
@@ -19,371 +23,153 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/pci.h>
-#include <linux/i2c-gpio.h>
 
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif
+#define SM501_CHAR_MAJOR 245
 #include <linux/sm501.h>
+#include <linux/sm501_regs.h>
 #include <linux/sm501-regs.h>
-#include <linux/serial_8250.h>
 
 #include <asm/io.h>
+#include <asm/uaccess.h>
 
-struct sm501_device {
-	struct list_head		list;
-	struct platform_device		pdev;
-};
-
-struct sm501_gpio;
-
-#ifdef CONFIG_MFD_SM501_GPIO
-#include <linux/gpio.h>
+static unsigned char __iomem *sm50x_base_reg = NULL;
+static unsigned char __iomem *sm50x_base_mem = NULL;
+resource_size_t sm50x_mem_size = 0;
+EXPORT_SYMBOL_GPL(sm50x_mem_size);
 
-struct sm501_gpio_chip {
-	struct gpio_chip	gpio;
-	struct sm501_gpio	*ourgpio;	/* to get back to parent. */
-	void __iomem		*regbase;
+static unsigned int sm501_mem_local[] = {
+	[0]	= 4*1024*1024,
+	[1]	= 8*1024*1024,
+	[2]	= 16*1024*1024,
+	[3]	= 32*1024*1024,
+	[4]	= 64*1024*1024,
+	[5]	= 2*1024*1024,
 };
 
-struct sm501_gpio {
-	struct sm501_gpio_chip	low;
-	struct sm501_gpio_chip	high;
-	spinlock_t		lock;
-
-	unsigned int		 registered : 1;
-	void __iomem		*regs;
-	struct resource		*regs_res;
-};
-#else
-struct sm501_gpio {
-	/* no gpio support, empty definition for sm501_devdata. */
+struct sm501_sub_device_list {
+	struct list_head		list;
+	struct platform_device		pdev;
 };
-#endif
 
 struct sm501_devdata {
 	spinlock_t			 reg_lock;
 	struct mutex			 clock_lock;
 	struct list_head		 devices;
-	struct sm501_gpio		 gpio;
 
 	struct device			*dev;
 	struct resource			*io_res;
 	struct resource			*mem_res;
 	struct resource			*regs_claim;
+	struct resource			*mem_claim;
 	struct sm501_platdata		*platdata;
 
-
 	unsigned int			 in_suspend;
-	unsigned long			 pm_misc;
-
 	int				 unit_power[20];
 	unsigned int			 pdev_id;
+	u8					 chipRevID;
 	unsigned int			 irq;
 	void __iomem			*regs;
-	unsigned int			 rev;
-};
-
-
-#define MHZ (1000 * 1000)
+	void __iomem			*fb_mem;
 
-#ifdef DEBUG
-static const unsigned int div_tab[] = {
-	[0]		= 1,
-	[1]		= 2,
-	[2]		= 4,
-	[3]		= 8,
-	[4]		= 16,
-	[5]		= 32,
-	[6]		= 64,
-	[7]		= 128,
-	[8]		= 3,
-	[9]		= 6,
-	[10]	        = 12,
-	[11]		= 24,
-	[12]		= 48,
-	[13]		= 96,
-	[14]		= 192,
-	[15]		= 384,
-	[16]		= 5,
-	[17]		= 10,
-	[18]		= 20,
-	[19]		= 40,
-	[20]		= 80,
-	[21]		= 160,
-	[22]		= 320,
-	[23]		= 604,
+	/* mtrr support */
+	int mtrr_reg;
+	u32 has_mtrr;
 };
 
-static unsigned long decode_div(unsigned long pll2, unsigned long val,
-				unsigned int lshft, unsigned int selbit,
-				unsigned long mask)
+/* SmRead8()
+ * 
+ *    Read the 8-bit value, to the 8-bit register location
+ *    specified by nOffset
+ *
+*/
+unsigned long SmRead8(unsigned long nOffset)
 {
-	if (val & selbit)
-		pll2 = 288 * MHZ;
-
-	return pll2 / div_tab[(val >> lshft) & mask];
+    return readb(sm50x_base_reg + nOffset);
 }
 
-#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
-
-/* sm501_dump_clk
+/* SmRead16()
+ * 
+ *    Read the 16-bit value, to the 16-bit register location
+ *    specified by nOffset
  *
- * Print out the current clock configuration for the device
 */
-
-static void sm501_dump_clk(struct sm501_devdata *sm)
+unsigned long SmRead16(unsigned long nOffset)
 {
-	unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
-	unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
-	unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
-	unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
-	unsigned long sdclk0, sdclk1;
-	unsigned long pll2 = 0;
-
-	switch (misct & 0x30) {
-	case 0x00:
-		pll2 = 336 * MHZ;
-		break;
-	case 0x10:
-		pll2 = 288 * MHZ;
-		break;
-	case 0x20:
-		pll2 = 240 * MHZ;
-		break;
-	case 0x30:
-		pll2 = 192 * MHZ;
-		break;
-	}
-
-	sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
-	sdclk0 /= div_tab[((misct >> 8) & 0xf)];
-
-	sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
-	sdclk1 /= div_tab[((misct >> 16) & 0xf)];
-
-	dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
-		misct, pm0, pm1);
-
-	dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
-		fmt_freq(pll2), sdclk0, sdclk1);
-
-	dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
-
-	dev_dbg(sm->dev, "PM0[%c]: "
-		 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
-		 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
-		 (pmc & 3 ) == 0 ? '*' : '-',
-		 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
-		 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
-		 fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
-		 fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
-
-	dev_dbg(sm->dev, "PM1[%c]: "
-		"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
-		"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
-		(pmc & 3 ) == 1 ? '*' : '-',
-		fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
-		fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
-		fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
-		fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
-}
-
-static void sm501_dump_regs(struct sm501_devdata *sm)
-{
-	void __iomem *regs = sm->regs;
-
-	dev_info(sm->dev, "System Control   %08x\n",
-			readl(regs + SM501_SYSTEM_CONTROL));
-	dev_info(sm->dev, "Misc Control     %08x\n",
-			readl(regs + SM501_MISC_CONTROL));
-	dev_info(sm->dev, "GPIO Control Low %08x\n",
-			readl(regs + SM501_GPIO31_0_CONTROL));
-	dev_info(sm->dev, "GPIO Control Hi  %08x\n",
-			readl(regs + SM501_GPIO63_32_CONTROL));
-	dev_info(sm->dev, "DRAM Control     %08x\n",
-			readl(regs + SM501_DRAM_CONTROL));
-	dev_info(sm->dev, "Arbitration Ctrl %08x\n",
-			readl(regs + SM501_ARBTRTN_CONTROL));
-	dev_info(sm->dev, "Misc Timing      %08x\n",
-			readl(regs + SM501_MISC_TIMING));
-}
-
-static void sm501_dump_gate(struct sm501_devdata *sm)
-{
-	dev_info(sm->dev, "CurrentGate      %08x\n",
-			readl(sm->regs + SM501_CURRENT_GATE));
-	dev_info(sm->dev, "CurrentClock     %08x\n",
-			readl(sm->regs + SM501_CURRENT_CLOCK));
-	dev_info(sm->dev, "PowerModeControl %08x\n",
-			readl(sm->regs + SM501_POWER_MODE_CONTROL));
-}
-
-#else
-static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
-static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
-static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
-#endif
+    return readw(sm50x_base_reg + nOffset);
+}
 
-/* sm501_sync_regs
+/* SmRead32()
+ * 
+ *    Read the 32-bit value, to the 32-bit register location
+ *    specified by nOffset
  *
- * ensure the
 */
-
-static void sm501_sync_regs(struct sm501_devdata *sm)
+unsigned long SmRead32(unsigned long nOffset)
 {
-	readl(sm->regs);
+    return readl(sm50x_base_reg + nOffset);
 }
 
-static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
+const unsigned char __iomem * SmIoAddress()
 {
-	/* during suspend/resume, we are currently not allowed to sleep,
-	 * so change to using mdelay() instead of msleep() if we
-	 * are in one of these paths */
-
-	if (sm->in_suspend)
-		mdelay(delay);
-	else
-		msleep(delay);
+	return (sm50x_base_reg);
 }
 
-/* sm501_misc_control
+EXPORT_SYMBOL_GPL(SmRead8);
+EXPORT_SYMBOL_GPL(SmRead16);
+EXPORT_SYMBOL_GPL(SmRead32);
+EXPORT_SYMBOL_GPL(SmIoAddress);
+
+/* SmWrite8()
+ * 
+ *    Write the 8-bit value, to the 8-bit register location
+ *    specified by nOffset
  *
- * alters the miscellaneous control parameters
 */
-
-int sm501_misc_control(struct device *dev,
-		       unsigned long set, unsigned long clear)
+void SmWrite8(unsigned long nOffset, unsigned long nData)
 {
-	struct sm501_devdata *sm = dev_get_drvdata(dev);
-	unsigned long misc;
-	unsigned long save;
-	unsigned long to;
-
-	spin_lock_irqsave(&sm->reg_lock, save);
-
-	misc = readl(sm->regs + SM501_MISC_CONTROL);
-	to = (misc & ~clear) | set;
-
-	if (to != misc) {
-		writel(to, sm->regs + SM501_MISC_CONTROL);
-		sm501_sync_regs(sm);
-
-		dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
-	}
-
-	spin_unlock_irqrestore(&sm->reg_lock, save);
-	return to;
+	writeb(nData,sm50x_base_reg + nOffset);
 }
 
-EXPORT_SYMBOL_GPL(sm501_misc_control);
-
-/* sm501_modify_reg
+/* SmWrite16()
+ * 
+ *    Write the 16-bit value, to the 16-bit register location
+ *    specified by nOffset
  *
- * Modify a register in the SM501 which may be shared with other
- * drivers.
 */
-
-unsigned long sm501_modify_reg(struct device *dev,
-			       unsigned long reg,
-			       unsigned long set,
-			       unsigned long clear)
+void SmWrite16(unsigned long nOffset, unsigned long nData)
 {
-	struct sm501_devdata *sm = dev_get_drvdata(dev);
-	unsigned long data;
-	unsigned long save;
-
-	spin_lock_irqsave(&sm->reg_lock, save);
-
-	data = readl(sm->regs + reg);
-	data |= set;
-	data &= ~clear;
-
-	writel(data, sm->regs + reg);
-	sm501_sync_regs(sm);
-
-	spin_unlock_irqrestore(&sm->reg_lock, save);
-
-	return data;
+	writew(nData,sm50x_base_reg + nOffset);
 }
 
-EXPORT_SYMBOL_GPL(sm501_modify_reg);
-
-/* sm501_unit_power
+/* SmWrite32()
+ * 
+ *    Write the 32-bit value, to the 32-bit register location
+ *    specified by nOffset
  *
- * alters the power active gate to set specific units on or off
- */
-
-int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
+*/
+void SmWrite32(unsigned long nOffset, unsigned long nData)
 {
-	struct sm501_devdata *sm = dev_get_drvdata(dev);
-	unsigned long mode;
-	unsigned long gate;
-	unsigned long clock;
-
-	mutex_lock(&sm->clock_lock);
-
-	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
-	gate = readl(sm->regs + SM501_CURRENT_GATE);
-	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
-
-	mode &= 3;		/* get current power mode */
-
-	if (unit >= ARRAY_SIZE(sm->unit_power)) {
-		dev_err(dev, "%s: bad unit %d\n", __func__, unit);
-		goto already;
-	}
-
-	dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
-		sm->unit_power[unit], to);
-
-	if (to == 0 && sm->unit_power[unit] == 0) {
-		dev_err(sm->dev, "unit %d is already shutdown\n", unit);
-		goto already;
-	}
-
-	sm->unit_power[unit] += to ? 1 : -1;
-	to = sm->unit_power[unit] ? 1 : 0;
-
-	if (to) {
-		if (gate & (1 << unit))
-			goto already;
-		gate |= (1 << unit);
-	} else {
-		if (!(gate & (1 << unit)))
-			goto already;
-		gate &= ~(1 << unit);
-	}
-
-	switch (mode) {
-	case 1:
-		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
-		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
-		mode = 0;
-		break;
-	case 2:
-	case 0:
-		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
-		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
-		mode = 1;
-		break;
-
-	default:
-		return -1;
-	}
-
-	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
-	sm501_sync_regs(sm);
-
-	dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
-		gate, clock, mode);
+	writel(nData,sm50x_base_reg + nOffset);
+}
 
-	sm501_mdelay(sm, 16);
+EXPORT_SYMBOL_GPL(SmWrite8);
+EXPORT_SYMBOL_GPL(SmWrite16);
+EXPORT_SYMBOL_GPL(SmWrite32);
 
- already:
-	mutex_unlock(&sm->clock_lock);
-	return gate;
+void SmMemset(unsigned long nOffset, unsigned char val, int count)
+{
+	memset((void __force *) (sm50x_base_reg + nOffset), val, count);
 }
 
-EXPORT_SYMBOL_GPL(sm501_unit_power);
+EXPORT_SYMBOL_GPL(SmMemset);
 
+static void sm501_sync_regs()
+{
+	SmRead32(0);
+}
 
 /* Perform a rounded division. */
 static long sm501fb_round_div(long num, long denom)
@@ -392,117 +178,170 @@
         return (2 * num + denom) / (2 * denom);
 }
 
+void sm501_configure_gpio(unsigned int gpio, unsigned char mode) 
+{ 
+    unsigned long conf; 
+    unsigned long reg; 
+    unsigned long offset = gpio; 
+ 
+    if (offset >= 32) { 
+        reg = SM501_GPIO63_32_CONTROL; 
+        offset = gpio - 32; 
+    } else 
+        reg = SM501_GPIO31_0_CONTROL; 
+ 
+    conf = readl(sm50x_base_reg + reg); 
+    conf &= ~(1 << offset); 
+    if (mode) 
+        conf |= (1 << offset); 
+    writel(conf, sm50x_base_reg + reg); 
+} 
+EXPORT_SYMBOL_GPL(sm501_configure_gpio);
+
+void sm501_date_gpio(unsigned int gpio, unsigned char mode) 
+{ 
+    unsigned long conf; 
+    unsigned long reg; 
+    unsigned long offset = gpio; 
+ 
+    if (offset >= 32) { 
+        reg = 0x10004; 
+        offset = gpio - 32; 
+    } else 
+        reg = 0x10000; 
+ 
+    conf = readl(sm50x_base_reg + reg); 
+//	printk("[date-1]conf = 0x%x\n",conf);//add by zhao
+    conf &= ~(1 << offset); 
+    if (mode) 
+        conf |= (1 << offset); 
+    writel(conf, sm50x_base_reg + reg); 
+} 
+
+EXPORT_SYMBOL_GPL(sm501_date_gpio);
+void sm501_dir_gpio(unsigned int gpio, unsigned char mode) 
+{ 
+    unsigned long conf; 
+    unsigned long reg; 
+    unsigned long offset = gpio; 
+ 
+    if (offset >= 32) { 
+        reg = 0x1000c; 
+        offset = gpio - 32; 
+    } else 
+        reg = 0x10008; 
+
+    conf = readl(sm50x_base_reg + reg); 
+    conf &= ~(1 << offset); 
+    if (mode) 
+        conf |= (1 << offset); 
+    writel(conf, sm50x_base_reg + reg); 
+} 
+EXPORT_SYMBOL_GPL(sm501_dir_gpio);
+
 /* clock value structure. */
 struct sm501_clock {
 	unsigned long mclk;
 	int divider;
 	int shift;
-	unsigned int m, n, k;
+
+	long multipleM;
+	int dividerN;
+	short divby2;
 };
 
-/* sm501_calc_clock
+/* sm501_select_clock
  *
- * Calculates the nearest discrete clock frequency that
- * can be achieved with the specified input clock.
+ * selects nearest discrete clock frequency the SM501 can achive
  *   the maximum divisor is 3 or 5
  */
-
-static int sm501_calc_clock(unsigned long freq,
-			    struct sm501_clock *clock,
-			    int max_div,
-			    unsigned long mclk,
-			    long *best_diff)
+static unsigned long sm501_select_clock(unsigned long freq,
+					struct sm501_clock *clock,
+					int max_div)
 {
-	int ret = 0;
+	unsigned long mclk;
 	int divider;
 	int shift;
 	long diff;
+	long best_diff = 999999999;
 
-	/* try dividers 1 and 3 for CRT and for panel,
-	   try divider 5 for panel only.*/
+	/* Try 288MHz and 336MHz clocks. */
+	for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
+		/* try dividers 1 and 3 for CRT and for panel,
+		   try divider 5 for panel only.*/
 
-	for (divider = 1; divider <= max_div; divider += 2) {
-		/* try all 8 shift values.*/
-		for (shift = 0; shift < 8; shift++) {
-			/* Calculate difference to requested clock */
-			diff = sm501fb_round_div(mclk, divider << shift) - freq;
-			if (diff < 0)
-				diff = -diff;
-
-			/* If it is less than the current, use it */
-			if (diff < *best_diff) {
-				*best_diff = diff;
-
-				clock->mclk = mclk;
-				clock->divider = divider;
-				clock->shift = shift;
-				ret = 1;
+		for (divider = 1; divider <= max_div; divider += 2) {
+			/* try all 8 shift values.*/
+			for (shift = 0; shift < 8; shift++) {
+				/* Calculate difference to requested clock */
+				diff = sm501fb_round_div(mclk, divider << shift) - freq;
+				if (diff < 0)
+					diff = -diff;
+
+				/* If it is less than the current, use it */
+				if (diff < best_diff) {
+					best_diff = diff;
+
+					clock->mclk = mclk;
+					clock->divider = divider;
+					clock->shift = shift;
+				}
 			}
 		}
 	}
 
-	return ret;
+	/* Return best clock. */
+	return clock->mclk / (clock->divider << clock->shift);
 }
 
-/* sm501_calc_pll
+
+#ifdef CONFIG_MTRR
+
+/* sm501fb_set_mtrr
  *
- * Calculates the nearest discrete clock frequency that can be
- * achieved using the programmable PLL.
- *   the maximum divisor is 3 or 5
- */
+ * mtrr support functions 
+*/
 
-static unsigned long sm501_calc_pll(unsigned long freq,
-					struct sm501_clock *clock,
-					int max_div)
+void  sm501fb_set_mtrr(struct device *dev)
 {
-	unsigned long mclk;
-	unsigned int m, n, k;
-	long best_diff = 999999999;
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
 
-	/*
-	 * The SM502 datasheet doesn't specify the min/max values for M and N.
-	 * N = 1 at least doesn't work in practice.
-	 */
-	for (m = 2; m <= 255; m++) {
-		for (n = 2; n <= 127; n++) {
-			for (k = 0; k <= 1; k++) {
-				mclk = (24000000UL * m / n) >> k;
-
-				if (sm501_calc_clock(freq, clock, max_div,
-						     mclk, &best_diff)) {
-					clock->m = m;
-					clock->n = n;
-					clock->k = k;
-				}
-			}
-		}
+	sm->mtrr_reg = mtrr_add(sm->mem_res->start,
+				   ((sm->mem_res->end - sm->mem_res->start) - 2*0x10000)-1, MTRR_TYPE_WRCOMB, 1);
+	if (sm->mtrr_reg < 0) {
+		dev_info(sm->dev,"unable to set MTRR\n");
+		return;
 	}
-
-	/* Return best clock. */
-	return clock->mclk / (clock->divider << clock->shift);
+	sm->has_mtrr = 1;
 }
+EXPORT_SYMBOL_GPL(sm501fb_set_mtrr);
 
-/* sm501_select_clock
+/* sm501fb_unset_mtrr
  *
- * Calculates the nearest discrete clock frequency that can be
- * achieved using the 288MHz and 336MHz PLLs.
- *   the maximum divisor is 3 or 5
- */
+ * mtrr support functions 
+*/
 
-static unsigned long sm501_select_clock(unsigned long freq,
-					struct sm501_clock *clock,
-					int max_div)
+void sm501fb_unset_mtrr(struct device *dev)
 {
-	unsigned long mclk;
-	long best_diff = 999999999;
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
 
-	/* Try 288MHz and 336MHz clocks. */
-	for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
-		sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
-	}
+  	if (sm->has_mtrr)
+  		mtrr_del(sm->mtrr_reg, sm->mem_res->start,
+			  ((sm->mem_res->end - sm->mem_res->start) - 2*0x10000)-1);
+}
+EXPORT_SYMBOL_GPL(sm501fb_unset_mtrr);
 
-	/* Return best clock. */
-	return clock->mclk / (clock->divider << clock->shift);
+#endif
+
+
+/* sm501_get_memory_size
+ *
+ * get memory size of sm501
+*/
+
+static resource_size_t sm501_get_memory_size()
+{
+	return sm501_mem_local[FIELD_GET(SmRead32(DRAM_CONTROL),DRAM_CONTROL,LOCAL_SIZE)];
 }
 
 /* sm501_set_clock
@@ -510,18 +349,15 @@
  * set one of the four clock sources to the closest available frequency to
  *  the one specified
 */
-
 unsigned long sm501_set_clock(struct device *dev,
 			      int clksrc,
 			      unsigned long req_freq)
 {
 	struct sm501_devdata *sm = dev_get_drvdata(dev);
-	unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
-	unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
-	unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
-	unsigned char reg;
-	unsigned int pll_reg = 0;
-	unsigned long sm501_freq; /* the actual frequency acheived */
+	unsigned long mode = SmRead32(POWER_MODE_CTRL);
+	unsigned long clock = SmRead32(CURRENT_POWER_CLOCK);
+	unsigned char reg = 0;
+	unsigned long sm501_freq,pllclock; /* the actual frequency acheived */
 
 	struct sm501_clock to;
 
@@ -534,28 +370,27 @@
 		/* This clock is divided in half so to achive the
 		 * requested frequency the value must be multiplied by
 		 * 2. This clock also has an additional pre divisor */
-
-		if (sm->rev >= 0xC0) {
-			/* SM502 -> use the programmable PLL */
-			sm501_freq = (sm501_calc_pll(2 * req_freq,
-						     &to, 5) / 2);
-			reg = to.shift & 0x07;/* bottom 3 bits are shift */
-			if (to.divider == 3)
-				reg |= 0x08; /* /3 divider required */
-			else if (to.divider == 5)
-				reg |= 0x10; /* /5 divider required */
-			reg |= 0x40; /* select the programmable PLL */
-			pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
-		} else {
-			sm501_freq = (sm501_select_clock(2 * req_freq,
-							 &to, 5) / 2);
-			reg = to.shift & 0x07;/* bottom 3 bits are shift */
+		if (sm->chipRevID < SM502_REV_ID){
+			sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
+			reg=to.shift & 0x07;/* bottom 3 bits are shift */
 			if (to.divider == 3)
 				reg |= 0x08; /* /3 divider required */
 			else if (to.divider == 5)
 				reg |= 0x10; /* /5 divider required */
 			if (to.mclk != 288000000)
 				reg |= 0x20; /* which mclk pll is source */
+		}else
+		{
+			/*For new PLL in SM502*/
+			to.multipleM = (2 * req_freq)/(1000*1000);
+			to.dividerN = 24;
+			to.divby2 = 0;
+
+			while (to.multipleM > 192){
+			to.multipleM /= 2;
+			to.dividerN /= 2;
+			}
+			sm501_freq = req_freq;
 		}
 		break;
 
@@ -589,25 +424,46 @@
 
 	mutex_lock(&sm->clock_lock);
 
-	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
-	gate = readl(sm->regs + SM501_CURRENT_GATE);
-	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
-
+	mode = SmRead32(POWER_MODE_CTRL);
+	clock = SmRead32(CURRENT_POWER_CLOCK);
+	
 	clock = clock & ~(0xFF << clksrc);
 	clock |= reg<<clksrc;
 
-	mode &= 3;	/* find current mode */
+		/*For new PLL in SM502*/
+	if ( (sm->chipRevID >= SM502_REV_ID)&& (clksrc==SM501_CLOCK_P2XCLK) ){
+
+		pllclock = SmRead32(CURRENT_POWER_PLLCLOCK);
+
+		pllclock &= FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, MULTIPLE_M)
+				  &  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, DIVIDE_N)
+				  &  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, DIVIDEBY2)
+					&  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, INPUT_SELECT)
+					  &  FIELD_CLEAR(CURRENT_POWER_PLLCLOCK, POWER);
+		
+		SmWrite32(CURRENT_POWER_PLLCLOCK,
+				  FIELD_VALUE(pllclock, CURRENT_POWER_PLLCLOCK, MULTIPLE_M, to.multipleM)|
+					  FIELD_VALUE(pllclock, CURRENT_POWER_PLLCLOCK, DIVIDE_N, to.dividerN)|
+				              FIELD_VALUE(pllclock, CURRENT_POWER_PLLCLOCK, DIVIDEBY2, to.divby2)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, POWER, ON)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, INPUT_SELECT,CRYSTAL)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, TEST_OUTPUT, DISABLE)|
+				              FIELD_SET(pllclock, CURRENT_POWER_PLLCLOCK, TESTMODE, DISABLE));		
+
+		clock = (FIELD_SET(clock, CURRENT_POWER_CLOCK, PLLCLK_SELECT, ENABLE)|
+					FIELD_SET(clock, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 1)|
+					FIELD_SET(clock, CURRENT_POWER_CLOCK, P2XCLK_SHIFT, 0)  );
+		}	
+	
+	mode = FIELD_GET(mode, POWER_MODE_CTRL, MODE);	/* find current mode */
 
 	switch (mode) {
-	case 1:
-		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
-		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
+	case 0:
+		SmWrite32(POWER_MODE0_CLOCK, clock);
 		mode = 0;
 		break;
-	case 2:
-	case 0:
-		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
-		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
+	case 1:
+		SmWrite32(POWER_MODE1_CLOCK, clock);
 		mode = 1;
 		break;
 
@@ -616,49 +472,63 @@
 		return -1;
 	}
 
-	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
-
-	if (pll_reg)
-		writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
-
-	sm501_sync_regs(sm);
+	sm501_sync_regs();
 
-	dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
-		 gate, clock, mode);
+	dev_info(sm->dev, "clock %08lx, mode %08lx\n",
+		  clock, mode);
 
-	sm501_mdelay(sm, 16);
+	msleep(16);
 	mutex_unlock(&sm->clock_lock);
 
-	sm501_dump_clk(sm);
-
 	return sm501_freq;
 }
 
 EXPORT_SYMBOL_GPL(sm501_set_clock);
 
-/* sm501_find_clock
+
+/* sm501_set_gate
  *
- * finds the closest available frequency for a given clock
+ * set one of the four gate sources to the closest available frequency to
+ *  the one specified
 */
 
-unsigned long sm501_find_clock(struct device *dev,
-			       int clksrc,
-			       unsigned long req_freq)
+void sm501_set_gate( unsigned long gate)
+{
+
+	unsigned long mode = SmRead32(POWER_MODE_CTRL);
+	mode = FIELD_GET(mode, POWER_MODE_CTRL, MODE);	
+
+	switch (mode) {
+	case 0:
+		SmWrite32(POWER_MODE0_GATE, gate);
+		break;
+	case 1:
+		SmWrite32(POWER_MODE1_GATE, gate);
+		break;
+	default:
+		return;
+	}
+
+	sm501_sync_regs();
+	msleep(16);
+}
+
+EXPORT_SYMBOL_GPL(sm501_set_gate);
+			      
+/* sm501_find_clock
+ *
+ * finds the closest available frequency for a given clock
+*/
+
+unsigned long sm501_find_clock(int clksrc,
+			       unsigned long req_freq)
 {
-	struct sm501_devdata *sm = dev_get_drvdata(dev);
 	unsigned long sm501_freq; /* the frequency achiveable by the 501 */
 	struct sm501_clock to;
 
 	switch (clksrc) {
 	case SM501_CLOCK_P2XCLK:
-		if (sm->rev >= 0xC0) {
-			/* SM502 -> use the programmable PLL */
-			sm501_freq = (sm501_calc_pll(2 * req_freq,
-						     &to, 5) / 2);
-		} else {
-			sm501_freq = (sm501_select_clock(2 * req_freq,
-							 &to, 5) / 2);
-		}
+		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
 		break;
 
 	case SM501_CLOCK_V2XCLK:
@@ -679,561 +549,375 @@
 
 EXPORT_SYMBOL_GPL(sm501_find_clock);
 
-static struct sm501_device *to_sm_device(struct platform_device *pdev)
-{
-	return container_of(pdev, struct sm501_device, pdev);
-}
-
-/* sm501_device_release
- *
- * A release function for the platform devices we create to allow us to
- * free any items we allocated
-*/
-
-static void sm501_device_release(struct device *dev)
-{
-	kfree(to_sm_device(to_platform_device(dev)));
-}
-
-/* sm501_create_subdev
- *
- * Create a skeleton platform device with resources for passing to a
- * sub-driver
-*/
-
-static struct platform_device *
-sm501_create_subdev(struct sm501_devdata *sm, char *name,
-		    unsigned int res_count, unsigned int platform_data_size)
+static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
 {
-	struct sm501_device *smdev;
-
-	smdev = kzalloc(sizeof(struct sm501_device) +
-			(sizeof(struct resource) * res_count) +
-			platform_data_size, GFP_KERNEL);
-	if (!smdev)
-		return NULL;
-
-	smdev->pdev.dev.release = sm501_device_release;
-
-	smdev->pdev.name = name;
-	smdev->pdev.id = sm->pdev_id;
-	smdev->pdev.dev.parent = sm->dev;
-
-	if (res_count) {
-		smdev->pdev.resource = (struct resource *)(smdev+1);
-		smdev->pdev.num_resources = res_count;
-	}
-	if (platform_data_size)
-		smdev->pdev.dev.platform_data = (void *)(smdev+1);
+	/* during suspend/resume, we are currently not allowed to sleep,
+	 * so change to using mdelay() instead of msleep() if we
+	 * are in one of these paths */
 
-	return &smdev->pdev;
+	if (sm->in_suspend)
+		mdelay(delay);
+	else
+		msleep(delay);
 }
 
-/* sm501_register_device
+/* sm501_modify_reg
  *
- * Register a platform device created with sm501_create_subdev()
+ * Modify a register in the SM501 which may be shared with other
+ * drivers.
 */
-
-static int sm501_register_device(struct sm501_devdata *sm,
-				 struct platform_device *pdev)
+unsigned long sm501_modify_reg(struct device *dev,
+			       unsigned long reg,
+			       unsigned long set,
+			       unsigned long clear)
 {
-	struct sm501_device *smdev = to_sm_device(pdev);
-	int ptr;
-	int ret;
-
-	for (ptr = 0; ptr < pdev->num_resources; ptr++) {
-		printk("%s[%d] flags %08lx: %08llx..%08llx\n",
-		       pdev->name, ptr,
-		       pdev->resource[ptr].flags,
-		       (unsigned long long)pdev->resource[ptr].start,
-		       (unsigned long long)pdev->resource[ptr].end);
-	}
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long data;
+	unsigned long save;
 
-	ret = platform_device_register(pdev);
+	spin_lock_irqsave(&sm->reg_lock, save);
 
-	if (ret >= 0) {
-		dev_dbg(sm->dev, "registered %s\n", pdev->name);
-		list_add_tail(&smdev->list, &sm->devices);
-	} else
-		dev_err(sm->dev, "error registering %s (%d)\n",
-			pdev->name, ret);
+	data = readl(sm->regs + reg);
+	data |= set;
+	data &= ~clear;
 
-	return ret;
-}
+	writel(data, sm->regs + reg);
+	sm501_sync_regs(sm);
 
-/* sm501_create_subio
- *
- * Fill in an IO resource for a sub device
-*/
+	spin_unlock_irqrestore(&sm->reg_lock, save);
 
-static void sm501_create_subio(struct sm501_devdata *sm,
-			       struct resource *res,
-			       resource_size_t offs,
-			       resource_size_t size)
-{
-	res->flags = IORESOURCE_MEM;
-	res->parent = sm->io_res;
-	res->start = sm->io_res->start + offs;
-	res->end = res->start + size - 1;
+	return data;
 }
 
-/* sm501_create_mem
- *
- * Fill in an MEM resource for a sub device
-*/
-
-static void sm501_create_mem(struct sm501_devdata *sm,
-			     struct resource *res,
-			     resource_size_t *offs,
-			     resource_size_t size)
-{
-	*offs -= size;		/* adjust memory size */
-
-	res->flags = IORESOURCE_MEM;
-	res->parent = sm->mem_res;
-	res->start = sm->mem_res->start + *offs;
-	res->end = res->start + size - 1;
-}
+EXPORT_SYMBOL_GPL(sm501_modify_reg);
 
-/* sm501_create_irq
+/* sm501_unit_power
  *
- * Fill in an IRQ resource for a sub device
-*/
-
-static void sm501_create_irq(struct sm501_devdata *sm,
-			     struct resource *res)
-{
-	res->flags = IORESOURCE_IRQ;
-	res->parent = NULL;
-	res->start = res->end = sm->irq;
-}
+ * alters the power active gate to set specific units on or off
+ */
 
-static int sm501_register_usbhost(struct sm501_devdata *sm,
-				  resource_size_t *mem_avail)
+int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
 {
-	struct platform_device *pdev;
+	struct sm501_devdata *sm = dev_get_drvdata(dev);
+	unsigned long mode;
+	unsigned long gate;
+	unsigned long clock;
 
-	pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
-	if (!pdev)
-		return -ENOMEM;
+	mutex_lock(&sm->clock_lock);
 
-	sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
-	sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
-	sm501_create_irq(sm, &pdev->resource[2]);
+	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
+	gate = readl(sm->regs + SM501_CURRENT_GATE);
+	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 
-	return sm501_register_device(sm, pdev);
-}
+	mode &= 3;		/* get current power mode */
 
-static void sm501_setup_uart_data(struct sm501_devdata *sm,
-				  struct plat_serial8250_port *uart_data,
-				  unsigned int offset)
-{
-	uart_data->membase = sm->regs + offset;
-	uart_data->mapbase = sm->io_res->start + offset;
-	uart_data->iotype = UPIO_MEM;
-	uart_data->irq = sm->irq;
-	uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
-	uart_data->regshift = 2;
-	uart_data->uartclk = (9600 * 16);
-}
+	if (unit >= ARRAY_SIZE(sm->unit_power)) {
+		dev_err(dev, "%s: bad unit %d\n", __func__, unit);
+		goto already;
+	}
 
-static int sm501_register_uart(struct sm501_devdata *sm, int devices)
-{
-	struct platform_device *pdev;
-	struct plat_serial8250_port *uart_data;
+	dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
+		sm->unit_power[unit], to);
 
-	pdev = sm501_create_subdev(sm, "serial8250", 0,
-				   sizeof(struct plat_serial8250_port) * 3);
-	if (!pdev)
-		return -ENOMEM;
+	if (to == 0 && sm->unit_power[unit] == 0) {
+		dev_err(sm->dev, "unit %d is already shutdown\n", unit);
+		goto already;
+	}
 
-	uart_data = pdev->dev.platform_data;
+	sm->unit_power[unit] += to ? 1 : -1;
+	to = sm->unit_power[unit] ? 1 : 0;
 
-	if (devices & SM501_USE_UART0) {
-		sm501_setup_uart_data(sm, uart_data++, 0x30000);
-		sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
-		sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
-		sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
-	}
-	if (devices & SM501_USE_UART1) {
-		sm501_setup_uart_data(sm, uart_data++, 0x30020);
-		sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
-		sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
-		sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
+	if (to) {
+		if (gate & (1 << unit))
+			goto already;
+		gate |= (1 << unit);
+	} else {
+		if (!(gate & (1 << unit)))
+			goto already;
+		gate &= ~(1 << unit);
 	}
 
-	pdev->id = PLAT8250_DEV_SM501;
+	switch (mode) {
+	case 1:
+		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
+		mode = 0;
+		break;
+	case 2:
+	case 0:
+		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
+		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
+		mode = 1;
+		break;
 
-	return sm501_register_device(sm, pdev);
-}
+	default:
+		return -1;
+	}
 
-static int sm501_register_display(struct sm501_devdata *sm,
-				  resource_size_t *mem_avail)
-{
-	struct platform_device *pdev;
+	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
+	sm501_sync_regs(sm);
 
-	pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
-	if (!pdev)
-		return -ENOMEM;
+	dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
+		gate, clock, mode);
 
-	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
-	sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
-	sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
-	sm501_create_irq(sm, &pdev->resource[3]);
+	sm501_mdelay(sm, 16);
 
-	return sm501_register_device(sm, pdev);
+ already:
+	mutex_unlock(&sm->clock_lock);
+	return gate;
 }
 
-#ifdef CONFIG_MFD_SM501_GPIO
-
-static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
-{
-	return container_of(gc, struct sm501_gpio_chip, gpio);
-}
+EXPORT_SYMBOL_GPL(sm501_unit_power);
 
-static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
-{
-	return container_of(gpio, struct sm501_devdata, gpio);
-}
 
-static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
+/* sm501_dbg_regs
+ *
+ * Debug attribute to attach to parent device to show core registers
+*/
 
+static ssize_t sm50x_dbg_regs(struct device *dev,
+			      struct device_attribute *attr, char *buff)
 {
-	struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
-	unsigned long result;
+	struct sm501_devdata *sm = dev_get_drvdata(dev)	;
+	unsigned long reg;
+	char *ptr = buff;
+	int ret;
 
-	result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
-	result >>= offset;
+	for (reg = 0x00; reg < 0x70; reg += 4) {
+		ret = sprintf(ptr, "%08x = %08x\n", reg, SmRead32(reg));
+		ptr += ret;
+	}
 
-	return result & 1UL;
+	return ptr - buff;
 }
 
-static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-
-{
-	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
-	struct sm501_gpio *smgpio = smchip->ourgpio;
-	unsigned long bit = 1 << offset;
-	void __iomem *regs = smchip->regbase;
-	unsigned long save;
-	unsigned long val;
-
-	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
-		__func__, chip, offset);
 
-	spin_lock_irqsave(&smgpio->lock, save);
+static DEVICE_ATTR(dbg_regs, 0666, sm50x_dbg_regs, NULL);
 
-	val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
-	if (value)
-		val |= bit;
-	writel(val, regs);
 
-	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
-	spin_unlock_irqrestore(&smgpio->lock, save);
-}
-
-static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
+static struct sm501_sub_device_list *get_sm_dev_list(struct platform_device *pdev)
 {
-	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
-	struct sm501_gpio *smgpio = smchip->ourgpio;
-	void __iomem *regs = smchip->regbase;
-	unsigned long bit = 1 << offset;
-	unsigned long save;
-	unsigned long ddr;
-
-	dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
-		 __func__, chip, offset);
-
-	spin_lock_irqsave(&smgpio->lock, save);
-
-	ddr = readl(regs + SM501_GPIO_DDR_LOW);
-	writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
-
-	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
-	spin_unlock_irqrestore(&smgpio->lock, save);
-
-	return 0;
+	return container_of(pdev, struct sm501_sub_device_list, pdev);
 }
 
-static int sm501_gpio_output(struct gpio_chip *chip,
-			     unsigned offset, int value)
-{
-	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
-	struct sm501_gpio *smgpio = smchip->ourgpio;
-	unsigned long bit = 1 << offset;
-	void __iomem *regs = smchip->regbase;
-	unsigned long save;
-	unsigned long val;
-	unsigned long ddr;
-
-	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
-		__func__, chip, offset, value);
-
-	spin_lock_irqsave(&smgpio->lock, save);
-
-	val = readl(regs + SM501_GPIO_DATA_LOW);
-	if (value)
-		val |= bit;
-	else
-		val &= ~bit;
-	writel(val, regs);
-
-	ddr = readl(regs + SM501_GPIO_DDR_LOW);
-	writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
-
-	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
-	writel(val, regs + SM501_GPIO_DATA_LOW);
-
-	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
-	spin_unlock_irqrestore(&smgpio->lock, save);
+/* sm501_devices_release
+ *
+ * A release function for the platform devices we create to allow us to
+ * free any items we allocated
+*/
 
-	return 0;
+static void sm501_devices_release(struct device *dev)
+{
+	kfree(get_sm_dev_list(to_platform_device(dev)));
 }
 
-static struct gpio_chip gpio_chip_template = {
-	.ngpio			= 32,
-	.direction_input	= sm501_gpio_input,
-	.direction_output	= sm501_gpio_output,
-	.set			= sm501_gpio_set,
-	.get			= sm501_gpio_get,
-};
-
-static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
-					      struct sm501_gpio *gpio,
-					      struct sm501_gpio_chip *chip)
-{
-	struct sm501_platdata *pdata = sm->platdata;
-	struct gpio_chip *gchip = &chip->gpio;
-	int base = pdata->gpio_base;
-
-	chip->gpio = gpio_chip_template;
-
-	if (chip == &gpio->high) {
-		if (base > 0)
-			base += 32;
-		chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
-		gchip->label  = "SM501-HIGH";
-	} else {
-		chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
-		gchip->label  = "SM501-LOW";
-	}
-
-	gchip->base   = base;
-	chip->ourgpio = gpio;
-
-	return gpiochip_add(gchip);
-}
+/* sm501_create_subdev
+ *
+ * Create a sub platform device with resources for passing to a
+ * sub-driver
+*/
 
-static int sm501_register_gpio(struct sm501_devdata *sm)
+static struct platform_device *
+sm501_create_subdev(struct sm501_devdata *sm,
+		    char *name, unsigned int res_count)
 {
-	struct sm501_gpio *gpio = &sm->gpio;
-	resource_size_t iobase = sm->io_res->start + SM501_GPIO;
-	int ret;
-	int tmp;
-
-	dev_dbg(sm->dev, "registering gpio block %08llx\n",
-		(unsigned long long)iobase);
+	struct sm501_sub_device_list *smdevs;
 
-	spin_lock_init(&gpio->lock);
-
-	gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
-	if (gpio->regs_res == NULL) {
-		dev_err(sm->dev, "gpio: failed to request region\n");
-		return -ENXIO;
-	}
-
-	gpio->regs = ioremap(iobase, 0x20);
-	if (gpio->regs == NULL) {
-		dev_err(sm->dev, "gpio: failed to remap registers\n");
-		ret = -ENXIO;
-		goto err_claimed;
-	}
-
-	/* Register both our chips. */
-
-	ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
-	if (ret) {
-		dev_err(sm->dev, "failed to add low chip\n");
-		goto err_mapped;
-	}
-
-	ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
-	if (ret) {
-		dev_err(sm->dev, "failed to add high chip\n");
-		goto err_low_chip;
-	}
-
-	gpio->registered = 1;
+	smdevs = kzalloc(sizeof(struct sm501_sub_device_list) +
+			sizeof(struct resource) * res_count, GFP_KERNEL);
+	if (!smdevs)
+		return NULL;
 
-	return 0;
+	smdevs->pdev.dev.release = sm501_devices_release;
 
- err_low_chip:
-	tmp = gpiochip_remove(&gpio->low.gpio);
-	if (tmp) {
-		dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
-		return ret;
-	}
+	smdevs->pdev.name = name;
+	smdevs->pdev.id = sm->pdev_id;
+	smdevs->pdev.resource = (struct resource *)(smdevs+1);
+	smdevs->pdev.num_resources = res_count;
 
- err_mapped:
-	iounmap(gpio->regs);
-
- err_claimed:
-	release_resource(gpio->regs_res);
-	kfree(gpio->regs_res);
+	smdevs->pdev.dev.parent = sm->dev;
 
-	return ret;
+	return &smdevs->pdev;
 }
 
-static void sm501_gpio_remove(struct sm501_devdata *sm)
+/* sm501_register_device
+ *
+ * Register a platform device created with sm501_create_subdev()
+*/
+
+extern int rtc_mytest();
+static int sm501_register_device(struct sm501_devdata *sm,
+				 struct platform_device *pdev)
 {
-	struct sm501_gpio *gpio = &sm->gpio;
+	struct sm501_sub_device_list *smdevs = get_sm_dev_list(pdev);
+	int ptr;
 	int ret;
 
-	if (!sm->gpio.registered)
-		return;
-
-	ret = gpiochip_remove(&gpio->low.gpio);
-	if (ret)
-		dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
+	for (ptr = 0; ptr < pdev->num_resources; ptr++) {
+		printk("%s[%d] flags %08lx: %08llx..%08llx\n",
+		       pdev->name, ptr,
+		       pdev->resource[ptr].flags,
+		       (unsigned long long)pdev->resource[ptr].start,
+		       (unsigned long long)pdev->resource[ptr].end);
+	}
 
-	ret = gpiochip_remove(&gpio->high.gpio);
-	if (ret)
-		dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
+	ret = platform_device_register(pdev);
 
-	iounmap(gpio->regs);
-	release_resource(gpio->regs_res);
-	kfree(gpio->regs_res);
-}
+	if (ret >= 0) {
+		dev_dbg(sm->dev, "registered %s\n", pdev->name);
+		list_add_tail(&smdevs->list, &sm->devices);
+	} else
+		dev_err(sm->dev, "error registering %s (%d)\n",
+			pdev->name, ret);
 
-static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
-{
-	struct sm501_gpio *gpio = &sm->gpio;
-	int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
 
-	return (pin % 32) + base;
+	return ret;
 }
 
-static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
+/* sm501_create_subio
+ *
+ * Fill in an IO resource for a sub device
+*/
+
+static void sm501_create_subio(struct sm501_devdata *sm,
+			       struct resource *res,
+			       resource_size_t offs,
+			       resource_size_t size)
 {
-	return sm->gpio.registered;
+	res->flags = IORESOURCE_MEM;
+	res->parent = sm->io_res;
+	res->start = sm->io_res->start + offs;
+	res->end = res->start + size - 1;
 }
-#else
-static inline int sm501_register_gpio(struct sm501_devdata *sm)
+
+/* sm501_create_mem
+ *
+ * Fill in an MEM resource for a sub device
+*/
+
+static void sm501_create_mem(struct sm501_devdata *sm,
+			     struct resource *res,
+			     resource_size_t offs,
+			     resource_size_t size)
 {
-	return 0;
+
+
+	res->flags = IORESOURCE_MEM;
+	res->parent = sm->mem_res;
+	res->start = sm->mem_res->start + offs;
+	res->end = res->start + size - 1;
 }
 
-static inline void sm501_gpio_remove(struct sm501_devdata *sm)
+/* sm501_create_irq
+ *
+ * Fill in an IRQ resource for a sub device
+*/
+
+static void sm501_create_irq(struct sm501_devdata *sm,
+			     struct resource *res)
 {
+	res->flags = IORESOURCE_IRQ;
+	res->parent = NULL;
+	res->start = res->end = sm->irq;
 }
 
-static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
+static int sm501_fill_usbdev(struct device *dev, struct platform_device *pdev)
 {
-	return -1;
+	pdev->dev.power.power_state = PMSG_ON;
+	/*Add for usb dma mask*/
+	pdev->dev.coherent_dma_mask = ~0x0;
+	pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 }
-
-static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
+static int sm501_register_usbhost(struct sm501_devdata *sm, 
+				  struct device *dev)
 {
-	return 0;
+	struct platform_device *pdev;
+	/*If the chip is SM107 just return without doing anything*/
+	if (sm50x_mem_size == 0x400000)
+		return 0;
+	
+	pdev = sm501_create_subdev(sm, "sm501-usb", 3);
+	if (!pdev)
+		return -ENOMEM;
+	sm501_fill_usbdev(dev, pdev);
+	sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
+	sm501_create_mem(sm, &pdev->resource[1], sm50x_mem_size-USB_DMA_BUFFER_SIZE, USB_DMA_BUFFER_SIZE);
+	sm501_create_irq(sm, &pdev->resource[2]);
+
+	return sm501_register_device(sm, pdev);
 }
-#endif
 
-static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
-					    struct sm501_platdata_gpio_i2c *iic)
+static int sm501_register_display(struct sm501_devdata *sm)
 {
-	struct i2c_gpio_platform_data *icd;
 	struct platform_device *pdev;
+	resource_size_t resource2Size;
 
-	pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
-				   sizeof(struct i2c_gpio_platform_data));
+	pdev = sm501_create_subdev(sm, "sm501-fb", 4);
 	if (!pdev)
 		return -ENOMEM;
 
-	icd = pdev->dev.platform_data;
-
-	/* We keep the pin_sda and pin_scl fields relative in case the
-	 * same platform data is passed to >1 SM501.
-	 */
-
-	icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
-	icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
-	icd->timeout = iic->timeout;
-	icd->udelay = iic->udelay;
-
-	/* note, we can't use either of the pin numbers, as the i2c-gpio
-	 * driver uses the platform.id field to generate the bus number
-	 * to register with the i2c core; The i2c core doesn't have enough
-	 * entries to deal with anything we currently use.
-	*/
-
-	pdev->id = iic->bus_num;
-
-	dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
-		 iic->bus_num,
-		 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
+	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
+	sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
+	sm501_create_mem(sm, &pdev->resource[2], 0, sm50x_mem_size-USB_DMA_BUFFER_SIZE);
+	sm501_create_irq(sm, &pdev->resource[3]);
 
 	return sm501_register_device(sm, pdev);
 }
 
-static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
-				   struct sm501_platdata *pdata)
+static int sm501_register_i2c(struct sm501_devdata *sm)
 {
-	struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
-	int index;
-	int ret;
-
-	for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
-		ret = sm501_register_gpio_i2c_instance(sm, iic);
-		if (ret < 0)
-			return ret;
-	}
+	struct platform_device *pdev;
+	pdev = sm501_create_subdev(sm, "sm501-i2c", 1);
+	if (!pdev)
+		return -ENOMEM;
+	sm501_create_irq(sm, &pdev->resource[0]);
 
-	return 0;
+	return sm501_register_device(sm, pdev);
 }
 
-/* sm501_dbg_regs
- *
- * Debug attribute to attach to parent device to show core registers
-*/
-
-static ssize_t sm501_dbg_regs(struct device *dev,
-			      struct device_attribute *attr, char *buff)
+static int sm501_register_uart(struct sm501_devdata *sm)
 {
-	struct sm501_devdata *sm = dev_get_drvdata(dev)	;
-	unsigned int reg;
-	char *ptr = buff;
-	int ret;
+	struct platform_device *pdev;
+	/*If the chip is SM107 just return without doing anything*/
+	if (sm50x_mem_size == 0x400000)
+		return 0;
+	
+	pdev = sm501_create_subdev(sm, "sm501-uart", 1);
+	if (!pdev)
+		return -ENOMEM;
 
-	for (reg = 0x00; reg < 0x70; reg += 4) {
-		ret = sprintf(ptr, "%08x = %08x\n",
-			      reg, readl(sm->regs + reg));
-		ptr += ret;
-	}
+//	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
+	sm501_create_irq(sm, &pdev->resource[0]);
 
-	return ptr - buff;
+	return sm501_register_device(sm, pdev);
 }
 
+static int sm501_register_audio(struct sm501_devdata *sm)
+{
+	struct platform_device *pdev;
 
-static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
+	/*If the chip is SM107 just return without doing anything*/
+	if (sm50x_mem_size == 0x400000)
+		return 0;
 
-/* sm501_init_reg
- *
- * Helper function for the init code to setup a register
- *
- * clear the bits which are set in r->mask, and then set
- * the bits set in r->set.
-*/
+	pdev = sm501_create_subdev(sm, "sm501-audio", 1);
+	if (!pdev)
+		return -ENOMEM;
+	sm501_create_irq(sm, &pdev->resource[0]);
 
-static inline void sm501_init_reg(struct sm501_devdata *sm,
-				  unsigned long reg,
-				  struct sm501_reg_init *r)
-{
-	unsigned long tmp;
+	return sm501_register_device(sm, pdev);
+}
 
-	tmp = readl(sm->regs + reg);
-	tmp &= ~r->mask;
-	tmp |= r->set;
-	writel(tmp, sm->regs + reg);
+static int sm501_register_gpio(struct sm501_devdata *sm)
+{
+    struct platform_device *pdev;
+ 
+    pdev = sm501_create_subdev(sm, "sm501-gpio", 4);
+    if (!pdev)
+        return -ENOMEM;
+ 
+    sm501_create_subio(sm, &pdev->resource[0], SM501_GPIO, 0x20);
+    return sm501_register_device(sm, pdev);
 }
 
 /* sm501_init_regs
@@ -1244,130 +928,126 @@
 static void sm501_init_regs(struct sm501_devdata *sm,
 			    struct sm501_initdata *init)
 {
-	sm501_misc_control(sm->dev,
-			   init->misc_control.set,
-			   init->misc_control.mask);
-
-	sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
-	sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
-	sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
-
-	if (init->m1xclk) {
-		dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
-		sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
+	ulong RegValue;
+	/*Set the local memory number of banks according to the chip type*/
+	sm50x_mem_size = sm501_get_memory_size();
+
+	RegValue= SmRead32(DRAM_CONTROL);
+	if (sm50x_mem_size == 0x400000){
+		dev_info(sm->dev, "SM107 is detected.\n");
+		RegValue = FIELD_SET(RegValue, DRAM_CONTROL, LOCAL_BANKS, 2);
+	}
+	else	{
+		dev_info(sm->dev, "SM502 is detected.\n");
+		RegValue = FIELD_SET(RegValue, DRAM_CONTROL, LOCAL_BANKS, 4);
 	}
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON2
+	RegValue = FIELD_SET(RegValue, DRAM_CONTROL,LOCAL,RESET);
+#endif
+	SmWrite32(DRAM_CONTROL, RegValue);
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON2
+	RegValue = FIELD_SET(RegValue, DRAM_CONTROL,LOCAL,NORMAL);
+	SmWrite32(DRAM_CONTROL, RegValue);	
+#endif
 
-	if (init->mclk) {
-		dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
-		sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
-	}
+	RegValue = SmRead32(SYSTEM_CTRL);
+	SmWrite32(SYSTEM_CTRL, FIELD_SET(RegValue, SYSTEM_CTRL, PCI_BURST, ENABLE)|
+//			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_MASTER, START)|
+			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_BURST_READ, ENABLE)|
+			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_RETRY, ENABLE)|
+			FIELD_SET(RegValue, SYSTEM_CTRL, PCI_CLOCK_RUN, ENABLE));
+	
+	RegValue = SmRead32(MISC_CTRL);
+	SmWrite32(MISC_CTRL, FIELD_SET(RegValue, MISC_CTRL, FPDATA, 24)|
+		FIELD_SET(RegValue, MISC_CTRL, BURST_LENGTH, 1));
+
+	RegValue = SmRead32(GPIO_CONTROL_HIGH);
+
+	SmWrite32(GPIO_CONTROL_HIGH, 
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 56, CRT0_ZVPORT8_PANEL0) |		
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 57, CRT1_ZVPORT9_PANEL1) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 58, CRT2_ZVPORT10_PANEL8) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 59, CRT3_ZVPORT11_PANEL9) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 60, CRT4_ZVPORT12_PANEL16) |
+		FIELD_SET(RegValue,GPIO_CONTROL_HIGH, 61, CRT5_ZVPORT13_PANEL17) );
 
-}
 
-/* Check the PLL sources for the M1CLK and M1XCLK
- *
- * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
- * there is a risk (see errata AB-5) that the SM501 will cease proper
- * function. If this happens, then it is likely the SM501 will
- * hang the system.
-*/
 
-static int sm501_check_clocks(struct sm501_devdata *sm)
-{
-	unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
-	unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
-	unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
+	if (init->mclk) {
+		dev_dbg(sm->dev, "setting MCLK to %ld\n", init->mclk);
+		sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
+	}
 
-	return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
+	if (init->m1xclk) {
+		dev_dbg(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
+		sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
+	
+	}
 }
 
-static unsigned int sm501_mem_local[] = {
-	[0]	= 4*1024*1024,
-	[1]	= 8*1024*1024,
-	[2]	= 16*1024*1024,
-	[3]	= 32*1024*1024,
-	[4]	= 64*1024*1024,
-	[5]	= 2*1024*1024,
-};
-
 /* sm501_init_dev
  *
  * Common init code for an SM501
 */
 
-static int sm501_init_dev(struct sm501_devdata *sm)
+static int sm501_init_dev(struct sm501_devdata *sm, struct device *dev)
 {
-	struct sm501_initdata *idata;
-	struct sm501_platdata *pdata;
-	resource_size_t mem_avail;
-	unsigned long dramctrl;
-	unsigned long devid;
 	int ret;
+	
 
 	mutex_init(&sm->clock_lock);
 	spin_lock_init(&sm->reg_lock);
-
 	INIT_LIST_HEAD(&sm->devices);
-
-	devid = readl(sm->regs + SM501_DEVICEID);
-
-	if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
-		dev_err(sm->dev, "incorrect device id %08lx\n", devid);
-		return -EINVAL;
-	}
-
-	/* disable irqs */
-	writel(0, sm->regs + SM501_IRQ_MASK);
-
-	dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
-	mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
-
-	dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
-		 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
-
-	sm->rev = devid & SM501_DEVICEID_REVMASK;
-
-	sm501_dump_gate(sm);
+	
+	sm50x_mem_size = sm501_get_memory_size();
+	
+	dev_info(sm->dev, "SM502/SM107 At %p: Version %08x, %ld Mb, IRQ %d\n",
+		 sm->regs, SmRead32( DEVICE_ID),(unsigned long)sm50x_mem_size >> 20, sm->irq);
+
+	dev_dbg(sm->dev, "CurrentGate      %08x\n", SmRead32(CURRENT_GATE));
+	dev_dbg(sm->dev, "CurrentClock     %08x\n", SmRead32(CURRENT_POWER_CLOCK));
+	dev_dbg(sm->dev, "PowerModeControl %08x\n", SmRead32(POWER_MODE_CTRL));
 
 	ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
 	if (ret)
 		dev_err(sm->dev, "failed to create debug regs file\n");
 
-	sm501_dump_clk(sm);
 
-	/* check to see if we have some device initialisation */
+	SmWrite32(ENDIAN_CONTROL,~0);
 
-	pdata = sm->platdata;
-	idata = pdata ? pdata->init : NULL;
+	/* check to see if we have some device initialisation */
 
-	if (idata) {
-		sm501_init_regs(sm, idata);
+	if (sm->platdata) {
+		struct sm501_platdata *pdata = sm->platdata;
 
-		if (idata->devices & SM501_USE_USB_HOST)
-			sm501_register_usbhost(sm, &mem_avail);
-		if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
-			sm501_register_uart(sm, idata->devices);
-		if (idata->devices & SM501_USE_GPIO)
-			sm501_register_gpio(sm);
-	}
+		if (pdata->init) {
+			sm501_init_regs(sm, sm->platdata->init);
 
-	if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
-		if (!sm501_gpio_isregistered(sm))
-			dev_err(sm->dev, "no gpio available for i2c gpio.\n");
-		else
-			sm501_register_gpio_i2c(sm, pdata);
-	}
+			if (pdata->init->devices & SM501_USE_FB)		
+			sm501_register_display(sm);
 
-	ret = sm501_check_clocks(sm);
-	if (ret) {
-		dev_err(sm->dev, "M1X and M clocks sourced from different "
-					"PLLs\n");
-		return -EINVAL;
+			printk(KERN_INFO"devices is 0x%x\n", pdata->init->devices);
+			if (pdata->init->devices & SM501_USE_USB_HOST )
+				sm501_register_usbhost(sm, dev);
+			if (pdata->init->devices & SM501_USE_AC97)
+				sm501_register_audio(sm);
+			if ((pdata->init->devices & SM501_USE_UART0) ||
+				(pdata->init->devices & SM501_USE_UART1))
+				sm501_register_uart(sm);
+			if (pdata->init->devices & SM501_USE_GPIO)
+			{
+				sm501_register_gpio(sm);
+//                rtc_mytest();
+			}
+#if 0
+			if (pdata->init->devices & SM501_USE_I2C) {
+				printk("Using SM501 I2C module\n");
+				sm501_register_i2c(sm);
+			}
+#endif			
+		}
 	}
 
-	/* always create a framebuffer */
-	sm501_register_display(sm, &mem_avail);
-
 	return 0;
 }
 
@@ -1402,6 +1082,7 @@
 		goto err_res;
 	}
 
+	/* check register */
 	sm->regs_claim = request_mem_region(sm->io_res->start,
 					    0x100, "sm501");
 
@@ -1413,16 +1094,26 @@
 
 	platform_set_drvdata(dev, sm);
 
-	sm->regs = ioremap(sm->io_res->start,
+	/* mapping register */
+	sm->regs = sm50x_base_reg = ioremap(sm->io_res->start,
 			   (sm->io_res->end - sm->io_res->start) - 1);
 
+//	printk("---------sm50x_base_reg:%08x \n",sm50x_base_reg);
+	/*
+	 * By Belcon:
+	 * mapping framebuffer
+	 */
+//	sm->fb_mem = ioremap(sm->mem_res->start, sm50x_mem_size - 1);
+
 	if (sm->regs == NULL) {
 		dev_err(&dev->dev, "cannot remap registers\n");
 		err = -EIO;
 		goto err_claim;
 	}
 
-	return sm501_init_dev(sm);
+	sm->chipRevID = FIELD_GET(SmRead32(DEVICE_ID), DEVICE_ID, REVISION);
+	
+	return sm501_init_dev(sm, &dev->dev);
 
  err_claim:
 	release_resource(sm->regs_claim);
@@ -1434,113 +1125,8 @@
 
 }
 
-#ifdef CONFIG_PM
-
-/* power management support */
-
-static void sm501_set_power(struct sm501_devdata *sm, int on)
-{
-	struct sm501_platdata *pd = sm->platdata;
-
-	if (pd == NULL)
-		return;
-
-	if (pd->get_power) {
-		if (pd->get_power(sm->dev) == on) {
-			dev_dbg(sm->dev, "is already %d\n", on);
-			return;
-		}
-	}
-
-	if (pd->set_power) {
-		dev_dbg(sm->dev, "setting power to %d\n", on);
-
-		pd->set_power(sm->dev, on);
-		sm501_mdelay(sm, 10);
-	}
-}
-
-static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	struct sm501_devdata *sm = platform_get_drvdata(pdev);
-
-	sm->in_suspend = 1;
-	sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
-
-	sm501_dump_regs(sm);
-
-	if (sm->platdata) {
-		if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
-			sm501_set_power(sm, 0);
-	}
-
-	return 0;
-}
-
-static int sm501_plat_resume(struct platform_device *pdev)
-{
-	struct sm501_devdata *sm = platform_get_drvdata(pdev);
-
-	sm501_set_power(sm, 1);
-
-	sm501_dump_regs(sm);
-	sm501_dump_gate(sm);
-	sm501_dump_clk(sm);
-
-	/* check to see if we are in the same state as when suspended */
-
-	if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
-		dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
-		writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
-
-		/* our suspend causes the controller state to change,
-		 * either by something attempting setup, power loss,
-		 * or an external reset event on power change */
-
-		if (sm->platdata && sm->platdata->init) {
-			sm501_init_regs(sm, sm->platdata->init);
-		}
-	}
-
-	/* dump our state from resume */
-
-	sm501_dump_regs(sm);
-	sm501_dump_clk(sm);
-
-	sm->in_suspend = 0;
-
-	return 0;
-}
-#else
-#define sm501_plat_suspend NULL
-#define sm501_plat_resume NULL
-#endif
-
-/* Initialisation data for PCI devices */
-
-static struct sm501_initdata sm501_pci_initdata = {
-	.gpio_high	= {
-		.set	= 0x3F000000,		/* 24bit panel */
-		.mask	= 0x0,
-	},
-	.misc_timing	= {
-		.set	= 0x010100,		/* SDRAM timing */
-		.mask	= 0x1F1F00,
-	},
-	.misc_control	= {
-		.set	= SM501_MISC_PNL_24BIT,
-		.mask	= 0,
-	},
-
-	.devices	= SM501_USE_ALL,
-
-	/* Errata AB-3 says that 72MHz is the fastest available
-	 * for 33MHZ PCI with proper bus-mastering operation */
-
-	.mclk		= 72 * MHZ,
-	.m1xclk		= 144 * MHZ,
-};
 
+/* Initialisation data for graphic modules */
 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
 	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
 			   SM501FB_FLAG_USE_HWCURSOR |
@@ -1549,15 +1135,22 @@
 };
 
 static struct sm501_platdata_fb sm501_fb_pdata = {
-	.fb_route	= SM501_FB_OWN,
 	.fb_crt		= &sm501_pdata_fbsub,
 	.fb_pnl		= &sm501_pdata_fbsub,
 };
 
+/* Initialisation data for PCI devices */
+static struct sm501_initdata sm501_pci_initdata = {
+	.devices	= SM501_USE_ALL,	
+	.mclk		= 72 * MHZ,
+	//.m1xclk		= 144 * MHZ, //yun
+	.m1xclk		= 122 * MHZ, //topstar
+};
+
 static struct sm501_platdata sm501_pci_platdata = {
 	.init		= &sm501_pci_initdata,
 	.fb		= &sm501_fb_pdata,
-	.gpio_base	= -1,
+	.gpio_base  = 0,
 };
 
 static int sm501_pci_probe(struct pci_dev *dev,
@@ -1565,6 +1158,7 @@
 {
 	struct sm501_devdata *sm;
 	int err;
+	unsigned long	mem_start, mem_end, mem_length;
 
 	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
 	if (sm == NULL) {
@@ -1594,8 +1188,8 @@
 	/* if the system is big-endian, we most probably have a
 	 * translation in the IO layer making the PCI bus little endian
 	 * so make the framebuffer swapped pixels */
-
-	sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
+	sm->platdata->init->flags |= SM501_FBPD_SWAP_FB_ENDIAN;
+	sm->platdata->fb->flags |= SM501_FBPD_SWAP_FB_ENDIAN;
 #endif
 
 	/* check our resources */
@@ -1612,29 +1206,43 @@
 		goto err3;
 	}
 
+	pci_read_config_byte(dev, PCI_REVISION_ID, &sm->chipRevID);
+
 	/* make our resources ready for sharing */
 
 	sm->io_res = &dev->resource[1];
 	sm->mem_res = &dev->resource[0];
 
-	sm->regs_claim = request_mem_region(sm->io_res->start,
-					    0x100, "sm501");
+	/* check register */
+	sm->regs_claim = request_mem_region(sm->io_res->start,0x100, "sm501");
+	
 	if (sm->regs_claim == NULL) {
 		dev_err(&dev->dev, "cannot claim registers\n");
 		err= -EBUSY;
 		goto err3;
 	}
 
-	sm->regs = ioremap(pci_resource_start(dev, 1),
-			   pci_resource_len(dev, 1));
-
+	/* mapping register */
+	sm->regs = sm50x_base_reg = ioremap(pci_resource_start(dev, 1), pci_resource_len(dev, 1));
+//	printk("--2-------sm50x_base_reg:%08x \n",sm50x_base_reg);
+	
 	if (sm->regs == NULL) {
 		dev_err(&dev->dev, "cannot remap registers\n");
 		err = -EIO;
 		goto err4;
 	}
 
-	sm501_init_dev(sm);
+	mem_start = pci_resource_start(dev, 0);
+	mem_end = pci_resource_end(dev, 0);
+	mem_length = pci_resource_len(dev, 0);
+	sm501_init_dev(sm, &dev->dev);
+	
+	/*
+	 * By Belcon:
+	 * mapping framebuffer
+	 */
+	sm->fb_mem = sm50x_base_mem = ioremap(mem_start, mem_length);
+
 	return 0;
 
  err4:
@@ -1650,22 +1258,20 @@
 }
 
 static void sm501_remove_sub(struct sm501_devdata *sm,
-			     struct sm501_device *smdev)
+			     struct sm501_sub_device_list *smdevs)
 {
-	list_del(&smdev->list);
-	platform_device_unregister(&smdev->pdev);
+	list_del(&smdevs->list);
+	platform_device_unregister(&smdevs->pdev);
 }
 
 static void sm501_dev_remove(struct sm501_devdata *sm)
 {
-	struct sm501_device *smdev, *tmp;
+	struct sm501_sub_device_list *smdevs, *tmp;
 
-	list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
-		sm501_remove_sub(sm, smdev);
+	list_for_each_entry_safe(smdevs, tmp, &sm->devices, list)
+		sm501_remove_sub(sm, smdevs);
 
 	device_remove_file(sm->dev, &dev_attr_dbg_regs);
-
-	sm501_gpio_remove(sm);
 }
 
 static void sm501_pci_remove(struct pci_dev *dev)
@@ -1674,10 +1280,13 @@
 
 	sm501_dev_remove(sm);
 	iounmap(sm->regs);
+	iounmap(sm->fb_mem );
 
 	release_resource(sm->regs_claim);
 	kfree(sm->regs_claim);
 
+
+	
 	pci_set_drvdata(dev, NULL);
 	pci_disable_device(dev);
 }
@@ -1694,14 +1303,75 @@
 
 	return 0;
 }
+static int sm501_chr_open(struct inode *inode, struct file *flip)
+{
+	return 0;
+}
+static int sm501_chr_release(struct inode *inode, struct file *flip)
+{
+	return 0;
+}
+
+static int sm501_chr_ioctl(struct inode *inode, struct file *flip, u32 cmd, unsigned long arg)
+{
+	switch (cmd)
+	{
+		case SM501_IOCTL_SMREAD:
+		{
+			unsigned long value = 0;
+			unsigned long ret_value = 0;
+			PREGDATA pregdata;
+			copy_from_user(pregdata, (void *)arg, sizeof(PREGDATA));
+			pregdata->data = SmRead32(pregdata->address);
+			copy_to_user((void *)arg, pregdata, sizeof(PREGDATA));
+			break;
+		}
+		case SM501_IOCTL_SMWRITE:
+		{
+			PREGDATA pregdata;
+			copy_from_user(pregdata, (void *)arg, sizeof(PREGDATA));
+			SmWrite32(pregdata->address, pregdata->data);
+			break;
+		}
+		case SM501_GET_CURSOR:
+		{
+			PREGDATA pregdata;
+			copy_from_user(pregdata, (void *)arg, sizeof(PREGDATA));
+			pregdata->data = sm50x_base_mem + pregdata->address;
+			copy_to_user((void *)arg, pregdata, sizeof(PREGDATA));
+			break;
+		}
+		case SM501_SET_CURSOR:
+		{
+			PCURSORDATA pcursor_data;
+			copy_from_user(pcursor_data, (void *)arg, sizeof(PCURSORDATA));
+			memcpy(sm50x_base_mem + pcursor_data->address, pcursor_data->data, 64 * 16);
+			break;
+		}
+		default:
+		{
+			printk("No such command!\n");
+		}
+	}
+	return 0;
+}
+#include "i2c-sm502.c" //mj
+
+static struct file_operations sm501_chr_fops = {
+	.owner		= THIS_MODULE,
+	.open		= sm501_chr_open,
+	.release	= sm501_chr_release,
+	.ioctl		= sm501_chr_ioctl,
+};
 
 static struct pci_device_id sm501_pci_tbl[] = {
-	{ 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+	{ 0x126f, 0x501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 	{ 0, },
 };
 
 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
 
+/*For PCI bus*/
 static struct pci_driver sm501_pci_drv = {
 	.name		= "sm501",
 	.id_table	= sm501_pci_tbl,
@@ -1709,8 +1379,7 @@
 	.remove		= sm501_pci_remove,
 };
 
-MODULE_ALIAS("platform:sm501");
-
+/*For Platform bus*/
 static struct platform_driver sm501_plat_drv = {
 	.driver		= {
 		.name	= "sm501",
@@ -1718,25 +1387,25 @@
 	},
 	.probe		= sm501_plat_probe,
 	.remove		= sm501_plat_remove,
-	.suspend	= sm501_plat_suspend,
-	.resume		= sm501_plat_resume,
 };
 
 static int __init sm501_base_init(void)
 {
 	platform_driver_register(&sm501_plat_drv);
+	register_chrdev(SM501_CHAR_MAJOR, "sm501", &sm501_chr_fops);
 	return pci_register_driver(&sm501_pci_drv);
 }
 
 static void __exit sm501_base_exit(void)
 {
 	platform_driver_unregister(&sm501_plat_drv);
+	unregister_chrdev(SM501_CHAR_MAJOR, "sm501");
 	pci_unregister_driver(&sm501_pci_drv);
 }
 
 module_init(sm501_base_init);
 module_exit(sm501_base_exit);
 
-MODULE_DESCRIPTION("SM501 Core Driver");
-MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
+MODULE_DESCRIPTION("SM50x/SM107 Core Driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders, Boyod Yang");
 MODULE_LICENSE("GPL v2");
diff -uNra linux-2.6.27.6/drivers/mtd/nand/fcr-nand.c linux-2.6.27.6.yaffs/drivers/mtd/nand/fcr-nand.c
--- linux-2.6.27.6/drivers/mtd/nand/fcr-nand.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mtd/nand/fcr-nand.c	2011-05-31 11:39:26.000000000 +0800
@@ -0,0 +1,164 @@
+/*
+ *  drivers/mtd/nand/fcr_soc.c
+ */
+
+//#includ <asm/mach-types.h>
+//#include <machine/types.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include "fcr-nand.h"
+/*
+ * MTD structure for fcr_soc board
+ */
+static struct mtd_info *fcr_soc_mtd = NULL;
+/*
+ * Define partitions for flash device
+ */
+static const struct mtd_partition partition_info[] = {
+/*	{
+	 .name = "boot",
+	 .offset = 0x0,
+	 .size = 1 * 1024 * 1024}
+	,*/{
+	 .name = "kernel",
+	 //.offset = 1*1024*1024,
+	 .offset = 0x0,
+	 .size = 32 * 1024 * 1024}
+	,{
+	 .name = "ramdisk",
+	 .offset = 32*1024*1024,
+	 .size = 32 * 1024 * 1024}
+#if 0
+	,
+		{
+	 .name = "jffs2",
+	 .offset = 64*1024*1024,
+	 .size = 32 * 1024 * 1024}
+	,{
+	 .name = "yaffs2",
+	 .offset = 96*1024*1024,
+	 .size = 32 * 1024 * 1024}
+#endif
+	,{
+	 .name = "test",
+	 .offset = 64*1024*1024,
+	 .size = 420 * 1024 * 1024}
+	 //.size = 900 * 1024 * 1024}
+};
+
+#define NUM_PARTITIONS 3
+
+static void fcr_soc_hwcontrol(struct mtd_info *mtd, int dat,unsigned int ctrl)
+{
+	struct nand_chip *chip = mtd->priv;
+
+//printk("--------%s--------------\n",__func__);
+if((ctrl & NAND_CTRL_ALE)==NAND_CTRL_ALE)
+		*(volatile unsigned char *)(0xffffffffbe000082) = dat;
+if ((ctrl & NAND_CTRL_CLE)==NAND_CTRL_CLE)
+		*(volatile unsigned char *)(0xffffffffbe000081) = dat;
+}
+
+
+//Main initialization for yaffs ----- by zhly
+int fcr_soc_foryaffs_init(struct mtd_info *mtd)
+{
+	struct nand_chip *this;
+	
+	if(!mtd)
+	{
+		if(!(mtd = kmalloc(sizeof(struct mtd_info),GFP_KERNEL)))
+		{
+			printk("unable to allocate mtd_info structure!\n");
+			return -ENOMEM;
+		}
+		memset(mtd, 0, sizeof(struct mtd_info));
+	}
+
+	this = kmalloc(sizeof(struct nand_chip),GFP_KERNEL);
+	if(!this)
+	{
+		printk("Unable to allocate nand_chip structure!\n");
+		return -ENOMEM;
+	}
+	memset(this,0,sizeof(struct nand_chip));
+		
+	fcr_soc_mtd=mtd;
+	fcr_soc_mtd->priv = this;
+
+	this->IO_ADDR_R = (void *)0xffffffffbf000040;
+	this->IO_ADDR_W = (void *)0xffffffffbf000040;
+	this->cmd_ctrl = fcr_soc_hwcontrol;
+	this->ecc.mode = NAND_ECC_SOFT;
+	
+	if(nand_scan(fcr_soc_mtd,1))
+	{
+		kfree(fcr_soc_mtd);
+		printk("nand_scan failed!\n");
+		return -1;		
+	}
+	fcr_soc_mtd->size=0x04000000;
+
+	return 0;
+}
+
+/*
+ * Main initialization routine
+ */
+int fcr_soc_nand_init(void)
+{
+	struct nand_chip *this;
+
+	/* Allocate memory for MTD device structure and private data */
+//printk("--------%s--------------\n",__func__);
+	fcr_soc_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
+	if (!fcr_soc_mtd) {
+		printk("Unable to allocate fcr_soc NAND MTD device structure.\n");
+		return -ENOMEM;
+	}
+
+	/* Get pointer to private data */
+	this = (struct nand_chip *)(&fcr_soc_mtd[1]);
+
+	/* Initialize structures */
+	memset(fcr_soc_mtd, 0, sizeof(struct mtd_info));
+	memset(this, 0, sizeof(struct nand_chip));
+
+	/* Link the private data with the MTD structure */
+	fcr_soc_mtd->priv = this;
+
+
+	/* Set address of NAND IO lines */
+	this->IO_ADDR_R = (void  *)0xffffffffbe000080;
+	this->IO_ADDR_W = (void  *)0xffffffffbe000080;
+	/* Set address of hardware control function */
+	this->cmd_ctrl = fcr_soc_hwcontrol;
+	/* 15 us command delay time */
+	this->chip_delay = 35;  //mj
+	this->ecc.mode = NAND_ECC_SOFT;
+	//this->ecc.mode = NAND_ECC_NONE;
+
+//	this->ecc.layout = 32;
+
+	/* Scan to find existence of the device */
+	if (nand_scan(fcr_soc_mtd, 1)) {
+		kfree(fcr_soc_mtd);
+		return -ENXIO;
+	}
+
+	/* Register the partitions */
+	add_mtd_partitions(fcr_soc_mtd, partition_info, NUM_PARTITIONS);
+//	add_mtd_device(fcr_soc_mtd,0,0,"total flash");
+//	add_mtd_device(fcr_soc_mtd,0,0x02000000,"kernel");
+//	add_mtd_device(fcr_soc_mtd,0x02000000,0x04000000,"squashfs");
+//	add_mtd_device(fcr_soc_mtd,0x02000000+0x04000000,0x04000000,"jffs2");
+//	add_mtd_device(fcr_soc_mtd,0x02000000+0x04000000+0x04000000,0x04000000,"yaffs2");
+//	add_mtd_device(fcr_soc_mtd,0x02000000+0x04000000+0x04000000+0x04000000,0x02000000,"cramfs");
+
+	/* Return happy */
+	return 0;
+}
+module_init(fcr_soc_nand_init);
+
+
diff -uNra linux-2.6.27.6/drivers/mtd/nand/fcr-nand.h linux-2.6.27.6.yaffs/drivers/mtd/nand/fcr-nand.h
--- linux-2.6.27.6/drivers/mtd/nand/fcr-nand.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mtd/nand/fcr-nand.h	2011-05-08 18:00:33.000000000 +0800
@@ -0,0 +1,18 @@
+/*
+ *fcr-nand.h
+ */
+
+#ifndef _FCR_NAND_H
+#define _FCR_NAND_H
+//#include <machine/types.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+static void fcr_soc_hwcontrol(struct mtd_info *mtd, int dat, unsigned int ctrl);
+
+int fcr_soc_foryaffs_init(struct mtd_info *mtd);
+
+int fcr_soc_nand_init(void);
+
+#endif
diff -uNra linux-2.6.27.6/drivers/mtd/nand/Kconfig linux-2.6.27.6.yaffs/drivers/mtd/nand/Kconfig
--- linux-2.6.27.6/drivers/mtd/nand/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mtd/nand/Kconfig	2011-05-08 18:00:33.000000000 +0800
@@ -11,6 +11,11 @@
 
 if MTD_NAND
 
+config MTD_NAND_TOPSTAR
+	bool "TOPSTAR"
+	help
+	topstar supper
+
 config MTD_NAND_VERIFY_WRITE
 	bool "Verify NAND page writes"
 	help
diff -uNra linux-2.6.27.6/drivers/mtd/nand/Makefile linux-2.6.27.6.yaffs/drivers/mtd/nand/Makefile
--- linux-2.6.27.6/drivers/mtd/nand/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mtd/nand/Makefile	2011-05-08 18:00:34.000000000 +0800
@@ -5,6 +5,7 @@
 obj-$(CONFIG_MTD_NAND)			+= nand.o nand_ecc.o
 obj-$(CONFIG_MTD_NAND_IDS)		+= nand_ids.o
 
+obj-$(CONFIG_MTD_NAND_TOPSTAR)		+= fcr-nand.o
 obj-$(CONFIG_MTD_NAND_CAFE)		+= cafe_nand.o
 obj-$(CONFIG_MTD_NAND_SPIA)		+= spia.o
 obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-delta.o
diff -uNra linux-2.6.27.6/drivers/mtd/nand/nand_base.c linux-2.6.27.6.yaffs/drivers/mtd/nand/nand_base.c
--- linux-2.6.27.6/drivers/mtd/nand/nand_base.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mtd/nand/nand_base.c	2011-05-08 18:00:33.000000000 +0800
@@ -71,6 +71,20 @@
 		 . length = 8}}
 };
 
+/**
+ * onenand_oob_32 - oob info for middle (1KB) page
+*/
+
+static struct nand_ecclayout nand_oob_32 = {
+	.eccbytes	= 10,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		},
+	.oobfree	= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
+};
+
+
 static struct nand_ecclayout nand_oob_64 = {
 	.eccbytes = 24,
 	.eccpos = {
@@ -1467,7 +1481,9 @@
 	}
 
 	if (!ops->datbuf)
-		ret = nand_do_read_oob(mtd, from, ops);
+	{	ret = nand_do_read_oob(mtd, from, ops);
+//		printk("-1--%s -%d----------\n",__func__,ret); //mj
+	}
 	else
 		ret = nand_do_read_ops(mtd, from, ops);
 
@@ -2325,6 +2341,21 @@
 	*maf_id = chip->read_byte(mtd);
 	dev_id = chip->read_byte(mtd);
 
+#if 0
+	{  //mj
+		int extid;
+		printk("manf:0x%08x, id:0x%08x\n",*maf_id,dev_id);
+		/* The 3rd id byte contains non relevant data ATM */
+		extid = chip->read_byte(mtd);
+		printk("3rd ID:0x%08x\n",extid);
+		/* The 4th id byte is the important one */
+		extid = chip->read_byte(mtd);
+		printk("4rd ID:0x%08x\n",extid);
+		//extid = chip->read_byte(mtd);
+		//printf("5rd ID:0x%02x\n",extid);
+	}
+#endif
+
 	/* Try again to make sure, as some systems the bus-hold or other
 	 * interface concerns can cause random data which looks like a
 	 * possibly credible NAND flash to appear. If the two results do
@@ -2337,6 +2368,20 @@
 
 	tmp_manf = chip->read_byte(mtd);
 	tmp_id = chip->read_byte(mtd);
+#if 0
+	{  //mj
+		int extid;
+		printk("manf:0x%08x, id:0x%08x\n",tmp_manf,tmp_id);
+		/* The 3rd id byte contains non relevant data ATM */
+		extid = chip->read_byte(mtd);
+		printk("3rd ID:0x%08x\n",extid);
+		/* The 4th id byte is the important one */
+		extid = chip->read_byte(mtd);
+		printk("4rd ID:0x%08x\n",extid);
+		//extid = chip->read_byte(mtd);
+		//printf("5rd ID:0x%02x\n",extid);
+	}
+#endif
 
 	if (tmp_manf != *maf_id || tmp_id != dev_id) {
 		printk(KERN_INFO "%s: second ID read did not match "
@@ -2472,7 +2517,8 @@
 	struct nand_flash_dev *type;
 
 	/* Get buswidth to select the correct functions */
-	busw = chip->options & NAND_BUSWIDTH_16;
+//	busw = chip->options & NAND_BUSWIDTH_16;
+	busw = chip->options ;
 	/* Set the default functions */
 	nand_set_defaults(chip, busw);
 
@@ -2539,6 +2585,9 @@
 		case 16:
 			chip->ecc.layout = &nand_oob_16;
 			break;
+		case 32:
+			chip->ecc.layout = &nand_oob_64;
+			break;
 		case 64:
 			chip->ecc.layout = &nand_oob_64;
 			break;
diff -uNra linux-2.6.27.6/drivers/mtd/nand/nand_bbt.c linux-2.6.27.6.yaffs/drivers/mtd/nand/nand_bbt.c
--- linux-2.6.27.6/drivers/mtd/nand/nand_bbt.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/mtd/nand/nand_bbt.c	2011-05-08 18:00:33.000000000 +0800
@@ -345,11 +345,12 @@
 		 */
 		ret = mtd->read_oob(mtd, offs, &ops);
 		if (ret)
+			{
+//			printk("-1--%s -%d----------\n",__func__,ret); //mj
 			return ret;
-
+			}
 		if (check_short_pattern(buf, bd))
 			return 1;
-
 		offs += mtd->writesize;
 	}
 	return 0;
@@ -422,7 +423,6 @@
 					      scanlen, len);
 		else
 			ret = scan_block_fast(mtd, bd, from, buf, len);
-
 		if (ret < 0)
 			return ret;
 
diff -uNra linux-2.6.27.6/drivers/parport/daisy.c linux-2.6.27.6.yaffs/drivers/parport/daisy.c
--- linux-2.6.27.6/drivers/parport/daisy.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/parport/daisy.c	2011-05-08 18:00:38.000000000 +0800
@@ -103,6 +103,7 @@
 
 	/* If mux present on normal port, need to create new
 	 * parports for each extra port. */
+//printk("--1---------------hah--mj:%s---\n",__func__);
 	if (port->muxport < 0 && mux_present(port) &&
 	    /* don't be fooled: a mux must have 2 or 4 ports. */
 	    ((num_ports = num_mux_ports(port)) == 2 || num_ports == 4)) {
@@ -137,10 +138,13 @@
 	if (port->muxport >= 0)
 		select_port(port);
 
+//printk("--2---------------hah--mj:%s---\n",__func__);
 	parport_daisy_deselect_all(port);
+//printk("--3---------------hah--mj:%s---\n",__func__);
 	detected += assign_addrs(port);
 
 	/* Count the potential legacy device at the end. */
+//printk("--4---------------hah--mj:%s---\n",__func__);
 	add_dev(numdevs++, port, -1);
 
 	/* Find out the legacy device's IEEE 1284 device ID. */
@@ -157,6 +161,7 @@
                    funny state; let's try to reset them and see if
                    they wake up. */
 		parport_daisy_fini(port);
+//printk("--5---------------hah--mj:%s---\n",__func__);
 		parport_write_control(port, PARPORT_CONTROL_SELECT);
 		udelay(50);
 		parport_write_control(port,
diff -uNra linux-2.6.27.6/drivers/parport/parport_gsc.h linux-2.6.27.6.yaffs/drivers/parport/parport_gsc.h
--- linux-2.6.27.6/drivers/parport/parport_gsc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/parport/parport_gsc.h	2011-05-08 18:00:38.000000000 +0800
@@ -34,7 +34,8 @@
 #include <asm/io.h>
 #include <linux/delay.h>
 
-#undef	DEBUG_PARPORT	/* undefine for production */
+//#undef	DEBUG_PARPORT	/* undefine for production */
+#define	DEBUG_PARPORT	/* undefine for production */
 #define DELAY_TIME 	0
 
 #if DELAY_TIME == 0
diff -uNra linux-2.6.27.6/drivers/parport/parport_pc.c linux-2.6.27.6.yaffs/drivers/parport/parport_pc.c
--- linux-2.6.27.6/drivers/parport/parport_pc.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/parport/parport_pc.c	2011-05-08 18:00:38.000000000 +0800
@@ -120,7 +120,8 @@
 	DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
 		m, v, ectr, (ectr & ~m) ^ v);
 
-	outb ((ectr & ~m) ^ v, ECONTROL (pb));
+	//outb ((ectr & ~m) ^ v, ECONTROL (pb));
+	writeb ((ectr & ~m) ^ v, ECONTROL (pb));
 }
 
 static __inline__ void frob_set_mode (struct parport *p, int mode)
@@ -149,7 +150,8 @@
 	}
 
 	/* Bits <7:5> contain the mode. */
-	oecr = inb (ECONTROL (p));
+	//oecr = inb (ECONTROL (p));
+	oecr = readb (ECONTROL (p));
 	mode = (oecr >> 5) & 0x7;
 	if (mode == m) return 0;
 
@@ -163,14 +165,16 @@
 		case ECR_ECP: /* ECP Parallel Port mode */
 			/* Busy wait for 200us */
 			for (counter = 0; counter < 40; counter++) {
-				if (inb (ECONTROL (p)) & 0x01)
+				//if (inb (ECONTROL (p)) & 0x01)
+				if (readb (ECONTROL (p)) & 0x01)
 					break;
 				if (signal_pending (current)) break;
 				udelay (5);
 			}
 
 			/* Poll slowly. */
-			while (!(inb (ECONTROL (p)) & 0x01)) {
+			//while (!(inb (ECONTROL (p)) & 0x01)) {
+			while (!(readb (ECONTROL (p)) & 0x01)) {
 				if (time_after_eq (jiffies, expire))
 					/* The FIFO is stuck. */
 					return -EBUSY;
@@ -257,8 +261,10 @@
 	/* To clear timeout some chips require double read */
 	parport_pc_read_status(pb);
 	r = parport_pc_read_status(pb);
-	outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
-	outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
+	//outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
+	writeb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
+	//outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
+	writeb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
 	r = parport_pc_read_status(pb);
 
 	return !(r & 0x01);
@@ -289,14 +295,16 @@
 	const struct parport_pc_private *priv = p->physport->private_data;
 	s->u.pc.ctr = priv->ctr;
 	if (priv->ecr)
-		s->u.pc.ecr = inb (ECONTROL (p));
+		//s->u.pc.ecr = inb (ECONTROL (p));
+		s->u.pc.ecr = readb (ECONTROL (p));
 }
 
 static void parport_pc_restore_state(struct parport *p, struct parport_state *s)
 {
 	struct parport_pc_private *priv = p->physport->private_data;
 	register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
-	outb (c, CONTROL (p));
+	//outb (c, CONTROL (p));
+	writeb (c, CONTROL (p));
 	priv->ctr = c;
 	if (priv->ecr)
 		ECR_WRITE (p, s->u.pc.ecr);
@@ -316,7 +324,8 @@
 		 *  nFault is 0 if there is at least 1 byte in the Warp's FIFO
 		 *  pError is 1 if there are 16 bytes in the Warp's FIFO
 		 */
-		status = inb (STATUS (port));
+		//status = inb (STATUS (port));
+		status = readb (STATUS (port));
 
 		while (!(status & 0x08) && (got < length)) {
 			if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
@@ -331,12 +340,14 @@
 				left -= 16;
 			} else {
 				/* grab single byte from the warp fifo */
-				*((char *)buf) = inb (EPPDATA (port));
+				//*((char *)buf) = inb (EPPDATA (port));
+				*((char *)buf) = readb (EPPDATA (port));
 				buf++;
 				got++;
 				left--;
 			}
-			status = inb (STATUS (port));
+			//status = inb (STATUS (port));
+			status = readb (STATUS (port));
 			if (status & 0x01) {
 				/* EPP timeout should never occur... */
 				printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
@@ -352,16 +363,19 @@
 		} else {
 			insb (EPPDATA (port), buf, length);
 		}
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			clear_epp_timeout (port);
 			return -EIO;
 		}
 		return length;
 	}
 	for (; got < length; got++) {
-		*((char*)buf) = inb (EPPDATA(port));
+		//*((char*)buf) = inb (EPPDATA(port));
+		*((char*)buf) = readb (EPPDATA(port));
 		buf++;
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			/* EPP timeout */
 			clear_epp_timeout (port);
 			break;
@@ -382,7 +396,8 @@
 		} else {
 			outsb (EPPDATA (port), buf, length);
 		}
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			clear_epp_timeout (port);
 			return -EIO;
 		}
@@ -391,7 +406,8 @@
 	for (; written < length; written++) {
 		outb (*((char*)buf), EPPDATA(port));
 		buf++;
-		if (inb (STATUS(port)) & 0x01) {
+		//if (inb (STATUS(port)) & 0x01) {
+		if (readb (STATUS(port)) & 0x01) {
 			clear_epp_timeout (port);
 			break;
 		}
@@ -407,16 +423,19 @@
 
 	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
 		insb (EPPADDR (port), buf, length);
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			clear_epp_timeout (port);
 			return -EIO;
 		}
 		return length;
 	}
 	for (; got < length; got++) {
-		*((char*)buf) = inb (EPPADDR (port));
+		//*((char*)buf) = inb (EPPADDR (port));
+		*((char*)buf) = readb (EPPADDR (port));
 		buf++;
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			clear_epp_timeout (port);
 			break;
 		}
@@ -433,7 +452,8 @@
 
 	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
 		outsb (EPPADDR (port), buf, length);
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			clear_epp_timeout (port);
 			return -EIO;
 		}
@@ -442,7 +462,8 @@
 	for (; written < length; written++) {
 		outb (*((char*)buf), EPPADDR (port));
 		buf++;
-		if (inb (STATUS (port)) & 0x01) {
+		//if (inb (STATUS (port)) & 0x01) {
+		if (readb (STATUS (port)) & 0x01) {
 			clear_epp_timeout (port);
 			break;
 		}
@@ -535,7 +556,8 @@
 
 	while (left) {
 		unsigned char byte;
-		unsigned char ecrval = inb (ECONTROL (port));
+		//unsigned char ecrval = inb (ECONTROL (port));
+		unsigned char ecrval = readb (ECONTROL (port));
 		int i = 0;
 
 		if (need_resched() && time_before (jiffies, expire))
@@ -562,7 +584,8 @@
 				printk (KERN_DEBUG "FIFO write timed out\n");
 				break;
 			}
-			ecrval = inb (ECONTROL (port));
+			//ecrval = inb (ECONTROL (port));
+			ecrval = readb (ECONTROL (port));
 			if (!(ecrval & (1<<2))) {
 				if (need_resched() &&
 				    time_before (jiffies, expire))
@@ -593,7 +616,8 @@
 			continue;
 		} else if (i++ < poll_for) {
 			udelay (10);
-			ecrval = inb (ECONTROL (port));
+			//ecrval = inb (ECONTROL (port));
+			ecrval = readb (ECONTROL (port));
 			goto poll;
 		}
 
@@ -689,7 +713,8 @@
 			break;
 		}
 		/* Is serviceIntr set? */
-		if (!(inb (ECONTROL (port)) & (1<<2))) {
+		//if (!(inb (ECONTROL (port)) & (1<<2))) {
+		if (!(readb (ECONTROL (port)) & (1<<2))) {
 			cond_resched();
 
 			goto false_alarm;
@@ -792,7 +817,8 @@
 
 		/* Adjust for the contents of the FIFO. */
 		for (written -= priv->fifo_depth; ; written++) {
-			if (inb (ECONTROL (port)) & 0x2) {
+			//if (inb (ECONTROL (port)) & 0x2) {
+			if (readb (ECONTROL (port)) & 0x2) {
 				/* Full up. */
 				break;
 			}
@@ -887,7 +913,8 @@
 
 		/* Adjust for the contents of the FIFO. */
 		for (written -= priv->fifo_depth; ; written++) {
-			if (inb (ECONTROL (port)) & 0x2) {
+			//if (inb (ECONTROL (port)) & 0x2) {
+			if (readb (ECONTROL (port)) & 0x2) {
 				/* Full up. */
 				break;
 			}
@@ -1619,19 +1646,27 @@
 
 	/* Do a simple read-write test to make sure the port exists. */
 	w = 0xc;
-	outb (w, CONTROL (pb));
+	//outb (w, CONTROL (pb));
+//printk("--mj:%s--1-\n",__func__);
+	writeb (w, CONTROL (pb));
 
+//printk("--mj:%s--2-\n",__func__);
 	/* Is there a control register that we can read from?  Some
 	 * ports don't allow reads, so read_control just returns a
 	 * software copy. Some ports _do_ allow reads, so bypass the
 	 * software copy here.  In addition, some bits aren't
 	 * writable. */
-	r = inb (CONTROL (pb));
+	//r = inb (CONTROL (pb));
+	r = readb (CONTROL (pb));
+//printk("--mj:%s--3-\n",__func__);
 	if ((r & 0xf) == w) {
 		w = 0xe;
-		outb (w, CONTROL (pb));
-		r = inb (CONTROL (pb));
-		outb (0xc, CONTROL (pb));
+		//outb (w, CONTROL (pb));
+		writeb (w, CONTROL (pb));
+		//r = inb (CONTROL (pb));
+		r = readb (CONTROL (pb));
+		//outb (0xc, CONTROL (pb));
+		writeb (0xc, CONTROL (pb));
 		if ((r & 0xf) == w)
 			return PARPORT_MODE_PCSPP;
 	}
@@ -1646,6 +1681,7 @@
 	 * this stage, so we expect back what we wrote. */
 	w = 0xaa;
 	parport_pc_write_data (pb, w);
+//printk("--mj:%s--4-\n",__func__);
 	r = parport_pc_read_data (pb);
 	if (r == w) {
 		w = 0x55;
@@ -1665,11 +1701,13 @@
 			pb->base);
 	}
 
+//printk("--mj:%s--5-\n",__func__);
 	/* It's possible that we can't read the control register or
 	 * the data register.  In that case just believe the user. */
 	if (user_specified)
 		return PARPORT_MODE_PCSPP;
 
+//printk("--mj:%s--6-\n",__func__);
 	return 0;
 }
 
@@ -1691,9 +1729,11 @@
 	struct parport_pc_private *priv = pb->private_data;
 	unsigned char r = 0xc;
 
-	outb (r, CONTROL (pb));
+	//outb (r, CONTROL (pb));
+	writeb (r, CONTROL (pb));
 	if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
-		outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
+		//outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
+		writeb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
 
 		r = inb (CONTROL (pb));
 		if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
@@ -1708,7 +1748,8 @@
 		goto no_reg;
 
 	priv->ecr = 1;
-	outb (0xc, CONTROL (pb));
+	//outb (0xc, CONTROL (pb));
+	writeb (0xc, CONTROL (pb));
 	
 	/* Go to mode 000 */
 	frob_set_mode (pb, ECR_SPP);
@@ -1716,7 +1757,8 @@
 	return 1;
 
  no_reg:
-	outb (0xc, CONTROL (pb));
+	//outb (0xc, CONTROL (pb));
+	writeb (0xc, CONTROL (pb));
 	return 0; 
 }
 
@@ -1748,11 +1790,13 @@
 	parport_pc_data_reverse (pb);
 	
 	parport_pc_write_data(pb, 0x55);
+printk("-supported-1-p->base:%lx---\n",pb->base);
 	if (parport_pc_read_data(pb) != 0x55) ok++;
 
 	parport_pc_write_data(pb, 0xaa);
 	if (parport_pc_read_data(pb) != 0xaa) ok++;
 
+printk("-supported-2-p->base:%lx---\n",pb->base);
 	/* cancel input mode */
 	parport_pc_data_forward (pb);
 
@@ -1784,7 +1828,8 @@
 	ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
 	ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
 	for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
-		outb (0xaa, FIFO (pb));
+		//outb (0xaa, FIFO (pb));
+		writeb (0xaa, FIFO (pb));
 
 	/*
 	 * Using LGS chipset it uses ECR register, but
@@ -1827,7 +1872,8 @@
 	frob_econtrol (pb, 1<<2, 1<<2);
 	frob_econtrol (pb, 1<<2, 0);
 	for (i = 1; i <= priv->fifo_depth; i++) {
-		outb (0xaa, FIFO (pb));
+		//outb (0xaa, FIFO (pb));
+		writeb (0xaa, FIFO (pb));
 		if (inb (ECONTROL (pb)) & (1<<2))
 			break;
 	}
@@ -1970,7 +2016,8 @@
 	oecr = inb (ECONTROL (pb));
 	/* Search for SMC style EPP+ECP mode */
 	ECR_WRITE (pb, 0x80);
-	outb (0x04, CONTROL (pb));
+	//outb (0x04, CONTROL (pb));
+	writeb (0x04, CONTROL (pb));
 	result = parport_EPP_supported(pb);
 
 	ECR_WRITE (pb, oecr);
@@ -2032,7 +2079,8 @@
 
 	/* If Full FIFO sure that writeIntrThreshold is generated */
 	for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++) 
-		outb (0xaa, FIFO (pb));
+		//outb (0xaa, FIFO (pb));
+		writeb (0xaa, FIFO (pb));
 		
 	pb->irq = probe_irq_off(irqs);
 	ECR_WRITE (pb, ECR_SPP << 5);
@@ -2184,6 +2232,7 @@
 	struct resource	*EPP_res = NULL;
 	struct platform_device *pdev = NULL;
 
+//printk("--mj:%s--1-\n",__func__);
 	if (!dev) {
 		/* We need a physical device to attach to, but none was
 		 * provided. Create our own. */
@@ -2198,19 +2247,27 @@
 	if (!ops)
 		goto out1;
 
+//printk("--mj:%s--out1-\n",__func__);
+//printk("---p->base:%lx---",p->base);
 	priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
 	if (!priv)
 		goto out2;
 
+///printk("---p->base:%lx---",p->base);
 	/* a misnomer, actually - it's allocate and reserve parport number */
 	p = parport_register_port(base, irq, dma, ops);
 	if (!p)
 		goto out3;
 
-	base_res = request_region(base, 3, p->name);
+//printk("--mj:%s--out3-\n",__func__);
+//printk("---p->base:%lx---",p->base);
+#if 0
+	//base_res = request_region(base, 3, p->name);
+	base_res = request_mem_region(base, 3, p->name);
 	if (!base_res)
-		goto out4;
-
+	//	goto out4;
+#endif 
+//printk("--mj:%s--out4-\n",__func__);
 	memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
 	priv->ctr = 0xc;
 	priv->ctr_writable = ~0x10;
@@ -2225,19 +2282,24 @@
 	p->base_hi = base_hi;
 	p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
 	p->private_data = priv;
-
+//printk("--mj:%s--2-\n",__func__);
+//printk("---p->base:%lx---",p->base);
 	if (base_hi) {
 		ECR_res = request_region(base_hi, 3, p->name);
 		if (ECR_res)
 			parport_ECR_present(p);
 	}
 
+//printk("--mj:%s--3-\n",__func__);
+//printk("---p->base:%lx---",p->base);
+#if 0
 	if (base != 0x3bc) {
 		EPP_res = request_region(base+0x3, 5, p->name);
 		if (EPP_res)
 			if (!parport_EPP_supported(p))
 				parport_ECPEPP_supported(p);
 	}
+#endif
 	if (!parport_SPP_supported (p))
 		/* No port. */
 		goto out5;
@@ -2269,6 +2331,7 @@
 			parport_dma_probe(p);
 		}
 	}
+printk("--1-p->base:%lx---",p->base);
 	if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
                                            is mandatory (see above) */
 		p->dma = PARPORT_DMA_NONE;
@@ -2311,6 +2374,7 @@
 	printk ("(,...)");
 #endif /* CONFIG_PARPORT_1284 */
 	printk("]\n");
+printk("-2--p->base:%lx---",p->base);
 	if (probedirq != PARPORT_IRQ_NONE) 
 		printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
 
@@ -2370,6 +2434,8 @@
 		 */
 		ECR_WRITE (p, 0x34);
 
+//printk("--mj:%s--4-\n",__func__);
+//printk("-4-p->base:%lx---",p->base);
 	parport_pc_write_data(p, 0);
 	parport_pc_data_forward (p);
 
@@ -3173,13 +3239,17 @@
 parport_pc_find_isa_ports (int autoirq, int autodma)
 {
 	int count = 0;
-
+//printk("--mj:%s--partport_pc_probe55-\n",__func__);
+#if 0
 	if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
 		count++;
 	if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
 		count++;
 	if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
 		count++;
+#endif
+	if (parport_pc_probe_port(0xffffffffbe0000e0, 0x0, autoirq, autodma, NULL))
+		count++;
 
 	return count;
 }
@@ -3448,6 +3518,7 @@
 
 	if (parse_parport_params())
 		return -EINVAL;
+	printk("----1----\n");
 
 	err = platform_driver_register(&parport_pc_platform_driver);
 	if (err)
@@ -3466,6 +3537,7 @@
 						  irqval[i], dmaval[i], NULL);
 		}
 	} else
+	printk("----2----\n");
 		parport_pc_find_ports (irqval[0], dmaval[0]);
 
 	return 0;
@@ -3491,9 +3563,284 @@
 		parport_pc_unregister_port(port);
 	}
 }
+#if 0 //mj add 
+/* S3C2410 ¿ª·¢°åÀ©Õ¹²¢¿Ú16C552µÄlow-levelÇý¶¯
+ *
+ * Author: Allen He<wingwind@sina.com>
+ *
+ *
+ *
+ * The extended parallel port provides one port at a fixed address
+ * with 8 output data lines (D0 - D7), 1 output control line (STROBE)
+ * and 1 input status line (BUSY) able to cause an interrupt.
+ */
+
+//#define MODULE  //HYL Add 
+
+
+//#include <asm/irq.h>
+//#include <asm/hardware.h>
+//#include <asm/arch/cpu_s3c2410.h>
+#include <linux/parport_2410_16c552.h>
+#define INT_EINT8_23 34
+static struct parport *this_port = NULL;
+
+ unsigned char
+parport_16c552_read_data(struct parport *p)
+{
+	unsigned long flags;
+	unsigned char data;
+
+	//save_flags(flags);
+	//local_save_flags(flags);
+	//cli();
+	data=*((unsigned char *)(p->base+0x0)) ;
+	//local_restore_flags(flags);
+printk("-----------------hah--mj:%s-data:%08x--\n",__func__,data);
+	return data;
+}
+
+static void
+parport_16c552_write_data(struct parport *p, unsigned char data)
+{
+	unsigned long flags;
+parport_16c552_read_data(p);
+printk("-----------------hah--mj:%s---%08x---%02x\n",__func__,(p->base),data);
+	//save_flags(flags);
+	//cli();
+	*((unsigned char *)(p->base+0x0))=data;
+	//restore_flags(flags);
+	return;
+}
+
+
+
+unsigned char parport_16c552_read_control(struct parport *p)
+{
+	unsigned long flags;
+	unsigned char control = 0;
+
+	//save_flags(flags);
+	//cli();
+	control=*((unsigned char *)(p->base+0x2));
+	//restore_flags(flags);
+	return control;
+
+}
+
+void parport_16c552_write_control(struct parport *p, unsigned char d)
+{
+
+	unsigned long flags;
+
+	//save_flags(flags);
+	//cli();
+	*((unsigned char *)(p->base+0x2))=d;
+	//restore_flags(flags);
+	return;
+}
+
+static unsigned char
+parport_16c552_frob_control(struct parport *p, unsigned char mask,
+			   unsigned char val)
+{
+	unsigned char old = parport_16c552_read_control(p);
+	parport_16c552_write_control(p, (old & ~mask) ^ val);
+	return old;
+}
+
+static unsigned char
+parport_16c552_read_status(struct parport *p)
+{
+printk("-----------------hah--mj:%s-data:%08x--\n",__func__,*((unsigned char *)(p->base+0x1)));
+	return (*((unsigned char *)(p->base+0x1)));
+}
+
+static void
+parport_16c552_init_state(struct pardevice *d, struct parport_state *s)
+{
+}
+
+static void
+parport_16c552_save_state(struct parport *p, struct parport_state *s)
+{
+}
+
+static void
+parport_16c552_restore_state(struct parport *p, struct parport_state *s)
+{
+}
+
+static void
+//parport_16c552_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+parport_16c552_interrupt(void *dev_id)
+{
+//printk("-----------------hah--mj:%s---\n",__func__);
+	parport_generic_irq((struct parport *) dev_id);
+}
+
+static void
+parport_16c552_enable_irq(struct parport *p)
+{
+	enable_irq(INT_EINT8_23);
+}
+
+static void
+parport_16c552_disable_irq(struct parport *p)
+{
+	disable_irq(INT_EINT8_23);
+}
+
+static void
+parport_16c552_data_forward(struct parport *p)
+{
+	unsigned long flags;
+	////save_flags(flags);
+	//cli();
+	parport_16c552_frob_control(p,0x20,0x0);
+	//restore_flags(flags);
+}
+
+static void
+parport_16c552_data_reverse(struct parport *p)
+{
+	unsigned long flags;
+	//save_flags(flags);
+	//cli();
+	parport_16c552_frob_control(p,0x20,0x20);
+	//restore_flags(flags);
+}
+
+static void
+parport_16c552_inc_use_count(void)
+{
+//	MOD_INC_USE_COUNT;
+}
+
+static void
+parport_16c552_dec_use_count(void)
+{
+//	MOD_DEC_USE_COUNT;
+}
+
+static struct parport_operations parport_16c552_ops = {
+	parport_16c552_write_data,
+	parport_16c552_read_data,
+
+	parport_16c552_write_control,
+	parport_16c552_read_control,
+	parport_16c552_frob_control,
+
+	parport_16c552_read_status,
+
+	parport_16c552_enable_irq,
+	parport_16c552_disable_irq,
+
+	parport_16c552_data_forward,
+	parport_16c552_data_reverse,
+
+	parport_16c552_init_state,
+	parport_16c552_save_state,
+	parport_16c552_restore_state,
 
+	parport_16c552_inc_use_count,
+	parport_16c552_dec_use_count,
+
+	parport_ieee1284_epp_write_data,
+	parport_ieee1284_epp_read_data,
+	parport_ieee1284_epp_write_addr,
+	parport_ieee1284_epp_read_addr,
+
+	parport_ieee1284_ecp_write_data,
+	parport_ieee1284_ecp_read_data,
+	parport_ieee1284_ecp_write_addr,
+
+	parport_ieee1284_write_compat,
+	parport_ieee1284_read_nibble,
+	parport_ieee1284_read_byte,
+};
+
+
+int __init
+parport_16c552_init(void)
+{
+	struct parport *p;
+	unsigned long flags;
+
+//printk("--1---------------hah--mj:%s---\n",__func__);
+		/*·ÖÅäÄÚ´æÇøÓò*/
+		if(check_mem_region(brd_16c552_parportbase,0x3))//0x800 is a number defined as will.
+		{
+			printk("16c552 driver:memory already in use\n");
+			return -EBUSY;
+		}
+//printk("--2---------------hah--mj:%s---\n",__func__);
+		request_mem_region(brd_16c552_parportbase,0x3,"parport_16c552");		
+		
+///printk("--3---------------hah--mj:%s---\n",__func__);
+		p = parport_register_port(brd_16c552_parportbase,INT_EINT8_23,
+					  PARPORT_DMA_NONE,
+					  &parport_16c552_ops);
+//printk("--4---------------hah--mj:%s--,%s-,%08x\n",__func__,p->name,p);
+		if (!p)
+			return 0;
+		//if (request_irq(INT_EINT8_23, parport_16c552_interrupt,SA_SHIRQ, p->name, p)) {
+		if (request_irq(INT_EINT8_23, parport_16c552_interrupt,0, p->name, p)) {
+		//	parport_unregister_port (p);
+			return 0;
+		}
+	
+/*		// initialize the parport as a input device with disabling irq. 
+		save_flags(flags);
+		cli();
+		parport_16c552_frob_control(p,0x3f,0x24);		
+		restore_flags(flags);
+*/
+
+
+		this_port = p;
+		printk(KERN_INFO "%s: s3c2410 brd extended with 16c552, port using irq\n", p->name);
+		
+//printk("--5---------------hah--mj:%s---\n",__func__);
+		parport_proc_register(p);
+
+//printk("--6---------------hah--mj:%s---\n",__func__);
+		parport_announce_port (p);
+
+//printk("--0---------------hah--mj:%s---\n",__func__);
+		return 1;
+	
+}
+
+#if 0
+//#ifdef MODULE
+
+MODULE_AUTHOR("Wingwind");
+MODULE_DESCRIPTION("Parport Driver for 16c552 parellel Port");
+MODULE_SUPPORTED_DEVICE("S3c2410 extending 16c552 Parallel Port");
+MODULE_LICENSE("GPL");
+
+int
+init_module(void)
+{
+	return parport_16c552_init() ? 0 : -ENODEV;
+}
+
+void
+cleanup_module(void)
+{
+	if (this_port->irq != PARPORT_IRQ_NONE)
+		free_irq(IRQ_MFP_BUSY, this_port);
+	parport_proc_unregister(this_port);
+	parport_unregister_port(this_port);
+	release_mem_region(brd_16c552_parportbase,0x3,);	
+}
+#endif
+
+#endif
 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
 MODULE_DESCRIPTION("PC-style parallel port driver");
 MODULE_LICENSE("GPL");
+//module_init(parport_16c552_init)
 module_init(parport_pc_init)
 module_exit(parport_pc_exit)
diff -uNra linux-2.6.27.6/drivers/parport/share.c linux-2.6.27.6.yaffs/drivers/parport/share.c
--- linux-2.6.27.6/drivers/parport/share.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/parport/share.c	2011-05-08 18:00:38.000000000 +0800
@@ -362,7 +362,9 @@
 
 #ifdef CONFIG_PARPORT_1284
 	/* Analyse the IEEE1284.3 topology of the port. */
+//printk("--1---------------hah--mj:%s---\n",__func__);
 	parport_daisy_init(port);
+//printk("--2---------------hah--mj:%s---\n",__func__);
 #endif
 
 	if (!port->dev)
@@ -370,10 +372,14 @@
 				"no-device port driver!\n",
 				port->name);
 
+//printk("--3---------------hah--mj:%s---\n",__func__);
 	parport_proc_register(port);
+//printk("--4---------------hah--mj:%s---\n",__func__);
 	mutex_lock(&registration_lock);
 	spin_lock_irq(&parportlist_lock);
+//printk("--5---------------hah--mj:%s---\n",__func__);
 	list_add_tail(&port->list, &portlist);
+//printk("--6---------------hah--mj:%s---\n",__func__);
 	for (i = 1; i < 3; i++) {
 		struct parport *slave = port->slaves[i-1];
 		if (slave)
@@ -382,7 +388,9 @@
 	spin_unlock_irq(&parportlist_lock);
 
 	/* Let drivers know that new port(s) has arrived. */
+//printk("--7---------------hah--mj:%s---\n",__func__);
 	attach_driver_chain (port);
+//printk("--8---------------hah--mj:%s---\n",__func__);
 	for (i = 1; i < 3; i++) {
 		struct parport *slave = port->slaves[i-1];
 		if (slave)
diff -uNra linux-2.6.27.6/drivers/scsi/atp8620.c linux-2.6.27.6.yaffs/drivers/scsi/atp8620.c
--- linux-2.6.27.6/drivers/scsi/atp8620.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/atp8620.c	2011-05-08 18:01:03.000000000 +0800
@@ -0,0 +1,5346 @@
+/* $ Id: ATP8620.C , v 0.10 2006/11/14 11:25:00 $
+ *
+ *  Copyright (C) 2005 ACARD Technology Corp.
+*********************************************************
+          modify history
+
+*********************************************************
+*/
+#define NCQ_SUPPORT	1
+#define DEBUG_80_PORT	0
+#define DISK_NCQ_CHECK	0
+#include <linux/module.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/pci.h>
+#include <linux/blk.h>
+#include "scsi.h"
+#include "hosts.h"
+#include "sd.h"
+#else
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/pci.h>
+#include <linux/blkdev.h>
+#include <linux/dma-mapping.h>
+#include <linux/stat.h>
+#include <linux/list.h>
+#include <scsi/scsi_host.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <scsi/scsi.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_device.h>
+#include <scsi/scsi_host.h>
+#endif
+#include <linux/stat.h>
+#ifndef IRQF_SHARED
+	#define IRQF_SHARED SA_SHIRQ
+#endif
+#ifndef DMA_32BIT_MASK
+	#define DMA_32BIT_MASK 0xFFFFFFFFUL
+#endif
+#include "atp8620.h"
+static int oldide=0;
+static int __devinit atp8620_init_one(struct pci_dev *dev);
+
+// following function is implement necessary
+static int  adapter_initialize(struct pci_dev *pPciDev);
+static void adapter_release_resource(void *pScsiHostData);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+static int  adapter_reset(Scsi_Cmnd *pScsiCmd, unsigned int reset_flags);
+static void adapter_intr_handle(int irq, void *dev_id, struct pt_regs *regs);
+#else
+static int  adapter_reset(Scsi_Cmnd *pScsiCmd);
+static irqreturn_t adapter_intr_handle(int irq, void *dev_id);
+#endif
+static int  adapter_queuecommand(Scsi_Cmnd *pScsiCmd, void (*done) (Scsi_Cmnd *));
+static void adapter_timer(unsigned long para);
+//========================================================================
+//=== scsidrv.c ============================================================
+//========================================================================
+static int adapter_probe(struct pci_dev *pPciDev, const struct pci_device_id *ent);
+static void adapter_remove (struct pci_dev *pPciDev);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+static int adapter_biosparam(Scsi_Disk * disk, kdev_t dev, int *ip);
+
+static int adapter_proc_info(char *buffer, char **start, off_t offset, int length,
+                             int hostno, int inout);
+static int adapter_detect(Scsi_Host_Template *tpnt);
+static int adapter_release (struct Scsi_Host *pScsiHost);
+#else	
+static int adapter_biosparam(struct scsi_device *disk, struct block_device *dev,
+                             sector_t capacity, int *ip);
+static int adapter_proc_info(struct Scsi_Host *HBAptr, char *buffer, char **start,
+                             off_t offset, int length, int inout);
+#endif
+static int adapter_set_info(char *buffer, int length, struct Scsi_Host *HBAptr);
+static const char *adapter_info(struct Scsi_Host *notused);
+//========================================================================
+typedef struct _ScsiHostData {
+	struct pci_dev *pPciDev;
+	struct Scsi_Host *pScsiHost;
+	void *DeviceExtension;
+	unsigned int szDeviceExtension;
+} T_ScsiHostData,*P_ScsiHostData;
+//========================================================================
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	static Scsi_Host_Template driver_template = SCSI_DRV_TEMPLATE;
+	static struct Scsi_Host *AdapterHost[MAX_ADAPTER];
+	static int AdapterCounter;
+#else
+	static struct scsi_host_template  driver_template = SCSI_DRV_TEMPLATE;
+#endif
+static struct pci_device_id device_id_table[] = PCI_DEVICE_ID_TABLE;
+//========================================================================
+static struct pci_driver adapter_driver = {
+	.id_table	= device_id_table,
+	.name	= DRIVER_NAME,
+	.probe	= adapter_probe,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	.remove	= adapter_remove,
+#else
+	.remove	= __devexit_p(adapter_remove),
+#endif
+};
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+//void msleep(int mdelay_time)
+//{
+//	int i;
+//	
+//	for (i = 0 ; i < mdelay_time ; i++) {
+//		udelay(1000);
+//	}
+//	return;
+//}
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+#define sg_page(sg) ((sg)->page)
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24)
+#define KERNEL_V2625
+#else
+#define scsi_sg_count(cmd) ((cmd)->use_sg)
+#endif
+//========================================================================
+static int adapter_probe(struct pci_dev *pPciDev, const struct pci_device_id *ent)
+{
+	int init_status;
+	struct Scsi_Host *pScsiHost;
+
+	if (pci_enable_device(pPciDev)) {
+		printk("adapter_probe:PCI device can not enable\n\r");
+		return -EIO;
+	}
+        if (pci_set_dma_mask(pPciDev, DMA_32BIT_MASK)) {
+		printk("adapter_probe DMA ERROR\n\r");
+                return -EIO;
+        }
+	if (pPciDev->irq == 0) {
+		printk("adapter_probe:IRQ incorrecte\n\r");
+		return -EIO;
+	}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	if (!(pScsiHost = scsi_register(&driver_template, sizeof(T_ScsiHostData)))) {
+#else
+	if (!(pScsiHost = scsi_host_alloc(&driver_template, sizeof(T_ScsiHostData)))) {
+#endif
+		printk("adapter_probe:SCSI host allocate fail\n\r");
+		return -ENOMEM;
+	}
+	memset(pScsiHost->hostdata,0,(int)sizeof(T_ScsiHostData));  // clear already in kernel 2.6
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#else
+	if (scsi_add_host(pScsiHost, &pPciDev->dev)) {
+		printk("adapter_probe:SCSI host add fail\n\r");
+		scsi_host_put(pScsiHost);
+		return -EIO;
+	}
+#endif
+	((P_ScsiHostData)(pScsiHost->hostdata))->pPciDev = pPciDev;
+	((P_ScsiHostData)(pScsiHost->hostdata))->pScsiHost = pScsiHost;
+	((P_ScsiHostData)(pScsiHost->hostdata))->DeviceExtension = NULL;
+	((P_ScsiHostData)(pScsiHost->hostdata))->szDeviceExtension = 0;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	AdapterHost[AdapterCounter] = pScsiHost;
+	AdapterCounter++;
+#else
+#endif
+	pci_set_drvdata(pPciDev,pScsiHost->hostdata);
+	if ((init_status = adapter_initialize(pPciDev))!= 0) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+		scsi_unregister(pScsiHost);
+		AdapterCounter--;
+		AdapterHost[AdapterCounter] = NULL;
+#else
+		scsi_remove_host(pScsiHost);
+		scsi_host_put(pScsiHost);
+#endif
+		printk("adapter_probe:SCSI adapter initialize fail\n\r");
+		return init_status;
+	}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#else
+	scsi_scan_host(pScsiHost);
+#endif
+
+if(oldide)
+{
+PHW_DEVICE_EXTENSION pHwDeviceExtension = ((P_ScsiHostData)(pScsiHost->hostdata))->DeviceExtension;
+//	if(!pHwDeviceExtension->DeviceInfo[0].FG_DeviceInstall && !pHwDeviceExtension->DeviceInfo[0].FG_DeviceInstall)
+	atp8620_init_one(pPciDev);
+}
+
+	return 0;
+}
+//========================================================================
+static void adapter_remove (struct pci_dev *pPciDev)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	pci_set_drvdata(pPciDev, NULL);
+	AdapterCounter--;
+#else
+	P_ScsiHostData pScsiHostData;
+
+	pScsiHostData = pci_get_drvdata(pPciDev);
+	scsi_remove_host(pScsiHostData->pScsiHost);
+	adapter_release_resource(pScsiHostData);
+	scsi_host_put(pScsiHostData->pScsiHost);
+	pci_set_drvdata(pPciDev, NULL);
+#endif
+	return;
+}
+//========================================================================
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+
+#include "scsi_module.c"
+//========================================================================
+static int adapter_detect(Scsi_Host_Template * tpnt)
+{
+	int i;
+	
+	for (i = 0 ; i < MAX_ADAPTER ; i++) {
+		AdapterHost[i] = NULL;
+	}
+	AdapterCounter = 0;
+	if (pci_module_init(&adapter_driver) == 0) {
+		// ADAPTER INITIALIZE SUCCESSFUL
+		return AdapterCounter;
+	}
+	return 0;
+}
+//========================================================================
+static int adapter_release (struct Scsi_Host *pScsiHost)
+{
+	
+	if (AdapterCounter > 0) {
+		pci_unregister_driver(&adapter_driver);
+	}
+	adapter_release_resource(pScsiHost->hostdata);
+	scsi_unregister(pScsiHost);
+	return 0;
+}
+//========================================================================
+#else
+//========================================================================
+static int __init adapter_init(void)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	int i;
+	
+	for (i = 0 ; i < MAX_ADAPTER ; i++) {
+		AdapterHost[i] = NULL;
+	}
+	AdapterCounter = 0;
+#endif
+	return pci_register_driver(&adapter_driver);
+}
+//========================================================================
+static void __exit adapter_exit(void)
+{
+	pci_unregister_driver(&adapter_driver);
+	return;
+}
+//========================================================================
+module_init(adapter_init);
+module_exit(adapter_exit);
+//========================================================================
+#endif
+//========================================================================
+MODULE_DEVICE_TABLE(pci, device_id_table);
+//========================================================================
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+static int adapter_biosparam(Scsi_Disk * disk, kdev_t dev, int *ip)
+{
+	unsigned long head,sector,cylinder,hdd_capacity;
+	
+	hdd_capacity = (unsigned long)(disk->capacity);
+#else
+static int adapter_biosparam(struct scsi_device *disk, struct block_device *dev,
+						  sector_t capacity, int *ip)
+{
+	unsigned long head,sector,cylinder,hdd_capacity;
+
+	hdd_capacity = (unsigned long)(capacity);
+#endif
+	head     = 64;
+	sector   = 32;
+	cylinder = hdd_capacity / (head * sector);
+	if (cylinder > 1024) {
+		head     = 255;
+		sector   = 63;
+		cylinder = hdd_capacity / (head * sector);
+	}
+	ip[0] = (int)head;
+	ip[1] = (int)sector;
+	ip[2] = (int)cylinder;
+	return 0;
+}
+//========================================================================
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+static int adapter_proc_info(char *buffer, char **start, off_t offset, int length,
+		      int hostno, int inout)
+{
+	struct Scsi_Host *pScsiHost;
+	static u8 buff[512];
+	int i,len = 0;
+
+	pScsiHost = NULL;
+	for (i = 0; i < MAX_ADAPTER; i++) {
+		if ((pScsiHost = AdapterHost[i]) != NULL) {
+			if (pScsiHost->host_no == hostno) {
+				break;
+			}
+			pScsiHost = NULL;
+		}
+	}
+	if (pScsiHost == NULL) {
+		len += sprintf(buffer, "Can't find adapter for host number %d\n\r", hostno);
+		*start = buffer + offset;	// Start of wanted data 
+		len -= offset;		// Start slop
+		if (len > length) {
+			len = length;	// Ending slop
+		}
+		return (len);
+	}
+#else	
+static int adapter_proc_info(struct Scsi_Host *pScsiHost, char *buffer,
+			char **start, off_t offset, int length, int inout)
+{
+	static u8 buff[512];
+	int len = 0;
+	
+#endif
+	if (inout != 0) {
+		//Has data been written to the file?
+		return (adapter_set_info(buffer, length, pScsiHost));
+	}
+	if (offset == 0) {
+		memset(buff, 0, sizeof(buff));
+	}
+	len += sprintf(buffer, "%s Version: %d.%d.%d",PROC_INFORMATION,DRV_VERSION_MAJOR,DRV_VERSION_MINOR,DRV_VERSION_BUILD);
+	*start = buffer + offset;	// Start of wanted data
+	len -= offset;		// Start slop
+	if (len > length) {
+		len = length;	// Ending slop
+	}
+	return (len);
+}
+//========================================================================
+static int adapter_set_info(char *buffer, int length, struct Scsi_Host *HBAptr)
+{
+	return -EINVAL; 	// Currently this is a no-op
+}
+//========================================================================
+static const char *adapter_info(struct Scsi_Host *notused)
+{
+	static char buffer[128];
+
+	sprintf(buffer,"%s Version:%d.%d.%d",ADAPTER_INFORMATION,DRV_VERSION_MAJOR,DRV_VERSION_MINOR,DRV_VERSION_BUILD);
+	return buffer;
+}
+//========================================================================
+//========================================================================
+//========================================================================
+MODULE_AUTHOR("Johnny Weng");
+MODULE_DESCRIPTION("ACARD ATP8620 LINUX SCSI Driver");
+MODULE_LICENSE("GPL");
+//========================================================================
+static unsigned char ModePage0[16] = {15,0,0,8,0,0,0,0,0,0,2,0,0,0,0,0};
+static unsigned char ModePage1[24] = {23,0,0,8,0,0,0,0,0,0,2,0,0x01,0x0a,0xc0,0x08,0x18,0x0a,0,0,0,0,0,0};
+static unsigned char ModePage8[24] = {23,0,0,8,0,0,0,0,0,0,2,0,0x08,0x0a,0x04,0,0xff,0xff,0,0,3,0xd7,0xff,0xff};
+static unsigned char ModePage1c[24] = {23,0,0,8,0,0,0,0,0,0,2,0,0x1c,0x0a,0,3,0,0,0,0,0,0,0,1};
+static unsigned char ModePage0DBD[8] = {7,0,0,0,0,0,0,0};
+static unsigned char ModePage1DBD[16] = {15,0,0,0,0x01,0x0a,0xc0,0x08,0x18,0x0a,0,0,0,0,0,0};
+static unsigned char ModePage8DBD[16] = {15,0,0,0,0x18,0x0a,0x04,0,0xff,0xff,0,0,3,0xd7,0xff,0xff};
+static unsigned char ModePage1cDBD[16] = {15,0,0,0,0x1c,0x0a,0,3,0,0,0,0,0,0,0,1};
+//static unsigned char AutoSenseCdb[6] = {3,0,0,0,14,0};
+//========================================================================
+static int adapter_initialize(struct pci_dev *pPciDev)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension;
+	P_ScsiHostData pScsiHostData;
+	struct Scsi_Host *pScsiHost;
+	P_Channel pChannel;
+	P_DeviceInfo pDeviceInfo;
+	unsigned char *pUncachedExtension;
+	dma_addr_t pDmaUncachedExtension;
+	dma_addr_t pDmaCommandTable;
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	unsigned int base_io,base_io1,base_io2;
+	unsigned int signature;
+	int i,j,status;
+	unsigned char statusX;
+
+	status        = 0;
+	pScsiHostData = pci_get_drvdata(pPciDev);
+	pScsiHost     = pScsiHostData->pScsiHost;
+	if (  (WORKINGTABLE_MEM_LEN/sizeof(T_WorkingTable)) < MAX_QUEUE_SUPPORT ) {
+		printk("Queue pool(%d) too small \n\r",(int)(WORKINGTABLE_MEM_LEN / sizeof(T_WorkingTable)) );
+		return -ENOMEM;
+	}
+	//=======================================================================================
+	// allocate memory
+	//=======================================================================================
+	pHwDeviceExtension = (PHW_DEVICE_EXTENSION)__get_free_pages(GFP_ATOMIC,EXTENSION_MEM);
+	if (pHwDeviceExtension == NULL) {
+		printk("adapter_initialize:Unable to pHwDeviceExtension memory.\n\r");
+		return -ENOMEM;
+	}
+	memset(pHwDeviceExtension,0,EXTENSION_MEM_LEN);
+	base_io  = (unsigned int)(pci_resource_start(pPciDev, 0));	// get base IO 
+	base_io  &= 0xFFFFFFFE;
+	base_io1 = (unsigned int)(pci_resource_start(pPciDev, 1));	// get base IO 1
+	base_io1 &= 0xFFFFFFFE;
+	base_io2 = (unsigned int)(pci_resource_start(pPciDev, 2));	// get base IO 2
+	base_io2 &= 0xFFFFFFFE;
+	//=======================================================================================
+	// initialize Device Extension
+	//=======================================================================================
+	pci_read_config_word(pPciDev, 0x00,&(pHwDeviceExtension->VendorID));
+	pci_read_config_word(pPciDev, 0x02,&(pHwDeviceExtension->DeviceID));
+	pci_read_config_word(pPciDev, 0x2C,&(pHwDeviceExtension->SubVendorID));
+	pci_read_config_word(pPciDev, 0x2E,&(pHwDeviceExtension->SubDeviceID));
+	pci_read_config_byte(pPciDev, 0x08,&(pHwDeviceExtension->ChipRevision));
+	pHwDeviceExtension->IrqNum	= pPciDev->irq;
+	pHwDeviceExtension->BaseIoPort0	= base_io;
+	pHwDeviceExtension->BaseIoPort1	= base_io1;
+	pHwDeviceExtension->BaseIoPort2	= base_io2;
+	pHwDeviceExtension->spin_lock	= SPIN_LOCK_UNLOCKED;
+	pHwDeviceExtension->pScsiHost	= pScsiHost;
+	pHwDeviceExtension->pPciDev	= pPciDev;
+	pHwDeviceExtension->pWorkingTablePool = (P_WorkingTable)(((unsigned char *)pHwDeviceExtension)+MEM_4KB);
+	if (AllocateExtensionMemory(pHwDeviceExtension) == 0) {
+		free_pages((unsigned long)pHwDeviceExtension,EXTENSION_MEM);
+		printk("adapter_initialize:Unable to pUncachedExtension memory.\n\r");
+		return -ENOMEM;
+	}
+	pScsiHostData->DeviceExtension   = pHwDeviceExtension;
+	pScsiHostData->szDeviceExtension = EXTENSION_MEM_LEN;
+	//================================================================
+	// register IRQ
+	//================================================================
+	Debug80Port(0xF1,1);
+	if (request_irq(pHwDeviceExtension->IrqNum, adapter_intr_handle,
+				IRQF_SHARED, DRIVER_NAME, pScsiHost)) {
+		printk("adapter_initialize:Unable to allocate IRQ for adapter.\n\r");
+		free_pages((unsigned long)pHwDeviceExtension,EXTENSION_MEM);
+		return -EIO;
+	}
+	Debug80Port(0xF2,1);
+	//================================================================
+	// Initialize host adapter
+	//================================================================
+#if 0
+	if(!request_region(base_io, 0xFF, DRIVER_NAME)) {
+		free_irq(pPciDev->irq,pScsiHost);
+		printk("adapter_initialize:Unable to allocate Base IO region 0.\n\r");
+		return -EIO;
+	}
+#endif
+	if(!request_region(base_io1, 0xFF, DRIVER_NAME)) {
+		free_irq(pPciDev->irq,pScsiHost);
+		release_region(base_io, 0xFF);
+		printk("adapter_initialize:Unable to allocate Base IO region 1.\n\r");
+		return -EIO;
+	}
+	//================================================================
+	// Reset Chip
+	//================================================================
+	outb(0x01,pHwDeviceExtension->BaseIoPort0 + 0x0004);
+	while (inb(pHwDeviceExtension->BaseIoPort0 + 0x0004) & 0x01) {
+		udelay(10);
+		cpu_relax();
+	}
+	//================================================================
+	// Disable INTA#
+	//================================================================
+	outb(0x00,pHwDeviceExtension->BaseIoPort0 + 0x0004);
+	//================================================================
+	// Disable IDE to INTA#
+	//================================================================
+	outb(0x00,pHwDeviceExtension->BaseIoPort0 + 0x0091);
+	//================================================================
+	// Initialize IDE channel 
+	//================================================================
+	pChannel			= &(pHwDeviceExtension->IdeChannel);
+	pChannel->IdePortP1XX	= pHwDeviceExtension->BaseIoPort0+0x0080;
+	pChannel->IdePortP3XX	= pHwDeviceExtension->BaseIoPort0+0x008E;
+	pChannel->IdePortPSFF	= pHwDeviceExtension->BaseIoPort0+0x0090;
+	pChannel->IdeRegPrdTable	= pHwDeviceExtension->BaseIoPort0+0x0098;
+	pChannel->IdeRegSpeed	= pHwDeviceExtension->BaseIoPort0+0x0094;
+	pChannel->QueueCount	= 0;
+	pChannel->FG_SataChannel	= 0;
+	pChannel->MaxDeviceCount	= 2;
+	//============================================
+	// Initialize IDE Master Device
+	//============================================
+	pDeviceInfo		= &(pHwDeviceExtension->DeviceInfo[0]);
+	pDeviceInfo->HD_V1X6	= 0xA0;
+	pDeviceInfo->pChannel	= pChannel;
+	pDeviceInfo->FG_SerialATA	= 0;
+	//============================================
+	// Initialize IDE Slave Device
+	//============================================
+	pDeviceInfo++;
+	pDeviceInfo->HD_V1X6	= 0xB0;
+	pDeviceInfo->pChannel	= pChannel;
+	pDeviceInfo->FG_SerialATA	= 0;
+	//============================================
+	// SCAN IDE PHYSICAL HARD DISK
+	//============================================
+	pDeviceInfo = &(pHwDeviceExtension->DeviceInfo[0]);
+	for (i = 0 ; i < pChannel->MaxDeviceCount ; i++) {
+		ScanATA(pHwDeviceExtension,pDeviceInfo);
+		if (pDeviceInfo->FG_DeviceInstall) {
+			SetChipIo(pDeviceInfo);
+		} else {
+			ScanATAPI(pHwDeviceExtension,pDeviceInfo);
+			if (pDeviceInfo->FG_DeviceInstall) {
+				SetChipIo(pDeviceInfo);
+			}
+		}
+		pDeviceInfo++;
+	}
+	//============================================
+	// Initialize SATA channel 
+	//============================================
+	pChannel   = &(pHwDeviceExtension->SataChannel[0]);
+	pUncachedExtension = pHwDeviceExtension->pUncachedExtension;
+	pDmaUncachedExtension = pHwDeviceExtension->pDmaUncachedExtension;
+	for (i = 0 ; i < MAX_SATA_CHANNEL ; i++) {
+		pChannel->BaseIoPort			= pHwDeviceExtension->BaseIoPort1 + (i * 0x80);
+		pChannel->FG_SataChannel			= 1;
+		pChannel->ChannelOrder			= (unsigned char)(i + 1);
+		pChannel->pCommandPtr			= &(pChannel->CommandPtr);
+		pChannel->pCommandPtr->pCommandHead	= (P_CommandHead)pUncachedExtension;
+		pChannel->pReciveFIS			= (P_ReciveFIS)(pUncachedExtension+MEM_512B);
+		pChannel->pCommandPtr->pCommandTable	= (P_CommandTable)(pHwDeviceExtension->pSataChCmdTable[i]);
+		pChannel->pCommandPtr->pDmaCommandTable	= pHwDeviceExtension->pDmaSataChCmdTable[i];
+		pDmaCommandTable				= pChannel->pCommandPtr->pDmaCommandTable;
+		//============================================
+		// set Command List to chip
+		//============================================
+		outl(pDmaUncachedExtension,pChannel->BaseIoPort);
+		outl(0,pChannel->BaseIoPort + 0x0004);
+		//============================================
+		// set Recived FIS to chip
+		//============================================
+		outl((pDmaUncachedExtension + MEM_512B),pChannel->BaseIoPort + 0x0008);
+		outl(0,pChannel->BaseIoPort + 0x000C);
+		//============================================
+		// initialize SATA channel
+		//============================================
+		outb(0x01,pChannel->BaseIoPort + 0x002C);
+		outb(0x00,pChannel->BaseIoPort + 0x002C);
+		outb(0x04,pChannel->BaseIoPort + 0x0074);
+		outb(0x17,pChannel->BaseIoPort + 0x0018);
+		outl(0,pChannel->BaseIoPort + 0x0014);
+		outl(0xFFFFFFFF,pChannel->BaseIoPort + 0x0030);	// Clear SError(SERR);
+		//============================================
+		// setup Command Table
+		//============================================
+		pCommandHead  =	pChannel->pCommandPtr->pCommandHead;
+		pCommandTable =	pChannel->pCommandPtr->pCommandTable;
+		for (j = 0 ; j <= MAX_COMMAND_QUEUE_CH ; j++) {
+			pCommandHead->CommandFISLen	= 5;
+			pCommandHead->AtapiPioFIS		= 0;
+			pCommandHead->ReadWrite		= 0;
+			pCommandHead->PreFetchAble	= 0;
+			pCommandHead->Reset		= 0;
+			pCommandHead->Bist		= 0;
+			pCommandHead->ClearBusy		= 0;
+			pCommandHead->Reserved0		= 0;
+			pCommandHead->PortMultiplier	= 0;
+			pCommandHead->PRDTL		= 0;
+			pCommandHead->PRD_ByteCount	= 0;
+			pCommandHead->CommandTablePtrU	= 0;
+#if __LITTLE_ENDIAN
+			pCommandHead->CommandTablePtr	= pDmaCommandTable;
+#else
+			pCommandHead->CommandTablePtr	= cpu_to_le32(pDmaCommandTable);
+#endif
+			pCommandHead++;
+			pCommandTable++;
+			pDmaCommandTable += MEM_512B;
+		}
+		pUncachedExtension += MEM_1KB;
+		pDmaUncachedExtension += MEM_1KB;
+		//============================================
+		// Initialize SATA Device
+		//============================================
+		pDeviceInfo = &(pHwDeviceExtension->DeviceInfo[(i * MAX_SATA_HDD) + 2]);
+		for (j = 0 ; j < MAX_SATA_HDD ; j++) {
+			pDeviceInfo->FG_SerialATA		= 1;
+			pDeviceInfo->FG_OnSataChannel	= 1;
+			pDeviceInfo->FG_PMId		= j;
+			pDeviceInfo->pChannel		= pChannel;
+			pDeviceInfo++;
+		}
+		pChannel++;
+	}
+//	for (i = 0 ; i < 800000 ; i++) {
+//		udelay(10);
+//		cpu_relax();
+//	}
+	msleep(5000);
+	//================================
+	// SCAN SATA PHYSICAL HARD DISK
+	//================================
+	for (i = 0 ; i < MAX_SATA_CHANNEL ; i++) {
+		pDeviceInfo = &(pHwDeviceExtension->DeviceInfo[(i * MAX_SATA_HDD) + 2]);
+		pChannel = &(pHwDeviceExtension->SataChannel[i]);
+		pChannel->FG_PortMultiplier = 0;
+		pChannel->MaxDeviceCount	  = 1;
+		// check Port Multiplier
+		for (j = 0 ; j < 300000 ; j++) {
+			statusX = (inb(pChannel->BaseIoPort + 0x0028) & 0x0F);
+			if (statusX == 0x03) {
+				break;
+			}
+			udelay(10);
+		}
+		if (statusX == 0x03) {
+			// physical ready
+			//==========================================================================================
+			// clear BUSY & DRQ bit to release channel
+			//==========================================================================================
+			status = inb(pChannel->BaseIoPort + 0x0018) | 0x08;
+			outb(status,pChannel->BaseIoPort + 0x0018);
+			while(inb(pChannel->BaseIoPort + 0x0018) & 0x08) {
+				udelay(10);
+				cpu_relax();
+			}
+			if (SoftwareReset(pChannel,0x0F)) {
+				signature = inl(pChannel->BaseIoPort + 0x0024);
+				if (signature == 0x96690101) { 
+					// found Port Multiplier
+					pChannel->FG_PortMultiplier = 1;
+					PortMultiplierEnumerate(pHwDeviceExtension,pChannel,pDeviceInfo);
+					outb(0x17,pChannel->BaseIoPort + 0x0018);		// CLEAR BSY & DRQ
+					outl(0x00000109,pChannel->BaseIoPort + 0x0014);	// enable P0IS.NOTIS, P0IS.SDBS, P0IS.DHRS
+					outl(0x11111112,pChannel->BaseIoPort + 0x0074);	// enable PMx D2H & PM bit
+				} else if (signature == 0xEB140101) {
+					// found ATAPI DEVICE
+					SendIdentifyCommand(pHwDeviceExtension,pDeviceInfo,0,0xA1);
+					outb(0x17,pChannel->BaseIoPort + 0x0018);		// CLEAR BSY & DRQ
+					outl(0x00000009,pChannel->BaseIoPort + 0x0014);	// enable P0IS.SDBS, P0IS.DHRS
+					outl(0,pChannel->BaseIoPort + 0x0074);
+				} else if (signature == 0x00000101) {
+					// found ATA DEVICE
+					SendIdentifyCommand(pHwDeviceExtension,pDeviceInfo,0,0xEC);
+					outb(0x17,pChannel->BaseIoPort + 0x0018);		// CLEAR BSY & DRQ
+					outl(0x00000009,pChannel->BaseIoPort + 0x0014);	// enable P0IS.SDBS, P0IS.DHRS
+					outl(0,pChannel->BaseIoPort + 0x0074);
+					statusX = inb(pChannel->BaseIoPort + 0x007A) | 0x77;
+					outb(statusX,pChannel->BaseIoPort + 0x007A);
+				}
+			}
+		}
+		outl(0xFFFFFFFF,pChannel->BaseIoPort + 0x0030);				// clear interrupt
+	}
+	pci_write_config_word(pPciDev, 0x04, 0x0007);		// Set PCI Command Reigster
+	pci_read_config_byte(pPciDev, 0x0D,&statusX);		// Set PCI Latency Timer
+	if (statusX < 0x20) {
+		pci_write_config_byte(pPciDev,0x0D,0xC0);
+	}
+	pHwDeviceExtension->pScsiHost->max_id	= 12;
+	pHwDeviceExtension->pScsiHost->max_channel	= 0;
+	pHwDeviceExtension->pScsiHost->this_id	= 16;
+	pHwDeviceExtension->pScsiHost->n_io_port	= 0x80;
+	//================================================================
+	// enable IDE to INTA#
+	//================================================================
+	outb(0x08,pHwDeviceExtension->BaseIoPort0 + 0x0091);
+	//================================================================
+	// enable INTA
+	//================================================================
+	outb(0x02,pHwDeviceExtension->BaseIoPort0 + 0x0004);
+	//================================================================
+	// start timer
+	//================================================================
+	init_timer(&(pHwDeviceExtension->AdapterTimer));
+	(pHwDeviceExtension->AdapterTimer).data	= (unsigned long)(pHwDeviceExtension);
+	(pHwDeviceExtension->AdapterTimer).function	= adapter_timer;
+	(pHwDeviceExtension->AdapterTimer).expires	= jiffies + TIMER_SCALE;
+	add_timer(&(pHwDeviceExtension->AdapterTimer));
+	Debug80Port(0xF4,1);
+	return 0;
+}
+//========================================================================
+static int AllocateExtensionMemory(PHW_DEVICE_EXTENSION pHwDeviceExtension)
+{
+	unsigned char *pAllocateBuffer;
+	dma_addr_t pDmaAllocateBufferr;
+
+	//=== allocate SATA Channel 1 Command Table========================================
+	pAllocateBuffer = pci_alloc_consistent(pHwDeviceExtension->pPciDev,MEM_4KB,&pDmaAllocateBufferr);
+	if (pAllocateBuffer == NULL) {
+		return 0;
+	}
+	memset(pAllocateBuffer,0,MEM_4KB);
+	pHwDeviceExtension->pSataChCmdTable[0]	= pAllocateBuffer;
+	pHwDeviceExtension->pDmaSataChCmdTable[0]	= pDmaAllocateBufferr;
+	//=== allocate SATA Channel 2 Command Table========================================
+	pAllocateBuffer = pci_alloc_consistent(pHwDeviceExtension->pPciDev,MEM_4KB,&pDmaAllocateBufferr);
+	if (pAllocateBuffer == NULL) {
+		pci_free_consistent(pHwDeviceExtension->pPciDev,
+					MEM_4KB,
+					pHwDeviceExtension->pSataChCmdTable[0],
+					pHwDeviceExtension->pDmaSataChCmdTable[0]);
+		return 0;
+	}
+	memset(pAllocateBuffer,0,MEM_4KB);
+	pHwDeviceExtension->pSataChCmdTable[1]	= pAllocateBuffer;
+	pHwDeviceExtension->pDmaSataChCmdTable[1]	= pDmaAllocateBufferr;
+	//=== allocate Uncache Extension Memory ============================================
+	pAllocateBuffer = pci_alloc_consistent(pHwDeviceExtension->pPciDev,MEM_4KB,&pDmaAllocateBufferr);
+	if (pAllocateBuffer == NULL) {
+		pci_free_consistent(pHwDeviceExtension->pPciDev,
+					MEM_4KB,
+					pHwDeviceExtension->pSataChCmdTable[0],
+					pHwDeviceExtension->pDmaSataChCmdTable[0]);
+		pci_free_consistent(pHwDeviceExtension->pPciDev,
+					MEM_4KB,
+					pHwDeviceExtension->pSataChCmdTable[1],
+					pHwDeviceExtension->pDmaSataChCmdTable[1]);
+		return 0;
+	}
+	memset(pAllocateBuffer,0,MEM_4KB);
+	pHwDeviceExtension->pUncachedExtension	= pAllocateBuffer;
+	pHwDeviceExtension->pDmaUncachedExtension	= pDmaAllocateBufferr;
+	//================================================================================
+	pHwDeviceExtension->pIdentifyBuffer	= pAllocateBuffer + MEM_2KB;
+	pHwDeviceExtension->pDmaIdentifyBuffer	= pDmaAllocateBufferr + MEM_2KB;
+	pHwDeviceExtension->pIdeMailBox		= (P_MailBox)(pAllocateBuffer + MEM_2KB+MEM_512B);
+	pHwDeviceExtension->pDmaIdeMailBox		= pDmaAllocateBufferr + (MEM_2KB+MEM_512B);
+	pHwDeviceExtension->FG_ExtensionAllocate   = 0xFF;
+	return 1;
+}
+//========================================================================
+static void ReleaseExtensionMemory(PHW_DEVICE_EXTENSION pHwDeviceExtension)
+{
+	if (pHwDeviceExtension->FG_ExtensionAllocate) {
+		pci_free_consistent(pHwDeviceExtension->pPciDev,
+					MEM_4KB,
+					pHwDeviceExtension->pSataChCmdTable[0],
+					pHwDeviceExtension->pDmaSataChCmdTable[0]);
+		pci_free_consistent(pHwDeviceExtension->pPciDev,
+					MEM_4KB,
+					pHwDeviceExtension->pSataChCmdTable[1],
+					pHwDeviceExtension->pDmaSataChCmdTable[1]);
+		pci_free_consistent(pHwDeviceExtension->pPciDev,
+					MEM_4KB,
+					pHwDeviceExtension->pUncachedExtension,
+					pHwDeviceExtension->pDmaUncachedExtension);
+	}
+	pHwDeviceExtension->FG_ExtensionAllocate = 0;
+	return;
+}
+//========================================================================
+static void adapter_release_resource(void *pscsihostdata)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension;
+	struct pci_dev *pPciDev;
+	struct Scsi_Host *pScsiHost;
+	P_ScsiHostData pScsiHostData;
+
+	pScsiHostData = (P_ScsiHostData)pscsihostdata;
+	if (pScsiHostData->DeviceExtension != NULL) {
+		pHwDeviceExtension = (PHW_DEVICE_EXTENSION)(pScsiHostData->DeviceExtension);
+		pScsiHost          = pScsiHostData->pScsiHost;
+		pPciDev            = pScsiHostData->pPciDev;
+		//================================================================
+		// stop timer
+		//================================================================
+		pHwDeviceExtension->FG_TimerStop = 1;
+		mDelay(30);
+		del_timer_sync(&(pHwDeviceExtension->AdapterTimer));
+		//================================================================
+		outb(0x00,pHwDeviceExtension->BaseIoPort0 + 0x0004);		// Disable INTA#
+		//================================================================
+		// release Resource
+		//================================================================
+		release_region(pHwDeviceExtension->BaseIoPort0, 0xFF);
+		release_region(pHwDeviceExtension->BaseIoPort1, 0xFF);
+		//================================================================
+		// unregister IRQ
+		//================================================================
+		free_irq(pHwDeviceExtension->IrqNum,pScsiHost);
+		//================================================================
+		// free memory
+		//================================================================
+		ReleaseExtensionMemory(pHwDeviceExtension);
+		free_pages((unsigned long)pHwDeviceExtension,EXTENSION_MEM);
+		pScsiHostData->DeviceExtension   = NULL;
+		pScsiHostData->szDeviceExtension = 0;
+	}
+	return;
+}
+//========================================================================
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+static int adapter_reset(Scsi_Cmnd * pScsiCmd, unsigned int reset_flags)
+#else
+static int adapter_reset(Scsi_Cmnd * pScsiCmd)
+#endif
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension;
+	P_WorkingTable pWorkingTable;
+	P_Channel pChannel;
+	P_DeviceInfo pDeviceInfo;
+	struct Scsi_Host *pScsiHost;
+	unsigned int signature;
+	int i,j;
+	unsigned char status;
+	
+	Debug80Port(0xFA,1);
+	pScsiHost = (struct Scsi_Host *)(pScsiCmd->device->host);
+	pHwDeviceExtension = (PHW_DEVICE_EXTENSION)(((P_ScsiHostData)(pScsiHost->hostdata))->DeviceExtension);
+	//========================================================================
+	// STOP TIMER
+	//========================================================================
+	del_timer_sync(&(pHwDeviceExtension->AdapterTimer));
+	//================================================================
+	// Reset Chip
+	//================================================================
+	outb(0x01,pHwDeviceExtension->BaseIoPort0 + 0x0004);
+	while (inb(pHwDeviceExtension->BaseIoPort0 + 0x0004) & 0x01) {
+		udelay(10);
+		cpu_relax();
+	}
+	//================================================================
+	// Disable INTA#
+	//================================================================
+	outb(0x00,pHwDeviceExtension->BaseIoPort0 + 0x0004);
+	//========================================================================
+	// Clear all request
+	//========================================================================
+	pChannel = &(pHwDeviceExtension->IdeChannel);
+	pChannel->FG_StopIO	= 0;
+	pChannel->pCurRequest	= 0;
+	pChannel->pPendingIO	= 0;
+	pChannel->QueueCount	= 0;
+	pChannel->QueueStartTag	= 0;
+	outb(0,pChannel->IdePortPSFF);		//Stop DMA
+	//===========================================
+	for (j = 0 ; j < MAX_SATA_CHANNEL ; j++) {
+		pChannel = &(pHwDeviceExtension->SataChannel[j]);
+		pChannel->FG_StopIO	= 0;
+		pChannel->FG_ErrD2H	= 0;
+		pChannel->FG_ErrSDB	= 0;
+		pChannel->pCurRequest	= 0;
+		pChannel->pPendingIO	= 0;
+		for (i = 0 ; i <= MAX_COMMAND_QUEUE_CH ; i++) {
+			pChannel->pExecuteIO[i]	= 0;
+		}
+		pChannel->QueueCount	= 0;
+		pChannel->QueueStartTag	= 0;
+		pChannel->FG_ErrPMx	= 0;
+	}
+	pHwDeviceExtension->IoCounter	= 0;
+	//========================================================================
+	// Clear all WorkingTable
+	//========================================================================
+	pWorkingTable = (P_WorkingTable)(pHwDeviceExtension->pWorkingTablePool);
+	for (i = 0 ; i < MAX_QUEUE_SUPPORT ; i++) {
+		pWorkingTable->FG_TableActive = 0;
+		pWorkingTable++;
+	}
+	//============================================
+	// Initialize IDE channel
+	//============================================
+	pDeviceInfo = &(pHwDeviceExtension->DeviceInfo[0]);
+	for (i = 0 ; i < pChannel->MaxDeviceCount ; i++) {
+		ScanATA(pHwDeviceExtension,pDeviceInfo);
+		if (pDeviceInfo->FG_DeviceInstall) {
+			SetChipIo(pDeviceInfo);
+		} else {
+			ScanATAPI(pHwDeviceExtension,pDeviceInfo);
+			if (pDeviceInfo->FG_DeviceInstall) {
+				SetChipIo(pDeviceInfo);
+			}
+		}
+		pDeviceInfo++;
+	}
+	//============================================
+	// Initialize SATA channel 
+	//============================================
+	pChannel   = &(pHwDeviceExtension->SataChannel[0]);
+	for (i = 0 ; i < MAX_SATA_CHANNEL ; i++) {
+		pChannel = &(pHwDeviceExtension->SataChannel[i]);
+		//============================================
+		// initialize SATA channel
+		//============================================
+		outb(0x01,pChannel->BaseIoPort + 0x002C);
+		outb(0x00,pChannel->BaseIoPort + 0x002C);
+		outb(0x04,pChannel->BaseIoPort + 0x0074);
+		outb(0x17,pChannel->BaseIoPort + 0x0018);
+		outl(0,pChannel->BaseIoPort + 0x0014);
+		//============================================
+		outl(0xFFFFFFFF,pChannel->BaseIoPort + 0x0030);	// Clear SError(SERR);
+		pDeviceInfo = &(pHwDeviceExtension->DeviceInfo[(i * MAX_SATA_HDD) + 2]);
+		//============================================
+		// check Port Multiplier
+		if ((inb(pChannel->BaseIoPort + 0x0028) & 0x0F) == 0x03) {
+			// physical ready
+			//==========================================================================================
+			// clear BUSY & DRQ bit to release channel
+			//==========================================================================================
+			status = inb(pChannel->BaseIoPort + 0x0018) | 0x08;
+			outb(status,pChannel->BaseIoPort + 0x0018);
+			while(inb(pChannel->BaseIoPort + 0x0018) & 0x08) {
+				udelay(10);
+				cpu_relax();
+			}
+			if (SoftwareReset(pChannel,0x0F)) {
+				signature = inl(pChannel->BaseIoPort + 0x0024);
+				if (signature == 0x96690101) {
+					// found Port Multiplier
+					pChannel->FG_PortMultiplier = 1;
+					PortMultiplierEnumerate(pHwDeviceExtension,pChannel,pDeviceInfo);
+					outb(0x17,pChannel->BaseIoPort + 0x0018);		// CLEAR BSY & DRQ
+					outl(0x00000109,pChannel->BaseIoPort + 0x0014);	// enable P0IS.NOTIS, P0IS.SDBS, P0IS.DHRS
+					outl(0x11111112,pChannel->BaseIoPort + 0x0074);	// enable PMx D2H & PM bit
+				} else if (signature == 0xEB140101) {
+					// found ATAPI DEVICE
+					SendIdentifyCommand(pHwDeviceExtension,pDeviceInfo,0,0xA1);
+					outb(0x17,pChannel->BaseIoPort + 0x0018);		// CLEAR BSY & DRQ
+					outl(0x00000009,pChannel->BaseIoPort + 0x0014);	// enable P0IS.SDBS, P0IS.DHRS
+					outl(0,pChannel->BaseIoPort + 0x0074);
+				} else if (signature == 0x00000101) {
+					// found ATA DEVICE
+					SendIdentifyCommand(pHwDeviceExtension,pDeviceInfo,0,0xEC);
+					outb(0x17,pChannel->BaseIoPort + 0x0018);		// CLEAR BSY & DRQ
+					outl(0x00000009,pChannel->BaseIoPort + 0x0014);	// enable P0IS.SDBS, P0IS.DHRS
+					outl(0,pChannel->BaseIoPort + 0x0074);
+				}
+			}
+		}
+	}
+	//========================================================================
+	// RESTART TIMER
+	//========================================================================
+	(pHwDeviceExtension->AdapterTimer).expires = jiffies + TIMER_SCALE;
+	add_timer(&(pHwDeviceExtension->AdapterTimer));
+	//========================================================================
+	return STATUS_GOOD;
+}
+static void I2C_READ(void *DeviceExtension,Scsi_Cmnd *pScsiCmd)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	unsigned char status;
+
+	status = inb(pHwDeviceExtension->BaseIoPort0 + 0x00B0);
+	outb(pScsiCmd->cmnd[1],pHwDeviceExtension->BaseIoPort0 + 0x00B1);//start bit	
+	outb((status|STA|RD|IFM),pHwDeviceExtension->BaseIoPort0 + 0x00B0);//start bit	
+	pHwDeviceExtension->pScsiCmd = pScsiCmd;
+	pHwDeviceExtension->I2C_STEP = R_F2;	
+}
+//===================================================================================
+static int adapter_queuecommand(Scsi_Cmnd *pScsiCmd, void (*done) (Scsi_Cmnd *))
+{
+	struct Scsi_Host *pScsiHost;
+	struct scatterlist *sg_list;
+	PHW_DEVICE_EXTENSION pHwDeviceExtension;
+	P_Channel pChannel;
+	P_DeviceInfo pDeviceInfo;
+	PUINQUIRYDATA pInquiryBuff;
+	P_WorkingTable pWorkingTable;
+	unsigned char *km_buffer;
+	unsigned long km_flags,len,flags;
+	unsigned char temp_buffer[250];
+	int i,j;
+
+	pScsiHost = (struct Scsi_Host *)(pScsiCmd->device->host);
+	pHwDeviceExtension = (PHW_DEVICE_EXTENSION)(((P_ScsiHostData)(pScsiHost->hostdata))->DeviceExtension);
+	if (	  (pScsiCmd->device->lun > 0)			// only support lun0
+		 ||(pScsiCmd->device->id >= MAXTARGETHDD )
+	   ) {
+		if((pScsiCmd->device->lun == 7) && (pScsiCmd->device->id ==0)){
+			pScsiCmd->scsi_done = done;
+		//	pScsiCmd->result = SAM_STAT_GOOD;
+			pScsiCmd->result = STATUS_PENDING;
+			switch (pScsiCmd->cmnd[0]){
+				case I2C_CMD_READ:
+					I2C_READ(pHwDeviceExtension,pScsiCmd);
+				case I2C_CMD_WRITE:
+//					I2C_WRITE(pHwDeviceExtension,pScsiCmd);
+				default:
+					pScsiCmd->result = STATUS_NO_DEVICE;
+					done(pScsiCmd);
+					
+			}
+			//I2C DRIVER 
+		}else{
+			pScsiCmd->result = STATUS_NO_DEVICE;
+			done(pScsiCmd);
+			return 0;
+		}
+	}
+	pScsiCmd->result = SAM_STAT_GOOD;
+	pDeviceInfo = &(pHwDeviceExtension->DeviceInfo[pScsiCmd->device->id]);
+	if (pDeviceInfo->FG_DeviceInstall == 0) {
+		pScsiCmd->result = STATUS_NO_DEVICE;
+		done(pScsiCmd);
+	} else {
+	//	printk("adapter_queuecommand cmd %x\n",pScsiCmd->cmnd[0]);
+#ifdef KERNEL_V2625
+		sg_list = scsi_sglist(pScsiCmd);
+		len	= scsi_bufflen(pScsiCmd);
+	//	printk("sglist %x len %x\n",(unsigned long)sg_list,len);
+#else
+		sg_list = (struct scatterlist *)(pScsiCmd->request_buffer);
+		len = pScsiCmd->request_bufflen;
+#endif
+		pChannel = pDeviceInfo->pChannel;
+		
+		if (len > 250) {
+			len = 250;
+		}
+		memset(temp_buffer,0,sizeof(temp_buffer));
+		if (pDeviceInfo->FG_AtapiDevice == 0) {
+			// Hard Disk (ATA Device)
+			switch (pScsiCmd->cmnd[0]) {
+			case INQUIRY:
+				temp_buffer[2] = 0x02;
+				temp_buffer[3] = 0x02;
+				temp_buffer[4] = 0x7d;
+				temp_buffer[7] = 0x30;
+				pInquiryBuff   = (PUINQUIRYDATA)(temp_buffer);
+				if (	  ((pDeviceInfo->ModelName[0] == 'S') || (pDeviceInfo->ModelName[0] == 's'))
+					&&((pDeviceInfo->ModelName[1] == 'T') || (pDeviceInfo->ModelName[1] == 't'))
+				   ) {
+					memcpy(pInquiryBuff->VendorId,"Seagate ",8);
+					// set Product name string
+					for (i = 0 ; i < 16 ; i++) {
+						pInquiryBuff->ProductId[i]	= pDeviceInfo->ModelName[i];
+					}
+				} else if (  ((pDeviceInfo->ModelName[0] == 'H') || (pDeviceInfo->ModelName[0] == 'I'))
+					  &&((pDeviceInfo->ModelName[1] == 'D') || (pDeviceInfo->ModelName[1] == 'C'))
+					  ) {
+					memcpy(pInquiryBuff->VendorId,"Hitachi ",8);
+					// set Product name string
+					for (i = 0 ; i < 16 ; i++) {
+						pInquiryBuff->ProductId[i]	= pDeviceInfo->ModelName[i];
+					}
+				} else if (  ((pDeviceInfo->ModelName[0] == 'M') || (pDeviceInfo->ModelName[0] == 'M'))
+					  &&((pDeviceInfo->ModelName[1] == 'a') || (pDeviceInfo->ModelName[1] == 'A'))
+					  ) {
+					memcpy(pInquiryBuff->VendorId,"Maxtor  ",8);
+					// set Product name string
+					for (i = 0 ; i < 16 ; i++) {
+						pInquiryBuff->ProductId[i]	= pDeviceInfo->ModelName[i+7];
+					}
+				} else if (  ((pDeviceInfo->ModelName[0] == 'W') || (pDeviceInfo->ModelName[0] == 'w'))
+					  &&((pDeviceInfo->ModelName[1] == 'D') || (pDeviceInfo->ModelName[1] == 'd'))
+					  &&((pDeviceInfo->ModelName[2] == 'C') || (pDeviceInfo->ModelName[1] == 'c'))
+					  ) {
+					memcpy(pInquiryBuff->VendorId,"WDC     ",8);
+					// set Product name string
+					for (i = 0 ; i < 16 ; i++) {
+						pInquiryBuff->ProductId[i]	= pDeviceInfo->ModelName[i+4];
+					}
+				} else {
+					for (i = 0 ; i < 8 ; i++) {
+						pInquiryBuff->VendorId[i] = pDeviceInfo->ModelName[i];
+					}
+					// set Product name string
+					for (i = 0 ; i < 16 ; i++) {
+						pInquiryBuff->ProductId[i]	= pDeviceInfo->ModelName[i+8];
+					}
+				}
+				// set Product Revision string
+				for	(i = 0 ; i < 4 ; i++) {
+					pInquiryBuff->ProductRevisionLevel[i] = pDeviceInfo->FirmWareRev[i];
+				}
+				for (i = 0 ; i < 19 ; i++) {
+					pInquiryBuff->VendorSpecific[i] = pDeviceInfo->SerialNo[i];
+				}
+				break;
+			case READ_CAPACITY:
+				i =  ((pDeviceInfo->Capacity).U64L).U64L_L - 1;
+				// Max. LBA
+				temp_buffer[0] = (unsigned char)(i >> 24);
+				temp_buffer[1] = (unsigned char)(i >> 16);
+				temp_buffer[2] = (unsigned char)(i >> 8);
+				temp_buffer[3] = (unsigned char)i;
+				// set block size
+				temp_buffer[4] = 0x00;
+				temp_buffer[5] = 0x00;
+				temp_buffer[6] = 0x02;
+				temp_buffer[7] = 0x00;
+				break;
+			case REQUEST_SENSE:	// request sense
+				temp_buffer[0]  = 0x70;
+				temp_buffer[2]  = pDeviceInfo->SenseKey;
+				temp_buffer[12] = pDeviceInfo->SenseAsc;
+				temp_buffer[13] = pDeviceInfo->SenseAscQ;
+				pDeviceInfo->SenseKey  = 0;
+				pDeviceInfo->SenseAsc  = 0;
+				pDeviceInfo->SenseAscQ = 0;
+				break;
+			case MODE_SENSE:		// mode sense 6
+//	printk("CDB = %02X %02X %02X %02X %02X %02X\n",pScsiCmd->cmnd[0],pScsiCmd->cmnd[1],pScsiCmd->cmnd[2],pScsiCmd->cmnd[3],pScsiCmd->cmnd[4],pScsiCmd->cmnd[5]);
+				i =  ((pDeviceInfo->Capacity).U64L).U64L_L;
+				switch (pScsiCmd->cmnd[2] & 0x3F) {
+				case 0x00:
+					if (pScsiCmd->cmnd[1] & 0x08) { 
+						// DBD = 1
+						memcpy(temp_buffer,ModePage0DBD,sizeof(ModePage0DBD));
+					} else {
+						memcpy(temp_buffer,ModePage0,sizeof(ModePage0));
+						temp_buffer[4] = (unsigned char)(i>>24);
+						temp_buffer[5] = (unsigned char)(i>>16);
+						temp_buffer[6] = (unsigned char)(i>>8);
+						temp_buffer[7] = (unsigned char)i;
+					}
+					break;
+				case 0x01:
+					if (pScsiCmd->cmnd[1] & 0x08) {
+						// DBD = 1
+						memcpy(temp_buffer,ModePage1DBD,sizeof(ModePage1DBD));
+					} else {
+						memcpy(temp_buffer,ModePage1,sizeof(ModePage1));
+						temp_buffer[4] = (unsigned char)(i>>24);
+						temp_buffer[5] = (unsigned char)(i>>16);
+						temp_buffer[6] = (unsigned char)(i>>8);
+						temp_buffer[7] = (unsigned char)i;
+					}
+					break;
+				case 0x08:
+					if (pScsiCmd->cmnd[1] & 0x08) {
+						// DBD = 1
+						memcpy(temp_buffer,ModePage8DBD,sizeof(ModePage8DBD));
+					} else {
+						memcpy(temp_buffer,ModePage8,sizeof(ModePage8));
+						temp_buffer[4] = (unsigned char)(i>>24);
+						temp_buffer[5] = (unsigned char)(i>>16);
+						temp_buffer[6] = (unsigned char)(i>>8);
+						temp_buffer[7] = (unsigned char)i;
+					}
+					break;
+				case 0x1C:
+					if (pScsiCmd->cmnd[1] & 0x08) {
+						// DBD = 1
+						memcpy(temp_buffer,ModePage1cDBD,sizeof(ModePage1cDBD));
+					} else {
+						memcpy(temp_buffer,ModePage1c,sizeof(ModePage1c));
+						temp_buffer[4] = (unsigned char)(i>>24);
+						temp_buffer[5] = (unsigned char)(i>>16);
+						temp_buffer[6] = (unsigned char)(i>>8);
+						temp_buffer[7] = (unsigned char)i;
+					}
+					break;
+				case 0x3F:
+					if (pScsiCmd->cmnd[1] & 0x08) {
+						// DBD = 1
+						memcpy(&(temp_buffer[4]),&(ModePage1[12]),12);
+						memcpy(&(temp_buffer[16]),&(ModePage8[12]),12);
+						memcpy(&(temp_buffer[28]),&(ModePage1c[12]),12);
+						memcpy(&(temp_buffer[40]),&(ModePage0[12]),4);
+						temp_buffer[0] = 40;
+					} else {
+						memcpy(&(temp_buffer[0]),&(ModePage1[0]),24);
+						memcpy(&(temp_buffer[24]),&(ModePage8[12]),12);
+						memcpy(&(temp_buffer[36]),&(ModePage1c[12]),12);
+						memcpy(&(temp_buffer[48]),&(ModePage0[12]),4);
+						temp_buffer[0] = 52;
+						temp_buffer[4] = (unsigned char)(i>>24);
+						temp_buffer[5] = (unsigned char)(i>>16);
+						temp_buffer[6] = (unsigned char)(i>>8);
+						temp_buffer[7] = (unsigned char)i;
+					}
+					break;
+				default:
+					pDeviceInfo->SenseKey  = ILLEGAL_REQUEST;
+					pDeviceInfo->SenseAsc  = 0x24;
+					pDeviceInfo->SenseAscQ = 0x00;
+					pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+					break;
+				}
+				break;
+			case ALLOW_MEDIUM_REMOVAL:
+			case MODE_SELECT:
+			case TEST_UNIT_READY:
+			case START_STOP:
+			case SEEK_6:
+			case SEEK_10:
+			case SYNCHRONIZE_CACHE:
+				len = 0;
+				break;		
+			case VERIFY:
+			case READ_6:	// read
+			case READ_10:
+			case READ_12:
+			case READ_16:
+			case WRITE_6:	// write
+			case WRITE_10:
+			case WRITE_12:
+			case WRITE_16:
+				spin_lock_irqsave(&(pHwDeviceExtension->spin_lock),flags);
+				pWorkingTable = AllocateWorkingTable(pHwDeviceExtension);
+				if (pWorkingTable) {
+					pWorkingTable->FG_Updata		= 0;
+					pWorkingTable->FG_NonData		= 0;
+					pWorkingTable->pDevice			= pDeviceInfo;
+					pWorkingTable->pWorkingScsiCmd		= pScsiCmd;
+					pWorkingTable->IoTagID			= pHwDeviceExtension->IoTagID;
+#ifdef KERNEL_V2625
+					pWorkingTable->request_buffer		= scsi_sglist(pScsiCmd);
+					pWorkingTable->request_bufflen		= scsi_bufflen(pScsiCmd);
+					pWorkingTable->use_sg			= scsi_sg_count(pScsiCmd);//This version always use use_sg
+#else
+					pWorkingTable->request_buffer		= pScsiCmd->request_buffer;
+					pWorkingTable->request_bufflen		= pScsiCmd->request_bufflen;
+					pWorkingTable->use_sg			= pScsiCmd->use_sg;
+#endif
+					switch(pScsiCmd->cmnd[0]) {
+						case READ_6:
+						case WRITE_6:
+							((pWorkingTable->StartLBA).U64L).U64L_H = 0;
+							((pWorkingTable->StartLBA).U64L).U64L_L =
+								(((((unsigned int)pScsiCmd->cmnd[1])<<16) & 0x000F0000)+
+								((((unsigned int)pScsiCmd->cmnd[2])<<8)  & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[3]))     & 0x000000FF));
+							((pWorkingTable->TransferLen).U64L).U64L_H = 0;
+							((pWorkingTable->TransferLen).U64L).U64L_L =
+									(((unsigned int)pScsiCmd->cmnd[4]) & 0x000000FF);
+							break;
+						case READ_10:
+						case WRITE_10:						
+							((pWorkingTable->StartLBA).U64L).U64L_H = 0;
+							((pWorkingTable->StartLBA).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[2])<<24) & 0xFF000000)+
+								((((unsigned int)pScsiCmd->cmnd[3])<<16) & 0x00FF0000)+
+								((((unsigned int)pScsiCmd->cmnd[4])<<8) & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[5])) & 0x000000FF);
+							((pWorkingTable->TransferLen).U64L).U64L_H = 0;
+							((pWorkingTable->TransferLen).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[7])<<8) & 0x0000FF00) +
+								((((unsigned int)pScsiCmd->cmnd[8])) & 0x000000FF);
+							break;
+						case READ_12:
+						case WRITE_12:
+							((pWorkingTable->StartLBA).U64L).U64L_H = 0;
+							((pWorkingTable->StartLBA).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[2])<<24) & 0xFF000000)+
+								((((unsigned int)pScsiCmd->cmnd[3])<<16) & 0x00FF0000)+
+								((((unsigned int)pScsiCmd->cmnd[4])<<8) & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[5]))    & 0x000000FF);
+							((pWorkingTable->TransferLen).U64L).U64L_H = 0;
+							((pWorkingTable->TransferLen).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[6])<<24) & 0xFF000000)+
+								((((unsigned int)pScsiCmd->cmnd[7])<<16) & 0x00FF0000)+
+								((((unsigned int)pScsiCmd->cmnd[8])<<8) & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[9]))    & 0x000000FF);
+							break;
+						case READ_16:
+						case WRITE_16:
+							((pWorkingTable->StartLBA).U64L).U64L_H =
+									((((unsigned int)pScsiCmd->cmnd[2])<<24) & 0xFF000000)+
+								((((unsigned int)pScsiCmd->cmnd[3])<<16) & 0x00FF0000)+
+								((((unsigned int)pScsiCmd->cmnd[4])<<8) & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[5]))    & 0x000000FF);
+							((pWorkingTable->StartLBA).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[6])<<24) & 0xFF000000)+
+								((((unsigned int)pScsiCmd->cmnd[7])<<16) & 0x00FF0000)+
+								((((unsigned int)pScsiCmd->cmnd[8])<<8) & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[9]))    & 0x000000FF);
+							((pWorkingTable->TransferLen).U64L).U64L_H = 0;
+							((pWorkingTable->TransferLen).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[10])<<24) & 0xFF000000)+
+								((((unsigned int)pScsiCmd->cmnd[11])<<16) & 0x00FF0000)+
+								((((unsigned int)pScsiCmd->cmnd[12])<<8) & 0x0000FF00)+
+								((((unsigned int)pScsiCmd->cmnd[13]))    & 0x000000FF);
+							break;						
+					}
+					((pWorkingTable->StartLBAOrg).U64L).U64L_H =
+								((pWorkingTable->StartLBA).U64L).U64L_H;
+					((pWorkingTable->StartLBAOrg).U64L).U64L_L =
+								((pWorkingTable->StartLBA).U64L).U64L_L;
+					((pWorkingTable->TransferLenOrg).U64L).U64L_H =
+								((pWorkingTable->TransferLen).U64L).U64L_H;
+					((pWorkingTable->TransferLenOrg).U64L).U64L_L =
+								((pWorkingTable->TransferLen).U64L).U64L_L;
+					ConvertCommandATA(pWorkingTable);
+					pHwDeviceExtension->IoTagID++;
+					if (pDeviceInfo->pChannel->FG_SataChannel) {
+						// SATA IO
+						if (pDeviceInfo->QueueCount >= pDeviceInfo->MaxQueueDepth) {
+							pScsiCmd->result = STATUS_BUSY;
+							ReleaseWorkingTable(pWorkingTable);
+						} else {
+							pScsiCmd->result = STATUS_PENDING;
+							pChannel = pDeviceInfo->pChannel;
+							if (pChannel->pPendingIO) {
+								// there are pending IO in Task Queue
+								ChannelIoHook(pWorkingTable);
+							} else {
+								if (pDeviceInfo->FG_QueueSupported) {
+									if (pChannel->FG_StopIO) {
+										ChannelIoHook(pWorkingTable);
+									} else {
+										if (pChannel->QueueCount >= MAX_COMMAND_QUEUE_CH) {
+											ChannelIoHook(pWorkingTable);
+										} else {
+											j = (int)(pChannel->QueueStartTag);
+											for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+												if (pChannel->pExecuteIO[j] == 0) {
+													// found empty Queue tag
+													break;
+												}
+												if ( ++j >= MAX_COMMAND_QUEUE_CH) {
+													j = 0;
+												}
+											}
+											if (i >= MAX_COMMAND_QUEUE_CH) {
+												ChannelIoHook(pWorkingTable);
+											} else {
+												pChannel->pExecuteIO[j] = pWorkingTable;
+												pWorkingTable->TagID   = (unsigned char)j;
+												if ( ++j >= MAX_COMMAND_QUEUE_CH) {
+													j = 0;
+												}
+												pChannel->QueueStartTag = (unsigned char)j;
+												ExecuteSataATA(pHwDeviceExtension,pWorkingTable);
+											}
+										}
+									}
+								} else {
+									for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+										if (pChannel->pExecuteIO[i] != 0) {
+											// found a executing IO
+											break;
+										}
+									}
+									if ((i < MAX_COMMAND_QUEUE_CH) || (pChannel->FG_StopIO)) {
+										// channel have IO in process
+										ChannelIoHook(pWorkingTable);
+									} else {
+										// send IO to Device
+										pChannel->pExecuteIO[0]	= pWorkingTable;
+										pWorkingTable->TagID	= 0;
+										pChannel->FG_StopIO	= 1;
+										ExecuteSataATA(pHwDeviceExtension,pWorkingTable);
+									}
+								}
+							}
+							if (pScsiCmd->result != STATUS_PENDING) {
+								pChannel->pExecuteIO[pWorkingTable->TagID] = 0;
+								ReleaseWorkingTable(pWorkingTable);
+							} else {
+								pChannel->QueueCount++;
+								pDeviceInfo->QueueCount++;
+							}
+						}
+					} else {
+						// IDE IO
+						pScsiCmd->result = STATUS_PENDING;
+						if (pChannel->pPendingIO) {
+							// there are pending IO in Task Queue
+							ChannelIoHook(pWorkingTable);
+						} else {
+							if (pChannel->pCurRequest) {
+								ChannelIoHook(pWorkingTable);
+							} else {
+								pChannel->pCurRequest = pWorkingTable;
+								ExecuteIdeATA(pHwDeviceExtension,pChannel);
+							}
+						}
+						if (pScsiCmd->result != STATUS_PENDING) {
+							ReleaseWorkingTable(pWorkingTable);
+							pChannel->pCurRequest = 0;
+						} else {
+							pChannel->QueueCount++;
+							pDeviceInfo->QueueCount++;
+						}
+					}
+				} else {
+					pScsiCmd->result = STATUS_BUSY;
+				}
+				spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+				len = 0;
+				break;
+			case Updata_NonData:
+			case Fireware_ReadBuffer:
+			case Fireware_WriteBuffer:
+				spin_lock_irqsave(&(pHwDeviceExtension->spin_lock),flags);
+				pWorkingTable = AllocateWorkingTable(pHwDeviceExtension);
+				if (pWorkingTable) {
+					pWorkingTable->FG_Updata		= 1;
+					pWorkingTable->FG_NonData		= 0;
+					pWorkingTable->pDevice			= pDeviceInfo;
+					pWorkingTable->pWorkingScsiCmd		= pScsiCmd;
+					pWorkingTable->IoTagID			= pHwDeviceExtension->IoTagID;
+#ifdef KERNEL_V2625
+					pWorkingTable->request_buffer		= scsi_sglist(pScsiCmd);
+					pWorkingTable->request_bufflen		= scsi_bufflen(pScsiCmd);
+					pWorkingTable->use_sg			= scsi_sg_count(pScsiCmd);//This version always use use_sg
+#else
+					pWorkingTable->request_buffer		= pScsiCmd->request_buffer;
+					pWorkingTable->request_bufflen		= pScsiCmd->request_bufflen;
+					pWorkingTable->use_sg			= pScsiCmd->use_sg;
+#endif
+/*
+					switch(pScsiCmd->cmnd[0]) {						
+						case Fireware_ReadBuffer:
+						case Fireware_WriteBuffer:						
+							((pWorkingTable->StartLBA).U64L).U64L_H = 0;
+							((pWorkingTable->StartLBA).U64L).U64L_L = 0;								
+							((pWorkingTable->TransferLen).U64L).U64L_H = 0;
+							((pWorkingTable->TransferLen).U64L).U64L_L =
+								((((unsigned int)pScsiCmd->cmnd[7])<<8) & 0x0000FF00) +
+								((((unsigned int)pScsiCmd->cmnd[8])) & 0x000000FF);
+							break;
+						case Updata_NonData:
+							break;
+*/					
+				//	((pWorkingTable->StartLBAOrg).U64L).U64L_H =
+				//				((pWorkingTable->StartLBA).U64L).U64L_H;
+				//	((pWorkingTable->StartLBAOrg).U64L).U64L_L =
+				//				((pWorkingTable->StartLBA).U64L).U64L_L;
+				//	((pWorkingTable->TransferLenOrg).U64L).U64L_H =
+				//				((pWorkingTable->TransferLen).U64L).U64L_H;
+				//	((pWorkingTable->TransferLenOrg).U64L).U64L_L =
+				//				((pWorkingTable->TransferLen).U64L).U64L_L;
+				//	ConvertCommandATA(pWorkingTable);
+					pHwDeviceExtension->IoTagID++;
+					if (pDeviceInfo->pChannel->FG_SataChannel) {
+						// SATA IO
+						if (pDeviceInfo->QueueCount >= pDeviceInfo->MaxQueueDepth) {
+							pScsiCmd->result = STATUS_BUSY;
+							ReleaseWorkingTable(pWorkingTable);
+						} else {
+							pScsiCmd->result = STATUS_PENDING;
+							pChannel = pDeviceInfo->pChannel;
+							if (pChannel->pPendingIO) {
+								// there are pending IO in Task Queue
+								ChannelIoHook(pWorkingTable);							
+							} else {								
+									for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+										if (pChannel->pExecuteIO[i] != 0) {
+											// found a executing IO
+											break;
+										}
+									}
+									if ((i < MAX_COMMAND_QUEUE_CH) || (pChannel->FG_StopIO)) {
+										// channel have IO in process
+										ChannelIoHook(pWorkingTable);
+									} else {
+										// send IO to Device
+										pChannel->pExecuteIO[0]	= pWorkingTable;
+										pWorkingTable->TagID	= 0;
+										pChannel->FG_StopIO	= 1;
+										ExecuteUpdata(pHwDeviceExtension,pWorkingTable);
+									}
+								}
+							}
+							if (pScsiCmd->result != STATUS_PENDING) {
+								pChannel->pExecuteIO[pWorkingTable->TagID] = 0;
+								ReleaseWorkingTable(pWorkingTable);
+							} else {
+								pChannel->QueueCount++;
+								pDeviceInfo->QueueCount++;
+							}
+						}					 
+				} else {
+					pScsiCmd->result = STATUS_BUSY;
+				}
+				spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+				len = 0;
+				break;
+			default:
+				pDeviceInfo->SenseKey  = ILLEGAL_REQUEST;
+				pDeviceInfo->SenseAsc  = 0x20;
+				pDeviceInfo->SenseAscQ = 0x00;
+				pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+				break;
+			}
+
+			if ( (scsi_sg_count(pScsiCmd)) && (len > 0) ) {
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+				memcpy(sg_list->address,temp_buffer,len);
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_USER0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_USER0) + sg_list->offset;
+				memcpy(km_buffer,temp_buffer,len);
+				kunmap_atomic(km_buffer - sg_list->offset,KM_USER0);
+				local_irq_restore(km_flags);
+#endif
+			}
+#ifdef KERNEL_V2625
+			
+#else
+			else {
+				memcpy(pScsiCmd->request_buffer,temp_buffer,len);
+			}
+#endif
+			if (pScsiCmd->result != STATUS_PENDING) {
+				done(pScsiCmd);
+			} else {
+				pScsiCmd->scsi_done = done;
+			}
+		} else {
+			// CD/DVD (ATAPI Device)
+			if (  (pScsiCmd->cmnd[0] == REQUEST_SENSE) 
+			   && (pDeviceInfo->FG_InternalError)  ) {
+				if (len > 14) {
+					len = 14;
+				}
+				memset(temp_buffer,0,len);
+				temp_buffer[0]  = 0x70;
+				temp_buffer[2]  = pDeviceInfo->SenseKey;
+				temp_buffer[12] = pDeviceInfo->SenseAsc;
+				temp_buffer[13] = pDeviceInfo->SenseAscQ;
+
+				if ( (scsi_sg_count(pScsiCmd)) && (len > 0) ) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+					memcpy(sg_list->address,temp_buffer,len);
+#else
+					local_irq_save(km_flags);
+					km_buffer = kmap_atomic(sg_page(sg_list),KM_USER0) + sg_list->offset;
+//					km_buffer = kmap_atomic(sg_list->page,KM_USER0) + sg_list->offset;
+					memcpy(km_buffer,temp_buffer,len);
+					kunmap_atomic(km_buffer - sg_list->offset,KM_USER0);
+					local_irq_restore(km_flags);
+#endif
+				} else {
+					
+#ifndef KERNEL_V2625
+					memcpy(pScsiCmd->request_buffer,temp_buffer,len);
+#endif
+				}
+				pDeviceInfo->FG_InternalError = 0;
+				pDeviceInfo->SenseKey  = 0;
+				pDeviceInfo->SenseAsc  = 0;
+				pDeviceInfo->SenseAscQ = 0;
+			} else {
+				spin_lock_irqsave(&(pHwDeviceExtension->spin_lock),flags);
+				pWorkingTable = AllocateWorkingTable(pHwDeviceExtension);
+				if (pWorkingTable) {
+					pWorkingTable->FG_Updata	= 0;
+					pWorkingTable->FG_NonData	= 0;
+					pWorkingTable->pDevice		= pDeviceInfo;
+					pWorkingTable->pWorkingScsiCmd	= pScsiCmd;
+					pWorkingTable->IoTagID		= pHwDeviceExtension->IoTagID;
+#ifdef KERNEL_V2625
+					pWorkingTable->request_buffer		= scsi_sglist(pScsiCmd);
+					pWorkingTable->request_bufflen		= scsi_bufflen(pScsiCmd);
+					pWorkingTable->use_sg			= scsi_sg_count(pScsiCmd);//This version always use use_sg
+#else
+					pWorkingTable->request_buffer		= pScsiCmd->request_buffer;
+					pWorkingTable->request_bufflen		= pScsiCmd->request_bufflen;
+					pWorkingTable->use_sg			= pScsiCmd->use_sg;
+#endif
+//					pWorkingTable->pDataBufPtr	= vbuf;
+					if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+						pWorkingTable->pDataBufPtr = sg_list->address;
+#else
+						pWorkingTable->pDataBufPtr = 0;
+#endif
+					} else {
+						pWorkingTable->pDataBufPtr = pWorkingTable->request_buffer;
+					}
+					pWorkingTable->DataCounter = pWorkingTable->request_bufflen;
+					pScsiCmd->result = STATUS_PENDING;
+					pHwDeviceExtension->IoTagID++;
+					if (pDeviceInfo->pChannel->FG_SataChannel) {
+						// SATA IO
+						pScsiCmd->result = STATUS_PENDING;
+						pChannel = pDeviceInfo->pChannel;
+						if (pChannel->pPendingIO != 0) {
+							// there are pending IO in Task Queue
+							ChannelIoHook(pWorkingTable);
+						} else {
+							for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+								if (pChannel->pExecuteIO[i] != 0) {
+									// found a executing IO
+									break;
+								}
+							}
+							if (i < MAX_COMMAND_QUEUE_CH) {
+								// channel have IO in process
+								pChannel->pPendingIO = pWorkingTable;
+							} else {
+								// send IO to Device
+								pChannel->pExecuteIO[0] = pWorkingTable;
+								pWorkingTable->TagID = 0;
+								pChannel->FG_StopIO = 1;
+								ExecuteSataATAPI(pHwDeviceExtension,pWorkingTable);
+							}
+						}
+						pChannel->QueueCount++;
+						pDeviceInfo->QueueCount++;
+					} else {
+						// IDE IO
+						pScsiCmd->result = STATUS_PENDING;
+						if (pChannel->pPendingIO != 0) {
+							// there are pending IO in Task Queue
+							ChannelIoHook(pWorkingTable);
+						} else {
+							if (pChannel->pCurRequest) {
+								ChannelIoHook(pWorkingTable);
+							} else {
+								pChannel->pCurRequest = pWorkingTable;
+								ExecuteIdeATAPI(pHwDeviceExtension,pChannel);
+							}
+						}
+					}
+				} else {
+					pScsiCmd->result = STATUS_BUSY;
+				}
+				spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+			}
+			if (pScsiCmd->result != STATUS_PENDING) {
+				done(pScsiCmd);
+			} else {
+				pScsiCmd->scsi_done = done;
+			}
+		}
+	}
+	return 0;
+}
+//========================================================================
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+static void adapter_intr_handle(int irq, void *dev_id, struct pt_regs *regs)
+#else
+static irqreturn_t adapter_intr_handle(int irq, void *dev_id)
+#endif
+{
+	struct Scsi_Host *pScsiHost;
+	PHW_DEVICE_EXTENSION pHwDeviceExtension;
+	P_Channel pIdeChannel,pSataChannel;
+	P_WorkingTable pWorkingTable,pWorkingTable1;
+	P_DeviceInfo pIdeDevice,pSataDevice;
+	P_ReciveFIS pReciveFIS;
+	Scsi_Cmnd *pScsiCmd,*pScsiCmdX;
+	struct scatterlist *sg_list;
+	PUINQUIRYDATA pInquirybuf;
+	unsigned char *pBuf,*km_buffer;
+	unsigned char *SrbDataBuffer;
+	unsigned char *SrbExtOriginalBuffer;
+	unsigned long flags,km_flags;
+	unsigned int D2H_status,interrupt_status;
+	unsigned int CompleteMap,CompleteMapSDBFG,cancel_ci;
+	unsigned short BlockLen;
+	int i,j,km_sg_used;
+	unsigned short int_status,word;
+	unsigned char status,PortMultiplier;
+	unsigned char temp[5],len;
+
+	km_buffer = NULL;
+	km_flags = 0;
+	pScsiHost = (struct Scsi_Host *)dev_id;
+	pHwDeviceExtension = (PHW_DEVICE_EXTENSION)(((P_ScsiHostData)(pScsiHost->hostdata))->DeviceExtension);
+	spin_lock_irqsave(&(pHwDeviceExtension->spin_lock),flags);
+	if (inb(pHwDeviceExtension->BaseIoPort0 + 0x0B) & 0x40) {
+		pScsiCmd = 	pHwDeviceExtension->pScsiCmd;
+		status = inb(pHwDeviceExtension->BaseIoPort0 + 0x00B0);
+		switch (pHwDeviceExtension->I2C_STEP){	
+			case R_F2:	
+				outb(0x40,pHwDeviceExtension->BaseIoPort0 + 0x0b);	
+				outb(pScsiCmd->cmnd[2],pHwDeviceExtension->BaseIoPort0 + 0x00B1);//register addr	
+				outb((status|WR|IFM),pHwDeviceExtension->BaseIoPort0 + 0x00B0);	//clear intr				
+				pHwDeviceExtension->I2C_STEP = R_F3;
+				break;
+			case R_F3:
+				outb(0x40,pHwDeviceExtension->BaseIoPort0 + 0x0b);//clear intr
+				outb(pScsiCmd->cmnd[1],pHwDeviceExtension->BaseIoPort0 + 0x00B1);//device id	
+				outb((status|WR|IFM),pHwDeviceExtension->BaseIoPort0 + 0x00B0);
+				pHwDeviceExtension->I2C_STEP = R_F4;
+				break;
+			case R_F4:
+				outb(0x40,pHwDeviceExtension->BaseIoPort0 + 0x0b);//clear intr
+				outb((status|RD|IFM),pHwDeviceExtension->BaseIoPort0 + 0x00B0);
+				pHwDeviceExtension->I2C_STEP = R_F5;
+				break;
+			case R_F5:
+				len = 8;
+				outb(0x40,pHwDeviceExtension->BaseIoPort0 + 0x0b);//clear intr				
+				temp[0] = inb(pHwDeviceExtension->BaseIoPort0 + 0x00B2);//received data
+				pHwDeviceExtension->I2C_STEP = NONE;
+				if ( (scsi_sg_count(pScsiCmd)) && (len > 0) ) {
+	
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+					memcpy(sg_list->address,temp,len);
+#else
+					local_irq_save(km_flags);
+					km_buffer = kmap_atomic(sg_page(sg_list),KM_USER0) + sg_list->offset;
+	//				km_buffer = kmap_atomic(sg_list->page,KM_USER0) + sg_list->offset;
+					memcpy(km_buffer,temp,len);
+					kunmap_atomic(km_buffer - sg_list->offset,KM_USER0);
+					local_irq_restore(km_flags);
+#endif
+				}
+#ifdef KERNEL_V2625
+				
+#else
+				else {
+					memcpy(pScsiCmd->request_buffer,temp,len);
+				}
+#endif
+				break;
+			case W_F1:
+				break;
+			case W_F2:
+				break;
+			case W_F3:
+				break;
+		}
+		spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+		return;
+#else
+		return IRQ_NONE;
+#endif
+		
+	}else if ((int_status = inw(pHwDeviceExtension->BaseIoPort0 + 0x08)) == 0) {
+		// It's not our interrupt
+		spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+		return;
+#else
+		return IRQ_NONE;
+#endif
+	}
+	if (int_status & 0x0100) {
+		// IDE interrupt income
+		pIdeChannel = &(pHwDeviceExtension->IdeChannel);
+		// clear interrupt
+		outb(0x00,pIdeChannel->IdePortPSFF);					// STOP DMA
+		status = inb(pIdeChannel->IdePortPSFF + 0x0002) | 0x04;
+		outb(status,pIdeChannel->IdePortPSFF + 0x0002);
+		status = inb(pIdeChannel->IdePortP1XX + 0x0007);			// clear PCI interrupt
+		if (pIdeChannel->pCurRequest != 0) {
+			pWorkingTable	= pIdeChannel->pCurRequest;
+			pIdeDevice	= pWorkingTable->pDevice;
+			pScsiCmd	= pWorkingTable->pWorkingScsiCmd;
+			if (pIdeDevice->FG_AtapiDevice == 0) {
+				// IDE hard disk
+				HardDiskInterrupt(pHwDeviceExtension,pIdeChannel);
+			} else {
+				// IDE atapi device
+				CdRomInterrupt(pHwDeviceExtension,pIdeChannel);
+			}
+			if (pScsiCmd->result != STATUS_PENDING) {
+				pIdeChannel->QueueCount--;
+				pIdeDevice->QueueCount--;
+				pIdeChannel->pCurRequest = 0;
+				ReleaseWorkingTable(pWorkingTable);
+				pScsiCmd->scsi_done(pScsiCmd);
+			}
+			while((pIdeChannel->pCurRequest == 0) && (pIdeChannel->pPendingIO != 0)) {
+				pIdeChannel->pCurRequest = pIdeChannel->pPendingIO;
+				pIdeChannel->pPendingIO  = pIdeChannel->pPendingIO->pNextTable;
+				pIdeChannel->pCurRequest->pNextTable = 0;
+				pIdeDevice = pIdeChannel->pCurRequest->pDevice;
+				if (pIdeDevice->FG_AtapiDevice) {
+					ExecuteIdeATAPI(pHwDeviceExtension,pIdeChannel);
+				} else {
+					ExecuteIdeATA(pHwDeviceExtension,pIdeChannel);
+				}
+				pScsiCmdX = pIdeChannel->pCurRequest->pWorkingScsiCmd;
+				if (pScsiCmdX->result == SAM_STAT_CHECK_CONDITION) {
+					pIdeChannel->QueueCount--;
+					pIdeDevice->QueueCount--;
+					ReleaseWorkingTable(pIdeChannel->pCurRequest);
+					pIdeChannel->pCurRequest = 0;
+					pScsiCmdX->scsi_done(pScsiCmdX);
+				}
+			}
+		}
+		spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+		return;
+#else
+		return IRQ_HANDLED;
+#endif
+	}
+	pSataChannel = &(pHwDeviceExtension->SataChannel[0]);
+	for (i = 0 ; i < MAX_SATA_CHANNEL ; i++) {
+		if (int_status & 0x0001) {
+			interrupt_status	= inl(pSataChannel->BaseIoPort + 0x0010);
+			D2H_status	= inl(pSataChannel->BaseIoPort + 0x0070);
+			D2H_status	= (D2H_status & 0x11111110) | (interrupt_status & 0x00000001); //D2H int flag & D2H Reg FIS int
+			if ((interrupt_status & 0x00400308) || (D2H_status)) {
+				break;
+			}
+		}
+		int_status >>= 1;
+		pSataChannel++;
+	}
+	if (i >= MAX_SATA_CHANNEL) {
+		spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+		return;
+#else
+		return IRQ_NONE;
+#endif
+	}
+	//================================================================
+	// SATA interrupt income
+	//================================================================
+	while ((interrupt_status = inl(pSataChannel->BaseIoPort + 0x0010)) == 0xFFFFFFFF) {
+		printk("interrupt_status get wrong value\n\r");
+		udelay(100);
+		cpu_relax();
+	}
+	
+	if (interrupt_status & 0x0001FE08) {
+		// SET DEVICE BITS FIS , Queue command complete 
+		CompleteMapSDBFG = inl(pSataChannel->BaseIoPort + 0x0044);
+		PortMultiplier = 0;
+		if (interrupt_status & 0x0001FE00) {
+			// some one send status 0x41 back(error bit assert)
+			pSataChannel->FG_ErrPMx |= ((unsigned char)(interrupt_status >> 9));
+			pSataChannel->FG_StopIO = 0x01;
+			outl(0x0001FE00,pSataChannel->BaseIoPort + 0x0010);
+			pSataChannel->FG_ErrSDB = 1;
+		} else {
+			CompleteMap = CompleteMapSDBFG;
+			for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+				if (CompleteMap & 0x00000001) {
+					// found a command complete
+					pWorkingTable = pSataChannel->pExecuteIO[i];
+					if (pWorkingTable) {
+						pSataDevice = pWorkingTable->pDevice;
+						pReciveFIS  = pSataChannel->pReciveFIS + pSataDevice->FG_PMId;
+						pScsiCmd	   = pWorkingTable->pWorkingScsiCmd;
+			//			printk("q command %x end status %x\n",pScsiCmd->cmnd[0],pReciveFIS->SetDeviceBitsFIS.Status);	
+						if (pReciveFIS->SetDeviceBitsFIS.Status & 0x01) {
+							// command execute error
+							pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+							ConvertSenseKey(pSataChannel,pWorkingTable,pReciveFIS->Device2HostFIS.Error);
+						} else {
+							
+							pScsiCmd->result = SAM_STAT_GOOD;
+							pSataDevice->SenseKey	= 0;
+							pSataDevice->SenseAsc	= 0;
+							pSataDevice->SenseAscQ	= 0;
+						}
+						pSataChannel->QueueCount--;
+						pSataDevice->QueueCount--;
+						if (pWorkingTable->use_sg) {
+							sg_list = (struct scatterlist *)pWorkingTable->request_buffer;
+
+			        			pci_unmap_sg(pHwDeviceExtension->pPciDev,
+									sg_list,
+									pWorkingTable->use_sg,
+# if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+									scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+# else
+									pScsiCmd->sc_data_direction
+# endif
+								   );
+
+						} else {
+							pci_unmap_single(pHwDeviceExtension->pPciDev,
+									pWorkingTable->pDmaSingleMapAddr,
+									pWorkingTable->request_bufflen,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+									scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+#else
+									pScsiCmd->sc_data_direction
+#endif
+								       );
+						}
+						ReleaseWorkingTable(pWorkingTable);
+						pScsiCmd->scsi_done(pScsiCmd);
+						pSataChannel->pExecuteIO[i] = 0;
+					} else {
+						pSataChannel->pExecuteIO[i] = 0;	//??
+					}
+				}
+				CompleteMap >>= 1;
+				if (CompleteMap == 0) {
+					break;
+				}	
+			}
+			// clear SDBFG bits
+			outl(CompleteMapSDBFG,pSataChannel->BaseIoPort + 0x0044);
+			// clear interrupt flag
+			outl(0xFFFE01F6,pSataChannel->BaseIoPort + 0x0010);
+		}
+	} else if (D2H_status) {
+		if (pSataChannel->FG_StopIO == 0) {
+			// NCQ Hard Disk
+			for (i = 0 ; i < 8 ; i++) {
+				if (D2H_status & (0x00000001 << (i * 4))) {
+					pReciveFIS = pSataChannel->pReciveFIS + i;
+					if (pReciveFIS->SetDeviceBitsFIS.Status & 0x01) {
+						// command error
+						pSataChannel->FG_ErrPMx |= (0x01 << i);
+						pSataChannel->FG_StopIO = 0x01;
+						pSataChannel->FG_ErrD2H = 1;
+					}
+				}
+			}
+			//=== clear interrupt ==========================================================================
+			if (D2H_status & 0x11111110) {
+				// clear interrupt flag for PM1 - PM7
+				outl((D2H_status & 0xFFFFFFF0),pSataChannel->BaseIoPort + 0x0070);
+			}
+			if (D2H_status & 0x00000001) {
+				// clear interrupt flage for PM0
+				outl(0xEEEEEEE1,pSataChannel->BaseIoPort + 0x0010);
+			}
+		} else {
+			// None NCQ Hard Disk/ATAPI device
+			pWorkingTable	= pSataChannel->pExecuteIO[0];
+			pSataDevice	= pWorkingTable->pDevice;
+			pReciveFIS	= ((pSataChannel->pReciveFIS) + (pSataDevice->FG_PMId));
+			pScsiCmd		= pWorkingTable->pWorkingScsiCmd;
+		//	printk("d2h command %x end status %x\n",pScsiCmd->cmnd[0],pReciveFIS->Device2HostFIS.Status);
+			if (pSataDevice->FG_AtapiDevice) { // CDROM/DVD
+				if (pReciveFIS->Device2HostFIS.Status & 0x01) {
+					// command execute error
+					pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+				} else {					
+					switch (pScsiCmd->cmnd[0]) {
+					case REQUEST_SENSE:
+						sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+						if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+							pBuf  = sg_list->address;
+#else
+							local_irq_save(km_flags);
+							km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//							km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+							pBuf = km_buffer;
+#endif
+						} else {
+							pBuf = pWorkingTable->request_buffer;
+						}
+						if ((pBuf[2] == 0x06) && (pBuf[12]==0x28)) {
+							pSataDevice->DeviceBlockSize = 2048;
+						} else if ((pBuf[2] == 0x02) && (pBuf[12]==0x3a)) {
+							pSataDevice->DeviceBlockSize = 2048;
+						}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#else
+						if (pWorkingTable->use_sg) {
+							kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+							local_irq_restore(km_flags);
+						}
+#endif
+						break;
+				 	case INQUIRY:
+						sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+						if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+							pBuf  = sg_list->address;
+#else
+							local_irq_save(km_flags);
+							km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//							km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+							pBuf = km_buffer;
+#endif
+						} else {
+							pBuf = pWorkingTable->request_buffer;
+						}
+						pInquirybuf = (PUINQUIRYDATA)pBuf;
+						pInquirybuf->VersionInfo &= 0xF8;
+						pInquirybuf->VersionInfo |= 0x02;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#else
+						if (pWorkingTable->use_sg) {
+							kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+							local_irq_restore(km_flags);
+						}
+#endif
+						break;
+/*
+					case 0x46:
+						SrbDataBuffer = (unsigned char *)pWorkingTable->request_buffer;
+						sg_list = (struct scatterlist *)(pWorkingTable->pOrgRequesrBuff);
+						if (pWorkingTable->old_use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+							SrbExtOriginalBuffer  = sg_list->address;
+#else
+							local_irq_save(km_flags);
+							km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//							km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+							SrbExtOriginalBuffer = km_buffer;
+#endif
+						} else {
+							SrbExtOriginalBuffer = pWorkingTable->pOrgRequesrBuff;
+						}
+						for (i = 0 ; i < pWorkingTable->request_bufflen ; i++) {
+							*SrbExtOriginalBuffer = *SrbDataBuffer;
+							SrbExtOriginalBuffer++;
+							SrbDataBuffer++;
+						}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#else
+						if (pWorkingTable->old_use_sg) {
+							kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+							local_irq_restore(km_flags);
+						}
+#endif
+						break;
+*/
+					case MODE_SENSE_10:		// mode sense 10
+						SrbDataBuffer = (unsigned char *)pWorkingTable->request_buffer;
+						sg_list = (struct scatterlist *)(pWorkingTable->pOrgRequesrBuff);
+						km_sg_used = 0;
+						if (pWorkingTable->old_use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+							SrbExtOriginalBuffer  = sg_list->address;
+#else
+							local_irq_save(km_flags);
+							km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//							km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+							SrbExtOriginalBuffer = km_buffer;
+							km_sg_used = 1;
+#endif
+						} else {
+							SrbExtOriginalBuffer = pWorkingTable->pOrgRequesrBuff;
+						}
+						BlockLen = pSataDevice->DeviceBlockSize;
+						word = ((((unsigned short)SrbDataBuffer[0]) << 8) & 0xff00)+
+						       ((((unsigned short)SrbDataBuffer[1])     ) & 0x00ff);
+						if (pWorkingTable->OrgCmnd[0] == MODE_SENSE) {
+							// rebuild mode parameter header
+							SrbExtOriginalBuffer[0] = word - 3;		// data length	
+							SrbExtOriginalBuffer[1] = SrbDataBuffer[2];	// medium type
+							SrbExtOriginalBuffer[2] = 0;		// device-specific parameter
+							SrbExtOriginalBuffer[3] = 0;		// block descriptor length
+							i=4;
+							// rebuild block descriptor
+							if ((pWorkingTable->OrgCmnd[1] & 0x08) == 0) {
+								SrbExtOriginalBuffer[0] += 8;
+								// set block descriptor length
+								SrbExtOriginalBuffer[3] = 8;
+								// build descriptor block
+								//SrbExtOriginalBuffer[4] = 0x83;
+								for (i = 4 ; i <= 8 ; i++) {
+									SrbExtOriginalBuffer[i] = 0;
+								}
+								SrbExtOriginalBuffer[9]  = (unsigned char)(BlockLen>>16);
+								SrbExtOriginalBuffer[10] = (unsigned char)(BlockLen>>8);
+								SrbExtOriginalBuffer[11] = (unsigned char)BlockLen;
+								if ((pWorkingTable->OrgCmnd[2] & 0xc0) == 0x40) {
+									// PC = 0x01
+									SrbExtOriginalBuffer[9]  = 0xFF;
+									SrbExtOriginalBuffer[10] = 0xFF;
+									SrbExtOriginalBuffer[11] = 0xFF;
+								}
+								i = 12;
+							}
+							SrbExtOriginalBuffer += (unsigned char)i;
+							SrbDataBuffer += 8;
+							// moving page list data
+							for (i = 0 ; i < (pWorkingTable->pOrgRequestBuffLen - 12) ; i++) {
+								*SrbExtOriginalBuffer = *SrbDataBuffer;
+								SrbExtOriginalBuffer++;
+								SrbDataBuffer++;
+							}
+						} else {
+							// MODE_SENSE_10
+							if (	(((unsigned short)(pWorkingTable->request_bufflen)) > (word + 16)) &&
+									 ((pScsiCmd->cmnd[1] & 0x08) == 0)
+							   ) {
+								// host buffer > data + block descriptor length + head len
+								// and DBD bit = 0
+								word = word + 8;			// add block descriptor length
+								// rebuild parameter header
+								SrbExtOriginalBuffer[0] = (unsigned char)(word >> 8);	// data length	
+								SrbExtOriginalBuffer[1] = (unsigned char)word;	
+								for (i = 2 ; i <= 5 ; i++) {
+									SrbExtOriginalBuffer[i] = SrbDataBuffer[i];
+								}
+								SrbExtOriginalBuffer[6] = 0;
+								SrbExtOriginalBuffer[7] = 8;
+								word = word - 8;
+								// copy sense data
+								for (i = 0 ; i < word ; i++) {
+									SrbExtOriginalBuffer[i+16] = SrbDataBuffer[i+8];
+								}
+								// rebuild block descriptor
+								for (i = 8 ; i <= 12 ; i++) {
+									SrbExtOriginalBuffer[i] = 0;
+								}	
+								SrbExtOriginalBuffer[13] = (unsigned char)(BlockLen>>16);
+								SrbExtOriginalBuffer[14] = (unsigned char)(BlockLen>>8);
+								SrbExtOriginalBuffer[15] = (unsigned char)BlockLen;
+								if ((pWorkingTable->OrgCmnd[2] & 0xc0) == 0x40) {
+									SrbExtOriginalBuffer[13] = 0xFF;
+									SrbExtOriginalBuffer[14] = 0xFF;
+									SrbExtOriginalBuffer[15] = 0xFF;
+								}
+								pWorkingTable->OrgCmnd[0] = 0;
+							} else {
+								word +=2; // total transfer length
+								if (word > pWorkingTable->request_bufflen) {
+									word = (unsigned short)(pWorkingTable->request_bufflen);
+								}
+								for (i = 0 ; i < word ; i++) {
+									SrbExtOriginalBuffer[i] = SrbDataBuffer[i];
+								}	
+							}
+						}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+						if (km_sg_used) {
+							kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+							local_irq_restore(km_flags);
+						}
+#endif						
+						break;
+					}
+					pScsiCmd->result = SAM_STAT_GOOD;
+					pSataDevice->SenseKey = 0;
+					pSataDevice->SenseAsc = 0;
+					pSataDevice->SenseAscQ = 0;
+				}
+				if (pWorkingTable->request_bufflen) {
+					if (pWorkingTable->use_sg) {
+						sg_list = (struct scatterlist *)pWorkingTable->request_buffer;
+
+		        			pci_unmap_sg(pHwDeviceExtension->pPciDev,
+								sg_list,
+								pWorkingTable->use_sg,
+# if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+								scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+# else
+								pScsiCmd->sc_data_direction
+# endif
+							   );
+
+					} else {
+						pci_unmap_single(pHwDeviceExtension->pPciDev,
+								pWorkingTable->pDmaSingleMapAddr,
+								pWorkingTable->request_bufflen,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+								scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+#else
+								pScsiCmd->sc_data_direction
+#endif
+							       );
+					}
+				}
+				RestoreCmdATAPI(pWorkingTable);
+				pSataChannel->QueueCount--;
+				pSataChannel->FG_StopIO = 0;
+				pSataDevice->QueueCount--;
+				pSataChannel->pExecuteIO[0] = 0;
+				ReleaseWorkingTable(pWorkingTable);
+				pScsiCmd->scsi_done(pScsiCmd);
+				// clear interrupt flag
+				if (D2H_status & 0x11111110) {
+					// clear interrupt flag for PM1 - PM7
+					outl((D2H_status & 0x33333330),pSataChannel->BaseIoPort + 0x0070);
+				} else {
+					// clear interrupt flage for PM0
+					outb(0x03,pSataChannel->BaseIoPort + 0x0010);
+				}
+			} else {
+				// Hard Disk
+				if (pReciveFIS->Device2HostFIS.Status & 0x01) {
+					// command execute error
+					pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+					ConvertSenseKey(pSataChannel,pWorkingTable,pReciveFIS->Device2HostFIS.Error);
+					pSataDevice->FG_InternalError = 1;
+				} else {
+					pScsiCmd->result		= SAM_STAT_GOOD;
+					pSataDevice->SenseKey	= 0;
+					pSataDevice->SenseAsc	= 0;
+					pSataDevice->SenseAscQ	= 0;
+				}
+				if(pWorkingTable->FG_NonData){
+
+				}else{
+					if (pWorkingTable->use_sg) {
+						sg_list = (struct scatterlist *)pWorkingTable->request_buffer;
+	
+						pci_unmap_sg(pHwDeviceExtension->pPciDev,
+								sg_list,
+								pWorkingTable->use_sg,
+	# if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+								scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+	# else
+								pScsiCmd->sc_data_direction
+	# endif
+							);
+	
+					} else {
+						pci_unmap_single(pHwDeviceExtension->pPciDev,
+								pWorkingTable->pDmaSingleMapAddr,
+								pWorkingTable->request_bufflen,
+	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+								scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+	#else
+								pScsiCmd->sc_data_direction
+	#endif
+							);
+					}
+				}
+				pSataChannel->QueueCount--;
+				pSataChannel->FG_StopIO = 0;
+				pSataDevice->QueueCount--;
+				pSataChannel->pExecuteIO[0] = 0;
+				ReleaseWorkingTable(pWorkingTable);
+				pScsiCmd->scsi_done(pScsiCmd);
+				// clear interrupt flag
+				if (D2H_status & 0x11111110) {
+					// clear interrupt flag for PM1 - PM7
+					outl((D2H_status & 0x11111110),pSataChannel->BaseIoPort + 0x0070);
+				} else { // clear interrupt flage for PM0
+					outb(0x01,pSataChannel->BaseIoPort + 0x0010);
+				}
+			}
+		}
+	}
+	if (pSataChannel->FG_ErrPMx) {
+		for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+			if (pSataChannel->pExecuteIO[i]) {
+				pWorkingTable = pSataChannel->pExecuteIO[i];
+				pSataDevice = pWorkingTable->pDevice;
+				if ((pSataChannel->FG_ErrPMx & (0x01 << (pSataDevice->FG_PMId))) == 0) {
+					// found a none error command is still executeing
+					break;
+				}
+			}
+		}
+		if (i >= MAX_COMMAND_QUEUE_CH) {
+			// all normal command were finished
+			for (j = 0 ; j < 8 ; j++) {
+				if (pSataChannel->FG_ErrPMx & (0x01 << j)) {
+					PortMultiplier = (unsigned char)j;
+					//==========================================================================================
+					// disable INTA#
+					//==========================================================================================
+					outb(0,pHwDeviceExtension->BaseIoPort0 + 0x0004);
+					cancel_ci = 0;
+					for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+						// found out the IO match current PM number;
+						if (pSataChannel->pExecuteIO[i]) {
+							if (((P_DeviceInfo)((pSataChannel->pExecuteIO[i])->pDevice))->FG_PMId == PortMultiplier) {
+								cancel_ci |= (0x00000001 << i);
+							}
+						}
+					}
+					//==========================================================================================
+					outb(PortMultiplier,pSataChannel->BaseIoPort+0x003F);	// set Port multiple number to b27-24
+					outl(cancel_ci,pSataChannel->BaseIoPort + 0x0040);	// force clear CI bits
+					//==========================================================================================
+					for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+						if (( cancel_ci >> i) & 0x00000001) {
+							pWorkingTable1 = pSataChannel->pExecuteIO[i];
+							pSataChannel->pExecuteIO[i] = 0;
+							// insert this Io to first Pending IO
+							pWorkingTable1->pNextTable = pSataChannel->pPendingIO;
+							pWorkingTable1->pPrevTable = 0;
+							pSataChannel->pPendingIO = pWorkingTable1;
+							if (pWorkingTable1->pNextTable) {
+								((P_WorkingTable)(pWorkingTable1->pNextTable))->pPrevTable = pWorkingTable1;
+							}
+						}
+					}
+					PMxReset(pSataChannel,PortMultiplier);
+					//==========================================================================================
+					outb(PortMultiplier,pSataChannel->BaseIoPort+0x003F);	// set Port multiple number to b27-24
+					outl(cancel_ci,pSataChannel->BaseIoPort + 0x0040);	// force clear CI bits
+					//==========================================================================================
+					// clear BUSY & DRQ bit to release channel
+					//==========================================================================================
+					status = inb(pSataChannel->BaseIoPort + 0x0018) | 0x08;
+					outb(status,pSataChannel->BaseIoPort + 0x0018);
+					while(inb(pSataChannel->BaseIoPort + 0x0018) & 0x08) {
+						udelay(10);
+						cpu_relax();
+					}
+					//==========================================================================================
+					// Enable INTA#
+					//==========================================================================================
+					outb(0x02,pHwDeviceExtension->BaseIoPort0 + 0x0004);// Enable INTA#
+					pSataChannel->FG_StopIO = 0;
+					pSataChannel->FG_ErrPMx = 0;
+					pSataChannel->FG_ErrSDB = 0;
+					pSataChannel->FG_ErrD2H = 0;
+				}
+			}
+		}
+	}
+	if (pSataChannel->FG_StopIO) {
+		spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+		return;
+#else
+		return IRQ_HANDLED;
+#endif
+	}
+	if (pSataChannel->pPendingIO) {
+		pWorkingTable = pSataChannel->pPendingIO;
+		pSataDevice = pWorkingTable->pDevice;
+		
+		if ((pSataDevice->FG_QueueSupported) && (!pWorkingTable->FG_Updata)) {
+			j = (int)(pSataChannel->QueueStartTag);
+			for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+				if (pSataChannel->pExecuteIO[j] == 0) {
+					// found empty Queue tag
+					break;
+				}
+				if ( ++j >= MAX_COMMAND_QUEUE_CH) {
+					j = 0;
+				}
+			}
+			pSataChannel->pExecuteIO[j] = pWorkingTable;
+			pWorkingTable->TagID	  = (unsigned char)j;
+			if ( ++j >= MAX_COMMAND_QUEUE_CH) {
+				j = 0;
+			}
+			pSataChannel->QueueStartTag = (unsigned char)j;
+			ExecuteSataATA(pHwDeviceExtension,pWorkingTable);
+			ChannelIoRemove(pWorkingTable);
+		} else {
+			// search executing IO
+			for (i = 0 ; i < MAX_COMMAND_QUEUE_CH ; i++) {
+				if (pSataChannel->pExecuteIO[i] != 0) {
+					// found a executing IO
+					break;
+				}
+			}
+			if (i >= MAX_COMMAND_QUEUE_CH) {
+				// send IO to Device
+				pSataChannel->pExecuteIO[0] = pWorkingTable;
+				pWorkingTable->TagID	  = 0;
+				pSataChannel->FG_StopIO	  = 1;
+				ExecuteSataATA(pHwDeviceExtension,pWorkingTable);
+				ChannelIoRemove(pWorkingTable);
+			}
+		}
+	}
+	if (interrupt_status & 0x00400040) {
+		// PhyRdy signal changed & new ComInit incomes.
+		outl(0xFFFFFFFF,pSataChannel->BaseIoPort+0x30);	// clear interrupt
+	}
+	spin_unlock_irqrestore(&(pHwDeviceExtension->spin_lock),flags);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+	return;
+#else
+	return IRQ_HANDLED;
+#endif
+}
+//========================================================================
+static void adapter_timer(unsigned long para)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension;
+	unsigned char FG_SendWorkingTable;
+	
+	pHwDeviceExtension = (PHW_DEVICE_EXTENSION)para;
+	FG_SendWorkingTable = 0;
+	
+	if (FG_SendWorkingTable) {
+//		SendWorkingTableOut(pHwDeviceExtension);
+	}
+	if (!(pHwDeviceExtension->FG_TimerStop)) {
+		(pHwDeviceExtension->AdapterTimer).expires = jiffies + TIMER_SCALE;
+		add_timer(&(pHwDeviceExtension->AdapterTimer));
+	}
+	return;
+}
+//========================================================================
+//	IDE function
+//========================================================================
+static unsigned char SendIdentifyCmd2IDE(P_DeviceInfo pDeviceInfo,void *pBuffer,unsigned char IdentifyCmd)
+{
+	P_Channel pIdeChannel;
+	PUIdentify pIdentifyBuff;
+	unsigned short *pTempBuf;
+	int i;
+	unsigned char status;
+
+	pIdeChannel = pDeviceInfo->pChannel;
+	pIdentifyBuff = (PUIdentify)pBuffer;
+	outb(pDeviceInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	udelay(300);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	if (  (status == 0x7F) || (status & 0x80)   ) {
+		return 0;
+	}
+	//  issure Identify command
+	outb(pDeviceInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	outb(IdentifyCmd,pIdeChannel->IdePortP1XX + 0x0007);
+	for (i = 0 ; i < 20000 ; i++) {
+		// wait 2 S
+		cpu_relax();
+		udelay(100);		// delay 100us
+		status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+		if (status & 0x80)
+			continue;	// BUS BUSY
+		if (status & 0x08)	
+			break;		// DRQ ASSERT
+		if (status & 0x01)	
+			break;		// ERROR BIT ASSERT
+	}
+	if (  (status == 0x08)||(status == 0x58)||(status == 0x48)   ) {
+		pTempBuf = (unsigned short *)pBuffer;
+		for (i = 0 ; i < 256 ; i++) {
+			*pTempBuf = (unsigned short)inw(pIdeChannel->IdePortP1XX);
+			pTempBuf++;
+		}
+		status = inb(pIdeChannel->IdePortPSFF + 0x0002) | 0x04;
+		outb(status,pIdeChannel->IdePortPSFF + 0x0002);
+		status = inb(pIdeChannel->IdePortP1XX+ 0x0007);
+		return 1;
+	}	
+	status = inb(pIdeChannel->IdePortPSFF + 0x0002) | 0x04;
+	outb(status,pIdeChannel->IdePortPSFF + 0x0002);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	return 0;
+}
+//===================================================================================================
+static unsigned char PioTimming[5] = { 0x6e,0x58,0x44,0x33,0x31 };
+static void SetPIOfeature(P_DeviceInfo pHardDiskInfo,PUIdentify pIdentifyBuff,unsigned char MAXMODE)
+{	
+	unsigned short PIOxferclk;
+	unsigned char PIOmode,status;
+	int i,j;
+	P_Channel pIdeChannel;
+
+	pIdeChannel = pHardDiskInfo->pChannel;
+	pHardDiskInfo->MultiBlk = 1;
+	if (pIdentifyBuff->MultipleBlk > 1) {
+		// set multiple block
+		outb(pHardDiskInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+		for (i = 0 ; i < 100000 ; i++) {
+			// wait 5 seconds for bus free
+			udelay(50);
+			cpu_relax();
+			status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+			if (status & 0x80)
+				continue;
+			break;
+		}
+		if ((status & 0x80) == 0) {
+			outb(pIdentifyBuff->MultipleBlk,pIdeChannel->IdePortP1XX + 0x0002);
+			outb(0xC6,pIdeChannel->IdePortP1XX + 0x0007);
+			for (i = 0 ; i < 200000 ; i++) {
+				// wait 10 seconds for command complete
+				udelay(50);
+				cpu_relax();
+				status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+				if (status & 0x80)
+					continue;
+				break;
+			}
+			if ((status & 0x89) == 0) {
+				pHardDiskInfo->MultiBlk = pIdentifyBuff->MultipleBlk;
+			}
+		}
+	}// end of set multiple block
+	if (pIdentifyBuff->PIOMode & 0x04) {
+		pHardDiskInfo->PIO_Mode	= 2;
+	} else if (pIdentifyBuff->PIOMode & 0x02) {
+		pHardDiskInfo->PIO_Mode	= 1;
+	} else {
+		pHardDiskInfo->PIO_Mode	= 0;
+	}
+	if (pIdentifyBuff->FG_ValidMap & 0x0002) {
+		// set PIO mode depanded on minimum PIO transfer cycle time
+		PIOxferclk = pIdentifyBuff->MinPioTransCycle / 30;
+		if (( pIdentifyBuff->MinPioTransCycle % 30 ) > 0) {
+			PIOxferclk++;
+		}
+		if (PIOxferclk <= 4) {
+			// 120 ns
+			pHardDiskInfo->PIO_Mode	= 4;
+		} else if (PIOxferclk <= 6) {
+			// 180 ns
+			pHardDiskInfo->PIO_Mode	= 3;
+		} else if (PIOxferclk <= 8) {
+			// 240 ns
+			pHardDiskInfo->PIO_Mode	= 2;
+		} else if (PIOxferclk <= 13) {
+			// 383 ns
+			pHardDiskInfo->PIO_Mode	= 1;
+		} else {
+			// 600 ns
+			pHardDiskInfo->PIO_Mode	= 0;
+		}
+	}
+	if (pHardDiskInfo->PIO_Mode > MAXMODE) {
+		pHardDiskInfo->PIO_Mode = MAXMODE;
+	}
+	pHardDiskInfo->PIOxferclk = PioTimming[pHardDiskInfo->PIO_Mode];
+	// end of set PIO mode
+	// set PIO mode feature
+	PIOmode = pHardDiskInfo->PIO_Mode | 0x08;
+	// wait for bus free
+	outb(pHardDiskInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	for (j = 0 ; j < 2 ; j++) {
+		for (i = 0 ; i < 100000 ; i++) {
+			// wait 5 seconds for bus free
+			udelay(50);
+			cpu_relax();
+			status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+			if (status & 0x80)
+				continue;
+			break;
+		}
+		if ((status & 0x80) == 0) {
+			// bus is free now
+			outb(0x03,pIdeChannel->IdePortP1XX + 0x0001);
+			outb(PIOmode,pIdeChannel->IdePortP1XX + 0x0002);
+			outb(0xEF,pIdeChannel->IdePortP1XX + 0x0007);
+			// wait for command complete
+			for (i = 0 ; i < 200000 ; i++) {
+				// wait 10 seconds for command complete
+				udelay(50);
+				cpu_relax();
+				status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+				if (status & 0x80)
+					continue;
+				break;
+			}
+			if ((status & 0x89) == 0) {
+				return ;
+			}
+		}
+	}
+	pHardDiskInfo->PIO_Mode = 0;
+	pHardDiskInfo->PIOxferclk = 0x6d;
+	return;
+}
+//===================================================================================================
+static void GetUltraMode(P_DeviceInfo pHardDiskInfo,unsigned char UltraMap)
+{
+	pHardDiskInfo->DMA_Mode = 0;
+	if (UltraMap & 0x40) {
+		// Ultra 133
+		pHardDiskInfo->DMA_Mode	= 7;
+	} else if (UltraMap & 0x20) {
+		// Ultra 100
+		pHardDiskInfo->DMA_Mode	= 6;
+	} else if (UltraMap & 0x10) {
+		// Ultra 66
+		pHardDiskInfo->DMA_Mode	= 5;
+	} else if (UltraMap & 0x8) {
+		// Ultra 44
+		pHardDiskInfo->DMA_Mode	= 4;
+	} else if (UltraMap & 0x04) {
+		// Ultra 33
+		pHardDiskInfo->DMA_Mode	= 3;
+	} else if (UltraMap & 0x02) {
+		// Ultra 1 
+		pHardDiskInfo->DMA_Mode	= 2;
+	} else if (UltraMap & 0x01) {
+		// Ultra 0 
+		pHardDiskInfo->DMA_Mode	= 1;
+	} else {
+		// no ultra support
+		return;
+	}
+}
+//===================================================================================================
+static void SetUltra(P_DeviceInfo pHardDiskInfo,unsigned char MAXMODE)
+{
+	unsigned char	Ultramode,status;
+	P_Channel	pIdeChannel;
+	int		i,j;
+
+	pIdeChannel = pHardDiskInfo->pChannel;
+	// set DMA mode feature
+	if (pHardDiskInfo->DMA_Mode == 0) {
+		return;
+	}
+	Ultramode = pHardDiskInfo->DMA_Mode;
+	Ultramode--;
+	if (Ultramode > MAXMODE) {
+		Ultramode = MAXMODE;
+		pHardDiskInfo->DMA_Mode = Ultramode+1;
+	}
+	Ultramode |= 0x40;
+	// wait for bus free
+	outb(pHardDiskInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	for (j = 0 ; j < 2 ; j++) {
+		for (i = 0 ; i < 100000 ; i++) {
+			// wait 5 seconds for bus free
+			cpu_relax();
+			udelay(50);
+			status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+			if (status & 0x80)
+				continue;
+			break;
+		}
+		if ((status & 0x80) == 0) {
+			outb(0x03,pIdeChannel->IdePortP1XX + 0x0001);
+			outb(Ultramode,pIdeChannel->IdePortP1XX + 0x0002);
+			outb(0xEF,pIdeChannel->IdePortP1XX + 0x0007);
+			// wait for command complete
+			for (i = 0 ; i < 200000 ; i++) {
+				// wait 10 seconds for command complete
+				cpu_relax();
+				udelay(50);
+				status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+				if (status & 0x80)
+					continue;
+				break;
+			}
+			if ((status & 0x89) == 0) {
+				pHardDiskInfo->DMA_Mode |= 0xc0;
+				return ;
+			}
+		}
+	}
+	pHardDiskInfo->DMA_Mode = 0;
+	return;
+}
+//===================================================================================================
+static void SetUltrafeature(P_DeviceInfo pHardDiskInfo,PUIdentify pIdentifyBuff,unsigned char MAXMODE)
+{ 
+	GetUltraMode(pHardDiskInfo,pIdentifyBuff->UltraModeMap);
+	SetUltra(pHardDiskInfo,MAXMODE);
+	return;
+}
+//===================================================================================================
+static void SetDMAfeature(P_DeviceInfo pHardDiskInfo,PUIdentify PidentifyBuff,unsigned char MAXMODE)
+{ 
+	unsigned char DMAmode,status;
+	int i;
+	P_Channel pIdeChannel;
+
+	
+	pIdeChannel = pHardDiskInfo->pChannel;
+	pHardDiskInfo->DMA_Mode = 0;
+	if ((PidentifyBuff->MultiWordDMASupport & 0x04) > 0) {
+		// 120ns
+		pHardDiskInfo->DMA_Mode	= 2;
+		pHardDiskInfo->DMAxferclk	= 0x31;  //(90ns/30ns)
+	} else if ((PidentifyBuff->MultiWordDMASupport & 0x02) > 0) {
+		// 150ns
+		pHardDiskInfo->DMA_Mode	= 1;
+		pHardDiskInfo->DMAxferclk	= 0x33;  //(90ns/90ns)
+	} else {
+		// 480ns
+		pHardDiskInfo->DMA_Mode	= 0;
+		pHardDiskInfo->DMAxferclk	= 0x6e;  //(180ns/420ns)
+	}
+	if (pHardDiskInfo->DMA_Mode > MAXMODE)
+	{
+		pHardDiskInfo->DMA_Mode	= MAXMODE;
+	}
+	// end of set DMA mode
+	// set DMA mode feature
+	DMAmode = pHardDiskInfo->DMA_Mode | 0x20;
+	// wait for bus free
+	outb(pHardDiskInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	for (i = 0 ; i < 10000 ; i++) {
+		// wait 5 seconds for bus free
+		cpu_relax();
+		udelay(500);
+		status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+		if (status & 0x80)
+			continue;
+		break;
+	}
+	if ((status & 0x80) == 0) {
+		outb(0x03,pIdeChannel->IdePortP1XX + 0x0001);
+		outb(DMAmode,pIdeChannel->IdePortP1XX + 0x0002);
+		outb(0xEF,pIdeChannel->IdePortP1XX + 0x0007);
+		// wait for command complete
+		for (i = 0 ; i < 20000 ; i++) {
+			// wait 10 seconds for command complete
+			cpu_relax();
+			udelay(500);
+			status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+			if (status & 0x80)
+				continue;
+			break;
+		}
+		if ((status & 0x89) == 0) {
+			pHardDiskInfo->DMA_Mode |= 0x80;
+			return ;
+		}
+	}
+	pHardDiskInfo->DMA_Mode = 0;
+	return;
+}
+//===================================================================================================
+static void SetChipIo(P_DeviceInfo pHardDiskInfo)
+{
+	P_Channel pIdeChannel = pHardDiskInfo->pChannel;
+	unsigned char UltraMode,PioM,PioS;
+
+	UltraMode = inb(pIdeChannel->IdeRegSpeed + 0x0003);
+	if (pHardDiskInfo->HD_V1X6 & 0x10) { // slave device
+		if(pHardDiskInfo->HddType == 0xC0){
+			outb(pHardDiskInfo->PIOxferclk,pIdeChannel->IdeRegSpeed + 1);	// set PIO
+			UltraMode &= 0x0F;			// keep master ultra mode
+			UltraMode |= (((pHardDiskInfo->DMA_Mode) & 0x07) << 4);
+		}else if(pHardDiskInfo->HddType == 0x80){
+			outb(pHardDiskInfo->DMAxferclk,pIdeChannel->IdeRegSpeed + 1);
+			UltraMode &= 0x0F;	
+		}
+		
+	} else {
+		// master device
+		if(pHardDiskInfo->HddType == 0xC0){
+			outb(pHardDiskInfo->PIOxferclk,pIdeChannel->IdeRegSpeed);	// set PIO
+			UltraMode &= 0xF0;		// keep slave ultra mode
+			UltraMode |= ((pHardDiskInfo->DMA_Mode) & 0x07);
+		}else if(pHardDiskInfo->HddType == 0x80){
+			outb(pHardDiskInfo->DMAxferclk,pIdeChannel->IdeRegSpeed);
+			UltraMode &= 0xF0;
+		}
+	}
+	outb(UltraMode,pIdeChannel->IdeRegSpeed + 3);	// set PIO
+	PioM = inb(pIdeChannel->IdeRegSpeed);	// get master PIO
+	PioS = inb(pIdeChannel->IdeRegSpeed + 1);	// get slave PIO
+	if (PioM < PioS) {
+		PioM = PioS;
+	}
+	outb(PioM,pIdeChannel->IdeRegSpeed + 2);	// set Command PIO
+	return;
+}
+//===================================================================================================
+static void ScanATA(PHW_DEVICE_EXTENSION DeviceExtension,P_DeviceInfo pHardDiskInfo)
+{
+	PUIdentify pIdentifyBuff;
+	P_Channel pIdeChannel;
+	int j;
+	unsigned char TempBuf[512],status;
+
+	pIdeChannel = pHardDiskInfo->pChannel;
+	outb(pHardDiskInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	udelay(100);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	if (  (status == 0x7F) || (status & 0x80)   ) {
+		return;
+	}
+	pIdentifyBuff = (PUIdentify)TempBuf;
+	if (SendIdentifyCmd2IDE(pHardDiskInfo,pIdentifyBuff,0xEC)) {
+		
+		// got ATA device
+		if (	  ((pIdentifyBuff->ConfigBitInfo & 0x8000) == 0)
+			&&(pIdentifyBuff->FG_ValidMap & 0x0004)
+			|| (pIdentifyBuff->ConfigBitInfo & 0x848A)
+		   ) {	// only support ULTRA device
+			pHardDiskInfo->FG_DeviceInstall	= 1;
+			pHardDiskInfo->HD_V1X6		|= 0x40;
+#if __LITTLE_ENDIAN
+#else
+			pIdentifyBuff->TotalLBA = ((pIdentifyBuff->TotalLBA >> 16) & 0x0000FFFF) +
+							((pIdentifyBuff->TotalLBA << 16) & 0xFFFF0000);
+#endif
+			((pHardDiskInfo->Capacity).U64L).U64L_H = 0;
+			((pHardDiskInfo->Capacity).U64C).U64C_L_HH = (u8)(pIdentifyBuff->TotalLBA >> 24);
+			((pHardDiskInfo->Capacity).U64C).U64C_L_HL = (u8)(pIdentifyBuff->TotalLBA >> 16);
+			((pHardDiskInfo->Capacity).U64C).U64C_L_LH = (u8)(pIdentifyBuff->TotalLBA >> 8);
+			((pHardDiskInfo->Capacity).U64C).U64C_L_LL = (u8)(pIdentifyBuff->TotalLBA);
+#if __LITTLE_ENDIAN
+			for (j = 0 ; j < 40 ; j += 2) {
+				pHardDiskInfo->ModelName[j]   = pIdentifyBuff->ModelName[j+1];
+				pHardDiskInfo->ModelName[j+1] = pIdentifyBuff->ModelName[j];
+			}
+			for (j = 0 ; j < 20 ; j += 2) {
+				pHardDiskInfo->SerialNo[j]   = pIdentifyBuff->SerialNo[j+1];
+				pHardDiskInfo->SerialNo[j+1] = pIdentifyBuff->SerialNo[j];
+			}
+			for (j = 0 ; j < 8 ; j += 2) {
+				pHardDiskInfo->FirmWareRev[j]   = pIdentifyBuff->FirmWareRev[j+1];
+				pHardDiskInfo->FirmWareRev[j+1] = pIdentifyBuff->FirmWareRev[j];
+			}
+#else			
+			for (j = 0 ; j < 20 ; j++) {
+				pHardDiskInfo->SerialNo[j]	= pIdentifyBuff->SerialNo[j];
+			}
+			for (j = 0 ; j < 40 ; j++) {
+				pHardDiskInfo->ModelName[j]	= pIdentifyBuff->ModelName[j];
+			}
+			for (j = 0 ; j < 8 ; j++) {
+				pHardDiskInfo->FirmWareRev[j]	= pIdentifyBuff->FirmWareRev[j];
+			}
+#endif
+			//=====================================================================================
+			// check 48 bit LBA capability
+			//=====================================================================================
+			if (pIdentifyBuff->Word83 & 0x0400) {
+#if __LITTLE_ENDIAN
+#else
+				pIdentifyBuff->LBA_48bits_High = ((pIdentifyBuff->LBA_48bits_High >> 16) & 0x0000FFFF) +
+							((pIdentifyBuff->LBA_48bits_High << 16) & 0xFFFF0000);
+				pIdentifyBuff->LBA_48bits_Low = ((pIdentifyBuff->LBA_48bits_Low >> 16) & 0x0000FFFF) +
+							((pIdentifyBuff->LBA_48bits_Low << 16) & 0xFFFF0000);
+#endif
+				if ( ((pIdentifyBuff->LBA_48bits_Low == 0)	         && (pIdentifyBuff->LBA_48bits_High == 0))			||
+				     ((pIdentifyBuff->LBA_48bits_Low == 0xFFFFFFFF) && (pIdentifyBuff->LBA_48bits_High == 0xFFFFFFFF))
+				   ) {
+					pHardDiskInfo->FG_Support48Bits = 0;
+				} else {
+					pHardDiskInfo->FG_Support48Bits = 1;
+					((pHardDiskInfo->Capacity).U64C).U64C_H_HH = (u8)(pIdentifyBuff->LBA_48bits_High >> 24);
+					((pHardDiskInfo->Capacity).U64C).U64C_H_HL = (u8)(pIdentifyBuff->LBA_48bits_High >> 16);
+					((pHardDiskInfo->Capacity).U64C).U64C_H_LH = (u8)(pIdentifyBuff->LBA_48bits_High >> 8);
+					((pHardDiskInfo->Capacity).U64C).U64C_H_LL = (u8)(pIdentifyBuff->LBA_48bits_High);
+					((pHardDiskInfo->Capacity).U64C).U64C_L_HH = (u8)(pIdentifyBuff->LBA_48bits_Low >> 24);
+					((pHardDiskInfo->Capacity).U64C).U64C_L_HL = (u8)(pIdentifyBuff->LBA_48bits_Low >> 16);
+					((pHardDiskInfo->Capacity).U64C).U64C_L_LH = (u8)(pIdentifyBuff->LBA_48bits_Low >> 8);
+					((pHardDiskInfo->Capacity).U64C).U64C_L_LL = (u8)(pIdentifyBuff->LBA_48bits_Low);
+				}
+			} else {
+				pHardDiskInfo->FG_Support48Bits	= 0;
+			}
+//	printk("Capacity : %ld(%08lX) \n\r",pHardDiskInfo->Capacity.U64L.U64L_L,pHardDiskInfo->Capacity.U64L.U64L_L);
+//	printk("Capacity : %ld(%08lX) \n\r",pIdentifyBuff->LBA_48bits_Low,pIdentifyBuff->LBA_48bits_Low);
+			//=====================================================================================
+			// set device's PIO & DMA feature
+			//=====================================================================================
+			pHardDiskInfo->DMA_Mode	= 0;			
+			SetPIOfeature(pHardDiskInfo,pIdentifyBuff,_MAX_PIO_MODE);
+			pHardDiskInfo->HddType = 0;
+			if (pIdentifyBuff->FG_ValidMap & 0x0004)	/* support ULTRA mode(valid 88)*/
+			{
+				printk("ULTRA Capability %x\n",pIdentifyBuff->Capability);
+				SetUltrafeature(pHardDiskInfo,pIdentifyBuff,_MAX_ULTRA);
+				pHardDiskInfo->HddType = 0xC0;
+			//	pHardDiskInfo->HddType = 0xC0;
+			}
+			else if (	  (pIdentifyBuff->Capability & 0x0100) 
+					&&(pIdentifyBuff->MultiWordDMASupport&0x07)
+					&&(pHardDiskInfo->DMA_Mode==0)
+				   )
+			{	
+				printk("multiword DMA Capability %x\n",pIdentifyBuff->Capability);
+				SetDMAfeature(pHardDiskInfo,pIdentifyBuff,0x0F);
+				pHardDiskInfo->HddType = 0x80;
+			//	pHardDiskInfo->HddType = 0x80;
+			}
+			SetUltrafeature(pHardDiskInfo,pIdentifyBuff,_MAX_ULTRA);
+			pHardDiskInfo->DeviceBlockSize	= 512;
+			pHardDiskInfo->FG_IdeExcept	= 0;
+			pHardDiskInfo->A0Wait		= 0;
+			printk("found ATA : %.30s\n",pHardDiskInfo->ModelName);
+			return;
+		}// end of ATA device
+	}// end of send EC command
+	
+	pHardDiskInfo->FG_DeviceInstall = 0;
+	return;
+}
+//========================================================================
+static void ExecuteIdeATA(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_WorkingTable pWorkingTable;
+	P_DeviceInfo pDeviceInfo;
+	Scsi_Cmnd *pScsiCmd;
+	unsigned char V1X6;
+
+	pWorkingTable = pIdeChannel->pCurRequest;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pDeviceInfo = pWorkingTable->pDevice;
+	BuildPrdTable(pHwDeviceExtension,pWorkingTable,pWorkingTable->pMailBox);
+	if (pScsiCmd->result == SAM_STAT_CHECK_CONDITION) {
+		return;
+	}
+	switch(pWorkingTable->XferCmd) {
+	// execute 48 bits command
+	case IDE_READ_DMA_EXT:		// READ DMA EXT
+	case IDE_WRITE_DMA_EXT:		// WRITE DMA EXT
+	case IDE_VERIFY_EXT:		// VERIFY EXT
+		// set IDE register
+		outb((((pWorkingTable->TransferLen).U64C).U64C_L_LH),pIdeChannel->IdePortP1XX + 0x0002);
+		outb((((pWorkingTable->TransferLen).U64C).U64C_L_LL),pIdeChannel->IdePortP1XX + 0X0002);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_HH),pIdeChannel->IdePortP1XX + 0x0003);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_LL),pIdeChannel->IdePortP1XX + 0x0003);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_H_LL),pIdeChannel->IdePortP1XX + 0x0004);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_LH),pIdeChannel->IdePortP1XX + 0x0004);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_H_LH),pIdeChannel->IdePortP1XX + 0x0005);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_HL),pIdeChannel->IdePortP1XX + 0x0005);
+		outb((pDeviceInfo->HD_V1X6),pIdeChannel->IdePortP1XX + 0x0006);
+		break;
+	// execute 28 bits command
+	case IDE_READ_DMA:		// READ DMA
+	case IDE_WRITE_DMA:		// WRITE DMA
+	case IDE_VERIFY:			// VERIFY 
+	case IDE_SEEK:			// SEEK
+		outb((((pWorkingTable->TransferLen).U64C).U64C_L_LL),pIdeChannel->IdePortP1XX + 0X0002);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_LL),pIdeChannel->IdePortP1XX + 0x0003);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_LH),pIdeChannel->IdePortP1XX + 0x0004);
+		outb((((pWorkingTable->StartLBA).U64C).U64C_L_HL),pIdeChannel->IdePortP1XX + 0x0005);
+		V1X6 = (pDeviceInfo->HD_V1X6) | ((((pWorkingTable->StartLBA).U64C).U64C_L_HH) & 0x0F);
+		outb(V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+		break;
+	default:
+		outb(pDeviceInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+		break;
+	}
+	switch(pWorkingTable->XferCmd) {
+	case IDE_READ_DMA:	// READ DMA
+	case IDE_READ_DMA_EXT:	// READ DMA EXT
+		outb(0x08,pIdeChannel->IdePortPSFF);					// stop DMA
+		outl(pWorkingTable->LmailBox,pIdeChannel->IdeRegPrdTable);		// set PRD table
+		outb(pWorkingTable->XferCmd,pIdeChannel->IdePortP1XX + 0x0007);	// send IDE command
+		outb(0x09,pIdeChannel->IdePortPSFF);					// start DMA
+		break;
+	case IDE_WRITE_DMA:	// WRITE DMA
+	case IDE_WRITE_DMA_EXT:	// WRITE DMA EXT
+		outb(0x00,pIdeChannel->IdePortPSFF);					// stop DMA
+		outl(pWorkingTable->LmailBox,pIdeChannel->IdeRegPrdTable);		// set PRD table
+		outb(pWorkingTable->XferCmd,pIdeChannel->IdePortP1XX + 0x0007);	// send IDE command
+		outb(0x01,pIdeChannel->IdePortPSFF);					// start DMA
+		break;
+	default:
+		outb(pWorkingTable->XferCmd,pIdeChannel->IdePortP1XX + 0X0007);	// send IDE command
+		break;
+	}
+	return;
+}
+//========================================================================
+static void HardDiskInterrupt(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	struct scatterlist *sg_list;
+	P_WorkingTable pWorkingTable;
+	Scsi_Cmnd *pScsiCmd;
+	unsigned char status;
+
+	pWorkingTable = pIdeChannel->pCurRequest;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	if (status & 0x01) {
+		// IO error
+		status = inb(pIdeChannel->IdePortP1XX + 0x0001);
+		ConvertSenseKey(pIdeChannel,pWorkingTable,status);
+		pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+	} else { // Command Complete
+		pScsiCmd->result = SAM_STAT_GOOD;
+	}
+	if (pWorkingTable->use_sg) {
+		sg_list = (struct scatterlist *)pWorkingTable->request_buffer;
+
+	        pci_unmap_sg(pHwDeviceExtension->pPciDev,
+				sg_list,
+				pWorkingTable->use_sg,
+# if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+				scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+# else
+				pScsiCmd->sc_data_direction
+# endif
+			   );
+
+	} else {
+		pci_unmap_single(pHwDeviceExtension->pPciDev,
+				pWorkingTable->pDmaSingleMapAddr,
+				pWorkingTable->request_bufflen,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+				scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+#else
+				pScsiCmd->sc_data_direction
+#endif
+			       );
+	}
+	return;
+}
+//========================================================================
+static void ScanATAPI(PHW_DEVICE_EXTENSION DeviceExtension,P_DeviceInfo pDeviceInfo)
+{
+	PUIdentify pIdentifyBuff;
+	P_Channel pIdeChannel;
+	int j;
+	unsigned char status,TempBuf[512];
+
+	pIdeChannel = pDeviceInfo->pChannel;
+	outb(pDeviceInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	udelay(100);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	if (  (status == 0x7F) || (status & 0x80)   ) {
+		return;
+	}
+	pIdentifyBuff = (PUIdentify)TempBuf;
+	//=============================================================================================
+	// RESET IDE DEVICE 
+	//=============================================================================================
+	outb(pDeviceInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	outb(0x08,pIdeChannel->IdePortP1XX + 0x0007);
+	msleep(250);
+	if (SendIdentifyCmd2IDE(pDeviceInfo,pIdentifyBuff,0xA1)) {
+		// Got ATAPI device
+		if ((pIdentifyBuff->ConfigBitInfo & 0x8000) == 0x8000) {
+			// ATAPI device confirm
+			pDeviceInfo->FG_DeviceInstall = 1;
+			pDeviceInfo->FG_AtapiDevice   = 1;
+			//=============================================================================================
+			// SET DEVICE'S PARAMETER
+			//=============================================================================================
+#if __LITTLE_ENDIAN
+			for (j = 0 ; j < 40 ; j += 2) {
+				pDeviceInfo->ModelName[j]   = pIdentifyBuff->ModelName[j+1];
+				pDeviceInfo->ModelName[j+1] = pIdentifyBuff->ModelName[j];
+			}
+			for (j = 0 ; j < 20 ; j += 2) {
+				pDeviceInfo->SerialNo[j]   = pIdentifyBuff->SerialNo[j+1];
+				pDeviceInfo->SerialNo[j+1] = pIdentifyBuff->SerialNo[j];
+			}
+			for (j = 0 ; j < 8 ; j += 2) {
+				pDeviceInfo->FirmWareRev[j]   = pIdentifyBuff->FirmWareRev[j+1];
+				pDeviceInfo->FirmWareRev[j+1] = pIdentifyBuff->FirmWareRev[j];
+			}
+#else			
+			for (j = 0 ; j < 20 ; j++) {
+				pDeviceInfo->SerialNo[j]	= pIdentifyBuff->SerialNo[j];
+			}
+			for (j = 0 ; j < 40 ; j++) {
+				pDeviceInfo->ModelName[j]	= pIdentifyBuff->ModelName[j];
+			}
+			for (j = 0 ; j < 8 ; j++) {
+				pDeviceInfo->FirmWareRev[j]	= pIdentifyBuff->FirmWareRev[j];
+			}
+#endif
+			switch (pIdentifyBuff->ConfigBitInfo & 0x0060) {
+			case 0x0000:
+				pDeviceInfo->A0Wait = 3000+500;
+				break;
+			case 0x0020:
+				pDeviceInfo->A0Wait = 0;
+				break;
+			case 0x0040:
+				pDeviceInfo->A0Wait = 50+500;
+				break;
+			default:
+				pDeviceInfo->A0Wait = 3000+500;
+			}
+			if (pDeviceInfo->A0Wait == 0) {
+				pDeviceInfo->FG_DeviceInstall = 0;
+				return;
+			}
+			if ((pIdentifyBuff->ConfigBitInfo & 0x1f00)==0) {
+				// Direct access device
+				pDeviceInfo->DeviceBlockSize = 512;
+			} else if ((pIdentifyBuff->ConfigBitInfo & 0x1f00)==0x0500) {
+				// CD-ROM device
+				pDeviceInfo->FG_DiscDevice = 1;
+				pDeviceInfo->DeviceBlockSize = 2048;
+			} else {
+				pDeviceInfo->FG_DeviceInstall = 0;
+				pDeviceInfo->DeviceBlockSize = 0;
+			}
+			pDeviceInfo->FG_Support48Bits = 0;
+			pDeviceInfo->FG_IdeExcept = 0;
+			((pDeviceInfo->Capacity).U64L).U64L_L = 0;
+			((pDeviceInfo->Capacity).U64L).U64L_H = 0;
+			if (pDeviceInfo->FG_DeviceInstall) {
+				// set device's IO mode
+				SetPIOfeature(pDeviceInfo,pIdentifyBuff,_MAX_PIO_MODE);
+				if (pIdentifyBuff->FG_ValidMap & 0x0004) {
+					SetUltrafeature(pDeviceInfo,pIdentifyBuff,_ULTRA_DMA33);
+				}
+				if (	  (pIdentifyBuff->Capability & 0x0100) 
+					&&(pIdentifyBuff->MultiWordDMASupport&0x07)
+					&&(pDeviceInfo->DMA_Mode==0)
+				   ) {
+					// set multiword DMA 
+					SetDMAfeature(pDeviceInfo,pIdentifyBuff,0x0F);
+				}
+				pDeviceInfo->FG_IdeExcept		=	0;
+			} // end of pHardDisk->HddFlag !=0
+			return;
+		} // end of ATAPI device confirm
+	} // end of send A1 command
+	pDeviceInfo->FG_DeviceInstall = 0;
+	return;
+}
+//========================================================================
+static void ExecuteIdeATAPI(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_DeviceInfo pCdRomInfo;
+	P_WorkingTable pWorkingTable;
+	Scsi_Cmnd *pScsiCmd;
+	
+	pWorkingTable = pIdeChannel->pCurRequest;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pCdRomInfo = pWorkingTable->pDevice;
+	pIdeChannel = pCdRomInfo->pChannel;
+	ConvertCmdATAPI(pWorkingTable);
+	if (	(pScsiCmd->cmnd[0] == READ_6) ||
+		(pScsiCmd->cmnd[0] == READ_10) ||
+		(pScsiCmd->cmnd[0] == WRITE_6) ||
+		(pScsiCmd->cmnd[0] == WRITE_10) ||
+		(pScsiCmd->cmnd[0] == ATAPI_READ_CD) ||
+		(pScsiCmd->cmnd[0] == ATAPI_WRITE_CONTINUE)
+	   ) {
+		if (pCdRomInfo->DMA_Mode) {
+			// DO DMA I/O
+			BuildPrdTable(pHwDeviceExtension,pWorkingTable,pWorkingTable->pMailBox);
+			DoDmaATAPIXfer(pWorkingTable);
+			if (pScsiCmd->result == SAM_STAT_CHECK_CONDITION) {
+				RestoreCmdATAPI(pWorkingTable);
+			}
+		} else {
+			// DO PIO I/O
+			DoPioATAPIXfer(pWorkingTable);
+			if (pScsiCmd->result == SAM_STAT_CHECK_CONDITION) {
+				RestoreCmdATAPI(pWorkingTable);
+			}
+		}
+	} else {
+		DoPioATAPIXfer(pWorkingTable);
+		if (pScsiCmd->result == SAM_STAT_CHECK_CONDITION) {
+			RestoreCmdATAPI(pWorkingTable);
+		}
+	}
+	return;
+}
+//===================================================================================================
+static void RestoreCmdATAPI(P_WorkingTable pWorkingTable)
+{
+	P_DeviceInfo pCdRomInfo;
+	Scsi_Cmnd *pScsiCmd;
+	int i;
+	
+	pCdRomInfo	= pWorkingTable->pDevice;
+	pScsiCmd		= pWorkingTable->pWorkingScsiCmd;
+	switch (pScsiCmd->cmnd[0]) {
+	case ATAPI_READ_CD:
+		if (	  (pWorkingTable->OrgCmnd[0] == READ_10)
+			||(pWorkingTable->OrgCmnd[0] == 0xD8)
+		   ) {
+			// restore cdb
+			for (i = 0 ; i < 12 ; i++) {
+				pScsiCmd->cmnd[i] = pWorkingTable->OrgCmnd[i];
+			}
+		}
+		break;
+/*
+	case 0x46:
+		for (i = 0 ; i < 12 ; i++) {
+			pScsiCmd->cmnd[i] = pWorkingTable->OrgCmnd[i];
+		}
+		// restore SRB's DataBuffer
+		pWorkingTable->request_buffer  = pWorkingTable->pOrgRequesrBuff;
+		pWorkingTable->request_bufflen = pWorkingTable->pOrgRequestBuffLen;
+		pWorkingTable->use_sg      = pWorkingTable->old_use_sg;
+		break;
+*/
+	case MODE_SENSE_10:
+		if (pWorkingTable->OrgCmnd[0] == MODE_SENSE) {
+			// restore cdb
+			for (i = 0 ; i < 12 ; i++) {
+				pScsiCmd->cmnd[i] = pWorkingTable->OrgCmnd[i];
+			}
+			// restore SRB's DataBuffer
+			pWorkingTable->request_buffer  = pWorkingTable->pOrgRequesrBuff;
+			pWorkingTable->request_bufflen = pWorkingTable->pOrgRequestBuffLen;
+			pWorkingTable->use_sg 	 =pWorkingTable->old_use_sg;
+//			pScsiCmd->use_sg          = pWorkingTable->use_sg;
+		} else {
+			// reset SRB's DataBuffer
+			pWorkingTable->request_buffer  = pWorkingTable->pOrgRequesrBuff;
+			pWorkingTable->request_bufflen = pWorkingTable->pOrgRequestBuffLen;
+			pWorkingTable->use_sg      = pWorkingTable->old_use_sg;
+		}
+		pWorkingTable->OrgCmnd[0]=0;
+		break;
+	case MODE_SELECT_10:
+		for (i = 0 ; i < 12 ; i++) {
+			pScsiCmd->cmnd[i] = pWorkingTable->OrgCmnd[i];
+		}
+		// reset SRB's DataBuffer
+		pWorkingTable->request_buffer  = pWorkingTable->pOrgRequesrBuff;
+		pWorkingTable->request_bufflen = pWorkingTable->pOrgRequestBuffLen;
+		pWorkingTable->use_sg      = pWorkingTable->old_use_sg;
+		pWorkingTable->OrgCmnd[0] = 0;
+		break;
+	case 0xB9:
+	case 0xBA:
+		for (i = 0 ; i < 12 ; i++) {
+			pScsiCmd->cmnd[i] = pWorkingTable->OrgCmnd[i];
+		}
+		break;
+	}
+	return;
+}
+//===================================================================================================
+static void DoPioATAPIXfer(P_WorkingTable pWorkingTable)
+{
+	P_DeviceInfo pCdRomInfo = pWorkingTable->pDevice;
+	P_Channel pIdeChannel = pCdRomInfo->pChannel;
+	Scsi_Cmnd *pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	int i,j;
+	unsigned short IdeCommand;
+	unsigned char status;
+
+	// make sure the IDE bus is free
+	outb(pCdRomInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	udelay(200);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	if (  (status == 0x7F) || (status & 0x80)   ) {
+		return;
+	}
+	outb(0,pIdeChannel->IdePortP1XX + 0x0001);		// PIO transfer
+	outb(0xFF,pIdeChannel->IdePortP1XX + 0x0004);	// no byte count limit
+	outb(0xFE,pIdeChannel->IdePortP1XX + 0x0005);
+	outb(pCdRomInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	outb(0xA0,pIdeChannel->IdePortP1XX + 0x0007);
+	for (i = 0 ; i < 250000 ; j++) {
+		// wait drq income with 2.5 S
+		status = inb( pIdeChannel->IdePortP1XX + 0x0007);
+		if ((status & 0x80) == 0) {
+			if (status & 0x08) {
+				break;
+			}
+		}
+		udelay(10);
+		cpu_relax();
+	}
+	if ((status & 0x88) == 0x08) {
+		do {
+			status = inb(pIdeChannel->IdePortP1XX + 0x0002);
+		} while ((status & 0x03) != 0x01);
+		// send CDB
+		for (i = 0 ; i < 12 ; i+=2) {
+			IdeCommand = ((((unsigned short)(pScsiCmd->cmnd[i+1])) << 8) & 0xFF00)+
+				     ((((unsigned short)(pScsiCmd->cmnd[i]  ))     ) & 0x00FF);
+			outw(IdeCommand,pIdeChannel->IdePortP1XX);
+		}
+		pWorkingTable->FG_DoIoByDMA = 0;
+		return;
+	}
+	// DRQ NOT READY
+	pCdRomInfo->FG_InternalError = 1;
+	pCdRomInfo->SenseKey = NOT_READY;
+	pCdRomInfo->SenseAsc = 0x00;
+	pCdRomInfo->SenseAscQ = 0x00;
+	pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+	return;
+}
+//===================================================================================================
+static void DoDmaATAPIXfer(P_WorkingTable pWorkingTable)
+{
+	P_DeviceInfo pCdRomInfo = pWorkingTable->pDevice;
+	P_Channel pIdeChannel = pCdRomInfo->pChannel;
+	Scsi_Cmnd *pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	int i,j;
+	unsigned short IdeCommand;
+	unsigned char status,dma_cmd;
+
+	// make sure the IDE bus is free
+	outb(pCdRomInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	udelay(100);
+	status = inb(pIdeChannel->IdePortP1XX + 0x0007);
+	if (  (status == 0x7F) || (status & 0x80)   ) {
+		return;
+	}
+	outb(0x01,pIdeChannel->IdePortP1XX + 0x0001);	// DMA transfer
+	outb(0xFF,pIdeChannel->IdePortP1XX + 0x0004);// no byte count limit
+	outb(0xFF,pIdeChannel->IdePortP1XX + 0x0005);
+	outb(pCdRomInfo->HD_V1X6,pIdeChannel->IdePortP1XX + 0x0006);
+	outb(0xA0,pIdeChannel->IdePortP1XX + 0x0007);
+	for (i = 0 ; i < 250000 ; j++) {
+		// wait drq income with 2.5 S
+		status = inb( pIdeChannel->IdePortP1XX + 0x0007);
+		if ((status & 0x80) == 0) {
+			if (status & 0x08) {
+				break;
+			}
+		}
+		udelay(10);
+		cpu_relax();
+	}
+	if ((status & 0x88) == 0x08) {
+		do {
+			status = inb(pIdeChannel->IdePortP1XX + 0x0002);
+		}
+		while ((status & 0x03) != 0x01);
+		switch(pScsiCmd->cmnd[0]) {
+		case READ_6:
+		case READ_10:
+		case ATAPI_READ_CD:
+			dma_cmd = 0x09;	// DMA read
+			break;
+		default:
+			dma_cmd = 0x01;	// DMA write
+			break;
+		}
+		// STOP DMA
+		outb((dma_cmd&0x08),(pIdeChannel->IdePortPSFF));
+		// send CDB
+		for (i = 0 ; i < 12 ; i+=2) {
+			IdeCommand = ((((unsigned short)(pScsiCmd->cmnd[i+1])) << 8) & 0xFF00)+
+				     ((((unsigned short)(pScsiCmd->cmnd[i]  ))     ) & 0x00FF);
+			outw(IdeCommand,pIdeChannel->IdePortP1XX);
+		}
+		outl(pWorkingTable->LmailBox,pIdeChannel->IdeRegPrdTable);	// set PRD table
+		// START DMA
+		outb(dma_cmd,(pIdeChannel->IdePortPSFF));
+		pWorkingTable->FG_DoIoByDMA = 1;
+		return;
+	}
+	// DRQ NOT READY
+	pCdRomInfo->FG_InternalError = 1;
+	pCdRomInfo->SenseKey = NOT_READY;
+	pCdRomInfo->SenseAsc = 0x00;
+	pCdRomInfo->SenseAscQ = 0x00;
+	pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+	return;
+}
+//========================================================================
+static void CdRomInterrupt(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_WorkingTable pWorkingTable = pIdeChannel->pCurRequest;
+	P_DeviceInfo pCdRomInfo = pWorkingTable->pDevice;
+	Scsi_Cmnd *pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	struct scatterlist *sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+	PUINQUIRYDATA pInquirybuf;
+	unsigned long km_flags;
+	unsigned char *pBuf,*km_buffer;
+	unsigned char *SrbDataBuffer,*SrbExtOriginalBuffer;
+	int i,km_sg_used = 0;
+	unsigned short word,TransferBlock,sg_len,BlockLen,LastWord;
+	unsigned char port_status;
+#if __LITTLE_ENDIAN
+#else
+	u16 temp16;
+#endif
+
+	km_buffer = NULL;
+	km_flags = 0;
+	port_status = inb(pIdeChannel->IdePortP3XX) & 0xE9;
+	if (port_status & 0x01) {
+		// error bit assert
+		printk("ide command %x end chk status %x\n",pScsiCmd->cmnd[0],port_status);
+		pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+	} else if (port_status & 0x08) {
+		// drq assert
+		port_status   = inb(pIdeChannel->IdePortP1XX + 0x0002);
+		TransferBlock =  ((((unsigned short)(inb(pIdeChannel->IdePortP1XX + 0x0005)))<<8) & 0xFF00)+
+				((((unsigned short)(inb(pIdeChannel->IdePortP1XX + 0x0004)))   ) & 0x00FF);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+		if (	  ((pScsiCmd->sc_data_direction & SCSI_DATA_NONE) == SCSI_DATA_READ)
+			||(	  ((pScsiCmd->sc_data_direction & SCSI_DATA_NONE) == SCSI_DATA_UNKNOWN)
+				&&((port_status & 0x02) == 0x02)
+		   	 )
+		   ) {
+#else
+		if ((port_status & 0x02) == 0x02) {
+#endif
+			// read data form device
+			if (pWorkingTable->use_sg) {
+				sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+				sg_list += pWorkingTable->sg_offset;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+				pBuf = sg_list->address + pWorkingTable->sg_data_offset;
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+				pBuf = km_buffer;
+				pBuf += pWorkingTable->sg_data_offset;
+#endif
+				sg_len  = sg_list->length - pWorkingTable->sg_data_offset;
+				if (TransferBlock > pWorkingTable->DataCounter) {
+					word = pWorkingTable->DataCounter;
+				} else {
+					word = TransferBlock;
+				}
+				TransferBlock -= word;
+				while(word) {
+					if (sg_len >= word) {
+						for (i = 0 ; i < (word/2) ; i++) {
+#if __LITTLE_ENDIAN
+							*((unsigned short *)pBuf) = inw(pIdeChannel->IdePortP1XX);
+#else
+							temp16 = inw(pIdeChannel->IdePortP1XX);
+							*pBuf = (unsigned char)temp16;
+							*(pBuf+1) = (unsigned char)(temp16 >> 8);
+#endif							
+							pBuf += 2;
+						}
+					//	printk("word %d cnt %x TransferBlock %x datacnt %x\n",word,pWorkingTable->sg_offset,TransferBlock,pWorkingTable->DataCounter);
+						pWorkingTable->sg_data_offset += word;
+						word = 0;
+					} else {
+						word -= sg_len;
+						for (i = 0 ; i < (sg_len/2) ; i++) {
+#if __LITTLE_ENDIAN
+							*((unsigned short *)pBuf) = inw(pIdeChannel->IdePortP1XX);
+#else
+							temp16 = inw(pIdeChannel->IdePortP1XX);
+							*pBuf = (unsigned char)temp16;
+							*(pBuf+1) = (unsigned char)(temp16 >> 8);
+#endif							
+							pBuf += 2;
+						}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+						sg_list++;
+						pBuf = sg_list->address;
+#else
+						kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+#ifdef KERNEL_V2625
+						sg_list = sg_next(sg_list);
+#else
+						sg_list++;
+#endif
+						km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//						km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+						pBuf = km_buffer;
+#endif
+						sg_len = sg_list->length;
+						pWorkingTable->sg_offset++;
+						pWorkingTable->sg_data_offset = 0;
+					}
+				}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+				kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+				local_irq_restore(km_flags);
+#endif
+			//	printk("TransferBlock %x\n",TransferBlock);
+				for (i = 0 ; i < (TransferBlock/2) ; i++) {
+					inw(pIdeChannel->IdePortP1XX);
+			//		printk("temp %x\n",temp);
+				}
+				/*
+				LastWord = TransferBlock%2;
+				if(LastWord){
+					inw(pIdeChannel->IdePortP1XX);
+				}
+*/
+			} else {
+				if (TransferBlock > pWorkingTable->DataCounter) {
+					if (pWorkingTable->DataCounter) {
+						for (i = 0 ; i < ((pWorkingTable->DataCounter)/2) ; i++) {
+#if __LITTLE_ENDIAN
+							*((unsigned short *)(pWorkingTable->pDataBufPtr)) = inw(pIdeChannel->IdePortP1XX);
+#else
+							temp16 = inw(pIdeChannel->IdePortP1XX);
+							*(pWorkingTable->pDataBufPtr) = (unsigned char)(temp16);
+							*((pWorkingTable->pDataBufPtr)+1) = (unsigned char)(temp16 >> 8);
+#endif						
+							pWorkingTable->pDataBufPtr += 2;
+						}
+						TransferBlock -= (unsigned short)(pWorkingTable->DataCounter);
+						pWorkingTable->DataCounter = 0;
+						
+						for (i = 0 ; i < (TransferBlock/2) ; i++) {
+							inw(pIdeChannel->IdePortP1XX);
+						}
+						LastWord = TransferBlock%2;
+						if(LastWord){
+							inw(pIdeChannel->IdePortP1XX);
+						}
+					}
+				} else {
+					for (i = 0 ; i < (TransferBlock/2) ; i++) {
+#if __LITTLE_ENDIAN
+						*((unsigned short *)(pWorkingTable->pDataBufPtr)) = inw(pIdeChannel->IdePortP1XX);
+#else
+						temp16 = inw(pIdeChannel->IdePortP1XX);
+						*(pWorkingTable->pDataBufPtr) = (unsigned char)(temp16);
+						*((pWorkingTable->pDataBufPtr)+1) = (unsigned char)(temp16 >> 8);
+#endif						
+						pWorkingTable->pDataBufPtr += 2;
+					}
+					pWorkingTable->DataCounter -= ((unsigned long)TransferBlock);
+					
+				}
+			}
+		} else {
+			// write data to device
+			if (pWorkingTable->use_sg) {
+				sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+				sg_list += pWorkingTable->sg_offset;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+				pBuf  = sg_list->address + pWorkingTable->sg_data_offset;
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+				pBuf = km_buffer;
+				pBuf += pWorkingTable->sg_data_offset;
+#endif
+				sg_len = sg_list->length - pWorkingTable->sg_data_offset;
+				if (TransferBlock > pWorkingTable->DataCounter) {
+					word = pWorkingTable->DataCounter;
+				} else {
+					word = TransferBlock;
+				}
+				TransferBlock -= word;
+				while(word) {
+					if (sg_len >= word) {
+						for (i = 0 ; i < (word/2) ; i++) {
+#if __LITTLE_ENDIAN
+							outw(*((unsigned short *)pBuf),pIdeChannel->IdePortP1XX);
+#else						
+							temp16 = ((((u16)(*pBuf)) << 8) & 0xFF00) + (((u16)(*(pBuf+1))) & 0x00FF);
+							outw(temp16,pIdeChannel->IdePortP1XX);
+#endif
+							pBuf += 2;
+						}
+						pWorkingTable->sg_data_offset += word;
+						word = 0;
+					} else {
+						word -= sg_len;
+						for (i = 0 ; i < (sg_len/2) ; i++) {
+#if __LITTLE_ENDIAN
+							outw(*((unsigned short *)pBuf),pIdeChannel->IdePortP1XX);
+#else						
+							temp16 = ((((u16)(*pBuf)) << 8) & 0xFF00) + (((u16)(*(pBuf+1))) & 0x00FF);
+							outw(temp16,pIdeChannel->IdePortP1XX);
+#endif
+							pBuf += 2;
+						}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+						sg_list++;
+						pBuf = sg_list->address;
+#else
+						kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+#ifdef KERNEL_V2625
+						sg_list = sg_next(sg_list);
+#else
+						sg_list++;
+#endif
+						km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//						km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+						pBuf = km_buffer;
+#endif
+						sg_len  = sg_list->length;
+						pWorkingTable->sg_offset++;
+						pWorkingTable->sg_data_offset = 0;
+					}
+				}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+				kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+				local_irq_restore(km_flags);
+#endif
+				for (i = 0 ; i < (TransferBlock/2) ; i++) {
+					outw(0,pIdeChannel->IdePortP1XX);
+				}
+/*
+				LastWord = TransferBlock%2;
+				if(LastWord){
+					outw(0,pIdeChannel->IdePortP1XX);
+				}
+*/
+			} else {
+				if (TransferBlock > pWorkingTable->DataCounter) {
+					if (pWorkingTable->DataCounter) {
+						for (i = 0 ; i < ((pWorkingTable->DataCounter)/2) ; i++) {
+#if __LITTLE_ENDIAN
+							outw(*((unsigned short *)(pWorkingTable->pDataBufPtr)),pIdeChannel->IdePortP1XX);
+#else						
+							temp16 = ((((u16)(*pWorkingTable->pDataBufPtr)) << 8) & 0xFF00) + 
+								  (((u16)(*((pWorkingTable->pDataBufPtr)+1))) & 0x00FF);
+							outw(temp16,pIdeChannel->IdePortP1XX);
+#endif
+							pWorkingTable->pDataBufPtr += 2;
+						}
+						TransferBlock -= (unsigned short)(pWorkingTable->DataCounter);
+						pWorkingTable->DataCounter = 0;
+					}
+					for (i = 0 ; i <= TransferBlock ; i++) {
+						outw(0,pIdeChannel->IdePortP1XX);
+					}
+/*
+					LastWord = TransferBlock%2;
+					if(LastWord){
+						outw(0,pIdeChannel->IdePortP1XX);
+					}
+*/
+				} else {
+					for (i = 0 ; i < (TransferBlock/2) ; i++) {
+#if __LITTLE_ENDIAN
+						outw(*((unsigned short *)(pWorkingTable->pDataBufPtr)),pIdeChannel->IdePortP1XX);
+#else						
+						temp16 = ((((u16)(*pWorkingTable->pDataBufPtr)) << 8) & 0xFF00) + 
+							  (((u16)(*((pWorkingTable->pDataBufPtr)+1))) & 0x00FF);
+						outw(temp16,pIdeChannel->IdePortP1XX);
+#endif
+						pWorkingTable->pDataBufPtr += 2;
+					}
+					pWorkingTable->DataCounter -= ((unsigned long)TransferBlock);
+				}
+			}
+		}
+	} else {
+	//	printk("ide command %x end\n",pScsiCmd->cmnd[0]);
+		// complete
+		switch (pScsiCmd->cmnd[0]) {
+		case REQUEST_SENSE:
+			sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+			if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+				pBuf  = sg_list->address;
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+				pBuf = km_buffer;
+#endif
+			} else {
+				pBuf = pWorkingTable->request_buffer;
+			}
+			if ((pBuf[2] == 0x06) && (pBuf[12]==0x28)) {
+				pCdRomInfo->DeviceBlockSize = 2048;
+			} else if ((pBuf[2] == 0x02) && (pBuf[12]==0x3a)) {
+					pCdRomInfo->DeviceBlockSize = 2048;
+			}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+			if (pWorkingTable->use_sg) {
+				kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+				local_irq_restore(km_flags);
+			}
+#endif
+			break;
+		case INQUIRY:
+			sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+			if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+				pBuf = sg_list->address;
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+				pBuf = km_buffer;
+#endif
+			} else {
+				pBuf = pWorkingTable->request_buffer;
+			}
+			pInquirybuf = (PUINQUIRYDATA)pBuf;
+			pInquirybuf->VersionInfo &= 0xF8;
+			pInquirybuf->VersionInfo |= 0x02;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+			if (pWorkingTable->use_sg) {
+				kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+				local_irq_restore(km_flags);
+			}
+#endif
+			break;
+/*
+		case 0x46:
+			SrbDataBuffer = pWorkingTable->request_buffer;
+			sg_list = (struct scatterlist *)(pWorkingTable->pOrgRequesrBuff);
+			if (pWorkingTable->old_use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+				SrbExtOriginalBuffer  = sg_list->address;
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+				SrbExtOriginalBuffer = km_buffer;
+#endif
+			} else {
+				SrbExtOriginalBuffer = pWorkingTable->pOrgRequesrBuff;
+			}
+			for (i = 0 ; i < pWorkingTable->request_bufflen ; i++) {
+				*SrbExtOriginalBuffer = *SrbDataBuffer;
+				SrbExtOriginalBuffer++;
+				SrbDataBuffer++;
+			}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+			if (pWorkingTable->old_use_sg) {
+				kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+				local_irq_restore(km_flags);
+			}
+#endif
+			break;
+*/
+		case MODE_SENSE_10: //xx7
+			SrbDataBuffer = pWorkingTable->request_buffer;
+			sg_list = (struct scatterlist *)(pWorkingTable->pOrgRequesrBuff);
+			km_sg_used = 0;
+			if (pWorkingTable->old_use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+				SrbExtOriginalBuffer = sg_list->address;
+#else
+				local_irq_save(km_flags);
+				km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//				km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+				SrbExtOriginalBuffer = km_buffer;
+				km_sg_used = 1;
+#endif
+			} else {
+				SrbExtOriginalBuffer = pWorkingTable->pOrgRequesrBuff;
+			}
+			BlockLen = pCdRomInfo->DeviceBlockSize;
+			word = ((((unsigned short)SrbDataBuffer[0]) << 8) & 0xff00)+
+			       ((((unsigned short)SrbDataBuffer[1])     ) & 0x00ff);
+			if (pWorkingTable->OrgCmnd[0] == MODE_SENSE) {
+				// rebuild mode parameter header
+				SrbExtOriginalBuffer[0] = word - 3;		// data length	
+				SrbExtOriginalBuffer[1] = SrbDataBuffer[2];	// medium type
+				SrbExtOriginalBuffer[2] = 0;			// device-specific parameter
+				SrbExtOriginalBuffer[3] = 0; 			// block descriptor length
+				i=4;
+				// rebuild block descriptor
+				if ((pWorkingTable->OrgCmnd[1] & 0x08) == 0) {
+					SrbExtOriginalBuffer[0] += 8;
+					// set block descriptor length
+					SrbExtOriginalBuffer[3] = 8;
+					// build descriptor block
+					//SrbExtOriginalBuffer[4] = 0x83;
+					for (i = 4 ; i <= 8 ; i++) {
+						SrbExtOriginalBuffer[i] = 0;
+					}
+					SrbExtOriginalBuffer[9]  = (unsigned char)(BlockLen>>16);
+					SrbExtOriginalBuffer[10] = (unsigned char)(BlockLen>>8);
+					SrbExtOriginalBuffer[11] = (unsigned char)BlockLen;
+					if ((pWorkingTable->OrgCmnd[2] & 0xc0) == 0x40) {
+						// PC = 0x01
+						SrbExtOriginalBuffer[9]  = 0xFF;
+						SrbExtOriginalBuffer[10] = 0xFF;
+						SrbExtOriginalBuffer[11] = 0xFF;
+					}
+					i = 12;
+				}
+				SrbExtOriginalBuffer += (unsigned char)i;
+				SrbDataBuffer += 8;
+				// moving page list data
+				for (i = 0 ; i < (pWorkingTable->pOrgRequestBuffLen - 12) ; i++) {
+					*SrbExtOriginalBuffer = *SrbDataBuffer;
+					SrbExtOriginalBuffer++;
+					SrbDataBuffer++;
+				}
+			} else {
+				// MODE_SENSE_10
+				for (i = 0 ; i < word ; i++) {
+						SrbExtOriginalBuffer[i] = SrbDataBuffer[i];
+				}	
+				
+				if (	(((unsigned short)(pWorkingTable->request_bufflen)) > (word + 16)) &&
+						 ((pScsiCmd->cmnd[1] & 0x08) == 0)
+				   ) {
+					// host buffer > data + block descriptor length + head len
+					// and DBD bit = 0
+					word = word + 8;			// add block descriptor length
+					// rebuild parameter header
+					SrbExtOriginalBuffer[0] = (unsigned char)(word >> 8);			// data length	
+					SrbExtOriginalBuffer[1] = (unsigned char)word;	
+					for (i = 2 ; i <= 5 ; i++) {
+						SrbExtOriginalBuffer[i] = SrbDataBuffer[i];
+					}
+					SrbExtOriginalBuffer[6] = 0;
+					SrbExtOriginalBuffer[7] = 8;
+					word = word - 8;
+					// copy sense data
+					for (i = 0 ; i < word ; i++) {
+						SrbExtOriginalBuffer[i+16] = SrbDataBuffer[i+8];
+					}
+					// rebuild block descriptor
+					for (i = 8 ; i <= 12 ; i++) {
+						SrbExtOriginalBuffer[i] = 0;
+					}	
+					SrbExtOriginalBuffer[13] = (unsigned char)(BlockLen>>16);
+					SrbExtOriginalBuffer[14] = (unsigned char)(BlockLen>>8);
+					SrbExtOriginalBuffer[15] = (unsigned char)BlockLen;
+					if ((pWorkingTable->OrgCmnd[2] & 0xc0) == 0x40) {
+						SrbExtOriginalBuffer[13] = 0xFF;
+						SrbExtOriginalBuffer[14] = 0xFF;
+						SrbExtOriginalBuffer[15] = 0xFF;
+					}
+					pWorkingTable->OrgCmnd[0]=0;
+				} else {
+					word +=2; // total transfer length
+					if (word > pWorkingTable->request_bufflen) {
+						word = (unsigned short)(pWorkingTable->request_bufflen);
+					}
+					for (i = 0 ; i < word ; i++) {
+						SrbExtOriginalBuffer[i] = SrbDataBuffer[i];
+					}	
+				}
+				for (i = 0 ; i < 12 ; i++) {
+					pScsiCmd->cmnd[i] = pWorkingTable->OrgCmnd[i];
+				}
+
+			}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+			if (km_sg_used) {
+				kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+				local_irq_restore(km_flags);
+			}
+#endif
+			break;
+		}
+		pScsiCmd->result = SAM_STAT_GOOD;
+	}
+	if (pScsiCmd->result != STATUS_PENDING) {
+		
+		if (pWorkingTable->FG_DoIoByDMA) {
+			if (pWorkingTable->use_sg) {
+				sg_list = (struct scatterlist *)pWorkingTable->request_buffer;
+
+			        pci_unmap_sg(pHwDeviceExtension->pPciDev,
+						sg_list,
+						pWorkingTable->use_sg,
+# if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+						scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+# else
+						pScsiCmd->sc_data_direction
+# endif
+					   );
+
+			} else {
+				pci_unmap_single(pHwDeviceExtension->pPciDev,
+						pWorkingTable->pDmaSingleMapAddr,
+						pWorkingTable->request_bufflen,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+						scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+#else
+						pScsiCmd->sc_data_direction
+#endif
+					       );
+			}
+		}
+		RestoreCmdATAPI(pWorkingTable);
+	}
+	return;
+}
+//=======================================================================================
+static int SoftwareReset(P_Channel pSataChannel,unsigned char PMx)
+{
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	u32 ci_map;
+
+	if ((inb(pSataChannel->BaseIoPort + 0x0028) & 0x0F) != 0x03) {
+		// physical not ready
+		return 0;
+	}
+	//===============================================================================
+	pCommandHead  = pSataChannel->pCommandPtr->pCommandHead + MAX_COMMAND_QUEUE_CH;
+	pCommandTable = pSataChannel->pCommandPtr->pCommandTable + MAX_COMMAND_QUEUE_CH;
+	ci_map = (0x00000001 << MAX_COMMAND_QUEUE_CH);
+	//===============================================================================
+	pCommandHead->PortMultiplier = (PMx & 0x0F);
+	pCommandHead->CommandFISLen = 0x05;
+	pCommandHead->ClearBusy = 1;
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.PortMultiplier = (PMx & 0x0F);	// Port Multiplier
+	pCommandTable->CommandFIS.FIS_Flag = 0;
+	pCommandTable->CommandFIS.P3x6 = 0x04;			// RST bit = 1
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	while (inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) {
+		udelay(100);
+	}
+	//===============================================================================
+	udelay(10);
+	//===============================================================================
+	pCommandHead->ClearBusy = 0;
+	pCommandTable->CommandFIS.P3x6 = 0;	// RST bit = 0
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	while (inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) {
+		udelay(100);
+	}
+	//===============================================================================
+	udelay(100);
+	outb(inb(pSataChannel->BaseIoPort + 0x0010),pSataChannel->BaseIoPort + 0x0010);	// clear error
+	return 1;
+}
+//=======================================================================================
+static int PMxReset(P_Channel pSataChannel,unsigned char PMx)
+{
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	int i;
+	unsigned int signature,ci_map;
+	unsigned char status,status74;
+
+	//===============================================================================
+	// CLOverride force BSY,DRQ clear to 0
+	//===============================================================================
+	status = inb(pSataChannel->BaseIoPort + 0x0018) | 0x08;
+	outb(status,pSataChannel->BaseIoPort + 0x0018);
+	while((inb(pSataChannel->BaseIoPort + 0x0018) & 0x08) != 0) {
+		udelay(100); // delay 1ms
+		cpu_relax();
+	}
+	//===============================================================================
+	pCommandHead  = pSataChannel->pCommandPtr->pCommandHead  + MAX_COMMAND_QUEUE_CH;
+	pCommandTable = pSataChannel->pCommandPtr->pCommandTable + MAX_COMMAND_QUEUE_CH;
+	ci_map = (0x00000001 << MAX_COMMAND_QUEUE_CH);
+	//===============================================================================
+	pCommandHead->PortMultiplier = 0x0F;
+	pCommandHead->CommandFISLen = 0x05;
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.PortMultiplier = 0x0F;		// Port Multiplier
+	pCommandTable->CommandFIS.FIS_Flag = 1;
+	pCommandTable->CommandFIS.P1x1 = 0x02;
+	pCommandTable->CommandFIS.P1x2 = 0x01; // DET = 1
+	pCommandTable->CommandFIS.P1x3 = 0;
+	pCommandTable->CommandFIS.P1x4 = 0;
+	pCommandTable->CommandFIS.P1x5 = 0;
+	pCommandTable->CommandFIS.P1x6 = PMx;
+	pCommandTable->CommandFIS.Command = 0xE8;		// Write Port Multiplier
+	//=========================================================================================
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	while((inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) != 0) {
+		// wait for CI bit clear
+		udelay(100);
+		cpu_relax();
+	}
+	outb(inb(pSataChannel->BaseIoPort + 0x0010),pSataChannel->BaseIoPort + 0x0010);	//clear interrupt
+	//===============================================================================
+	pCommandTable->CommandFIS.P1x2 = 0; // DET = 0
+	//===============================================================================
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	while((inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) != 0) {
+		// wait for CI bit clear
+		udelay(100);
+	}
+	outb(inb(pSataChannel->BaseIoPort + 0x0010),pSataChannel->BaseIoPort + 0x0010);	//clear interrupt
+	status74 =  inb(pSataChannel->BaseIoPort + 0x0074);		// backup PM bit
+	outb((status74 | 0x04),pSataChannel->BaseIoPort + 0x0074);	// disable PM BIT bit 1,enable PASS D2H bit2
+	for (i = 0 ; i < 10000 ; i++) {
+		//===============================================================================
+		pCommandTable->CommandFIS.P1x1 = 0;
+		pCommandTable->CommandFIS.P1x2 = 0;
+		pCommandTable->CommandFIS.P1x3 = 0;
+		pCommandTable->CommandFIS.P1x4 = 0;
+		pCommandTable->CommandFIS.P1x5 = 0;
+		pCommandTable->CommandFIS.P1x6 = PMx;
+		pCommandTable->CommandFIS.Command = 0xE4;
+		//===============================================================================
+		outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+		while((inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) != 0) {
+			// wait for CI bit clear
+			udelay(100);
+		}
+		outb(inb(pSataChannel->BaseIoPort + 0x0010),pSataChannel->BaseIoPort + 0x0010);	//clear interrupt
+		//===============================================================================
+		status = inb(pSataChannel->BaseIoPort + 0x0024) & 0x0F;
+		if (status == 0x03) {
+			// physical ready ===================================================
+			pCommandTable->CommandFIS.P1x1 = 0x01;	// clear all error flag
+			pCommandTable->CommandFIS.P1x2 = 0xFF;
+			pCommandTable->CommandFIS.P1x3 = 0xFF;
+			pCommandTable->CommandFIS.P1x4 = 0xFF;
+			pCommandTable->CommandFIS.P1x5 = 0xFF;
+			pCommandTable->CommandFIS.Command = 0xE8;
+			//=======================================================================
+			outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+			while((inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) != 0) {
+				// wait for CI bit clear
+				udelay(100);
+			}
+			while((inb(pSataChannel->BaseIoPort + 0x0010) & 0x01) == 0) {
+				// wait D2H interrupt
+				udelay(100);
+			}
+			for (i = 0 ; i < 10000 ; i++) {
+				// wait signature
+				signature = inl(pSataChannel->BaseIoPort + 0x0024);
+				if ((signature == 0x00000101) || (signature == 0xEB140101)) {
+					// HDD or ATAPI send D2H back
+					break;
+				}
+				udelay(100);
+			}
+			//=======================================================================
+			outb(inb(pSataChannel->BaseIoPort + 0x0010),pSataChannel->BaseIoPort + 0x0010);	//clear interrupt
+			outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+			return 1;
+		}
+		udelay(100);
+	}
+	outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+	return 0;
+}
+//=======================================================================================
+static void PortMultiplierEnumerate(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pSataChannel,P_DeviceInfo pDeviceInfo)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	int i;
+	unsigned int ci_map,status;
+	unsigned char PM_FanOut;
+
+	//===============================================================================
+	pCommandHead = pSataChannel->pCommandPtr->pCommandHead  + MAX_COMMAND_QUEUE_CH;
+	pCommandTable = pSataChannel->pCommandPtr->pCommandTable + MAX_COMMAND_QUEUE_CH;
+	ci_map = (0x00000001 << MAX_COMMAND_QUEUE_CH);
+	//===============================================================================
+	pCommandHead->PortMultiplier = 0x0F;
+	pCommandHead->CommandFISLen = 0x05;
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.PortMultiplier = 0x0F; // Port Multiplier
+	pCommandTable->CommandFIS.FIS_Flag = 1;
+	pCommandTable->CommandFIS.P1x1 = 0x02;
+	pCommandTable->CommandFIS.P1x2 = 0;
+	pCommandTable->CommandFIS.P1x3 = 0;
+	pCommandTable->CommandFIS.P1x4 = 0;
+	pCommandTable->CommandFIS.P1x5 = 0;
+	pCommandTable->CommandFIS.P1x6 = 0x0F;
+	pCommandTable->CommandFIS.Command = 0xE4; // Read Port Multiplier
+	//=========================================================================================
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	while (inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) {
+		udelay(100);
+		cpu_relax();
+	}
+	outb(inb(pSataChannel->BaseIoPort + 0x0010),pSataChannel->BaseIoPort + 0x0010);	// clear interrupt
+	//=========================================================================================
+	PM_FanOut = inb(pSataChannel->BaseIoPort + 0x0024) & 0x0F;
+	if (PM_FanOut > MAX_SATA_HDD) {
+		PM_FanOut = MAX_SATA_HDD;
+	}
+	pSataChannel->MaxDeviceCount = PM_FanOut;
+	// send reset device command to device
+	for (i = 0 ; i < pSataChannel->MaxDeviceCount ; i++) {
+		if (PMxReset(pSataChannel,(unsigned char)i)) {
+			status = inl(pSataChannel->BaseIoPort + 0x0024);
+			if (status == 0xEB140101) {
+				// ATAPI Device
+				SendIdentifyCommand(pHwDeviceExtension,pDeviceInfo,i,0xA1);
+			} else if (status == 0x00000101) {
+				SendIdentifyCommand(pHwDeviceExtension,pDeviceInfo,i,0xEC);
+			}
+			pDeviceInfo->FG_OnSataChannel = 1;
+		}
+		pDeviceInfo++;
+	}
+	return;
+}
+//=======================================================================================
+static void SendIdentifyCommand(PHW_DEVICE_EXTENSION DeviceExtension,P_DeviceInfo pDeviceInfo,int PMx,unsigned char IdenCmd)
+{
+#if __LITTLE_ENDIAN
+#else
+	unsigned char *pTemp;
+#endif	
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_Channel pSataChannel;
+	PUIdentify pIdentifyBuff;
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	P_ReciveFIS pReciveFIS;
+	int i;
+	unsigned int ci_map;
+	unsigned char Ultramode,UltraMap;
+	unsigned char Error_status,status74;
+
+	pDeviceInfo->FG_DeviceInstall = 0;
+	pSataChannel = pDeviceInfo->pChannel;
+	if ((inb(pSataChannel->BaseIoPort + 0x0028) & 0x0F) != 0x03) {
+		// physical not ready
+		return;
+	}
+	pIdentifyBuff = (PUIdentify)(pHwDeviceExtension->pIdentifyBuffer);
+	status74 = inb(pSataChannel->BaseIoPort + 0x0074);
+	pCommandHead  = pSataChannel->pCommandPtr->pCommandHead  + MAX_COMMAND_QUEUE_CH;
+	pCommandTable = pSataChannel->pCommandPtr->pCommandTable + MAX_COMMAND_QUEUE_CH;
+	pReciveFIS    = ((pSataChannel->pReciveFIS) + PMx);
+	ci_map = (0x00000001 << MAX_COMMAND_QUEUE_CH);
+	// Device presence detacted and physical ready,building Command Table
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.PortMultiplier = (PMx & 0x0F); // Port Multiplier
+	pCommandTable->CommandFIS.FIS_Flag = 1;
+	pCommandTable->CommandFIS.P1x6 = 0xE0;
+	pCommandTable->CommandFIS.Command = IdenCmd;
+	// building PTD table
+	pCommandTable->MailBox->BufAddressU = 0;
+#if __LITTLE_ENDIAN
+	pCommandTable->MailBox->BufAddress = pHwDeviceExtension->pDmaIdentifyBuffer;
+	pCommandTable->MailBox->DataLength = 0x80000200;		// 512 bytes
+#else
+	pCommandTable->MailBox->BufAddress = cpu_to_le32(pHwDeviceExtension->pDmaIdentifyBuffer);
+	pCommandTable->MailBox->DataLength = cpu_to_le32(0x80000200);		// 512 bytes
+#endif
+	// building Command List Entry
+	pCommandHead->PortMultiplier = (PMx & 0x0F);
+	pCommandHead->CommandFISLen = 0x05;
+	pCommandHead->PRDTL = 0;
+	pCommandHead->PRD_ByteCount = 0;
+	// issure command
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	for (i = 0 ; i < 1000 ; i++) {
+		// wait CI bit clear
+		if ((inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) == 0) {
+			// CI bit to be clear
+			break;
+		}
+		udelay(1000);
+		cpu_relax();
+	}
+	if (i >= 1000) {
+		// time out
+		outb(0x16,pSataChannel->BaseIoPort + 0x0018);
+		outb(0x17,pSataChannel->BaseIoPort + 0x0018);
+		outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+		return;
+	}
+	for (i = 0 ; i < 1000 ; i++) {
+		//wait 1s for D2H/PIO FIS
+		if (inb(pSataChannel->BaseIoPort + 0x0010) & 0x03) {
+			// got D2H register FIS/ got PIO setup FIS
+			break;
+		}
+		udelay(1000);
+		cpu_relax();
+	}
+	if (i >= 1000) {
+		// time out
+		outb(0x16,pSataChannel->BaseIoPort + 0x0018);
+		outb(0x17,pSataChannel->BaseIoPort + 0x0018);
+		outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+		return;
+	}
+	Error_status = pReciveFIS->Device2HostFIS.Status;
+	outb(0x03,pSataChannel->BaseIoPort + 0x0010); // clear interrupt
+	if (Error_status & 0x01) {
+		// Identify command error
+		outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+		return;
+	}
+#if __LITTLE_ENDIAN
+#else
+	for (i = 0 ; i < 256 ; i+=2) {
+		Ultramode = (pHwDeviceExtension->pIdentifyBuffer)[i];
+		(pHwDeviceExtension->pIdentifyBuffer)[i] = (pHwDeviceExtension->pIdentifyBuffer)[i + 1];
+		(pHwDeviceExtension->pIdentifyBuffer)[i+1] = Ultramode;
+	}
+#endif	
+	if ((pIdentifyBuff->FG_ValidMap & 0x0004) == 0) {
+		// not support ULTRA device
+		outb(status74,pSataChannel->BaseIoPort + 0x0074);	// restore Reg74
+		return;
+	}
+	pDeviceInfo->FG_DeviceInstall	 = 1;
+	pDeviceInfo->FG_PMId		 = (unsigned char)PMx;
+#if __LITTLE_ENDIAN
+#else
+	pIdentifyBuff->TotalLBA = ((pIdentifyBuff->TotalLBA >> 16) & 0x0000FFFF) +
+							((pIdentifyBuff->TotalLBA << 16) & 0xFFFF0000);
+#endif
+	((pDeviceInfo->Capacity).U64L).U64L_H = 0;
+	((pDeviceInfo->Capacity).U64C).U64C_L_HH = (u8)(pIdentifyBuff->TotalLBA >> 24);
+	((pDeviceInfo->Capacity).U64C).U64C_L_HL = (u8)(pIdentifyBuff->TotalLBA >> 16);
+	((pDeviceInfo->Capacity).U64C).U64C_L_LH = (u8)(pIdentifyBuff->TotalLBA >> 8);
+	((pDeviceInfo->Capacity).U64C).U64C_L_LL = (u8)(pIdentifyBuff->TotalLBA);
+#if __LITTLE_ENDIAN
+	for (i = 0 ; i < 40 ; i += 2) {
+		pDeviceInfo->ModelName[i] = pIdentifyBuff->ModelName[i+1];
+		pDeviceInfo->ModelName[i+1] = pIdentifyBuff->ModelName[i];
+	}
+	for (i = 0 ; i < 20 ; i += 2) {
+		pDeviceInfo->SerialNo[i] = pIdentifyBuff->SerialNo[i+1];
+		pDeviceInfo->SerialNo[i+1] = pIdentifyBuff->SerialNo[i];
+	}	
+	for (i = 0 ; i < 8 ; i += 2) {
+		pDeviceInfo->FirmWareRev[i] = pIdentifyBuff->FirmWareRev[i+1];
+		pDeviceInfo->FirmWareRev[i+1] = pIdentifyBuff->FirmWareRev[i];
+	}
+#else
+	for (i = 0 ; i < 20 ; i++) {
+		pDeviceInfo->SerialNo[i] = pIdentifyBuff->SerialNo[i];
+	}
+	for (i = 0 ; i < 40 ; i++) {
+		pDeviceInfo->ModelName[i] = pIdentifyBuff->ModelName[i];
+	}
+	for (i = 0 ; i < 8 ; i++) {
+		pDeviceInfo->FirmWareRev[i] = pIdentifyBuff->FirmWareRev[i];
+	}
+#endif
+	//=====================================================================================
+	// check 48 bit LBA capability
+	//=====================================================================================
+	if (IdenCmd == 0xEC) {
+#if __LITTLE_ENDIAN
+#else
+		pIdentifyBuff->LBA_48bits_High = ((pIdentifyBuff->LBA_48bits_High >> 16) & 0x0000FFFF) +
+							((pIdentifyBuff->LBA_48bits_High << 16) & 0xFFFF0000);
+		pIdentifyBuff->LBA_48bits_Low = ((pIdentifyBuff->LBA_48bits_Low >> 16) & 0x0000FFFF) +
+							((pIdentifyBuff->LBA_48bits_Low << 16) & 0xFFFF0000);
+#endif
+		if (pIdentifyBuff->Word83 & 0x0400) {
+			if ( 	((pIdentifyBuff->LBA_48bits_Low == 0) && (pIdentifyBuff->LBA_48bits_High == 0))||
+				((pIdentifyBuff->LBA_48bits_Low == 0xFFFFFFFF) && (pIdentifyBuff->LBA_48bits_High == 0xFFFFFFFF))
+			   ) {
+				pDeviceInfo->FG_Support48Bits = 0;
+			} else {
+				pDeviceInfo->FG_Support48Bits = 1;
+				((pDeviceInfo->Capacity).U64C).U64C_H_HH = (u8)(pIdentifyBuff->LBA_48bits_High >> 24);
+				((pDeviceInfo->Capacity).U64C).U64C_H_HL = (u8)(pIdentifyBuff->LBA_48bits_High >> 16);
+				((pDeviceInfo->Capacity).U64C).U64C_H_LH = (u8)(pIdentifyBuff->LBA_48bits_High >> 8);
+				((pDeviceInfo->Capacity).U64C).U64C_H_LL = (u8)(pIdentifyBuff->LBA_48bits_High);
+				((pDeviceInfo->Capacity).U64C).U64C_L_HH = (u8)(pIdentifyBuff->LBA_48bits_Low >> 24);
+				((pDeviceInfo->Capacity).U64C).U64C_L_HL = (u8)(pIdentifyBuff->LBA_48bits_Low >> 16);
+				((pDeviceInfo->Capacity).U64C).U64C_L_LH = (u8)(pIdentifyBuff->LBA_48bits_Low >> 8);
+				((pDeviceInfo->Capacity).U64C).U64C_L_LL = (u8)(pIdentifyBuff->LBA_48bits_Low);
+			}
+		} else {
+			pDeviceInfo->FG_Support48Bits = 0;
+		}
+		pDeviceInfo->MaxQueueDepth = (unsigned char)(pIdentifyBuff->QueueDepth & 0x000F) + 1;
+#if DISK_NCQ_CHECK
+	printk("SATA1 support : %d ,SATA2 support : %d ,NCQ supported : %d ,QueueDepth : %d\n\r",
+			pIdentifyBuff->FG_SATA1_support,pIdentifyBuff->FG_SATA2_support,
+						pIdentifyBuff->FG_NcqSupport,pIdentifyBuff->QueueDepth);
+#endif
+#if NCQ_SUPPORT
+		if (	(pDeviceInfo->MaxQueueDepth > 1) &&
+			(pIdentifyBuff->FG_NcqSupport) &&
+			(pIdentifyBuff->FG_SATA2_support)
+		   ) {
+			pDeviceInfo->FG_QueueSupported = 1;
+			if (pDeviceInfo->MaxQueueDepth > MAX_COMMAND_QUEUE_CH) {
+				pDeviceInfo->MaxQueueDepth = MAX_COMMAND_QUEUE_CH;
+			}
+		} else {
+			pDeviceInfo->FG_QueueSupported = 0;
+			pDeviceInfo->MaxQueueDepth = 1;
+		}
+#else
+		pDeviceInfo->FG_QueueSupported = 0;
+		pDeviceInfo->MaxQueueDepth = 1;
+
+#endif
+		pDeviceInfo->FG_AtapiDevice = 0;
+		pDeviceInfo->FG_DiscDevice  = 0;
+		pDeviceInfo->DeviceBlockSize = 512;
+	} else {
+		pDeviceInfo->FG_Support48Bits	= 0;
+		pDeviceInfo->MaxQueueDepth	= 1;
+		pDeviceInfo->FG_QueueSupported	= 0;
+		((pDeviceInfo->Capacity).U64L).U64L_L = 0;
+		((pDeviceInfo->Capacity).U64L).U64L_H = 0;
+		pDeviceInfo->FG_AtapiDevice	= 1;
+		if ((pIdentifyBuff->ConfigBitInfo & 0x1f00)==0x0500) {
+			// CD-ROM device
+			pDeviceInfo->FG_DiscDevice  = 1;
+			pDeviceInfo->DeviceBlockSize = 2048;
+		} else {
+			// Direct access device
+			pDeviceInfo->FG_DiscDevice  = 0;
+			pDeviceInfo->DeviceBlockSize = 512;
+		}
+	}
+	//=====================================================================================
+	// set following for IDE device which useing bridge to convert to SATA
+	// some NCQ device need following procedure to make NCQ commnad effect (Hitachi HDT7225XX serial HDD)
+	//=====================================================================================
+	UltraMap = pIdentifyBuff->UltraModeMap;
+	pDeviceInfo->DMA_Mode	= 0;
+	if (UltraMap & 0x40) {
+		// Ultra 133
+		pDeviceInfo->DMA_Mode = 7;
+	} else if (UltraMap & 0x20) {
+		// Ultra 100
+		pDeviceInfo->DMA_Mode = 6;
+	} else if (UltraMap & 0x10) {
+		// Ultra 66
+		pDeviceInfo->DMA_Mode = 5;
+	} else if (UltraMap & 0x08) {
+		// Ultra 44
+		pDeviceInfo->DMA_Mode = 4;
+	} else if (UltraMap & 0x04) {
+		// Ultra 33
+		pDeviceInfo->DMA_Mode = 3;
+	} else if (UltraMap & 0x02) {
+		// Ultra 1 
+		pDeviceInfo->DMA_Mode = 2;
+	} else if (UltraMap & 0x01) {
+		// Ultra 0 
+		pDeviceInfo->DMA_Mode = 1;
+	}
+	Ultramode = pDeviceInfo->DMA_Mode;
+	Ultramode--;
+	Ultramode |= 0x40;
+	pCommandTable->CommandFIS.P1x1 = 0x03;
+	pCommandTable->CommandFIS.P1x2 = Ultramode;
+	pCommandTable->CommandFIS.P1x6 = 0xE0;
+	pCommandTable->CommandFIS.Command = 0xEF;
+	// issure command
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	for (i = 0 ; i < 1000 ; i++) {
+		// wait CI bit clear
+		if ((inl(pSataChannel->BaseIoPort + 0x0038) & ci_map) == 0) {
+			// CI bit to be clear
+			break;
+		}
+		udelay(1000);
+		cpu_relax();
+	}
+	if (i >= 1000) {
+		// time out
+		outb(0x16,pSataChannel->BaseIoPort + 0x0018);
+		outb(0x17,pSataChannel->BaseIoPort + 0x0018);
+		outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+		return;
+	}
+	for (i = 0 ; i < 1000 ; i++) {
+		//wait 1s for D2H/PIO FIS
+		if (inb(pSataChannel->BaseIoPort + 0x0010) & 0x03) {
+			// got D2H register FIS/ got PIO setup FIS
+			break;
+		}
+		udelay(1000);
+		cpu_relax();
+	}
+	if (i >= 1000) {
+		// time out
+		outb(0x16,pSataChannel->BaseIoPort + 0x0018);
+		outb(0x17,pSataChannel->BaseIoPort + 0x0018);
+		outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore Reg74
+		return;
+	}
+	Error_status = pReciveFIS->Device2HostFIS.Status;
+	outb(0x03,pSataChannel->BaseIoPort + 0x0010); // clear interrupt
+	outb(status74,pSataChannel->BaseIoPort + 0x0074); // restore PM bit
+	return;
+}
+//=======================================================================================
+static void ExecuteSataATA(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_DeviceInfo pDeviceInfo;
+	P_Channel pSataChannel;
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	Scsi_Cmnd *pScsiCmd;
+	unsigned int ci_map;
+	unsigned char status;
+
+	pDeviceInfo = pWorkingTable->pDevice;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pSataChannel = pDeviceInfo->pChannel;
+	//building Command Table
+	pCommandHead = (pSataChannel->pCommandPtr->pCommandHead + pWorkingTable->TagID);
+	pCommandTable = (pSataChannel->pCommandPtr->pCommandTable + pWorkingTable->TagID);
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.FIS_Flag = 1;
+	pCommandTable->CommandFIS.PortMultiplier = pDeviceInfo->FG_PMId;
+	if (pDeviceInfo->FG_QueueSupported) {
+		pCommandTable->CommandFIS.P1x1 = (((pWorkingTable->TransferLen).U64C).U64C_L_LL);
+		pCommandTable->CommandFIS.P1x1Exp = (((pWorkingTable->TransferLen).U64C).U64C_L_LH);
+		pCommandTable->CommandFIS.P1x2 = (((pWorkingTable->TagID) << 3) & 0xF8);
+		pCommandTable->CommandFIS.P1x2Exp = 0;
+		pCommandTable->CommandFIS.P1x3 = (((pWorkingTable->StartLBA).U64C).U64C_L_LL);
+		pCommandTable->CommandFIS.P1x4 = (((pWorkingTable->StartLBA).U64C).U64C_L_LH);
+		pCommandTable->CommandFIS.P1x5 = (((pWorkingTable->StartLBA).U64C).U64C_L_HL);
+		pCommandTable->CommandFIS.P1x3Exp = (((pWorkingTable->StartLBA).U64C).U64C_L_HH);
+		pCommandTable->CommandFIS.P1x4Exp = (((pWorkingTable->StartLBA).U64C).U64C_H_LL);
+		pCommandTable->CommandFIS.P1x5Exp = (((pWorkingTable->StartLBA).U64C).U64C_H_LH);
+		pCommandTable->CommandFIS.P1x6 = 0x40;
+		if (	(pScsiCmd->cmnd[0] == READ_6)||
+			(pScsiCmd->cmnd[0] == READ_10)||
+			(pScsiCmd->cmnd[0] == READ_12)||
+			(pScsiCmd->cmnd[0] == READ_16)
+		   ) {
+			pWorkingTable->XferCmd = IDE_NCQ_READ;
+			pCommandHead->ReadWrite = 0;
+		} else {
+			pWorkingTable->XferCmd = IDE_NCQ_WRITE;
+			pCommandHead->ReadWrite = 1;
+		}
+	} else {
+		if (	(pWorkingTable->XferCmd == IDE_READ_DMA_EXT)||
+			(pWorkingTable->XferCmd == IDE_WRITE_DMA_EXT)
+		   ) {
+			pCommandTable->CommandFIS.P1x1 = 0;
+			pCommandTable->CommandFIS.P1x1Exp = 0;
+			pCommandTable->CommandFIS.P1x2 = (((pWorkingTable->TransferLen).U64C).U64C_L_LL);
+			pCommandTable->CommandFIS.P1x2Exp = (((pWorkingTable->TransferLen).U64C).U64C_L_LH);
+			pCommandTable->CommandFIS.P1x3 = (((pWorkingTable->StartLBA).U64C).U64C_L_LL);
+			pCommandTable->CommandFIS.P1x4 = (((pWorkingTable->StartLBA).U64C).U64C_L_LH);
+			pCommandTable->CommandFIS.P1x5 = (((pWorkingTable->StartLBA).U64C).U64C_L_HL);
+			pCommandTable->CommandFIS.P1x3Exp = (((pWorkingTable->StartLBA).U64C).U64C_L_HH);
+			pCommandTable->CommandFIS.P1x4Exp = (((pWorkingTable->StartLBA).U64C).U64C_H_LL);
+			pCommandTable->CommandFIS.P1x5Exp = (((pWorkingTable->StartLBA).U64C).U64C_H_LH);
+			pCommandTable->CommandFIS.P1x6 = 0xE0;
+			if (	(pScsiCmd->cmnd[0] == READ_6)||
+				(pScsiCmd->cmnd[0] == READ_10)||
+				(pScsiCmd->cmnd[0] == READ_12)||
+				(pScsiCmd->cmnd[0] == READ_16)
+			   ) {
+				pCommandHead->ReadWrite = 0;
+			} else {
+				pCommandHead->ReadWrite = 1;
+			}
+		} else {
+			pCommandTable->CommandFIS.P1x1 = 0;
+			pCommandTable->CommandFIS.P1x1Exp = 0;
+			pCommandTable->CommandFIS.P1x2 = (((pWorkingTable->TransferLen).U64C).U64C_L_LL);
+			pCommandTable->CommandFIS.P1x2Exp = (((pWorkingTable->TransferLen).U64C).U64C_L_LH);
+			pCommandTable->CommandFIS.P1x3 = (((pWorkingTable->StartLBA).U64C).U64C_L_LL);
+			pCommandTable->CommandFIS.P1x4 = (((pWorkingTable->StartLBA).U64C).U64C_L_LH);
+			pCommandTable->CommandFIS.P1x5 = (((pWorkingTable->StartLBA).U64C).U64C_L_HL);
+			pCommandTable->CommandFIS.P1x3Exp = 0;
+			pCommandTable->CommandFIS.P1x4Exp = 0;
+			pCommandTable->CommandFIS.P1x5Exp = 0;
+			pCommandTable->CommandFIS.P1x6 = (0xE0 | ((((pWorkingTable->StartLBA).U64C).U64C_L_HH) & 0x0F));
+			if (	(pScsiCmd->cmnd[0] == READ_6)||
+				(pScsiCmd->cmnd[0] == READ_10)||
+				(pScsiCmd->cmnd[0] == READ_12)||
+				(pScsiCmd->cmnd[0] == READ_16)
+			   ) {
+				pCommandHead->ReadWrite = 0;
+			} else {
+				pCommandHead->ReadWrite = 1;
+			}
+		}
+	}
+	pCommandTable->CommandFIS.Command = pWorkingTable->XferCmd;
+	// building PTD table
+	BuildPrdTable(pHwDeviceExtension,pWorkingTable,&(pCommandTable->MailBox[0]));
+	// building Command List Entry
+	pCommandHead->CommandFISLen = 5;
+	pCommandHead->AtapiPioFIS = 0;
+	pCommandHead->PreFetchAble = 0;
+	pCommandHead->Reset = 0;
+	pCommandHead->Bist = 0;
+	pCommandHead->ClearBusy = 0;
+	pCommandHead->Reserved0 = 0;
+	pCommandHead->PortMultiplier = pDeviceInfo->FG_PMId;
+	pCommandHead->PRDTL = 0;
+	pCommandHead->PRD_ByteCount = 0;
+	// issure command
+	status = inb(pSataChannel->BaseIoPort + 0x0074) & 0xFE;
+	ci_map = 0x00000001;
+	ci_map <<= pWorkingTable->TagID;
+	if (pDeviceInfo->FG_QueueSupported) {
+		status |= 0x01; // enable NCQ bit
+		outb(status,pSataChannel->BaseIoPort + 0x0074);
+		outl(ci_map,pSataChannel->BaseIoPort + 0x0034);
+	} else {
+		outb(status,pSataChannel->BaseIoPort + 0x0074);
+	}
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	return;
+}
+static void ExecuteUpdata(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_DeviceInfo pDeviceInfo;
+	P_Channel pSataChannel;
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	Scsi_Cmnd *pScsiCmd;
+	unsigned int ci_map;
+	unsigned char status;
+
+	pDeviceInfo = pWorkingTable->pDevice;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pSataChannel = pDeviceInfo->pChannel;
+	//building Command Table
+	pCommandHead = (pSataChannel->pCommandPtr->pCommandHead + pWorkingTable->TagID);
+	pCommandTable = (pSataChannel->pCommandPtr->pCommandTable + pWorkingTable->TagID);
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.FIS_Flag = 1;
+	pCommandTable->CommandFIS.PortMultiplier = pDeviceInfo->FG_PMId;			
+	pCommandTable->CommandFIS.P1x1Exp = 0;
+	pCommandTable->CommandFIS.P1x2	  = pScsiCmd->cmnd[8];
+	pCommandTable->CommandFIS.P1x2Exp = 0;
+	pCommandTable->CommandFIS.P1x3 = pScsiCmd->cmnd[3];
+	pCommandTable->CommandFIS.P1x4 = pScsiCmd->cmnd[4];
+	pCommandTable->CommandFIS.P1x5 = pScsiCmd->cmnd[5];
+	pCommandTable->CommandFIS.P1x3Exp = 0;
+	pCommandTable->CommandFIS.P1x4Exp = 0;
+	pCommandTable->CommandFIS.P1x5Exp = 0;
+	pCommandTable->CommandFIS.P1x6 = (0xE0 | ((((pWorkingTable->StartLBA).U64C).U64C_L_HH) & 0x0F));
+	if (pScsiCmd->cmnd[0] == Updata_NonData	) {
+		pCommandTable->CommandFIS.P1x1 = pScsiCmd->cmnd[2];
+		pCommandHead->ReadWrite = 0;
+		pCommandTable->CommandFIS.Command = 0xFC;
+		pWorkingTable->FG_NonData = 1;
+	} else if(pScsiCmd->cmnd[0] == Fireware_ReadBuffer){
+		pCommandTable->CommandFIS.P1x1 = 0x3C;
+		pCommandHead->ReadWrite = 0;
+		pCommandTable->CommandFIS.Command = 0xFD;
+	}else {
+		pCommandTable->CommandFIS.P1x1 = 0x3B;
+		pCommandHead->ReadWrite = 1;
+		pCommandTable->CommandFIS.Command = 0xFD;
+	}	
+	
+	// building PTD table
+	if (pWorkingTable->FG_NonData == 0)
+	{
+		BuildPrdTable(pHwDeviceExtension,pWorkingTable,&(pCommandTable->MailBox[0]));
+	}
+	// building Command List Entry
+	pCommandHead->CommandFISLen = 5;
+	pCommandHead->AtapiPioFIS = 0;
+	pCommandHead->PreFetchAble = 0;
+	pCommandHead->Reset = 0;
+	pCommandHead->Bist = 0;
+	pCommandHead->ClearBusy = 0;
+	pCommandHead->Reserved0 = 0;
+	pCommandHead->PortMultiplier = pDeviceInfo->FG_PMId;
+	pCommandHead->PRDTL = 0;
+	pCommandHead->PRD_ByteCount = 0;
+	// issure command
+	status = inb(pSataChannel->BaseIoPort + 0x0074) & 0xFE;
+	ci_map = 0x00000001;
+	ci_map <<= pWorkingTable->TagID;	
+	outb(status,pSataChannel->BaseIoPort + 0x0074);	
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	return;
+}
+//=======================================================================================
+static void ExecuteSataATAPI(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_DeviceInfo pDeviceInfo;
+	P_Channel pSataChannel;
+	P_CommandHead pCommandHead;
+	P_CommandTable pCommandTable;
+	Scsi_Cmnd *pScsiCmd;
+	unsigned int ci_map;
+	unsigned char status;
+	int i;
+
+	pDeviceInfo = pWorkingTable->pDevice;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pSataChannel = pDeviceInfo->pChannel;
+	//building Command Table
+	pCommandHead = (pSataChannel->pCommandPtr->pCommandHead + pWorkingTable->TagID);
+	pCommandTable = (pSataChannel->pCommandPtr->pCommandTable + pWorkingTable->TagID);
+	pCommandTable->CommandFIS.FIS_Type = 0x27;
+	pCommandTable->CommandFIS.FIS_Flag = 1;
+	pCommandTable->CommandFIS.PortMultiplier = pDeviceInfo->FG_PMId;
+	ConvertCmdATAPI(pWorkingTable);
+	//building Command Table
+	if (pWorkingTable->request_bufflen) { 
+		// Do DMA
+		pCommandTable->CommandFIS.P1x1 = 1;
+		pWorkingTable->FG_DoIoByDMA = 1;
+	} else {
+		// Do PIO
+		pCommandTable->CommandFIS.P1x1 = 0;
+		pWorkingTable->FG_DoIoByDMA = 0;
+	}
+	pCommandTable->CommandFIS.P1x1Exp = 0;
+	pCommandTable->CommandFIS.P1x2 = 0;
+	pCommandTable->CommandFIS.P1x2Exp = 0;
+	pCommandTable->CommandFIS.P1x3 = 0;
+	pCommandTable->CommandFIS.P1x4 = 0xFF;
+	pCommandTable->CommandFIS.P1x5 = 0xFF;
+	pCommandTable->CommandFIS.P1x3Exp = 0;
+	pCommandTable->CommandFIS.P1x4Exp = 0;
+	pCommandTable->CommandFIS.P1x5Exp = 0;
+	pCommandTable->CommandFIS.P1x6 = 0x40;
+	pCommandTable->CommandFIS.Command = 0xA0;
+	for (i = 0 ; i < 16 ; i++) {
+		pCommandTable->AtapiCommnad[i] = pScsiCmd->cmnd[i];
+	}
+	if (pScsiCmd->sc_data_direction == DMA_TO_DEVICE) {
+		pCommandHead->ReadWrite	= 1;
+	} else {
+		pCommandHead->ReadWrite	= 0;
+	}
+	if (pWorkingTable->request_bufflen) {
+		// building PTD table
+		BuildPrdTable(pHwDeviceExtension,pWorkingTable,&(pCommandTable->MailBox[0]));
+	}
+	// building Command List Entry
+	pCommandHead->CommandFISLen = 5;
+	pCommandHead->AtapiPioFIS = 1;
+	pCommandHead->PreFetchAble = 0;
+	pCommandHead->Reset = 0;
+	pCommandHead->Bist = 0;
+	pCommandHead->ClearBusy = 0;
+	pCommandHead->Reserved0 = 0;
+	pCommandHead->PortMultiplier = pDeviceInfo->FG_PMId;
+	pCommandHead->PRDTL = 0;
+	pCommandHead->PRD_ByteCount = 0;
+	// issure command
+	status = inb(pSataChannel->BaseIoPort + 0x0074) & 0xFE;
+	outb(status,pSataChannel->BaseIoPort + 0x0074);
+	ci_map = 0x00000001;
+	ci_map <<= pWorkingTable->TagID;
+	outl(ci_map,pSataChannel->BaseIoPort + 0x0038);
+	return;
+}
+//=======================================================================================
+static void BuildPrdTable(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable,P_MailBox pMailBox)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	Scsi_Cmnd *pScsiCmd;
+	struct scatterlist *sg_list,*sg;
+	P_MailBox pmailbox;
+	P_DeviceInfo pDeviceInfo;
+	int sg_num,i,j;
+	u32 sg_addr,sg_len;
+
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pDeviceInfo = pWorkingTable->pDevice;
+	pmailbox = pMailBox;
+	if (pWorkingTable->use_sg) {
+		sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+
+//		sg_num = scsi_dma_map(pScsiCmd);
+//		target_id = scmd_id(pScsiCmd);
+//		scsi_for_each_sg(pScsiCmd, sg_list, sg_num, target_id) {
+
+		/* Add the below block for async cpu cache and memory,
+		   k3b project found.
+		   LiWengang <liwengang@loongson.cn>
+		   Jason Luan <luanjianhai@ccoss.com.cn>
+		 */
+		int index = 0;
+		for (index = 0; index < pWorkingTable->use_sg; index++){
+			unsigned long  addr = (unsigned long) sg_virt(sg_list);
+			dma_cache_wback_inv(addr, sg_list->length);
+		}
+
+
+		sg_num = pci_map_sg(pHwDeviceExtension->pPciDev,
+					sg_list,
+					pWorkingTable->use_sg,
+# if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+					scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+# else
+					pScsiCmd->sc_data_direction
+# endif
+				   );
+#ifdef KERNEL_V2625
+		for_each_sg(sg_list, sg, sg_num, i) {
+#else
+		for (j = 0 ; j < sg_num ; j++) {
+#endif
+			sg_addr	=  sg_dma_address(sg_list);
+			sg_len	=  sg_dma_len(sg_list);
+			while (sg_len > 0x00010000) {
+				pmailbox->BufAddressU =  0;
+#if __LITTLE_ENDIAN
+				pmailbox->BufAddress = sg_addr;
+				pmailbox->DataLength = 0x00010000;
+#else
+				pmailbox->BufAddress = cpu_to_le32(sg_addr);
+				pmailbox->DataLength = cpu_to_le32(0x00010000);
+#endif
+				sg_addr += 0x00010000;
+				sg_len -= 0x00010000;
+				pmailbox++;
+			} 
+			pmailbox->BufAddressU =  0;
+#if __LITTLE_ENDIAN
+			pmailbox->BufAddress = sg_addr;
+			pmailbox->DataLength = sg_len;
+#else
+			pmailbox->BufAddress = cpu_to_le32(sg_addr);
+			pmailbox->DataLength = cpu_to_le32(sg_len);
+#endif
+			pmailbox++;
+
+/*			sg_list = sg_next(sg_list);*/
+
+#ifdef KERNEL_V2625
+			sg_list = sg_next(sg_list);
+#else
+			sg_list++;
+#endif
+		}
+		pmailbox--;
+#if __LITTLE_ENDIAN
+		pmailbox->DataLength |= 0x80000000;
+#else
+		pmailbox->DataLength |= 0x00000080;
+#endif
+	} else {
+		if (  (pWorkingTable->pDmaSingleMapAddr = 
+				pci_map_single(pHwDeviceExtension->pPciDev,
+						pWorkingTable->request_buffer,
+						pWorkingTable->request_bufflen,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+						scsi_to_pci_dma_dir(pScsiCmd->sc_data_direction)
+#else
+						pScsiCmd->sc_data_direction
+#endif
+					     )
+		      ) == 0
+
+		   ) {
+			pDeviceInfo->SenseKey = 0x03;
+			pDeviceInfo->SenseAsc = 0x55;
+			pDeviceInfo->SenseAscQ = 0x01;
+			pScsiCmd->result = SAM_STAT_CHECK_CONDITION;
+			return;
+		}
+		sg_addr = pWorkingTable->pDmaSingleMapAddr;
+		sg_len = pWorkingTable->request_bufflen;
+		while (sg_len > 0x00010000) {
+			pmailbox->BufAddressU = 0;
+#if __LITTLE_ENDIAN
+			pmailbox->BufAddress = sg_addr;
+			pmailbox->DataLength = 0x00010000;
+#else
+			pmailbox->BufAddress = cpu_to_le32(sg_addr);
+			pmailbox->DataLength = cpu_to_le32(0x00010000);
+#endif
+			sg_addr += 0x00010000;
+			sg_len -= 0x00010000;
+			pmailbox++;
+		} 
+		sg_len |= 0x80000000;
+		pmailbox->BufAddressU = 0;
+#if __LITTLE_ENDIAN
+		pmailbox->BufAddress = sg_addr;
+		pmailbox->DataLength = sg_len;
+#else
+		pmailbox->BufAddress = cpu_to_le32(sg_addr);
+		pmailbox->DataLength = cpu_to_le32(sg_len);
+#endif
+	}
+	return;
+}
+//=======================================================================================
+static P_WorkingTable AllocateWorkingTable(PHW_DEVICE_EXTENSION DeviceExtension)
+{
+	PHW_DEVICE_EXTENSION pHwDeviceExtension = DeviceExtension;
+	P_WorkingTable pWorkingTable;
+	unsigned int i;
+
+	pWorkingTable = (P_WorkingTable)(pHwDeviceExtension->pWorkingTablePool);
+	for (i = 0 ; i < MAX_QUEUE_SUPPORT ; i++) {
+		if (pWorkingTable->FG_TableActive == 0) {
+			// found a empty TaskTable
+			memset(pWorkingTable,0,sizeof(T_WorkingTable));
+			pWorkingTable->FG_TableActive = 1;
+
+			pWorkingTable->pMailBox = pHwDeviceExtension->pIdeMailBox;
+			pWorkingTable->LmailBox = pHwDeviceExtension->pDmaIdeMailBox;
+			return pWorkingTable;
+		}
+		pWorkingTable++;
+	}
+	printk("---!!! Warnning,WorkingTable pool empty !!!---\n");
+	return 0;
+}
+//=======================================================================================
+static void ReleaseWorkingTable(P_WorkingTable pWorkingTable)
+{
+	pWorkingTable->FG_TableActive = 0;
+	return;
+}
+//=======================================================================================
+static void ChannelIoHook(P_WorkingTable pWorkingTable)
+{
+	P_Channel pChannel;
+	P_WorkingTable pWorkingTable1;
+
+	if (pWorkingTable->pDevice == 0) {
+		printk("Channel Io Hook : Device of WorkingTable lost,IoTagID:%ld \n\r",pWorkingTable->IoTagID);
+		return;
+	}
+	pChannel = ((P_DeviceInfo)(pWorkingTable->pDevice))->pChannel;
+	if (pChannel->pPendingIO == 0) {
+		pChannel->pPendingIO	= pWorkingTable;
+		pWorkingTable->pPrevTable	= 0;
+	} else {
+		pWorkingTable1 = pChannel->pPendingIO;
+		while (pWorkingTable1->pNextTable != 0) {
+			pWorkingTable1 = pWorkingTable1->pNextTable;
+		}
+		pWorkingTable1->pNextTable = pWorkingTable;
+		pWorkingTable->pPrevTable = pWorkingTable1;
+		pWorkingTable->pNextTable = 0;
+	}
+	return;
+}
+//=======================================================================================
+static void ChannelIoRemove(P_WorkingTable pWorkingTable)
+{
+	P_WorkingTable pWorkingTable2;
+	P_Channel pChannel;
+
+	if (pWorkingTable->pDevice == 0) {
+		printk("ChannelIoRemove : Device of WorkingTable lost,IoTagID:%ld \n\r",pWorkingTable->IoTagID);
+		return;
+	}
+	pChannel = ((P_DeviceInfo)(pWorkingTable->pDevice))->pChannel;
+	if (pWorkingTable->pPrevTable == 0) {
+		// this is first task table in task queue
+		pChannel->pPendingIO = pWorkingTable->pNextTable;
+		if (pWorkingTable->pNextTable != 0) {
+			((P_WorkingTable)(pWorkingTable->pNextTable))->pPrevTable = 0;
+		}
+	} else {
+		pWorkingTable2 = pWorkingTable->pPrevTable;
+		pWorkingTable2->pNextTable = pWorkingTable->pNextTable;
+		if (pWorkingTable->pNextTable != 0) {
+			((P_WorkingTable)(pWorkingTable->pNextTable))->pPrevTable = pWorkingTable2;
+		}
+	}
+	return;
+}
+//========================================================================
+static void ConvertCommandATA(P_WorkingTable pWorkingTable)
+{
+	T_U64 EndLBA;
+	Scsi_Cmnd *pScsiCmd;
+	P_DeviceInfo pHardDiskInfo;
+	unsigned char IdeCommand;
+
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pHardDiskInfo = pWorkingTable->pDevice;
+	AddU64(&(pWorkingTable->StartLBAOrg),&(pWorkingTable->TransferLenOrg),&EndLBA);
+	switch(pScsiCmd->cmnd[0]) {
+	case READ_6:
+		IdeCommand = IDE_READ_DMA;
+		break;
+	case READ_10:
+	case READ_12:
+	case READ_16:
+		if (  (((EndLBA.U64L).U64L_H) != 0) || ((EndLBA.U64L).U64L_L & 0xF0000000)  ) {
+			IdeCommand = IDE_READ_DMA_EXT;
+		} else {
+			IdeCommand = IDE_READ_DMA;
+		}
+		break;
+	case WRITE_6:
+		IdeCommand = IDE_WRITE_DMA;
+		break;
+	case WRITE_10:
+	case WRITE_12:
+	case WRITE_16:
+		if (  (((EndLBA.U64L).U64L_H) != 0) || ((EndLBA.U64L).U64L_L & 0xF0000000)  ) {
+			IdeCommand = IDE_WRITE_DMA_EXT;
+		} else {
+			IdeCommand = IDE_WRITE_DMA;
+		}
+		break;
+	case SEEK_10:
+	case SEEK_6:
+		IdeCommand = IDE_SEEK;
+		break;
+	case VERIFY:
+		if (  (((EndLBA.U64L).U64L_H) != 0) || ((EndLBA.U64L).U64L_L & 0xF0000000)  ) {
+			IdeCommand = IDE_VERIFY_EXT;
+		} else {
+			IdeCommand = IDE_VERIFY;
+		}
+		break;
+	case SYNCHRONIZE_CACHE:
+		if (pHardDiskInfo->FG_Support48Bits) {
+			IdeCommand = IDE_FLUSH_CACHE_EXT;
+		} else {
+			IdeCommand = IDE_FLUSH_CACHE;
+		}
+		break;
+	default:
+		IdeCommand = 0;
+		break;
+	}
+	pWorkingTable->XferCmd = IdeCommand;
+	return;
+}
+//========================================================================
+static void ConvertCmdATAPI(P_WorkingTable pWorkingTable)
+{
+	P_Channel pIdeChannel;
+	P_DeviceInfo pCdRomInfo;
+	struct scatterlist *sg_list;
+	Scsi_Cmnd *pScsiCmd;
+	unsigned long km_flags;
+	unsigned char *km_buffer;
+	unsigned char *SrbExtDataBuffer,*SrbDataBuffer;
+	int i,km_sg_used;
+	unsigned short blklen,pagelen,BlockLen;
+
+	km_buffer = NULL;
+	km_sg_used = 0;
+	km_flags = 0;
+	pScsiCmd = pWorkingTable->pWorkingScsiCmd;
+	pCdRomInfo = pWorkingTable->pDevice;
+	pIdeChannel = pCdRomInfo->pChannel; 
+	for (i = pScsiCmd->cmd_len ; i < 12; i++) {
+		pScsiCmd->cmnd[i] = 0;
+	}
+	// clear remain CDB
+	switch(pScsiCmd->cmnd[0]) {
+	case READ_6:
+	case READ_10:
+		BlockLen = pCdRomInfo->DeviceBlockSize;
+		if ((BlockLen != 2048) && (BlockLen != 512)) {
+			// backup original srb
+			for (i = 0 ; i < 12 ; i++) {
+				pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+			}
+			pScsiCmd->cmnd[0] = 0xBE;
+			pScsiCmd->cmnd[1] = 0;
+			pScsiCmd->cmnd[6] = 0;
+			switch(BlockLen) {
+			case 0x0920:
+				pScsiCmd->cmnd[9] = 0x58;
+				pScsiCmd->cmnd[10] = 0;
+				pScsiCmd->cmnd[11] = 0;
+				break;	
+			case 0x0930:
+				pScsiCmd->cmnd[9] = 0xF8;
+				pScsiCmd->cmnd[10] = 0;
+				pScsiCmd->cmnd[11] = 0;
+				break;
+			case 0x0940:
+				pScsiCmd->cmnd[9] = 0xF8;
+				pScsiCmd->cmnd[10] = 0x02;
+				pScsiCmd->cmnd[11] = 0;
+				break;
+			case 0x0990:
+				pScsiCmd->cmnd[9] = 0xF8;
+				pScsiCmd->cmnd[10] = 0x04;
+				pScsiCmd->cmnd[11] = 0;
+				break;
+			default:
+				pScsiCmd->cmnd[9] = 0x10;
+				pScsiCmd->cmnd[10] = 0;
+				pScsiCmd->cmnd[11] = 0;
+				break;
+			}
+		}
+		break;
+/*
+	case 0x46:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+		//	pScsiCmd->cmnd[i] = 0;
+		}
+		pWorkingTable->pOrgRequestBuffLen = pWorkingTable->request_bufflen;
+		pWorkingTable->pOrgRequesrBuff = pWorkingTable->request_buffer;
+		pWorkingTable->old_use_sg = pWorkingTable->use_sg;
+		pWorkingTable->use_sg = 0;
+		pWorkingTable->request_buffer = pWorkingTable->DataBuffer;
+		pWorkingTable->pDataBufPtr = pWorkingTable->DataBuffer;
+		break;
+*/
+	case MODE_SENSE:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+			pScsiCmd->cmnd[i]	  = 0;
+		}
+		pWorkingTable->pOrgRequestBuffLen = pWorkingTable->request_bufflen;
+		pWorkingTable->pOrgRequesrBuff = pWorkingTable->request_buffer;
+		pWorkingTable->old_use_sg = pWorkingTable->use_sg;
+		// rebuild CDB
+		pScsiCmd->cmnd[0] = MODE_SENSE_10;			// 1A -> 5A
+		pScsiCmd->cmnd[2] = pWorkingTable->OrgCmnd[2];	// PC flag & Page Code
+		pScsiCmd->cmnd[8] = pWorkingTable->OrgCmnd[4];	// Allocation length
+		pWorkingTable->use_sg = 0;
+		pWorkingTable->request_buffer = pWorkingTable->DataBuffer;
+		pWorkingTable->pDataBufPtr = pWorkingTable->DataBuffer;
+		break;
+	case MODE_SENSE_10:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+			pScsiCmd->cmnd[i]	  = 0;
+		}
+		pWorkingTable->pOrgRequestBuffLen = pWorkingTable->request_bufflen;
+		pWorkingTable->pOrgRequesrBuff = pWorkingTable->request_buffer;
+		pWorkingTable->old_use_sg = pWorkingTable->use_sg;
+		// rebuild CDB
+		
+		pScsiCmd->cmnd[0] = MODE_SENSE_10;		   // 1A -> 5A
+	/*	pScsiCmd->cmnd[1] = pWorkingTable->OrgCmnd[1]; */
+		pScsiCmd->cmnd[2] = pWorkingTable->OrgCmnd[2]; // PC flag & Page Code
+		pScsiCmd->cmnd[7] = pWorkingTable->OrgCmnd[7]; // Allocation length
+		pScsiCmd->cmnd[8] = pWorkingTable->OrgCmnd[8]; // Allocation length
+
+		pWorkingTable->use_sg = 0;
+		pWorkingTable->request_buffer = pWorkingTable->DataBuffer;
+		pWorkingTable->pDataBufPtr = pWorkingTable->DataBuffer;
+		break;
+	case MODE_SELECT:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+			pScsiCmd->cmnd[i] = 0;
+		}
+		pWorkingTable->pOrgRequestBuffLen = pWorkingTable->request_bufflen;
+		pWorkingTable->pOrgRequesrBuff = pWorkingTable->request_buffer;
+		pWorkingTable->old_use_sg = pWorkingTable->use_sg;
+		km_sg_used = 0;
+		sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+		if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+			SrbDataBuffer = (unsigned char *)(sg_list->address);
+#else
+			local_irq_save(km_flags);
+			km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//			km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+			SrbDataBuffer = km_buffer;
+			km_sg_used = 1;
+#endif
+		} else {
+			SrbDataBuffer =  (unsigned char *)(pWorkingTable->request_buffer);
+		}		
+		SrbExtDataBuffer = (unsigned char *)pWorkingTable->DataBuffer;
+		blklen = SrbDataBuffer[3];		// get block descriptor length
+		pagelen = SrbDataBuffer[blklen+5];	// get page len
+		// rebuild mode parameter header
+		for (i = 0 ; i < 8 ; i++) {
+			SrbExtDataBuffer[i] = 0;	// all field is reserved when mode select
+		}
+		// get read/write block length
+		
+		if (blklen >= 8) {
+			BlockLen =  ((((unsigned short)(SrbDataBuffer[9]))<<16)&0x00FF0000)+
+				    ((((unsigned short)(SrbDataBuffer[10]))<<8)&0x0000FF00)+
+				     (((unsigned short)(SrbDataBuffer[11]))&0x000000FF);
+			if (BlockLen != 0) {
+				pCdRomInfo->DeviceBlockSize = (unsigned short)BlockLen;
+			}
+		}
+		// rebuild page list
+		SrbDataBuffer += (4+blklen);// skip header & block descriptor
+		SrbExtDataBuffer += 8;	// skip header
+		pagelen += 2;		// total page list length
+		for (i = 0 ; i < pagelen ; i++) {
+			SrbExtDataBuffer[i] = SrbDataBuffer[i];
+		}
+		pagelen += 8;		// total transfer length
+		pWorkingTable->use_sg = 0;
+		pWorkingTable->request_bufflen = pagelen;
+		pWorkingTable->request_buffer = pWorkingTable->DataBuffer;
+		pWorkingTable->pDataBufPtr= pWorkingTable->DataBuffer;
+		// rebuild CDB
+		pScsiCmd->cmnd[0] = MODE_SELECT_10;
+		pScsiCmd->cmnd[1] = ((pWorkingTable->OrgCmnd[1] & 0x01)|0x10);	// keep SP & set PF=1
+		pScsiCmd->cmnd[7] = (unsigned char)(pagelen >> 8);
+		pScsiCmd->cmnd[8] = (unsigned char)pagelen;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#else
+		if (km_sg_used) {
+			kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+			local_irq_restore(km_flags);
+		}
+#endif
+		break;
+	case MODE_SELECT_10:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+			pScsiCmd->cmnd[i] = 0;
+		}
+		pWorkingTable->pOrgRequestBuffLen = pWorkingTable->request_bufflen;
+		pWorkingTable->pOrgRequesrBuff = pWorkingTable->request_buffer;
+		pWorkingTable->old_use_sg = pWorkingTable->use_sg;		
+		sg_list = (struct scatterlist *)(pWorkingTable->request_buffer);
+		if (pWorkingTable->use_sg) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+			SrbDataBuffer = (unsigned char *)(sg_list->address);
+#else
+			local_irq_save(km_flags);
+			km_buffer = kmap_atomic(sg_page(sg_list),KM_IRQ0) + sg_list->offset;
+//			km_buffer = kmap_atomic(sg_list->page,KM_IRQ0) + sg_list->offset;
+			SrbDataBuffer = km_buffer;
+			km_sg_used = 1;
+#endif
+		} else {
+			SrbDataBuffer =  (unsigned char *)(pWorkingTable->request_buffer);
+		}		
+		SrbExtDataBuffer = (unsigned char *)pWorkingTable->DataBuffer;
+		blklen = (((unsigned short)SrbDataBuffer[6])<<8)+SrbDataBuffer[7]; // get block descriptor length
+		pagelen = SrbDataBuffer[blklen+9];			     // get page len
+		// rebuild mode parameter header
+		for (i = 0 ; i < 8 ; i++) {
+			SrbExtDataBuffer[i] = 0; // all filed are reserved when mode select
+		}
+		// get read/write block length
+		if (blklen>0) {
+			BlockLen =  ((((unsigned short)SrbDataBuffer[13])<<16)&0x00FF0000)+
+				    ((((unsigned short)SrbDataBuffer[14])<<8)&0x0000FF00)+
+				     (((unsigned short)SrbDataBuffer[15])&0x000000FF);
+			if ((BlockLen != 0) && (SrbExtDataBuffer[0] != 5)) {
+				pCdRomInfo->DeviceBlockSize = (unsigned short)BlockLen;
+			}
+		}
+		// rebuild page list
+		SrbDataBuffer += (8+blklen);// skip header & block descriptor
+		SrbExtDataBuffer += 8;	// skip header
+		pagelen += 2;		// total page list length
+		for (i = 0 ; i < pagelen ; i++) {
+			SrbExtDataBuffer[i] = SrbDataBuffer[i];
+		}
+		pagelen += 8;		// total transfer length
+		if (pagelen % 2) {
+			pagelen++;
+		}		
+		pWorkingTable->use_sg = 0;
+		pWorkingTable->request_bufflen = pagelen;
+		pWorkingTable->request_buffer = pWorkingTable->DataBuffer;
+		pWorkingTable->pDataBufPtr= pWorkingTable->DataBuffer;
+		// rebuild CDB		
+		pScsiCmd->cmnd[0] = MODE_SELECT_10;
+		pScsiCmd->cmnd[1] = ((pWorkingTable->OrgCmnd[1] & 0x01)|0x10);	// keep SP & set PF=1
+		pScsiCmd->cmnd[7] = (unsigned char)(pagelen >>8);
+		pScsiCmd->cmnd[8] = (unsigned char)pagelen;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 
+#else
+		if (km_sg_used) {
+			kunmap_atomic(km_buffer - sg_list->offset,KM_IRQ0);
+			local_irq_restore(km_flags);
+		}
+#endif		
+		break;
+	case 0xCD:
+		// backup original srb
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+		}
+		pScsiCmd->cmnd[0] = 0xBA;
+		break;
+	case 0xD8:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+		}
+		pScsiCmd->cmnd[0] = ATAPI_READ_CD;
+		pScsiCmd->cmnd[6] = pScsiCmd->cmnd[7];
+		pScsiCmd->cmnd[7] = pScsiCmd->cmnd[8];
+		pScsiCmd->cmnd[8] = pScsiCmd->cmnd[9];
+		switch(pScsiCmd->cmnd[10]) {
+		case 0:
+			pScsiCmd->cmnd[9]  = 0xF8;
+			pScsiCmd->cmnd[10] = 0;
+			break;
+		case 1:
+			pScsiCmd->cmnd[9]  = 0xF8;
+			pScsiCmd->cmnd[10] = 0x02;
+			break;
+		case 2:
+			pScsiCmd->cmnd[9]  = 0xF8;
+			pScsiCmd->cmnd[10] = 0x04;
+			break;
+		case 3:
+			pScsiCmd->cmnd[9]  = 0x40;
+			pScsiCmd->cmnd[10] = 0x04;
+			break;
+		}
+		pScsiCmd->cmnd[11] = 0;
+		break;
+	case 0xD9:
+		for (i = 0 ; i < 12 ; i++) {
+			pWorkingTable->OrgCmnd[i] = pScsiCmd->cmnd[i];
+		}
+		pScsiCmd->cmnd[0] = 0xB9;
+		pScsiCmd->cmnd[6] = pScsiCmd->cmnd[7];
+		pScsiCmd->cmnd[7] = pScsiCmd->cmnd[8];
+		pScsiCmd->cmnd[8] = pScsiCmd->cmnd[9];
+		switch(pScsiCmd->cmnd[10]) {
+		case 0:
+			pScsiCmd->cmnd[9]  = 0xF8;
+			pScsiCmd->cmnd[10] = 0;
+			break;
+		case 1:
+			pScsiCmd->cmnd[9]  = 0xF8;
+			pScsiCmd->cmnd[10] = 0x02;
+			break;
+		case 2:
+			pScsiCmd->cmnd[9]  = 0xF8;
+			pScsiCmd->cmnd[10] = 0x04;
+			break;
+		case 3:
+			pScsiCmd->cmnd[9]  = 0x40;
+			pScsiCmd->cmnd[10] = 0x04;
+			break;
+		}
+		pScsiCmd->cmnd[11] = 0;
+		break;
+	}
+	return;
+}
+//=======================================================================================
+static void ConvertSenseKey(P_Channel pChannel,P_WorkingTable pWorkingTable,unsigned char status)
+{
+	P_DeviceInfo pDeviceInfo = pWorkingTable->pDevice;
+	T_U64 end_lba64;
+
+	if (status & 0x80) {
+		pDeviceInfo->SenseKey = 0x0B;
+		pDeviceInfo->SenseAsc = 0x47;
+		pDeviceInfo->SenseAscQ = 0x01;
+	} else if (status & 0x40) {
+		pDeviceInfo->SenseKey = 0x03;
+		pDeviceInfo->SenseAsc = 0x11;
+		if (	(pWorkingTable->XferCmd == IDE_READ_DMA) ||
+			(pWorkingTable->XferCmd == IDE_READ_DMA) ||
+			(pWorkingTable->XferCmd == 0xC4) ||
+			(pWorkingTable->XferCmd == 0x29) ||
+			(pWorkingTable->XferCmd == IDE_READ_PIO) ||
+			(pWorkingTable->XferCmd == IDE_READ_PIO_EXT) ||
+			(pWorkingTable->XferCmd == IDE_NCQ_READ)
+		   ) {
+			pDeviceInfo->SenseAscQ = 0x00;
+		} else {
+			pDeviceInfo->SenseAscQ = 0x0C;
+		}
+	} else if (status & 0x20) {
+		pDeviceInfo->SenseKey = 0x06;
+		pDeviceInfo->SenseAsc = 0x28;
+		pDeviceInfo->SenseAscQ = 0x00;
+	} else if (status & 0x10) {
+		AddU64(&(pWorkingTable->StartLBAOrg),&(pWorkingTable->TransferLenOrg),&end_lba64);
+		if (CmpU64(&end_lba64,&(pDeviceInfo->Capacity)) > 0) {
+			pDeviceInfo->SenseKey = 0x05;
+			pDeviceInfo->SenseAsc = 0x21;
+			pDeviceInfo->SenseAscQ = 0x00;
+		} else {
+			pDeviceInfo->SenseKey = 0x03;
+			pDeviceInfo->SenseAsc = 0x11;
+			if (	(pWorkingTable->XferCmd == IDE_READ_DMA) ||
+				(pWorkingTable->XferCmd == IDE_READ_DMA) ||
+				(pWorkingTable->XferCmd == 0xC4) ||
+				(pWorkingTable->XferCmd == 0x29) ||
+				(pWorkingTable->XferCmd == IDE_READ_PIO) ||
+				(pWorkingTable->XferCmd == IDE_READ_PIO_EXT) ||
+				(pWorkingTable->XferCmd == IDE_NCQ_READ)
+			   ) 		{
+				pDeviceInfo->SenseAscQ = 0x00;
+			} else {
+				pDeviceInfo->SenseAscQ = 0x0c;
+			}
+		}
+	} else if (status & 0x0A) {
+		pDeviceInfo->SenseKey = 0x02;
+		pDeviceInfo->SenseAsc = 0x3a;
+		pDeviceInfo->SenseAscQ = 0x00;
+	} else if (status & 0x04) {
+		// internal target failure
+		pDeviceInfo->SenseKey = 0x0b;
+		pDeviceInfo->SenseAsc = 0x44;
+		pDeviceInfo->SenseAscQ = 0x00;
+	} else {
+		pDeviceInfo->SenseKey = 0x0b;
+		pDeviceInfo->SenseAsc = 0x00;
+		pDeviceInfo->SenseAscQ = 0x00;
+	}
+	return;
+}
+//=======================================================================================
+static void AddU64(P_U64 pSrc64_1,P_U64 pSrc64_2,P_U64 pDest64)
+{
+	 (pDest64->U64L).U64L_L = (pSrc64_1->U64L).U64L_L + (pSrc64_2->U64L).U64L_L;
+	if (	  ((pDest64->U64L).U64L_L < (pSrc64_1->U64L).U64L_L)
+		&&((pDest64->U64L).U64L_L < (pSrc64_2->U64L).U64L_L)
+	   ) {
+		 (pDest64->U64L).U64L_H = (pSrc64_1->U64L).U64L_H + (pSrc64_2->U64L).U64L_H + 1;
+	} else {
+		 (pDest64->U64L).U64L_H = (pSrc64_1->U64L).U64L_H + (pSrc64_2->U64L).U64L_H;
+	}
+	return;
+}
+//=======================================================================================
+/*
+static void SubU64(P_U64 pSrc64_1,P_U64 pSrc64_2,P_U64 pDest64)
+{
+	 (pDest64->U64L).U64L_L = (pSrc64_1->U64L).U64L_L - (pSrc64_2->U64L).U64L_L;
+	if ((pDest64->U64L).U64L_L > (pSrc64_1->U64L).U64L_L) {
+		 (pDest64->U64L).U64L_H = (pSrc64_1->U64L).U64L_H - (pSrc64_2->U64L).U64L_H - 1;
+	} else {
+		 (pDest64->U64L).U64L_H = (pSrc64_1->U64L).U64L_H - (pSrc64_2->U64L).U64L_H;
+	}
+	return;
+}
+*/
+//=======================================================================================
+static int CmpU64(P_U64 pSrc64_1,P_U64 pSrc64_2)
+{
+	if (((pSrc64_1->U64L).U64L_H) == ((pSrc64_2->U64L).U64L_H)) {
+		if (((pSrc64_1->U64L).U64L_L) == ((pSrc64_2->U64L).U64L_L)) {
+			return 0;
+		} else if (((pSrc64_1->U64L).U64L_L) > ((pSrc64_2->U64L).U64L_L)) {
+			return 1;
+		} else {
+			return -1;
+		}
+
+	} else if (((pSrc64_1->U64L).U64L_H) > ((pSrc64_2->U64L).U64L_H)) {
+		return 1;
+	} else {
+		return -1;
+	}
+}
+//=======================================================================================
+static void mDelay(int interval)
+{
+	int i;
+	
+	for (i = 0 ; i < interval ; i++) {
+		udelay(1000);
+		cpu_relax();
+	}
+	return;
+}
+//=======================================================================================
+static void Debug80Port(unsigned char code,int delaytime)
+{
+#if DEBUG_80_PORT
+	outb(code,0x80);
+	udelay(delaytime);
+#endif
+	return;
+}
+//=======================================================================================
+//=======================================================================================
+#include <linux/ide.h>
+
+static int __devinit atp8620_init_one(struct pci_dev *dev)
+{
+	unsigned long base , ctl;
+    
+	base = dev->resource[0].start+0x80;
+	ctl = dev->resource[0].start+0x8e;
+	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
+
+
+	memset(&hw, 0, sizeof(hw));
+	ide_std_init_ports(&hw, base, ctl);
+	hw.irq = dev->irq;
+	hw.chipset = ide_pci;
+
+	return ide_host_add(NULL, hws, NULL);
+}
+
+
+static int __init atp8620_setup(char *options)
+{
+    if (!options || !*options)
+        return 0;
+    if(options[0]=='0')oldide=0;
+    else oldide=1;
+    return 1;
+}
+
+__setup("oldide=", atp8620_setup);
+
diff -uNra linux-2.6.27.6/drivers/scsi/atp8620.h linux-2.6.27.6.yaffs/drivers/scsi/atp8620.h
--- linux-2.6.27.6/drivers/scsi/atp8620.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/atp8620.h	2011-05-08 18:00:56.000000000 +0800
@@ -0,0 +1,740 @@
+#include <linux/types.h>
+#include <linux/kdev_t.h>
+#include <linux/version.h>
+#ifndef NULL
+#define NULL 0
+#endif
+//=============================================================================
+#define DRV_VERSION_MAJOR	1
+#define DRV_VERSION_MINOR	1
+#define DRV_VERSION_BUILD	5
+//==============================================================================
+#define _ULTRA_DMA133		6
+#define _ULTRA_DMA100		5
+#define _ULTRA_DMA66		4
+#define _ULTRA_DMA33		2
+#define _MAX_ULTRA		_ULTRA_DMA133
+#define _MAX_PIO_MODE		4
+//=============================================================================
+#define MAX_ADAPTER		4
+#define	MAX_COMMAND_QUEUE_CH	7
+#define	MAX_QUEUE_SUPPORT	16
+#define MAX_SCATTER		17
+#define MAX_XFER_SECTORS		128
+#define MAX_CMDLUN		1
+#define MAX_SATA_CHANNEL		2
+#define MAX_SATA_HDD		5 
+#define MAX_CHAIN_LEVEL		1
+#define MAXTARGETHDD		((MAX_SATA_CHANNEL * MAX_SATA_HDD) + 2)
+#define TIMER_SCALE		(HZ/10)		// 100mS
+//=============================================================================
+#define MEM_512B			(0x000200)
+#define MEM_1KB			(0x000400)
+#define MEM_2KB			(0x000800)
+#define MEM_4KB			(0x001000)
+#define MEM_8KB			(0x002000)
+#define MEM_16KB			(0x004000)
+#define MEM_32KB			(0x008000)
+#define MEM_64KB			(0x010000)
+#define MEM_128KB		(0x020000)
+#define MEM_256KB		(0x040000)
+#define MEM_512KB		(0x080000)
+#define MEM_1MB			(0x100000)
+#define MEM_2MB			(0x200000)
+//=============================================================================
+#define MEM_8KB_ORDER           1
+#define MEM_16KB_ORDER          2
+#define MEM_32KB_ORDER          3
+#define MEM_64KB_ORDER          4
+#define MEM_128KB_ORDER         5
+#define MEM_256KB_ORDER         6
+#define MEM_512KB_ORDER         7
+#define MEM_1MB_ORDER           8
+#define MEM_2MB_ORDER           9
+//==============================================================================
+#define EXTENSION_MEM		MEM_64KB_ORDER
+#define EXTENSION_MEM_LEN	MEM_64KB
+#define WORKINGTABLE_MEM_LEN	(MEM_32KB + MEM_16KB)
+//==============================================================================
+#define SCSIOP_INQUIRY		0x12
+#define SCSIOP_REQUEST_SENSE	0x03
+#define SCSIOP_READ_CAPACITY	0x25
+#define SCSIOP_MODE_SENSE	0x1A	//MODE SENSE (6)
+#define SCSIOP_MODE_SENSE10	0x5A	//MODE SENSE (10)
+#define SCSIOP_MEDIUM_REMOVAL	0x1E
+#define SCSIOP_MODE_SELECT	0x15	//MODE Select (6)
+#define SCSIOP_MODE_SELECT10	0x55	//MODE Select (10)
+#define SCSIOP_TEST_UNIT_READY	0x00
+#define SCSIOP_START_STOP_UNIT	0x1B
+#define SCSIOP_SEEK6		0x0B
+#define SCSIOP_SEEK		0x2B	//SEEK(10)
+#define SCSIOP_VERIFY		0x2F
+#define SCSIOP_READ6		0x08	//READ(6)	
+#define SCSIOP_READ10		0x28	//READ(10)
+#define SCSIOP_READ12		0xA8	//READ(12)
+#define SCSIOP_READ16		0x88	//READ(16)
+#define SCSIOP_WRITE6		0x0A	//WRITE(6)
+#define SCSIOP_WRITE10		0x2A	//WRITE(10)
+#define SCSIOP_WRITE12		0xAA	//WRITE(12)
+#define SCSIOP_WRITE16		0x8A	//WRITE(16)
+#define SCSIOP_SYNC_CACHE	0x35
+//vendor define==================================================================
+#define Updata_NonData		0x38
+#define Fireware_ReadBuffer	0x3C
+#define Fireware_WriteBuffer	0x3B
+//==============================================================================
+#define IDE_READ_PIO		0x20
+#define IDE_READ_PIO_EXT		0x24
+#define IDE_READ_DMA		0xC8
+#define IDE_READ_DMA_EXT		0x25
+#define IDE_NCQ_READ		0x60
+#define IDE_WRITE_PIO		0x30
+#define IDE_WRITE_PIO_EXT	0x34
+#define IDE_WRITE_DMA		0xCA
+#define IDE_WRITE_DMA_EXT	0x35
+#define IDE_NCQ_WRITE		0x61
+#define IDE_VERIFY		0x40
+#define IDE_VERIFY_EXT		0x42
+#define IDE_SEEK			0x70
+#define IDE_FLUSH_CACHE		0xE7
+#define IDE_FLUSH_CACHE_EXT	0xEA
+#define ATAPI_READ_CD		0xBE
+#define ATAPI_WRITE_CONTINUE	0xE1
+#define I2C_CMD_READ		0xF0
+#define I2C_CMD_WRITE		0xF1
+//======================vedor define=============================================
+//=========================I2C use======================================================
+#define STA		 	0x80
+#define STO 			0x40
+#define RD			0x20
+#define WR			0x10
+#define AC			0x8
+#define IFS			0x4
+#define IFM			0x2
+#define TIP			0x1
+//======================================I2C step
+#define	NONE			0
+#define R_F1			0x1
+#define R_F2			0x2
+#define R_F3			0x3
+#define R_F4			0x4
+#define R_F5			0x5
+#define W_F1			0x6
+#define W_F2			0x7
+#define W_F3			0x8
+#define W_F4			0x9
+//=============================================================================
+#define STATUS_RESET		(DID_RESET << 16)		// 0x00080000
+#define STATUS_GOOD		(DID_OK << 16)		// 0x00000000
+#define STATUS_BUSY		(DID_BUS_BUSY << 16)	// 0x00020000
+#define STATUS_NO_DEVICE		(DID_BAD_TARGET << 16)	// 0x00040000
+#define STATUS_CHECK_CONDITION	0x02
+#define STATUS_PENDING		0xFFF1
+
+#define  SAM_STAT_CHECK_CONDITION 0x02
+//;===========================================================================
+#define ATP8620_DEVID		0x000D
+#define DRIVER_NAME		"atp8620"
+#if __LITTLE_ENDIAN
+#define ADAPTER_INFORMATION	"ACARD ATP8620 PCI/PCI-X SATA Adapter Driver(LE)"
+#else
+#define ADAPTER_INFORMATION	"ACARD ATP8620 PCI/PCI-X SATA Adapter Driver(BE)"
+#endif
+#define ADAPTER_NAME		"atp8620"
+#define PROC_INFORMATION		"ACARD ATP8620 Driver"
+#define PROC_NAME		"atp8620"                   // folder name in /proc/scsi/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#define SCSI_DRV_TEMPLATE 			\
+{						\
+	next: NULL,				\
+	module: NULL,				\
+	name: ADAPTER_NAME,			\
+	proc_name: PROC_NAME,			\
+	proc_info: adapter_proc_info,		\
+	info: adapter_info,			\
+	bios_param: adapter_biosparam,		\
+	detect: adapter_detect, 			\
+	release: adapter_release,			\
+	queuecommand: adapter_queuecommand,		\
+	abort: NULL,				\
+	reset: adapter_reset,			\
+	command: NULL,				\
+	eh_strategy_handler: NULL,			\
+	eh_abort_handler: NULL, 			\
+	eh_device_reset_handler: NULL,		\
+	eh_bus_reset_handler: NULL,		\
+	eh_host_reset_handler: NULL,		\
+	slave_attach: NULL,			\
+	can_queue: MAX_QUEUE_SUPPORT,		\
+	this_id: 16,				\
+	sg_tablesize: MAX_SCATTER,			\
+	cmd_per_lun: MAX_CMDLUN,			\
+	present: 0,				\
+	unchecked_isa_dma: 0,			\
+	use_clustering: ENABLE_CLUSTERING,		\
+	use_new_eh_code: 1,			\
+	max_sectors: MAX_XFER_SECTORS,		\
+}
+#define PCI_DEVICE_ID_TABLE 								\
+{											\
+	{ PCI_VENDOR_ID_ARTOP, ATP8620_DEVID,  PCI_VENDOR_ID_ARTOP, ATP8620_DEVID },	\
+}
+#define DMA_TO_DEVICE	PCI_DMA_TODEVICE
+#else
+#define Scsi_Cmnd struct scsi_cmnd
+#define SCSI_DRV_TEMPLATE 					\
+{								\
+	.module			= THIS_MODULE,			\
+	.name			= ADAPTER_NAME		,	\
+	.proc_name		= PROC_NAME,			\
+	.proc_info		= adapter_proc_info,		\
+	.info			= adapter_info,			\
+	.bios_param		= adapter_biosparam,		\
+	.queuecommand		= adapter_queuecommand,		\
+	.eh_abort_handler	= NULL,				\
+	.eh_host_reset_handler	= adapter_reset,		\
+	.can_queue		= MAX_QUEUE_SUPPORT,		\
+	.this_id		= 16,				\
+	.sg_tablesize		= MAX_SCATTER,			\
+	.cmd_per_lun		= MAX_CMDLUN,			\
+	.use_clustering		= ENABLE_CLUSTERING,		\
+	.max_sectors		= MAX_XFER_SECTORS		\
+}
+#define PCI_DEVICE_ID_TABLE 						\
+{									\
+	{ PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP8620_DEVID)	},	\
+	{ 0, },								\
+}
+#endif
+//===========================================================================
+#if __LITTLE_ENDIAN
+typedef struct _U64C
+{
+	u8		U64C_L_LL;
+	u8		U64C_L_LH;
+	u8		U64C_L_HL;
+	u8		U64C_L_HH;
+	u8		U64C_H_LL;
+	u8		U64C_H_LH;
+	u8		U64C_H_HL;
+	u8		U64C_H_HH;
+}T_U64C,*P_U64C;
+typedef struct _U64I
+{
+	u16		U64I_LL;
+	u16		U64I_LH;
+	u16		U64I_HL;
+	u16		U64I_HH;
+}T_U64I,*P_U64I;
+typedef struct _U64L
+{
+	u32		U64L_L;
+	u32		U64L_H;
+}T_U64L,*P_U64L;
+#else
+typedef struct _U64C
+{
+	u8		U64C_H_HH;
+	u8		U64C_H_HL;
+	u8		U64C_H_LH;
+	u8		U64C_H_LL;
+	u8		U64C_L_HH;
+	u8		U64C_L_HL;
+	u8		U64C_L_LH;
+	u8		U64C_L_LL;
+}T_U64C,*P_U64C;
+typedef struct _U64I
+{
+	u16		U64I_HH;
+	u16		U64I_HL;
+	u16		U64I_LH;
+	u16		U64I_LL;
+}T_U64I,*P_U64I;
+typedef struct _U64L
+{
+	u32		U64L_H;
+	u32		U64L_L;
+}T_U64L,*P_U64L;
+#endif
+typedef union _U64
+{
+	T_U64L		U64L;
+	T_U64I		U64I;
+	T_U64C		U64C;
+} T_U64,*P_U64;
+//===========================================================================
+typedef struct _MailBox 
+{
+	unsigned int	BufAddress;
+	unsigned int	BufAddressU;
+	unsigned int	Reserved;
+	unsigned int	DataLength;
+} T_MailBox,*P_MailBox;
+//========================================================================
+//===========================================================================
+typedef struct _Host2DeviceFIS
+{
+	unsigned char	FIS_Type;
+#if __LITTLE_ENDIAN
+	unsigned char	PortMultiplier:4;
+	unsigned char	FG_Reserved:3;
+	unsigned char	FIS_Flag:1;
+#else
+	unsigned char	FIS_Flag:1;
+	unsigned char	FG_Reserved:3;
+	unsigned char	PortMultiplier:4;
+#endif
+	unsigned char	Command;
+	unsigned char	P1x1;
+	unsigned char	P1x3;
+	unsigned char	P1x4;
+	unsigned char	P1x5;
+	unsigned char	P1x6;
+	unsigned char	P1x3Exp;
+	unsigned char	P1x4Exp;
+	unsigned char	P1x5Exp;
+	unsigned char	P1x1Exp;
+	unsigned char	P1x2;
+	unsigned char	P1x2Exp;
+	unsigned char	Reserved1;
+	unsigned char	P3x6;
+	unsigned int	Reserved2[12];
+}T_Host2DeviceFIS,*P_Host2DeviceFIS;
+//===========================================================================
+typedef struct _CommandTable
+{
+	T_Host2DeviceFIS	CommandFIS;		// 64  bytes
+	unsigned char	AtapiCommnad[32];		// 32  bytes
+	unsigned char	Reserved[32];		// 64  bytes
+	T_MailBox	MailBox[24];		// 384 bytes
+}T_CommandTable,*P_CommandTable;			// 512 bytes
+//===========================================================================
+typedef struct _CommandHead
+{
+#if __LITTLE_ENDIAN
+	u8		CommandFISLen:5;
+	u8		AtapiPioFIS:1;
+	u8		ReadWrite:1;
+	u8		PreFetchAble:1;
+	u8		Reset:1;
+	u8		Bist:1;
+	u8		ClearBusy:1;
+	u8		Reserved0	:1;
+	u8		PortMultiplier:4;
+#else	
+	u8		PreFetchAble:1;
+	u8		ReadWrite:1;
+	u8		AtapiPioFIS:1;
+	u8		CommandFISLen:5;
+	u8		PortMultiplier:4;
+	u8		Reserved0:1;
+	u8		ClearBusy:1;
+	u8		Bist:1;
+	u8		Reset:1;
+#endif	
+	u16		PRDTL;
+	u32		PRD_ByteCount;
+	u32		CommandTablePtr;
+	u32		CommandTablePtrU;
+	u32		Reserved1[4];
+}T_CommandHead,*P_CommandHead;
+//===========================================================================
+typedef struct _CommandPtr
+{
+	P_CommandHead	pCommandHead;
+	P_CommandTable	pCommandTable;
+	dma_addr_t	pDmaCommandTable;
+}T_CommandPtr,*P_CommandPtr;
+//===========================================================================
+typedef struct _DmaSetupFIS
+{
+	unsigned char	FIS_Type;
+	unsigned char	FIS_Flag;
+	unsigned short	Reserved0;
+	unsigned int	DmaBufferIdentifierL;
+	unsigned int	DmaBufferIdentifierH;
+	unsigned int	Reserved1;
+	unsigned int	DmaBufferOffset;
+	unsigned int	DmaTransferCount;
+	unsigned int	Reserved2;
+} T_DmaSetupFIS,*P_DmaSetupFIS;
+//===========================================================================
+typedef struct _PioSetupFIS
+{
+	unsigned char	FIS_Type;
+	unsigned char	FIS_Flag;
+	unsigned char	Status;
+	unsigned char	Error;
+	unsigned char	P1x3;
+	unsigned char	P1x4;
+	unsigned char	P1x5;
+	unsigned char	P1x6;
+	unsigned char	P1x3Exp;
+	unsigned char	P1x4Exp;
+	unsigned char	P1x5Exp;
+	unsigned char	Reserved0;
+	unsigned char	P1x2;
+	unsigned char	P1x2Exp;
+	unsigned char	Reserved1;
+	unsigned char	E_Status;
+	unsigned short	TransferCount;
+	unsigned short	Reserved2;
+} T_PioSetupFIS,*P_PioSetupFIS;
+//===========================================================================
+typedef struct _Device2Host
+{
+	unsigned char	FIS_Type;
+	unsigned char	FIS_Flag;
+	unsigned char	Status;
+	unsigned char	Error;
+	unsigned char	P1x3;
+	unsigned char	P1x4;
+	unsigned char	P1x5;
+	unsigned char	P1x6;
+	unsigned char	P1x3Exp;
+	unsigned char	P1x4Exp;
+	unsigned char	P1x5Exp;
+	unsigned char	Reserved0;
+	unsigned char	P1x2;
+	unsigned char	P1x2Exp;
+	unsigned short	Reserved1;
+	unsigned int	Reserved2;
+}T_Device2Host,*P_Device2Host;
+//===========================================================================
+typedef struct _SetDeviceBitsFIS
+{
+	unsigned char	FIS_Type;
+	unsigned char	PortMultiplier:4;
+	unsigned char	FG_Interrupt:4;
+	unsigned char	Status;
+	unsigned char	Error;
+	unsigned int	CompleteMap;
+}T_SetDeviceBitsFIS,*P_SetDeviceBitsFIS;
+//===========================================================================
+typedef struct _ReciveFIS
+{
+	T_DmaSetupFIS	DmaSetupFIS;		//  28 bytes
+	unsigned int	Reserved0;		//   4 bytes
+	T_PioSetupFIS	PioSetupFIS;		//  20 bytes
+	unsigned int	Reserved1[3];		//  12 bytes
+	T_Device2Host	Device2HostFIS;		//  20bytes
+	unsigned int	Reserved2;		//   4 bytes
+	T_SetDeviceBitsFIS SetDeviceBitsFIS;	//   8 bytes
+	unsigned char	Reserved3[32];		//  32 bytes
+} T_ReciveFIS,*P_ReciveFIS;				// 128 bytes //256 bytes
+//========================================================================
+typedef struct _WorkingTable
+{
+	void		*pNextTable;
+	void		*pPrevTable;
+	void		*pDevice;
+	Scsi_Cmnd 	*pWorkingScsiCmd;
+	unsigned long	IoTagID;
+	P_MailBox	pMailBox;
+	unsigned int	LmailBox;
+	unsigned int	LmailBoxX;
+	unsigned int	pDmaSingleMapAddr;
+	unsigned int	sg_num;
+	unsigned int	PriorityLevel;
+	T_U64		StartLBA;
+	T_U64		TransferLen;
+	T_U64		StartLBAOrg;
+	T_U64		TransferLenOrg;
+	unsigned char	FG_TableActive:1;
+	unsigned char	FG_DmaToDevice:1;
+	unsigned char	FG_DoIoByDMA:1;
+	unsigned char	FG_Updata:1;
+	unsigned char	FG_NonData:1;
+	unsigned char	FG_Reserved:3;
+	unsigned char	TagID;
+	unsigned char	SenseKey;
+	unsigned char	SenseAsc;
+	unsigned char	SenseAscQ;
+	unsigned char	XferCmd;
+	void *		request_buffer;
+	unsigned long	request_bufflen;
+	// FOLLOWING IS FOR CDROM =============================
+	unsigned char	*pDataBufPtr;
+	unsigned long	DataCounter;
+	unsigned long	sg_offset;
+	unsigned long	sg_data_offset;
+	unsigned char	DataBuffer[932];
+	unsigned char	OrgCmnd[16];
+	void		*pOrgRequesrBuff;
+	unsigned long	pOrgRequestBuffLen;
+	unsigned long	Length;
+	unsigned long	use_sg;
+	unsigned long	old_use_sg;
+	unsigned char 	Rev[2];
+} T_WorkingTable,*P_WorkingTable;// this size should be equal to 4n bytes
+//========================================================================
+typedef struct _Channel
+{
+	//===========================================
+	unsigned int	MaxDeviceCount:4;
+	unsigned int	FG_PortMultiplier:1;
+	unsigned int	FG_StopIO:1;
+	unsigned int	FG_SataChannel:1;
+	unsigned int	FG_Reserved:23;
+	unsigned int	FG_ErrD2H:1;
+	unsigned int	FG_ErrSDB:1;
+	//===========================================
+	unsigned int	IdePortP1XX;
+	unsigned int	IdePortPSFF;
+	unsigned int	IdePortP3XX;
+	unsigned int	IdeRegPrdTable;
+	unsigned int	IdeRegSpeed;
+	P_WorkingTable	pCurRequest;
+	//===========================================
+	unsigned int	BaseIoPort;
+	P_ReciveFIS	pReciveFIS;
+	T_CommandPtr	CommandPtr;
+	P_CommandPtr	pCommandPtr;
+	P_WorkingTable	pPendingIO;
+	P_WorkingTable	pExecuteIO[MAX_COMMAND_QUEUE_CH];
+	unsigned char	QueueCount;
+	unsigned char	QueueStartTag;
+	unsigned char	ChannelOrder;
+	unsigned char	FG_ErrPMx;
+	unsigned char	Update;
+	unsigned char	rev[3];
+} T_Channel,*P_Channel;
+//========================================================================
+typedef struct _DeviceInfo
+{
+	unsigned char	FG_DeviceInstall:1;
+	unsigned char	FG_Support48Bits:1;
+	unsigned char	FG_QueueSupported:1;
+	unsigned char	FG_SerialATA:1;
+	unsigned char	FG_AtapiDevice:1;
+	unsigned char	FG_DiscDevice:1;
+	unsigned char	FG_OnSataChannel:1;
+	unsigned char	FG_InternalError:1;
+	unsigned char	HD_V1X6;
+	unsigned char	MultiBlk;
+	unsigned char	PIOxferclk;
+	unsigned char	PIO_Mode;
+	unsigned char	DMAxferclk;
+	unsigned char	DMA_Mode;
+	unsigned char	FG_IdeExcept;
+	unsigned char	SenseKey;
+	unsigned char	SenseAsc;
+	unsigned char	SenseAscQ;
+	unsigned char	FG_PMId:4;
+	unsigned char	FG_Reserved1:4;
+	unsigned char	MaxQueueDepth;
+	unsigned char	QueueCount;
+	unsigned char	HddType; /*fixed by gcc 2008-09-03 to support multiword dma*/
+	unsigned char	Reserved1;
+	unsigned short	A0Wait;
+	unsigned short	DeviceBlockSize;
+	T_U64		Capacity;
+//	unsigned int	Capacity_L;
+//	unsigned int	Capacity_H;
+	P_Channel	pChannel;
+	unsigned char	ModelName[40];
+	unsigned char	FirmWareRev[8];
+	unsigned char	SerialNo[20];
+} T_DeviceInfo,*P_DeviceInfo;
+//========================================================================
+typedef struct _HW_DEVICE_EXTENSION 
+{
+	unsigned short	VendorID;
+	unsigned short	DeviceID;
+	unsigned short	SubVendorID;
+	unsigned short	SubDeviceID;
+	unsigned char	ChipRevision;
+	unsigned char	IrqNum;
+	unsigned int	BaseIoPort0;
+	unsigned int	BaseIoPort1;
+	unsigned int	BaseIoPort2;
+	spinlock_t 	spin_lock;
+	struct Scsi_Host *pScsiHost;
+	struct pci_dev	*pPciDev;
+	struct timer_list AdapterTimer;
+	//====================================================================
+	T_Channel	IdeChannel;
+	T_Channel	SataChannel[MAX_SATA_CHANNEL];
+	T_DeviceInfo	DeviceInfo[(MAX_SATA_CHANNEL * MAX_SATA_HDD) + 2];
+	//====================================================================
+	P_WorkingTable	pWorkingTablePool;
+	unsigned char	*pSataChCmdTable[2];
+	dma_addr_t	pDmaSataChCmdTable[2];
+	unsigned char	*pUncachedExtension;	//Cmd Head+RcvFIS+IdeMailBox+IdentifyBuff
+	dma_addr_t	pDmaUncachedExtension;
+	unsigned char	*pIdentifyBuffer;
+	dma_addr_t	pDmaIdentifyBuffer;
+	P_MailBox	pIdeMailBox;
+	dma_addr_t	pDmaIdeMailBox;
+	unsigned int	IoTagID;
+	unsigned int	IoCounter;
+	unsigned char	FG_TimerStop;
+	unsigned char	FG_ExtensionAllocate;
+	Scsi_Cmnd 	*pScsiCmd; // for I2C use
+	unsigned char	I2C_STEP;   //for I2C use
+	unsigned char	Reserved2;
+} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
+//========================================================================
+typedef struct _IdentifyATADevice 
+{				// WORD
+   unsigned short	ConfigBitInfo;	// 00
+   unsigned short	CylinderNo;	// 01
+   unsigned short	Reserved0;	// 02
+   unsigned short	HeadNo;		// 03
+   unsigned short	Reserved1;	// 04
+   unsigned short	Reserved2;	// 05
+   unsigned short	SectorNo;	// 06
+   unsigned short	Reserved3;	// 07
+   unsigned short	Reserved4;	// 08
+   unsigned short	Reserved5;	// 09
+   unsigned char		SerialNo[20];	// 10-19
+   unsigned short	Reserved6;	// 20
+   unsigned short	Reserved7;	// 21
+   unsigned short	Reserved8;	// 22
+   unsigned char		FirmWareRev[8];	// 23-26
+   unsigned char		ModelName[40];	// 27-46
+#if __LITTLE_ENDIAN
+   unsigned char		MultipleBlk;	// 47(LOW BYTE)
+   unsigned char		Reserved9;	// 47(HIGH BYTE = 0x80)
+#else
+   unsigned char		Reserved9;	// 47(HIGH BYTE = 0x80)
+   unsigned char		MultipleBlk;	// 47(LOW BYTE)
+   
+#endif
+   unsigned short	ReservedA;	// 48
+   unsigned short	Capability;	// 49
+   unsigned short	Security;	// 50
+#if __LITTLE_ENDIAN
+   unsigned char		ReservedB;	// 51(LOW BYTE)
+   unsigned char		PIOMode;		// 51(HIGH BYTE)
+   unsigned char		ReservedC;		// 52(LOW BYTE)
+   unsigned char		DMAMode;		// 52(HIGH BYTE)
+#else
+   unsigned char		PIOMode;		// 51(HIGH BYTE)
+   unsigned char		ReservedB;	// 51(LOW BYTE)
+   unsigned char		DMAMode;		// 52(HIGH BYTE)
+   unsigned char		ReservedC;		// 52(LOW BYTE)
+#endif
+   unsigned short	FG_ValidMap;		// 53
+//   USHORT FG_Valid5458:1;	// 53
+//   USHORT FG_Valid6470:1;
+//   USHORT FG_Valid88: 1;
+//   USHORT FG_Vendor: 13;
+   unsigned short	Logical_CHS[3];		// 54 - 56
+   unsigned short	SectorCapacity0;	// 57
+   unsigned short	SectorCapacity1;		// 58
+   unsigned short	CurrRWMultiCommand;	// 59
+   unsigned int		TotalLBA;		// 60 - 61
+#if __LITTLE_ENDIAN
+   unsigned char		SingleWordDMASupport;	// 62 (LOW BYTE)
+   unsigned char		SingleWordDMAActive;	// 62 (HIGH BYTE)
+   unsigned char		MultiWordDMASupport;	// 63 (LOW BYTE)	
+   unsigned char		MultiWordDMAActive;	// 63 (HIGH BYTE)
+   unsigned char		AdvancePIOSupport;	// 64 (LOW BYTE)
+   unsigned char		ReservedD;		// 64 (HIGH BYTE)
+#else
+   unsigned char		SingleWordDMAActive;	// 62 (HIGH BYTE)
+   unsigned char		SingleWordDMASupport;	// 62 (LOW BYTE)
+   unsigned char		MultiWordDMAActive;	// 63 (HIGH BYTE)
+   unsigned char		MultiWordDMASupport;	// 63 (LOW BYTE)	
+   unsigned char		ReservedD;		// 64 (HIGH BYTE)
+   unsigned char		AdvancePIOSupport;	// 64 (LOW BYTE)
+#endif
+   unsigned short	MinMDMATransCycle;	// 65
+   unsigned short	ReCmdMinMDMATransCycle;	// 66
+   unsigned short	ReservedE;		// 67
+   unsigned short	MinPioTransCycle;	// 68
+   unsigned short	ResveredF[6];		// 69-74
+   unsigned short	QueueDepth;		// 75
+#if __LITTLE_ENDIAN			// 76
+   unsigned short	FG_Reserved76_0:1;
+   unsigned short	FG_SATA1_support:1;
+   unsigned short	FG_SATA2_support:1;
+   unsigned short	FG_Reserved76_47:5;
+   unsigned short	FG_NcqSupport:1;
+   unsigned short	FG_Reserved76_9F:7;
+#else
+   unsigned char		FG_Reserved76_9F:7;
+   unsigned char		FG_NcqSupport:1;
+   unsigned char		FG_Reserved76_47:5;
+   unsigned char		FG_SATA2_support:1;
+   unsigned char		FG_SATA1_support:1;
+   unsigned char		FG_Reserved76_0:1;
+#endif
+   unsigned short	ReservedG[6];		// 77-82
+   unsigned short	Word83;			// 83
+   unsigned short	ReservedH[4];		// 84-87
+   unsigned short	UltraModeMap;		// 88
+   unsigned short	ReservedI[4];		// 89 - 92
+   unsigned short	Word93;			// 93
+//   USHORT Word93BitIgnore : 13;	// 93 bit 0  - bit 12
+//   USHORT Cable80pin:1;		// 93 bit 13 80 PDIG-
+//   USHORT Word93Remain:2;	// 93 bit 14 - bit 15
+   unsigned short	ReservedJ[6];		// 94 - 99
+   unsigned int		LBA_48bits_Low;	// 100 - 101
+   unsigned int		LBA_48bits_High;	// 102 - 103
+   unsigned short	ReservedK[200];		// 104 - 255
+} UIdentify, *PUIdentify;
+//========================================================================
+typedef struct _UINQUIRYDATA {
+   unsigned char DeviceType;
+   unsigned char RemovableFlag;//bit7 removedable
+   unsigned char VersionInfo;  // bit0-2:ANSI version,bit3-5:ECMA version,bit6-7:ISO version
+   unsigned char ResponseDataFormat;
+   unsigned char AdditionalLength;
+   unsigned char Reserved[2];
+   unsigned char Flag;  //bit0:SoftReset,bit1:Commnad Queue,bit5:wide 16bits,bit6:wide 32bits 
+   unsigned char VendorId[8];
+   unsigned char ProductId[16];
+   unsigned char ProductRevisionLevel[4];
+   unsigned char VendorSpecific[20];
+   unsigned char Reserved3[40];
+} UINQUIRYDATA, *PUINQUIRYDATA;
+//========================================================================
+static int AllocateExtensionMemory(PHW_DEVICE_EXTENSION pHwDeviceExtension);
+static void ReleaseExtensionMemory(PHW_DEVICE_EXTENSION pHwDeviceExtension);
+//========================================================================
+static unsigned char SendIdentifyCmd2IDE(P_DeviceInfo pDeviceInfo,void *pBuffer,unsigned char IdentifyCmd);
+static void SetPIOfeature(P_DeviceInfo pHardDiskInfo,PUIdentify pIdentifyBuff,unsigned char MAXMODE);
+static void GetUltraMode(P_DeviceInfo pHardDiskInfo,unsigned char UltraMap);
+static void SetUltra(P_DeviceInfo pHardDiskInfo,unsigned char MAXMODE);
+static void SetUltrafeature(P_DeviceInfo pHardDiskInfo,PUIdentify pIdentifyBuff,unsigned char MAXMODE);
+static void SetDMAfeature(P_DeviceInfo pHardDiskInfo,PUIdentify PidentifyBuff,unsigned char MAXMODE);
+static void SetChipIo(P_DeviceInfo pHardDiskInfo);
+static void ScanATA(PHW_DEVICE_EXTENSION DeviceExtension,P_DeviceInfo pHardDiskInfo);
+static void ExecuteIdeATA(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel);
+static void HardDiskInterrupt(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel);
+static void ScanATAPI(PHW_DEVICE_EXTENSION DeviceExtension,P_DeviceInfo pHardDiskInfo);
+static void ExecuteIdeATAPI(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel);
+static void DoPioATAPIXfer(P_WorkingTable pWorkingTable);
+static void DoDmaATAPIXfer(P_WorkingTable pWorkingTable);
+static void CdRomInterrupt(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pIdeChannel);
+//========================================================================
+//========================================================================
+static int SoftwareReset(P_Channel pSataChannel,unsigned char PMx);
+static int PMxReset(P_Channel pSataChannel,unsigned char PMx);
+static void PortMultiplierEnumerate(PHW_DEVICE_EXTENSION DeviceExtension,P_Channel pSataChannel,P_DeviceInfo pDeviceInfo);
+static void SendIdentifyCommand(PHW_DEVICE_EXTENSION DeviceExtension,P_DeviceInfo pDeviceInfo,int PMx,unsigned char IdenCmd);
+static void ExecuteSataATA(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable);
+static void ExecuteSataATAPI(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable);
+//========================================================================
+//========================================================================
+static void BuildPrdTable(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable,P_MailBox pMailBox);
+static P_WorkingTable AllocateWorkingTable(PHW_DEVICE_EXTENSION DeviceExtension);
+static void ReleaseWorkingTable(P_WorkingTable pWorkingTable);
+static void ChannelIoHook(P_WorkingTable pWorkingTable);
+static void ChannelIoRemove(P_WorkingTable pWorkingTable);
+static void ConvertCommandATA(P_WorkingTable pWorkingTable);
+static void ConvertCmdATAPI(P_WorkingTable pWorkingTable);
+static void RestoreCmdATAPI(P_WorkingTable pWorkingTable);
+static void ConvertSenseKey(P_Channel pChannel,P_WorkingTable pWorkingTable,unsigned char status);
+//========================================================================
+//========================================================================
+static void AddU64(P_U64 Src64_1,P_U64 Src64_2,P_U64 Dest64);
+static int  CmpU64(P_U64 Src64_1,P_U64 Src64_2);
+static void mDelay(int interval);
+static void Debug80Port(unsigned char code,int delaytime);
+//========================================================================
+//===================updata fireware========================================
+static void ExecuteUpdata(PHW_DEVICE_EXTENSION DeviceExtension,P_WorkingTable pWorkingTable);
+//========================================================================
diff -uNra linux-2.6.27.6/drivers/scsi/Kconfig linux-2.6.27.6.yaffs/drivers/scsi/Kconfig
--- linux-2.6.27.6/drivers/scsi/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/Kconfig	2011-05-08 18:00:54.000000000 +0800
@@ -404,6 +404,15 @@
 	  To compile this driver as a module, choose M here: the
 	  module will be called atp870u.
 
+config SCSI_ACARD_ATP8620
+	tristate "ACARD ATP8620 SCSI support"
+	depends on PCI && SCSI
+	help
+	  This driver supports the ACARD SCSI host adapter.
+	  Support Chip <ATP8620>
+	  To compile this driver as a module, choose M here: the
+	  module will be called atp8620.
+
 config SCSI_AHA152X
 	tristate "Adaptec AHA152X/2825 support"
 	depends on ISA && SCSI && !64BIT
diff -uNra linux-2.6.27.6/drivers/scsi/Makefile linux-2.6.27.6.yaffs/drivers/scsi/Makefile
--- linux-2.6.27.6/drivers/scsi/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/Makefile	2011-05-08 18:01:03.000000000 +0800
@@ -98,6 +98,7 @@
 obj-$(CONFIG_MEGARAID_NEWGEN)	+= megaraid/
 obj-$(CONFIG_MEGARAID_SAS)	+= megaraid/
 obj-$(CONFIG_SCSI_ACARD)	+= atp870u.o
+obj-$(CONFIG_SCSI_ACARD_ATP8620)+= atp8620.o
 obj-$(CONFIG_SCSI_SUNESP)	+= esp_scsi.o	sun_esp.o
 obj-$(CONFIG_SCSI_GDTH)		+= gdth.o
 obj-$(CONFIG_SCSI_INITIO)	+= initio.o
diff -uNra linux-2.6.27.6/drivers/scsi/scsi_ioctl.c linux-2.6.27.6.yaffs/drivers/scsi/scsi_ioctl.c
--- linux-2.6.27.6/drivers/scsi/scsi_ioctl.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/scsi_ioctl.c	2011-05-08 18:01:03.000000000 +0800
@@ -43,6 +43,8 @@
 	unsigned int len, slen;
 	const char *string;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if (buffer) {
 		if (get_user(len, (unsigned int __user *) buffer))
 			return -EFAULT;
@@ -91,6 +93,8 @@
 	int result;
 	struct scsi_sense_hdr sshdr;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	SCSI_LOG_IOCTL(1, printk("Trying ioctl with scsi command %d\n", *cmd));
 
 	result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, 0,
@@ -188,6 +192,8 @@
 {
 	char scsi_cmd[MAX_COMMAND_SIZE];
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	/* No idea how this happens.... */
 	if (!sdev)
 		return -ENXIO;
@@ -281,6 +287,8 @@
 {
 	int val, result;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	/* The first set of iocts may be executed even if we're doing
 	 * error processing, as long as the device was opened
 	 * non-blocking */
diff -uNra linux-2.6.27.6/drivers/scsi/sg.c linux-2.6.27.6.yaffs/drivers/scsi/sg.c
--- linux-2.6.27.6/drivers/scsi/sg.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/sg.c	2011-05-08 18:01:00.000000000 +0800
@@ -803,6 +803,8 @@
 	Sg_request *srp;
 	unsigned long iflags;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	if ((!(sfp = (Sg_fd *) filp->private_data)) || (!(sdp = sfp->parentdp)))
 		return -ENXIO;
 
diff -uNra linux-2.6.27.6/drivers/scsi/sr_ioctl.c linux-2.6.27.6.yaffs/drivers/scsi/sr_ioctl.c
--- linux-2.6.27.6/drivers/scsi/sr_ioctl.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/scsi/sr_ioctl.c	2011-05-08 18:01:03.000000000 +0800
@@ -190,6 +190,8 @@
 
 	SDev = cd->device;
 
+	//printk("wgl : function = %s, %s\n", __func__, __FILE__);
+
 	if (!sense) {
 		sense = kmalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
 		if (!sense) {
diff -uNra linux-2.6.27.6/drivers/serial/8250.c linux-2.6.27.6.yaffs/drivers/serial/8250.c
--- linux-2.6.27.6/drivers/serial/8250.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/8250.c	2011-05-08 18:00:02.000000000 +0800
@@ -96,10 +96,15 @@
  * standard enumeration mechanism.   Platforms that can find all
  * serial ports via mechanisms like ACPI or PCI need not supply it.
  */
+/*
 #ifndef SERIAL_PORT_DFNS
 #define SERIAL_PORT_DFNS
 #endif
-
+*/
+#ifdef SERIAL_PORT_DFNS
+#undef SERIAL_PORT_DFNS
+#define SERIAL_PORT_DFNS
+#endif
 static const struct old_serial_port old_serial_port[] = {
 	SERIAL_PORT_DFNS /* defined in asm/serial.h */
 };
@@ -1477,6 +1482,7 @@
 		up = list_entry(l, struct uart_8250_port, list);
 
 		iir = serial_in(up, UART_IIR);
+		//printk("-----iir %x---------\n",iir);
 		if (!(iir & UART_IIR_NO_INT)) {
 			serial8250_handle_port(up);
 
@@ -2760,6 +2766,11 @@
 		port.hub6		= p->hub6;
 		port.private_data	= p->private_data;
 		port.dev		= &dev->dev;
+	printk("register port at index %d "
+				"(IO%lx MEM%llx IRQ%d): %d\n", i,
+				p->iobase, (unsigned long long)p->mapbase,
+				p->irq, ret);  //mj
+
 		if (share_irqs)
 			port.flags |= UPF_SHARE_IRQ;
 		ret = serial8250_register_port(&port);
@@ -2896,10 +2907,13 @@
 
 	mutex_lock(&serial_mutex);
 
+	printk("-%s--1--\n",__func__);
 	uart = serial8250_find_match_or_unused(port);
+	printk("-%s--2--\n",__func__);
 	if (uart) {
 		uart_remove_one_port(&serial8250_reg, &uart->port);
 
+	printk("-%s--3--\n",__func__);
 		uart->port.iobase       = port->iobase;
 		uart->port.membase      = port->membase;
 		uart->port.irq          = port->irq;
@@ -2962,33 +2976,45 @@
 	for (i = 0; i < NR_IRQS; i++)
 		spin_lock_init(&irq_lists[i].lock);
 
+//	printk("--%s------------1-------\n",__func__);
 	ret = uart_register_driver(&serial8250_reg);
+//	printk("--%s------------2-------\n",__func__);
 	if (ret)
 		goto out;
 
+//	printk("--%s------------3-------\n",__func__);
 	serial8250_isa_devs = platform_device_alloc("serial8250",
 						    PLAT8250_DEV_LEGACY);
+//	printk("--%s------------4-------\n",__func__);
+//	serial8250_isa_devs = platform_device_alloc("serial8250",PLAT8250_DEV_EXAR_ST16C554);
 	if (!serial8250_isa_devs) {
 		ret = -ENOMEM;
 		goto unreg_uart_drv;
 	}
 
 	ret = platform_device_add(serial8250_isa_devs);
+	printk("--%s------------5-------\n",__func__);
 	if (ret)
 		goto put_dev;
 
 	serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
 
+	printk("--%s------------6-------\n",__func__);
 	ret = platform_driver_register(&serial8250_isa_driver);
+//	printk("--%s------------7-------\n",__func__);
 	if (ret == 0)
 		goto out;
 
 	platform_device_del(serial8250_isa_devs);
+//	printk("--%s------------8-------\n",__func__);
  put_dev:
+//	printk("--%s------------9-------\n",__func__);
 	platform_device_put(serial8250_isa_devs);
  unreg_uart_drv:
+//	printk("--%s------------10-------\n",__func__);
 	uart_unregister_driver(&serial8250_reg);
  out:
+//	printk("--%s-------------11------\n",__func__);
 	return ret;
 }
 
diff -uNra linux-2.6.27.6/drivers/serial/8250_exar_st16c554.c linux-2.6.27.6.yaffs/drivers/serial/8250_exar_st16c554.c
--- linux-2.6.27.6/drivers/serial/8250_exar_st16c554.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/8250_exar_st16c554.c	2011-05-26 19:55:49.000000000 +0800
@@ -14,7 +14,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/serial_8250.h>
-
+/*
 #define PORT(_base,_irq)				\
 	{						\
 		.iobase		= _base,		\
@@ -23,12 +23,23 @@
 		.iotype		= UPIO_PORT,		\
 		.flags		= UPF_BOOT_AUTOCONF,	\
 	}
-
+*/
+#define PORT(_base,_irq)				\
+	{						\
+		.mapbase  = (resource_size_t)_base,		\
+		.irq		= _irq,			\
+		.uartclk	= 14745600,		\
+		.iotype		= UPIO_MEM,		\
+		.flags		= (UPF_BOOT_AUTOCONF|UPF_IOREMAP),	\
+		.regshift = 0, \
+	}
 static struct plat_serial8250_port exar_data[] = {
-	PORT(0x100, 5),
-	PORT(0x108, 5),
-	PORT(0x110, 5),
-	PORT(0x118, 5),
+	PORT(0x1e000000, 18),
+	PORT(0x1e000020, 19),
+	PORT(0x1e000040, 20),
+	PORT(0x1e000060, 21),
+	PORT(0x1e0000a0, 32),
+	PORT(0x1e0000c0, 33),
 	{ },
 };
 
diff -uNra linux-2.6.27.6/drivers/serial/Kconfig linux-2.6.27.6.yaffs/drivers/serial/Kconfig
--- linux-2.6.27.6/drivers/serial/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/Kconfig	2011-05-08 18:00:02.000000000 +0800
@@ -5,6 +5,22 @@
 menu "Serial drivers"
 	depends on HAS_IOMEM
 
+config SMIVGX_SERIAL_SECOND
+    bool "Silicon Motion VoyagerGX (SM501) serial port"
+
+config SMIVGX_EXT_CLOCK
+	bool "SMI external clock support"
+	depends on SMIVGX_SERIAL_SECOND
+
+config SMIVGX_SERIAL_CONSOLE
+	bool "SMI VoyagerGX console support"
+	depends on SMIVGX_SERIAL_SECOND
+	select SERIAL_CORE_CONSOLE
+
+config SMIVGX_UART_OUTPUT_BUF_SIZE
+	int "Output buffer size (in bytes)"
+	depends on SMIVGX_SERIAL_CONSOLE
+	default 1024
 #
 # The new 8250/16550 serial drivers
 config SERIAL_8250
diff -uNra linux-2.6.27.6/drivers/serial/Makefile linux-2.6.27.6.yaffs/drivers/serial/Makefile
--- linux-2.6.27.6/drivers/serial/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/Makefile	2011-05-08 18:00:03.000000000 +0800
@@ -65,6 +65,7 @@
 obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
 obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
 obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
+obj-$(CONFIG_SMIVGX_SERIAL_SECOND) += sm502/
 obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
 obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
 obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
diff -uNra linux-2.6.27.6/drivers/serial/serial_core.c linux-2.6.27.6.yaffs/drivers/serial/serial_core.c
--- linux-2.6.27.6/drivers/serial/serial_core.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/serial_core.c	2011-05-08 18:00:03.000000000 +0800
@@ -2189,6 +2189,7 @@
 	/*
 	 * If there isn't a port here, don't do anything further.
 	 */
+	printk("-%s--1--\n",__func__);
 	if (!port->iobase && !port->mapbase && !port->membase)
 		return;
 
@@ -2207,6 +2208,7 @@
 	if (port->type != PORT_UNKNOWN) {
 		unsigned long flags;
 
+	printk("-%s--2--\n",__func__);
 		uart_report_port(drv, port);
 
 		/* Power up port for set_mctrl() */
@@ -2437,6 +2439,7 @@
 
 	BUG_ON(in_interrupt());
 
+	printk("-%s--1--\n",__func__);
 	if (port->line >= drv->nr)
 		return -EINVAL;
 
@@ -2445,6 +2448,7 @@
 	mutex_lock(&port_mutex);
 	mutex_lock(&state->mutex);
 	if (state->port) {
+	printk("-%s--2--\n",__func__);
 		ret = -EINVAL;
 		goto out;
 	}
@@ -2464,6 +2468,7 @@
 		lockdep_set_class(&port->lock, &port_lock_key);
 	}
 
+	printk("-%s--3--\n",__func__);
 	uart_configure_port(drv, state, port);
 
 	/*
diff -uNra linux-2.6.27.6/drivers/serial/sm502/Makefile linux-2.6.27.6.yaffs/drivers/serial/sm502/Makefile
--- linux-2.6.27.6/drivers/serial/sm502/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/sm502/Makefile	2011-05-08 18:00:02.000000000 +0800
@@ -0,0 +1 @@
+obj-$(CONFIG_SMIVGX_SERIAL_SECOND) += smivgx_duart.o
diff -uNra linux-2.6.27.6/drivers/serial/sm502/Readme.txt linux-2.6.27.6.yaffs/drivers/serial/sm502/Readme.txt
--- linux-2.6.27.6/drivers/serial/sm502/Readme.txt	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/sm502/Readme.txt	2011-05-08 18:00:02.000000000 +0800
@@ -0,0 +1,129 @@
+           Linux VoyagerGX Serial driver information
+           =========================================
+
+
+Introduction
+------------
+Silicon Motion, Inc. VoyagerGX serial driver supports 16750 model UART device,
+and it utilizes two 64-byte FIFOs, one for reception and one for transmission.
+The driver supports the following baud rates.
+
+   - 50 bps	- 1200 bps	- 9600 bps	- 57600 bps
+   - 75 bps	- 1800 bps	- 12800 bps	- 115200 bps
+   - 110 bps	- 2000 bps	- 14400 bps	- 128000 bps
+   - 135 bps	- 2400 bps	- 19200 bps	- 256000 bps
+   - 150 bps	- 3600 bps	- 23040 bps
+   - 300 bps	- 4800 bps	- 28800 bps
+   - 600 bps	- 7200 bps	- 38400 bps
+
+
+Supported Kernel Version
+------------------------
+The driver has been developed and tested under Linux 2.4.20.
+
+
+Setup
+-----
+VoyagerGX serial driver initial setup information for Linux:
+
+* Copy the following device driver files to <linux source root>/drivers/char/
+
+    Config.in
+    Makefile
+    smivgx.h
+    smivgx_duart.c
+    tty_io.c
+
+* Use your favorite config program (menuconfig or xconfig) to configure the
+  driver. Go under "Characher devices", where you should find the following:
+
+    Silicon Motion VoyagerGX (SM501) serial port
+      SMI VoyagerGX console support
+      Output buffer size (in bytes)
+
+  The first line enables the driver, this one is a must. The second line
+  enables the console support for the driver. And finally you can change
+  the default size of the internal transmit buffer. The default size is
+  1024 bytes, which in most cases should be good eniugh.
+  After you're done with the configuration steps, save the changes abd exit
+  from the config program.
+
+  When the configuration is complete, run consequently these commands:
+
+    make dep
+    make clean
+    make bzImage
+
+  If you haven't got any error messages, at this point you shoud have
+  a compressed kernel image file ready.
+
+
+Errata
+------
+
+* The current Voyager GX Serial device does not work properly with the
+  standard serial device due to discrepancy in baud rate generator clock
+  where SMI clock can not get the actual baud rate.
+
+* Voyager Gx can only supports some of the baud rate up to 38400 bps to
+  communicate with the standard serial device.
+
+* SMI Voyager GX uses 8 MHz baud rate generator clock which is generated
+  from dividing 96 MHz PLL 0 by 12.
+
+* This table below provide the calculation of the actual baud rate generated
+  by SMI Serial Device using the following formula:
+
+	Desired Baud Rate = fClock / (16 * Divisor Value)
+
+  where:
+	fClock = 8 Mhz (default SMI Voyager GX baud rate generator clock)
+	Divisor Value = integer number between 2 to 65535.
+
+  NOTE: Unlike the original serial device, division by 1 generates a BAUD
+        signal that is constantly high.
+
+
+   ==========================================================================
+   | Desired Baud Rate	| Divisor Value	| Actual Baud Rate |   Difference   |
+   |       (bps)	|		|  to the nearest  | to the nearest |
+   |			|		|     integer	   |    integer	    |
+   |			|		|      (bps)	   |      (bps)	    |
+   ==========================================================================
+   |          50	|    10000	|	  50	   |	    -	    |
+   |          75	|     6667	|	  75	   |	    -	    |
+   |         110	|     4545      |        110	   |	    -	    |
+   |         135	|     3713	|        135	   |	    -	    |
+   |         150	|     3333	|        150	   |	    -	    |
+   |         300	|     1667	|        300	   |	    -	    |
+   |         600	|      833	|        600	   |	    -	    |
+   |        1200	|      417	|       1199	   |	    1	    |
+   |        1800	|      277	|       1805	   |	    5	    |
+   |        2000	|      250	|       2000	   |	    -	    |
+   |        2400	|      208	|       2403	   |	    3	    |
+   |        3600	|      139	|       3597	   |	    3	    |
+   |        4800	|      104	|       4808	   |	    8	    |
+   |        7200	|       69	|       7246	   |	   46	    |
+   |        9600	|       52	|       9615	   |	   15	    |
+   |       12800	|       39	|      12821	   |	   21	    |
+   |       14400	|       35	|      14286	   |	  114	    |
+   |       19200	|       26	|      19231	   |	   31	    |
+   |       23040	|       22	|      22727	   |	  313	    |
+   |       28800	|       17	|      29412	   |	  612	    |
+   |       38400	|       13	|      38462	   |	   62	    |
+   |       57600	|        9      |      55556	   |	 2044	    |
+   |      115200	|        4	|     125000	   |	 9800	    |
+   |      128000	|        4	|     125000	   |	 3000	    |
+   |      256000	|        2	|     250000       |	 6000	    |
+   ==========================================================================
+
+* There is an alternative solution to fix this problem, i.e., by changing the
+  12 Mhz or 24 Mhz crystal to other value that can support the desired baud
+  rate. However, this might cause the other modules in the Voyager GX to be
+  unusable, such as USB.
+
+  Formula to find the serial fClock:
+
+		         Crystal Value * 4
+		fClock = -----------------   where 4 and 12 are fixed values.
+		                12
diff -uNra linux-2.6.27.6/drivers/serial/sm502/smivgx_duart.c linux-2.6.27.6.yaffs/drivers/serial/sm502/smivgx_duart.c
--- linux-2.6.27.6/drivers/serial/sm502/smivgx_duart.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/sm502/smivgx_duart.c	2011-05-08 18:00:02.000000000 +0800
@@ -0,0 +1,1489 @@
+/******************************************************************************
+ * Copyright (C) 2004 Silicon Motion                                          *
+ *                                                                            *
+ * This program is free software; you can redistribute it and/or              *
+ * modify it under the terms of the GNU General Public License                *
+ * as published by the Free Software Foundation; either version 2             *
+ * of the License, or (at your option) any later version.                     *
+ *                                                                            *
+ * This program is distributed in the hope that it will be useful,            *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of             *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              *
+ * GNU General Public License for more details.                               *
+ *                                                                            *
+ * You should have received a copy of the GNU General Public License          *
+ * along with this program; if not, write to the Free Software                *
+ * Foundation, Inc.,                                                          *
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                  *
+ ******************************************************************************/
+
+/******************************************************************************
+ * Driver support for the on-chip VoyagerGX dual-channel serial port,         *
+ * running in asynchronous mode.  Also, support for doing a serial console    *
+ * on one of those ports.                                                     *
+ *                                                                            *
+ * The non-console part of this code is based heavily on the sb1250_duart.c   *
+ * driver also in this directory.  See tty_driver.h for a description of some *
+ * of the driver functions, though it (like most of the inline code           *
+ * documentation :) is a bit out of date.                                     *
+ *                                                                            *
+ * Note:                                                                      *
+ *   CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE is defined in Config.in               *
+ ******************************************************************************/
+
+#include <linux/types.h>
+#include <linux/serial.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/slab.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/termios.h>
+#include <linux/spinlock.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/errno.h>
+#include <linux/tty.h>
+#include <linux/sched.h>
+#include <linux/tty_flip.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/hardirq.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include "smivgx.h"
+
+//#define request_irq myrequest_irq 
+/*
+ * Version
+ */
+#define DUART_VERSION		1.0
+#define DUART_DATE		04/02/2004
+
+
+#define spin_lock_irqsave    
+#define spin_unlock_irqrestore 
+
+/*
+ * Debug output control
+ */
+#undef DUART_SPEW
+#define DUART_ERROR_MESSAGES
+#define DUART_DEBUG_PREFIX "SMI_VGX_UART "
+
+
+/*
+ * Global definitions
+ */
+#define JIFFIES_PER_SECOND	100
+#define DUART_SEND_WAIT		(JIFFIES_PER_SECOND * 3)
+
+#define OUTPUT_BUF_SIZE	512
+#define TX_INTEN		1
+
+/*
+ * Default transmission flags
+ */
+#define INPUT_CLOCK_RATE	8000000		/* 8MHz */
+#define DEFAULT_BAUD_RATE	115200
+#define DEFAULT_CFLAGS		(CS8 | B115200)
+
+
+/*
+ * Minimum maco
+ */
+#define MIN(a, b) (((a)<(b))?(a):(b))
+
+
+/*
+ * Driver object structures
+ */
+static struct tty_driver *smivgx_duart_driver;
+
+
+/*
+ * Reference count variable
+ */
+static int ref_count;
+
+
+/*
+ * Still not sure what the termios structures set up here are for,
+ * but we have to supply pointers to them to register the tty driver
+ */
+static struct tty_struct *duart_table[2];
+static struct termios    *duart_termios[2];
+static struct termios    *duart_termios_locked[2];
+
+
+/*
+ * PCI definitions
+ */
+#ifndef PCI_VENDOR_ID_SILICONMOTION
+#define PCI_VENDOR_ID_SILICONMOTION			0x126F
+#endif
+
+#ifndef PCI_DEVICE_ID_SILICONMOTION_SM501
+#define PCI_DEVICE_ID_SILICONMOTION_SM501	0x0501
+#endif
+
+#define SM501_MAGIC \
+	((PCI_VENDOR_ID_SILICONMOTION << 16) | \
+	 PCI_DEVICE_ID_SILICONMOTION_SM501)
+
+#define SM501_EXTENT		(2 * 1024 * 1024)
+
+#define SM501_MODULE_NAME	"smivgx_serial"
+#define PFX					SM501_MODULE_NAME ": "
+
+
+/*
+ * Register access definitions
+ */
+#define UART_REG_SPACING \
+	(UART_1_RECEIVE_BUFFER - UART_0_RECEIVE_BUFFER)
+
+/* Write to transmit, Read to receive */
+#define UART_DATA_REG(line) \
+	(UART_0_RECEIVE_BUFFER + (line) * UART_REG_SPACING)
+
+/* Read Only */
+#define UART_LINE_STATUS_REG(line) \
+	(UART_0_LINE_STATUS + (line) * UART_REG_SPACING)
+
+/* Read Only */
+#define UART_INT_STATUS_REG(line) \
+	(UART_0_STATUS + (line) * UART_REG_SPACING)
+
+/* Read/Write */
+#define UART_INTMASK_REG(line) \
+	(UART_0_INTERRUPT + (line) * UART_REG_SPACING)
+
+/* Write Only */
+#define UART_FIFO_CONTROL_REG(line) \
+	(UART_0_FIFO + (line) * UART_REG_SPACING)
+
+/* Read/Write */
+#define UART_LINE_CONTROL_REG(line) \
+	(UART_0_LINE_CTRL + (line) * UART_REG_SPACING)
+
+/* Write Only (?) */
+#define UART_DIVIDER_LOW_REG(line) \
+	(UART_0_DIVISOR_LATCH_LSB + (line) * UART_REG_SPACING)
+
+/* Write Only (?) */
+#define UART_DIVIDER_HIGH_REG(line) \
+	(UART_0_DIVISOR_LATCH_MSB + (line) * UART_REG_SPACING)
+
+
+/*
+ * Trigger values
+ */
+#define FIFO_LENGTH		64
+
+#define TRIGGER_DEFAULT	UART_0_FIFO_RX_TRIGGER_DEFAULT
+#define TRIGGER_QUARTER	UART_0_FIFO_RX_TRIGGER_QUARTER
+#define TRIGGER_HALF	UART_0_FIFO_RX_TRIGGER_HALF
+#define TRIGGER_MINUS_2	UART_0_FIFO_RX_TRIGGER_MINUS_2
+
+static unsigned int trigger_treshold[] =
+{
+	1, 16, 32, 62
+};
+
+
+/*
+ * This lock protects both the open flags for all the uart states as
+ * well as the reference count for the module
+ */
+static spinlock_t open_lock = SPIN_LOCK_UNLOCKED;
+
+
+/*
+ * Bit fields of flags in the flags field below
+ */
+#define SD_WRITE_WAKE       0x000000001
+
+
+/*
+ * Bit fields of flags in the flags field below
+ */
+typedef struct
+{
+	struct tty_struct   *tty;
+	unsigned char       outp_buf[CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE];
+	unsigned int        outp_head;
+	unsigned int        outp_tail;
+	unsigned int        outp_count;
+	spinlock_t          outp_lock;
+	unsigned int        outp_stopped;
+	unsigned int        outp_transmitting;
+	unsigned int        open;
+	unsigned long       flags;
+	unsigned int        last_cflags;
+	unsigned char       rx_fifo_trigger;
+	unsigned char       tx_fifo_trigger;
+	unsigned char       fifo_control_value;
+}
+uart_state_t, *puart_state_t;
+
+uart_state_t uart_states[2] = { [0 ... 1] = {
+tty:                0,
+					outp_head:          0,
+					outp_tail:          0,
+					outp_lock:          SPIN_LOCK_UNLOCKED,
+					outp_count:         0,
+					outp_transmitting:  0,
+					open:               0,
+					flags:              0,
+					last_cflags:        0,
+					rx_fifo_trigger:    0,
+					tx_fifo_trigger:    0,
+					fifo_control_value: 1,
+}};
+
+
+/*
+ * System-level info
+ */
+typedef struct
+{
+	/* Magic. */
+	unsigned int        magic;
+
+	/* The corresponding pci_dev structure. */
+	struct pci_dev*     dev;
+	unsigned int        device;
+	unsigned int        revision;
+
+	/* Hardware resources. */
+	unsigned int        phys_io;
+	unsigned char*      io;
+	unsigned int        irq;
+}
+smivgx_t, *psmivgx_t;
+
+psmivgx_t drv_data;
+int pci_session;
+
+
+/******************************************************************************
+ * MODULE PARAMETERS                                                          *
+ ******************************************************************************/
+
+static int io = -1;
+static int irq = -1;
+
+//module_param(io, int ,-1);
+MODULE_PARM_DESC(io, "sets base address for hostbus interface");
+//module_param(irq, int , -1);
+MODULE_PARM_DESC(irq, "sets IRQ for hostbus interface");
+
+void __init smivgx_serial_console_init(void);
+/******************************************************************************
+ * UTILITY FUNCTIONS FOR OUTPUT BUFFER                                        *
+ ******************************************************************************/
+
+unsigned char isempty(puart_state_t obj)
+{
+	return (obj->outp_count == 0);
+}
+
+unsigned char isfull(puart_state_t obj)
+{
+	return (obj->outp_count >= CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE);
+}
+
+unsigned int getvacant(puart_state_t obj)
+{
+	return (CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - obj->outp_count);
+}
+
+unsigned char getchar(puart_state_t obj)
+{
+	unsigned char ch = 0;
+
+	if (obj->outp_count)
+	{
+		ch = obj->outp_buf[obj->outp_head];
+		obj->outp_head = (obj->outp_head + 1) &
+			(CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - 1);
+		obj->outp_count--;
+	}
+
+	return ch;
+}
+
+static inline int copy_buf(char *dest, const char *src, int size, int from_user)
+{
+	if (from_user)
+	{
+		copy_from_user(dest, src, size);
+	}
+	else
+	{
+		memcpy(dest, src, size);
+	}
+
+	return size;
+}
+
+unsigned int storedata(puart_state_t obj,
+		int from_user, const unsigned char* buf, int count)
+{
+	int chars_written = 0;
+
+
+	/* Copy the data */
+	if (isfull(obj))
+	{
+		printk(DUART_DEBUG_PREFIX "[storedata]: the buffer is full!\n");
+	}
+	else
+	{
+		if (obj->outp_tail < obj->outp_head)
+		{
+			/* Straightforward case; copy from tail to head */
+			chars_written = copy_buf(obj->outp_buf + obj->outp_tail, buf,
+					MIN(count, obj->outp_head - obj->outp_tail), from_user);
+		}
+		else
+		{
+			/* Copy from tail to end of buffer, wrap around and then
+			   copy to head */
+			chars_written = copy_buf(obj->outp_buf + obj->outp_tail, buf,
+					MIN(CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - obj->outp_tail, count),
+					from_user);
+
+			if (chars_written < count)
+			{
+				chars_written += copy_buf(obj->outp_buf, buf + chars_written,
+						MIN(obj->outp_head, count - chars_written), from_user);
+			}
+		}
+
+		/* Update the pointers */
+		obj->outp_tail = (obj->outp_tail + chars_written) &
+			(CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - 1);
+		obj->outp_count += chars_written;
+
+#ifdef DUART_SPEW
+		printk(DUART_DEBUG_PREFIX "[storedata]: tail = %d\n", obj->outp_tail);
+		printk(DUART_DEBUG_PREFIX "[storedata]: head = %d\n", obj->outp_head);
+		printk(DUART_DEBUG_PREFIX "[storedata]: written = %d\n", chars_written);
+#endif
+	}
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[storedata]: --\n");
+#endif
+
+	return chars_written;
+}
+
+/******************************************************************************
+ * REGISTER ACCESS                                                            *
+ ******************************************************************************/
+
+inline unsigned int PEEK(psmivgx_t s, unsigned int address)
+{
+	register unsigned int value = readl(s->io + address);
+	rmb();
+	return value;
+}
+
+inline void POKE(psmivgx_t s, unsigned int address, unsigned int value)
+{
+	writel(value, s->io + address);
+	wmb();
+}
+
+inline unsigned char PEEKBYTE(psmivgx_t s, unsigned int address)
+{
+	register unsigned char value = readb(s->io + address);
+	rmb();
+	return value;
+}
+
+inline void POKEBYTE(psmivgx_t s, unsigned int address, unsigned char value)
+{
+	writeb(value, s->io + address);
+	wmb();
+}
+
+
+
+
+/******************************************************************************
+ * INLINE FUNCTIONS LOCAL TO THIS MODULE                                      *
+ ******************************************************************************/
+
+/*
+ * Mask out the passed interrupt lines at the duart level.  This should be
+ * called while holding the associated outp_lock
+ */
+static inline void duart_disable_ints(psmivgx_t s,
+		unsigned int line, unsigned char mask)
+{
+	unsigned char value;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_disable_ints]: ++(mask = 0x%02X)\n", mask);
+#endif
+
+	value = PEEKBYTE(s, UART_INTMASK_REG(line));
+	value &= ~mask;
+	POKEBYTE(s, UART_INTMASK_REG(line), value);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_disable_ints]: --\n");
+#endif
+}
+
+
+/*
+ * Unmask the passed interrupt lines at the duart level
+ */
+static inline void duart_enable_ints(psmivgx_t s,
+		unsigned int line, unsigned char mask)
+{
+	unsigned char value;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_enable_ints]: ++(mask = 0x%02X)\n", mask);
+#endif
+
+	value = PEEKBYTE(s, UART_INTMASK_REG(line));
+	value |= mask;
+	POKEBYTE(s, UART_INTMASK_REG(line), value);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_enable_ints]: --\n");
+#endif
+}
+
+
+/*
+ * Read the status register
+ */
+static inline unsigned char get_line_status_reg(psmivgx_t s, unsigned int line)
+{
+	return PEEKBYTE(s, UART_LINE_STATUS_REG(line));
+}
+
+
+/*
+ * Read the interrupt status register
+ */
+static inline unsigned char get_int_status_reg(psmivgx_t s, unsigned int line)
+{
+	return PEEKBYTE(s, UART_INT_STATUS_REG(line));
+}
+
+
+/*
+ * Derive which uart a call is for from the passed tty line
+ */
+static inline unsigned int get_line(struct tty_struct *tty)
+{
+	unsigned int line = tty->index;
+	return 0;
+}
+
+
+
+
+/******************************************************************************
+ * INTERRUPT HANDLING                                                         *
+ ******************************************************************************/
+
+/*
+ * Called from smivgx_interrupt_entry with a specific
+ * UART interrupt to process
+ */
+static void smivgx_uart_interrupt(psmivgx_t s, unsigned int line)
+{
+	unsigned int int_status;
+	puart_state_t obj = &uart_states[line];
+
+	//printk("int int int\n");
+	/* Read the interrupt status register */
+	//	int_status = get_int_status_reg(s, line);
+
+
+	/* Receive the data first */
+	//	if (TEST_FIELD(int_status, UART_0_STATUS_INTERRUPT, RX_DATA_RECEIVED) )
+	{
+
+		/* Read the interrupt status register */
+
+
+		unsigned int i;
+		unsigned char status;
+		unsigned char ch;
+		unsigned int flag;
+		//printk("11111111111111\n");
+
+
+		for (i = 0; ; i++)
+		{
+			/* Make sure we have something in the buffer */
+			//printk("1.55555555555555\n");
+			status = get_line_status_reg(s, line);
+			//printk("222222222222222222\n");
+			if (!TEST_FIELD(status, UART_0_LINE_STATUS_DATA, READY))
+				break;
+
+			/* Read the data */
+			ch = PEEKBYTE(s, UART_DATA_REG(line));
+
+			/* Reset the error flag */
+			flag = TTY_NORMAL;
+
+
+			//printk("____hex :%x  char:  %c\n",ch,ch);
+			/* Insert the character */
+			tty_insert_flip_char(obj->tty, ch, flag);
+		}
+
+
+		//	tty_flip_buffer_push(obj->tty);
+		tty_schedule_flip(obj->tty);	
+
+
+	}
+
+}
+
+
+/*
+ * Generic interrupt handler for both channels.  dev_id is a pointer
+ * to the proper uart_states structure, so from that we can derive
+ * which port interrupted
+ */
+static int smivgx_interrupt_entry(int irq, void *dev_id, struct pt_regs *regs)
+{
+	uart_state_t *us = (uart_state_t *)dev_id;
+	struct tty_struct *tty = us->tty;
+	unsigned int value;
+	int line = 0;
+	psmivgx_t s = (psmivgx_t)dev_id;
+	unsigned int int_status, line_status;
+
+	int_status = PEEKBYTE(s, UART_INT_STATUS_REG(line));
+	if (TEST_FIELD(int_status, UART_0_STATUS_INTERRUPT, RX_DATA_RECEIVED) ||
+			TEST_FIELD(int_status, UART_0_STATUS_INTERRUPT, RX_CHAR_TIMEOUT)){
+		int counter = 2048;
+		unsigned int ch;
+		line_status = get_line_status_reg(s,line);
+		if (TEST_FIELD(line_status, UART_0_LINE_STATUS_OVERRUN, ERROR))
+			tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+		if (TEST_FIELD(line_status, UART_0_LINE_STATUS_PARITY, ERROR)) {
+#ifdef DUART_SPEW
+			printk("Parity error!\n");
+#endif
+		}
+		while (counter > 0) {
+			line_status = get_line_status_reg(s,line);
+			if(TEST_FIELD(line_status, UART_0_LINE_STATUS_DATA, NOT_READY))
+				break;
+			ch = PEEKBYTE(s,UART_DATA_REG(line));
+			tty_insert_flip_char(tty, ch, 0);
+			//__________udelay(1);
+			counter--;
+		}
+		tty_flip_buffer_push(tty);
+	}
+
+	if (TEST_FIELD(int_status, UART_0_STATUS_INTERRUPT, TX_EMPTY)) {
+		smivgx_uart_interrupt(s,0);
+	}
+#ifdef DUART_SPEW
+	printk("[smivgx_interrupt_entry:] --\n");
+#endif
+	return IRQ_HANDLED;
+	//printk("<0>smivgx_interrupt_entry\n");
+	/* Determine which UART raised the interrupt */
+	//value = PEEK(s, INTERRUPT_STATUS);
+	//POKE(s,INTERRUPT_STATUS,value);
+
+	//	if (TEST_FIELD(value, INTERRUPT_STATUS_UART0, ACTIVE))
+	//		smivgx_uart_interrupt(s, 0);
+
+	//	if (TEST_FIELD(value, INTERRUPT_STATUS_UART1, ACTIVE))
+	//		smivgx_uart_interrupt(s, 1);
+	//	return 1;
+}
+
+
+/******************************************************************************
+ * ACTUAL DRIVER FUNCTIONS                                                    *
+ ******************************************************************************/
+
+/*
+ * Return the number of characters we can
+ * accomodate in a write at this instant
+ */
+static int duart_write_room(struct tty_struct *tty)
+{
+	return 1024;
+}
+
+
+/*
+ * The function enables the actual data transmission
+ */
+static void start_transmisson(unsigned int line)
+{
+	puart_state_t obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[start_transmisson]: ++(uart%d)\n", line);
+#endif
+
+	do
+	{
+		/* Make sure that the transmission
+		   has not been forced to stop */
+		if (obj->outp_stopped)
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[start_transmisson]: cannot start - duart_stop has been called\n");
+#endif
+			break;
+		}
+
+		/* If outp_count is not zero, then the
+		   transmission is in progress already */
+		if (obj->outp_transmitting)
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[start_transmisson]: already started\n");
+#endif
+			break;
+		}
+
+		/* Set the transmit fifo trigger level */
+		//		set_tx_trigger(drv_data, line, TRIGGER_DEFAULT);
+
+		/* Enable transmit interrupt */
+		duart_enable_ints(drv_data, line, GET_MASK(UART_0_INTERRUPT_TX_EMPTY));
+		obj->outp_transmitting = 1;
+	}
+	while (0);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[start_transmisson]: --\n");
+#endif
+}
+
+
+/*
+ * The function waits until the transfer is complete or
+ * until the specified timeout is reached
+ */
+static int wait_until_sent(unsigned int line, int timeout)
+{
+	int result = 0;
+	uart_state_t *obj = &uart_states[line];
+	unsigned long target_time = jiffies + timeout;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[wait_until_sent]: ++(timeout = %d, uart%d)\n",
+			timeout, line);
+#endif
+
+	while (1)
+	{
+		/* Stop if timed out */
+		if (jiffies > target_time)
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[wait_until_sent]: timed out\n");
+#endif
+			result = 1;
+			break;
+		}
+
+		/* Stop if everything is sent */
+		if (isempty(obj))
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[wait_until_sent]: the buffer is empty\n");
+#endif
+			break;
+		}
+
+		/* Wait a bit */
+		schedule_timeout(1);
+	}
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[wait_until_sent]: --\n");
+#endif
+	return result;
+}
+
+
+/*
+ * Buffer up to count characters from buf to be written.
+ * If we don't have other characters buffered, enable the
+ * tx interrupt to start sending
+ */
+static int duart_write(struct tty_struct* tty,const unsigned char* buf, int count)
+{
+
+	uart_state_t *us; 
+	int c, t, total = 0; 
+	unsigned long flags;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_write]: ++(%i chars by %i (%s))\n", count, current->pid, current->comm);
+#endif
+
+	if (!tty) return 0;
+
+	us = tty->driver_data;
+	if (!us) return 0;
+
+	spin_lock_irqsave(&us->outp_lock, flags);
+
+	for (;;) {
+		c = count;
+
+		t = OUTPUT_BUF_SIZE - us->outp_tail;
+		if (t < c) c = t; 
+
+		t = OUTPUT_BUF_SIZE - 1 - us->outp_count;
+		if (t < c) c = t; 
+
+		if (c <= 0) break;
+
+		memcpy(us->outp_buf + us->outp_tail, buf, c);
+
+		us->outp_count += c;
+		us->outp_tail = (us->outp_tail + c) & (OUTPUT_BUF_SIZE - 1);
+		buf += c;
+		count -= c;
+		total += c;
+	}
+
+	spin_unlock_irqrestore(&us->outp_lock, flags);
+
+	if (us->outp_count && !tty->stopped && !tty->hw_stopped && !(us->flags & TX_INTEN)) {
+		us->flags |= TX_INTEN;
+		if (0 == tty->index) {
+			duart_enable_ints(drv_data,0, GET_MASK(UART_0_INTERRUPT_TX_EMPTY));
+		} else {
+			duart_enable_ints(drv_data,1, GET_MASK(UART_1_INTERRUPT_TX_EMPTY));
+		}
+		us->outp_transmitting = 1;
+	}
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_write]: --(wrote %d character(s))\n", total);
+#endif
+
+	return total;
+#if 0
+	int i;
+	int line;
+	if(!tty) return 0;
+	line = get_line(tty);
+
+
+	/* Send the data */
+	for (i = 0; i < count; i++)
+	{	
+		//		printk("tx hex: %x char: %c\n",buf[i] ,buf[i]);
+
+		while((PEEK(drv_data,UART_LINE_STATUS_REG(line))&0x20) == 0);
+		POKEBYTE(drv_data, UART_DATA_REG(line), buf[i]);
+
+	}
+
+	return count;
+#endif
+}
+
+
+
+
+/*
+ * Return the number of characters in the output
+ * buffer that have yet to be written
+ */
+static int duart_chars_in_buffer(struct tty_struct *tty)
+{
+	int retval;
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t* obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_chars_in_buffer]: ++(uart%d)\n", line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&obj->outp_lock, flags);
+
+	retval = obj->outp_count;
+	if (retval == CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE)
+	{
+		obj->flags |= SD_WRITE_WAKE;
+	}
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&obj->outp_lock, flags);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_chars_in_buffer]: --(%i)\n", retval);
+#endif
+
+	return retval;
+}
+
+
+/*
+ * Kill everything we haven't yet shoved into the FIFO.
+ * Turn off the transmit interrupt since we've nothing more to transmit
+ */
+static void duart_flush_buffer(struct tty_struct *tty)
+{
+
+}
+
+
+/*
+ * Handle notification of a termios change.
+ */
+static void duart_set_termios(struct tty_struct *tty, struct termios *old)
+{
+
+}
+
+
+/*
+ * Stop pushing stuff into the fifo, now.
+ * Do the mask under the outp_lock to avoid races
+ * involving turning the interrupt line on/off
+ */
+static void duart_start(struct tty_struct *tty)
+{
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t *obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_start]: ++(uart%d)\n", line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&obj->outp_lock, flags);
+
+	/* Reset the stop flag */
+	obj->outp_stopped = 0;
+
+	/* Enable transmission interrupt */
+	start_transmisson(line);
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&obj->outp_lock, flags);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_start]: --\n");
+#endif
+}
+
+
+/*
+ * Stop pushing stuff into the fifo, now.
+ * Do the mask under the outp_lock to avoid races
+ * involving turning the interrupt line on/off
+ */
+static void duart_stop(struct tty_struct *tty)
+{
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t *obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_stop]: ++(uart%d)\n", line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&obj->outp_lock, flags);
+
+	/* Disable transmission interrupt */
+	duart_disable_ints(drv_data, line, GET_MASK(UART_0_INTERRUPT_TX_EMPTY));
+
+	/* Set the stop flag */
+	obj->outp_stopped = 1;
+	obj->outp_transmitting = 0;
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&obj->outp_lock, flags);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_stop]: --\n");
+#endif
+}
+
+
+/*
+ * IOCTL function dispatcher
+ */
+static int duart_ioctl(struct tty_struct *tty, struct file * file,
+		unsigned int cmd, unsigned long arg)
+{
+	int result = -ENOIOCTLCMD;
+	return result;
+}
+
+static int duart_compat_ioctl(struct tty_struct *tty, struct file * file,
+		unsigned int cmd, unsigned long arg)
+{
+	int result = -ENOIOCTLCMD;
+	printk("--------------compat_ioctl\n");
+	return result;
+}
+
+/*
+ * Not sure on the semantics of this; are we supposed to wait until the stuff
+ * already in the hardware FIFO drains, or are we supposed to wait until
+ * we've drained the output buffer, too?  I'm assuming the former, 'cause thats
+ * what the other drivers seem to assume
+ */
+static void duart_wait_until_sent(struct tty_struct *tty, int timeout)
+{
+	unsigned int line = get_line(tty);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_wait_until_sent]: ++(timeout = %d, uart%d)\n",
+			timeout, line);
+#endif
+
+	wait_until_sent(line, timeout);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_wait_until_sent]: --\n");
+#endif
+}
+
+/*
+ * Initializes the FIFO
+ */
+void init_fifo(unsigned int line)
+{
+	unsigned int value = uart_states[line].fifo_control_value;
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[init_fifo]: fifo_control_value is 0x%x\n", value);
+#endif
+	/*
+	 * FIXME:
+	 * _Need one elegant way
+	 */
+	if (line == 0) { 
+		value = SET_FIELD(value, UART_0_FIFO_TX_CLEAR, CLEAR);
+		value = SET_FIELD(value, UART_0_FIFO_RX_CLEAR, CLEAR);
+	} else {
+		value = SET_FIELD(value, UART_1_FIFO_TX_CLEAR, CLEAR);
+		value = SET_FIELD(value, UART_1_FIFO_RX_CLEAR, CLEAR);
+	}
+	value = SET_FIELD(value, UART_0_FIFO_ENABLE, ENABLE);
+	POKEBYTE(drv_data,UART_FIFO_CONTROL_REG(line), value);
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[init_fifo]: value is 0x%x\n", value);
+#endif
+}
+
+/*
+ * Open a tty line.  Note that this can be called multiple times,
+ * so ->open can be >1.  Only set up the tty struct if this is
+ * a "new" open, e.g. ->open was zero
+ */
+static int duart_open(struct tty_struct *tty, struct file *filp)
+{
+	uart_state_t* obj;
+	unsigned long flags;
+	//unsigned int line = get_line(tty);
+	unsigned int line = 0;
+
+	//printk("--------------duart open --------0\n");
+	/* Make sure we support the requested line */
+	if (line > 1) 
+		return -ENODEV;
+	//printk("--------------duart open --------1\n");
+	init_fifo(0);
+	/* Increase the reference counter */
+
+	tty->driver_data = NULL;
+	obj = &uart_states[line];
+	tty->driver_data = obj;
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&open_lock, flags);
+	if (!obj->open) {
+		obj->tty = tty;
+		obj->tty->termios->c_cflag = obj->last_cflags;
+	}
+	obj->open++;
+	obj->flags &= ~0x1;
+	//uart_states[0].tty=tty;
+
+#ifdef	CONFIG_SMIVGX_EXT_CLOCK
+	/*set GPIO Clock as uart's input	--by boyod */	
+	value = PEEK(drv_data,MISCELLANEOUS_TIMING);
+	value = SET_FIELD(value, MISCELLANEOUS_TIMING_UART0_PLL, ENABLE);
+	POKE(drv_data,MISCELLANEOUS_TIMING, value);
+#endif
+
+	//	duart_enable_ints(drv_data, line, 0x3);
+	//	duart_enable_ints(drv_data, line, 0x1);
+	duart_enable_ints(drv_data, line, GET_MASK(UART_0_INTERRUPT_RX_BUFFER));
+
+	{ 
+		unsigned int value;
+		value = PEEK(drv_data, INTERRUPT_MASK);
+		value = SET_FIELD(value, INTERRUPT_MASK_UART0, ENABLE);
+		POKE(drv_data, INTERRUPT_MASK, value);
+	}
+
+	spin_unlock_irqrestore(&open_lock, flags);
+//	printk("--------------duart open --------2\n");
+	return 0;
+}
+
+/*
+ * Close a reference count out.  If reference count hits zero, null the
+ * tty, kill the interrupts.  The tty_io driver is responsible for making
+ * sure we've cleared out our internal buffers before calling close()
+ */
+static void duart_close(struct tty_struct *tty, struct file *filp)
+{
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t *obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_close]: ++(%i (%s), uart%d)\n",
+			current->pid, current->comm, line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&open_lock, flags);
+
+	obj->open--;
+	ref_count--;
+
+	if (!obj->open)
+	{
+		unsigned int value;
+
+		duart_disable_ints(drv_data, line, 0xFF);
+
+		switch (line)
+		{
+			case 0:
+				value = PEEK(drv_data, INTERRUPT_MASK);
+				value = SET_FIELD(value, INTERRUPT_MASK_UART0, DISABLE);
+				POKE(drv_data, INTERRUPT_MASK, value);
+
+				value = PEEK(drv_data, GPIO_CONTROL_HIGH);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_37, GPIO);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_38, GPIO);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_39, GPIO);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_40, GPIO);
+				POKE(drv_data, GPIO_CONTROL_HIGH, value);
+
+				value = PEEK(drv_data, CURRENT_GATE);
+				value = SET_FIELD(value, CURRENT_GATE_UART0, DISABLE);
+				//			set_power(drv_data, value, PEEK(drv_data, CURRENT_CLOCK));
+				break;
+
+			case 1:
+				value = PEEK(drv_data, INTERRUPT_MASK);
+				value = SET_FIELD(value, INTERRUPT_MASK_UART1, DISABLE);
+				POKE(drv_data, INTERRUPT_MASK, value);
+
+				value = PEEK(drv_data, MISCELLANEOUS_CONTROL);
+				value = SET_FIELD(value, MISCELLANEOUS_CONTROL_UART1_SELECT, SSP);
+				POKE(drv_data, MISCELLANEOUS_CONTROL, value);
+
+				value = PEEK(drv_data, GPIO_CONTROL_HIGH);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_41, GPIO);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_42, GPIO);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_43, GPIO);
+				value = SET_FIELD(value, GPIO_CONTROL_HIGH_44, GPIO);
+				POKE(drv_data, GPIO_CONTROL_HIGH, value);
+
+				value = PEEK(drv_data, CURRENT_GATE);
+				value = SET_FIELD(value, CURRENT_GATE_UART1, DISABLE);
+				//set_power(drv_data, value, PEEK(drv_data, CURRENT_CLOCK));
+
+				break;
+		}
+	}
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&open_lock, flags);
+
+	/* Decrease the reference counter */
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_close]: --\n");
+#endif
+}
+
+/*
+ * VoyagerGX deinitialization
+ */
+static void __devinit cleanup(psmivgx_t s)
+{
+	unsigned int ret;
+	unsigned int value;
+
+
+	if (s == NULL)
+		return;
+
+
+	ret = tty_unregister_driver(smivgx_duart_driver);
+	if (ret)
+		printk(DUART_DEBUG_PREFIX "[cleanup]: unable to unregister voyagergx duart serial driver (%d)\n", ret);
+
+	if (s->irq)
+	{
+		/* Remove interrupt service handler. */
+		synchronize_irq();
+		free_irq(s->irq, s);
+	}
+
+	if (s->io != NULL)
+	{
+		/* Disable interrupts */
+		value = PEEK(s, INTERRUPT_MASK);
+		value = SET_FIELD(value, INTERRUPT_MASK_UART0, DISABLE);
+		value = SET_FIELD(value, INTERRUPT_MASK_UART1, DISABLE);
+		POKE(s, INTERRUPT_MASK, value);
+
+		/* Disable UART0 and UART1. */
+		value = PEEK(s, CURRENT_GATE);
+		value = SET_FIELD(value, CURRENT_GATE_UART0, DISABLE);
+		value = SET_FIELD(value, CURRENT_GATE_UART1, DISABLE);
+		//set_power(s, value, PEEK(s, CURRENT_CLOCK));
+
+		/* Unmap I/O space. */
+		iounmap(s->io);
+		release_mem_region(s->phys_io, SM501_EXTENT);
+	}
+
+	/* Free state structure. */
+	kfree(s);
+
+}
+
+static inline void set_rx_trigger(unsigned int line, unsigned int trigger)
+{
+	puart_state_t	obj = &uart_states[line];
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[set_rx_trigger]: ++\n");
+	printk(DUART_DEBUG_PREFIX "[set_rx_trigger]: trigger is 0x%x\n", trigger);
+	printk(DUART_DEBUG_PREFIX "[set_rx_trigger]: obj->fifo_control_value is 0x%x\n", obj->fifo_control_value);
+#endif
+	if (line == 0) {
+		obj->rx_fifo_trigger = trigger & RAW_MASK(UART_0_FIFO_RX_TRIGGER);
+		obj->fifo_control_value = SET_FIELDV(obj->fifo_control_value,UART_0_FIFO_RX_TRIGGER, obj->rx_fifo_trigger);
+	} else {
+		obj->rx_fifo_trigger = trigger & RAW_MASK(UART_1_FIFO_RX_TRIGGER);
+		obj->fifo_control_value = SET_FIELDV(obj->fifo_control_value,UART_1_FIFO_RX_TRIGGER, obj->rx_fifo_trigger);
+	}
+	POKE(drv_data,UART_FIFO_CONTROL_REG(line), obj->fifo_control_value);
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[set_rx_trigger]: --\n");
+#endif
+}
+
+static inline void set_tx_trigger(unsigned int line, unsigned int trigger)
+{
+	puart_state_t	obj = &uart_states[line];
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[set_tx_trigger]: ++\n");
+	printk(DUART_DEBUG_PREFIX "[set_tx_trigger]: trigger is 0x%x\n", trigger);
+	printk(DUART_DEBUG_PREFIX "[set_tx_trigger]: obj->fifo_control_value is 0x%x\n", obj->fifo_control_value);
+#endif
+	if (line == 0) {
+		obj->tx_fifo_trigger = trigger & RAW_MASK(UART_0_FIFO_TX_TRIGGER);
+		obj->fifo_control_value = SET_FIELDV(obj->fifo_control_value, UART_0_FIFO_TX_TRIGGER, obj->tx_fifo_trigger);
+	} else {
+		obj->tx_fifo_trigger = trigger & RAW_MASK(UART_1_FIFO_TX_TRIGGER);
+		obj->fifo_control_value = SET_FIELDV(obj->fifo_control_value, UART_1_FIFO_TX_TRIGGER, obj->tx_fifo_trigger);
+	}
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[set_tx_trigger]: init fifo reg 0x%02x\n", obj->fifo_control_value);
+#endif
+	POKE(drv_data,UART_FIFO_CONTROL_REG(line), obj->fifo_control_value);
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[set_tx_trigger]: --\n");
+#endif
+}
+
+static void duart_hw_init(void)
+{
+	unsigned int	value;
+
+	value = PEEK(drv_data, GPIO_CONTROL_HIGH);
+	value = SET_FIELD(value, GPIO_CONTROL_HIGH_37, UART0_TX);
+	value = SET_FIELD(value, GPIO_CONTROL_HIGH_38, UART0_RX);
+	POKE(drv_data, GPIO_CONTROL_HIGH, value);
+
+	duart_disable_ints(drv_data,0, 0xff);
+
+	set_rx_trigger(0, TRIGGER_HALF);
+	/* Set the transmit fifo trigger level */
+	set_tx_trigger(0, TRIGGER_DEFAULT);
+}
+
+/*
+ * VoyagerGX initialization
+ */
+static int smivgx_init(struct platform_device *pdev)
+{
+	int res = -1;
+	psmivgx_t s = NULL;
+	unsigned int value;
+	struct pci_dev *pcidev=container_of(pdev->dev.parent,struct pci_dev,dev);
+	//prom_printf("smivgx_init enter\n");
+
+	/* Init the pointers */
+	drv_data = NULL;
+	pci_session = -1;
+
+	/* Allocate the state structure. */
+	s = kmalloc(sizeof(smivgx_t), GFP_KERNEL);
+	if (s == NULL)
+	{
+		printk(DUART_DEBUG_PREFIX "[smivgx_init]: out of memory\n");
+		return -ENOMEM;
+	}
+	memset(s, 0, sizeof(smivgx_t));
+
+	do
+	{
+
+		/* Enable PCI device. */
+		//		res = pci_enable_device(pcidev);
+
+		drv_data = s;
+		pci_session = 0;
+		//pci_set_drvdata(pcidev, drv_data);
+		smivgx_duart_driver = alloc_tty_driver(2);
+		/* Register the driver */
+		smivgx_duart_driver->driver_name      = "serial";
+
+		smivgx_duart_driver->name             = "ttyS";
+		smivgx_duart_driver->major            = TTY_MAJOR;
+		smivgx_duart_driver->minor_start      = 64;
+	  //smivgx_duart_driver.num               = 2;
+		smivgx_duart_driver->type             = TTY_DRIVER_TYPE_SERIAL;
+		smivgx_duart_driver->subtype          = SERIAL_TYPE_NORMAL;
+		smivgx_duart_driver->init_termios     = tty_std_termios;
+		smivgx_duart_driver->flags            = TTY_DRIVER_REAL_RAW;
+		smivgx_duart_driver->refcount         = &ref_count;
+	  //smivgx_duart_driver->table            = duart_table;
+		smivgx_duart_driver->termios          = duart_termios;
+		smivgx_duart_driver->termios_locked   = duart_termios_locked;
+
+		smivgx_duart_driver->ops->open             = duart_open;
+		smivgx_duart_driver->ops->close            = duart_close;
+		smivgx_duart_driver->ops->write            = duart_write;
+		smivgx_duart_driver->ops->write_room       = duart_write_room;
+		smivgx_duart_driver->ops->chars_in_buffer  = duart_chars_in_buffer;
+		smivgx_duart_driver->ops->flush_buffer     = duart_flush_buffer;
+		smivgx_duart_driver->ops->ioctl            = duart_ioctl;
+		//smivgx_duart_driver->ops->compat_ioctl     = duart_compat_ioctl;
+		smivgx_duart_driver->ops->set_termios      = duart_set_termios;
+		smivgx_duart_driver->ops->stop             = duart_stop;
+		smivgx_duart_driver->ops->start            = duart_start;
+		smivgx_duart_driver->ops->wait_until_sent  = duart_wait_until_sent;
+
+		/* Interrupts are now active, our ISR can be called. */
+		res = tty_register_driver(smivgx_duart_driver);
+		if (res)
+			printk(DUART_DEBUG_PREFIX "[smivgx_init]: " \
+					"couldn't register voyagergx duart serial driver\n");
+
+		/* Initialize state structure. */
+		s->magic   = SM501_MAGIC;
+		s->dev     = pcidev;
+		s->phys_io = (pcidev == NULL) ? io : pci_resource_start(pcidev, 1);
+		s->irq     = (pcidev == NULL) ? irq : pcidev->irq;
+
+		s->io = ioremap_nocache(s->phys_io, SM501_EXTENT);
+		//prom_printf("s->io=%llx\n",s->io);
+		if (s->io == NULL)
+		{
+			printk(DUART_DEBUG_PREFIX "[smivgx_init]: " \
+					"unable to map memory %08x-%08x\n",
+					s->phys_io, s->phys_io + SM501_EXTENT - 1);
+			res = -EBUSY;
+			break;
+		}
+		smivgx_serial_console_init();
+
+		/* Read device ID from I/O space. */
+		value = PEEK(s, DEVICE_ID);
+		s->device = GET_FIELD(value, DEVICE_ID_DEVICE);
+		s->revision = GET_FIELD(value, DEVICE_ID_REVISION);
+
+		printk(DUART_DEBUG_PREFIX "[smivgx_init]: " \
+				"found chip, device=%04x revision=%02x io=%p irq=%u\n",
+				s->device, s->revision, s->io, s->irq);
+
+		printk(DUART_DEBUG_PREFIX "[smivgx_init]: transmit buffer length = %d\n",
+				CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE);
+
+		duart_hw_init();
+
+		/* Set interrupt service handler. */
+		res = request_irq(36, smivgx_interrupt_entry, SA_SHIRQ, SM501_MODULE_NAME, drv_data);
+
+		if (res != 0)
+			panic(DUART_DEBUG_PREFIX "[smivgx_init]: unable to request irq %u\n", 36);
+
+		return 0;
+	}
+	while (0);
+
+	/* Uninitialize anything we have done so far. */
+	cleanup(s);
+
+	return res;
+}
+
+/*
+ * VoyagerGX removal
+ */
+static void __devinit smivgx_remove(struct platform_device *pdev)
+{
+	struct pci_dev* pcidev=container_of(pdev->dev.parent,struct pci_dev,dev);
+
+
+	/* cleanup state structure pointer. */
+	cleanup((pci_session == 0)? drv_data : pci_get_drvdata(pcidev));
+
+	if (pci_session == 1)
+		pci_set_drvdata(pcidev, NULL);
+
+	pci_session = -1;
+	drv_data = NULL;
+
+}
+
+/*
+ * PCI initialization structures
+ */
+static struct pci_device_id id_table[] __devinitdata =
+{
+	{ PCI_VENDOR_ID_SILICONMOTION, PCI_DEVICE_ID_SILICONMOTION_SM501, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
+	{ 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, id_table);
+
+static struct platform_driver smivgx_duart_pci_driver = {
+	.probe		= smivgx_init,
+	.remove		= smivgx_remove,
+	.driver		= {
+		.name	= "sm501-uart",
+		.owner	= THIS_MODULE,
+	},
+};
+
+/*
+ * Set up the driver and register it, register the 2 UART interrupts.
+ * This is called from tty_init, or as a part of the module init
+ */
+static int __init smivgx_duart_init(void)
+{
+	int res = -ENODEV;
+	res = platform_driver_register(&smivgx_duart_pci_driver);
+
+	return res;
+}
+
+/*
+ * Unload the driver.  Unregister stuff, get ready to go away
+ */
+static void __exit smivgx_duart_fini(void)
+{
+
+	platform_driver_unregister(&smivgx_duart_pci_driver);
+
+}
+
+/******************************************************************************
+ * MODULE ENTRY POINTS AND DESCRIPTION                                        *
+ ******************************************************************************/
+
+module_init(smivgx_duart_init);
+module_exit(smivgx_duart_fini);
+
+#ifdef CONFIG_SMIVGX_SERIAL_CONSOLE
+
+static void ser_console_write(struct console *cons, const char *str,
+		unsigned int count)
+{
+	unsigned int i;
+	unsigned long flags;
+	unsigned int line = 0;
+
+	/* Enter the critical section */
+
+	for (i = 0; i < count; i++)
+	{
+		if (str[i] == '\n')
+		{
+			/* Expand LF -> CRLF */
+			while((PEEK(drv_data,UART_LINE_STATUS_REG(line))&0x20) == 0);
+			POKEBYTE(drv_data, UART_DATA_REG(line), '\r');
+		}
+
+		while((PEEK(drv_data,UART_LINE_STATUS_REG(line))&0x20) == 0);
+		POKEBYTE(drv_data, UART_DATA_REG(line), str[i]);
+	}
+
+}
+
+static struct tty_driver * ser_console_device(struct console *c,int *index)
+{
+	*index = c->index;
+	return smivgx_duart_driver;
+}
+
+static int ser_console_setup(struct console *cons, char *str)
+{
+	return 0;
+}
+
+static struct console smivgx_ser_cons =
+{
+name:		"ttyS",
+			write:		ser_console_write,
+			device:		ser_console_device,
+			setup:		ser_console_setup,
+			flags:		CON_PRINTBUFFER,
+			index:		-1,
+};
+
+void __init smivgx_serial_console_init(void)
+{
+	register_console(&smivgx_ser_cons);
+}
+
+#endif /* CONFIG_SERIAL_CONSOLE */
+
+
diff -uNra linux-2.6.27.6/drivers/serial/sm502/smivgx_duart.c.old linux-2.6.27.6.yaffs/drivers/serial/sm502/smivgx_duart.c.old
--- linux-2.6.27.6/drivers/serial/sm502/smivgx_duart.c.old	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/sm502/smivgx_duart.c.old	2011-05-08 18:00:02.000000000 +0800
@@ -0,0 +1,1300 @@
+/******************************************************************************
+ * Copyright (C) 2004 Silicon Motion                                          *
+ *                                                                            *
+ * This program is free software; you can redistribute it and/or              *
+ * modify it under the terms of the GNU General Public License                *
+ * as published by the Free Software Foundation; either version 2             *
+ * of the License, or (at your option) any later version.                     *
+ *                                                                            *
+ * This program is distributed in the hope that it will be useful,            *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of             *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              *
+ * GNU General Public License for more details.                               *
+ *                                                                            *
+ * You should have received a copy of the GNU General Public License          *
+ * along with this program; if not, write to the Free Software                *
+ * Foundation, Inc.,                                                          *
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                  *
+ ******************************************************************************/
+
+/******************************************************************************
+ * Driver support for the on-chip VoyagerGX dual-channel serial port,         *
+ * running in asynchronous mode.  Also, support for doing a serial console    *
+ * on one of those ports.                                                     *
+ *                                                                            *
+ * The non-console part of this code is based heavily on the sb1250_duart.c   *
+ * driver also in this directory.  See tty_driver.h for a description of some *
+ * of the driver functions, though it (like most of the inline code           *
+ * documentation :) is a bit out of date.                                     *
+ *                                                                            *
+ * Note:                                                                      *
+ *   CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE is defined in Config.in               *
+ ******************************************************************************/
+
+#include <linux/types.h>
+#include <linux/serial.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/slab.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/termios.h>
+#include <linux/spinlock.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/errno.h>
+#include <linux/tty.h>
+#include <linux/sched.h>
+#include <linux/tty_flip.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/hardirq.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include "smivgx.h"
+
+//#define request_irq myrequest_irq 
+/*
+ * Version
+ */
+#define DUART_VERSION		1.0
+#define DUART_DATE		04/02/2004
+
+
+#define spin_lock_irqsave    
+#define spin_unlock_irqrestore 
+
+/*
+ * Debug output control
+ */
+#undef DUART_SPEW
+#define DUART_ERROR_MESSAGES
+#define DUART_DEBUG_PREFIX "SMI_VGX_UART "
+
+
+/*
+ * Global definitions
+ */
+#define JIFFIES_PER_SECOND	100
+#define DUART_SEND_WAIT		(JIFFIES_PER_SECOND * 3)
+
+
+/*
+ * Default transmission flags
+ */
+#define INPUT_CLOCK_RATE	8000000		/* 8MHz */
+#define DEFAULT_BAUD_RATE	115200
+#define DEFAULT_CFLAGS		(CS8 | B115200)
+
+
+/*
+ * Minimum maco
+ */
+#define MIN(a, b) (((a)<(b))?(a):(b))
+
+
+/*
+ * Driver object structures
+ */
+static struct tty_driver smivgx_duart_driver;
+
+
+/*
+ * Reference count variable
+ */
+static int ref_count;
+
+
+/*
+ * Still not sure what the termios structures set up here are for,
+ * but we have to supply pointers to them to register the tty driver
+ */
+static struct tty_struct *duart_table[2];
+static struct termios    *duart_termios[2];
+static struct termios    *duart_termios_locked[2];
+
+
+/*
+ * PCI definitions
+ */
+#ifndef PCI_VENDOR_ID_SILICONMOTION
+#define PCI_VENDOR_ID_SILICONMOTION			0x126F
+#endif
+
+#ifndef PCI_DEVICE_ID_SILICONMOTION_SM501
+#define PCI_DEVICE_ID_SILICONMOTION_SM501	0x0501
+#endif
+
+#define SM501_MAGIC \
+	((PCI_VENDOR_ID_SILICONMOTION << 16) | \
+	  PCI_DEVICE_ID_SILICONMOTION_SM501)
+
+#define SM501_EXTENT		(2 * 1024 * 1024)
+
+#define SM501_MODULE_NAME	"smivgx_serial"
+#define PFX					SM501_MODULE_NAME ": "
+
+
+/*
+ * Register access definitions
+ */
+#define UART_REG_SPACING \
+	(UART_1_RECEIVE_BUFFER - UART_0_RECEIVE_BUFFER)
+
+/* Write to transmit, Read to receive */
+#define UART_DATA_REG(line) \
+	(UART_0_RECEIVE_BUFFER + (line) * UART_REG_SPACING)
+
+/* Read Only */
+#define UART_LINE_STATUS_REG(line) \
+	(UART_0_LINE_STATUS + (line) * UART_REG_SPACING)
+
+/* Read Only */
+#define UART_INT_STATUS_REG(line) \
+	(UART_0_STATUS + (line) * UART_REG_SPACING)
+
+/* Read/Write */
+#define UART_INTMASK_REG(line) \
+	(UART_0_INTERRUPT + (line) * UART_REG_SPACING)
+
+/* Write Only */
+#define UART_FIFO_CONTROL_REG(line) \
+	(UART_0_FIFO + (line) * UART_REG_SPACING)
+
+/* Read/Write */
+#define UART_LINE_CONTROL_REG(line) \
+	(UART_0_LINE_CTRL + (line) * UART_REG_SPACING)
+
+/* Write Only (?) */
+#define UART_DIVIDER_LOW_REG(line) \
+	(UART_0_DIVISOR_LATCH_LSB + (line) * UART_REG_SPACING)
+
+/* Write Only (?) */
+#define UART_DIVIDER_HIGH_REG(line) \
+	(UART_0_DIVISOR_LATCH_MSB + (line) * UART_REG_SPACING)
+
+
+/*
+ * Trigger values
+ */
+#define FIFO_LENGTH		64
+
+#define TRIGGER_DEFAULT	UART_0_FIFO_RX_TRIGGER_DEFAULT
+#define TRIGGER_QUARTER	UART_0_FIFO_RX_TRIGGER_QUARTER
+#define TRIGGER_HALF	UART_0_FIFO_RX_TRIGGER_HALF
+#define TRIGGER_MINUS_2	UART_0_FIFO_RX_TRIGGER_MINUS_2
+
+static unsigned int trigger_treshold[] =
+{
+	1, 16, 32, 62
+};
+
+
+/*
+ * This lock protects both the open flags for all the uart states as
+ * well as the reference count for the module
+ */
+static spinlock_t open_lock = SPIN_LOCK_UNLOCKED;
+
+
+/*
+ * Bit fields of flags in the flags field below
+ */
+#define SD_WRITE_WAKE       0x000000001
+
+
+/*
+ * Bit fields of flags in the flags field below
+ */
+typedef struct
+{
+	struct tty_struct   *tty;
+	unsigned char       outp_buf[CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE];
+	unsigned int        outp_head;
+	unsigned int        outp_tail;
+	unsigned int        outp_count;
+	spinlock_t          outp_lock;
+	unsigned int        outp_stopped;
+	unsigned int        outp_transmitting;
+	unsigned int        open;
+	unsigned long       flags;
+	unsigned int        last_cflags;
+	unsigned char       rx_fifo_trigger;
+	unsigned char       tx_fifo_trigger;
+	unsigned char       fifo_control_value;
+}
+uart_state_t, *puart_state_t;
+
+uart_state_t uart_states[2] = { [0 ... 1] = {
+	tty:                0,
+	outp_head:          0,
+	outp_tail:          0,
+	outp_lock:          SPIN_LOCK_UNLOCKED,
+	outp_count:         0,
+	outp_transmitting:  0,
+	open:               0,
+	flags:              0,
+	last_cflags:        0,
+	rx_fifo_trigger:    0,
+	tx_fifo_trigger:    0,
+	fifo_control_value: 1,
+}};
+
+
+/*
+ * System-level info
+ */
+typedef struct
+{
+	/* Magic. */
+	unsigned int        magic;
+
+	/* The corresponding pci_dev structure. */
+	struct pci_dev*     dev;
+	unsigned int        device;
+	unsigned int        revision;
+
+	/* Hardware resources. */
+	unsigned int        phys_io;
+	unsigned char*      io;
+	unsigned int        irq;
+}
+smivgx_t, *psmivgx_t;
+
+psmivgx_t drv_data;
+int pci_session;
+
+
+/******************************************************************************
+ * MODULE PARAMETERS                                                          *
+ ******************************************************************************/
+
+static int io = -1;
+static int irq = -1;
+
+//module_param(io, int ,-1);
+MODULE_PARM_DESC(io, "sets base address for hostbus interface");
+//module_param(irq, int , -1);
+MODULE_PARM_DESC(irq, "sets IRQ for hostbus interface");
+
+void __init smivgx_serial_console_init(void);
+/******************************************************************************
+ * UTILITY FUNCTIONS FOR OUTPUT BUFFER                                        *
+ ******************************************************************************/
+
+unsigned char isempty(puart_state_t obj)
+{
+	return (obj->outp_count == 0);
+}
+
+unsigned char isfull(puart_state_t obj)
+{
+	return (obj->outp_count >= CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE);
+}
+
+unsigned int getvacant(puart_state_t obj)
+{
+	return (CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - obj->outp_count);
+}
+
+unsigned char getchar(puart_state_t obj)
+{
+	unsigned char ch = 0;
+
+	if (obj->outp_count)
+	{
+		ch = obj->outp_buf[obj->outp_head];
+		obj->outp_head = (obj->outp_head + 1) &
+			(CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - 1);
+		obj->outp_count--;
+	}
+
+	return ch;
+}
+
+static inline int copy_buf(char *dest, const char *src, int size, int from_user)
+{
+	if (from_user)
+	{
+		copy_from_user(dest, src, size);
+	}
+	else
+	{
+		memcpy(dest, src, size);
+	}
+
+	return size;
+}
+
+unsigned int storedata(puart_state_t obj,
+					   int from_user, const unsigned char* buf, int count)
+{
+	int chars_written = 0;
+
+
+	/* Copy the data */
+	if (isfull(obj))
+	{
+		printk(DUART_DEBUG_PREFIX "[storedata]: the buffer is full!\n");
+	}
+	else
+	{
+		if (obj->outp_tail < obj->outp_head)
+		{
+			/* Straightforward case; copy from tail to head */
+			chars_written = copy_buf(obj->outp_buf + obj->outp_tail, buf,
+				MIN(count, obj->outp_head - obj->outp_tail), from_user);
+		}
+		else
+		{
+			/* Copy from tail to end of buffer, wrap around and then
+			copy to head */
+			chars_written = copy_buf(obj->outp_buf + obj->outp_tail, buf,
+				MIN(CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - obj->outp_tail, count),
+				from_user);
+
+			if (chars_written < count)
+			{
+				chars_written += copy_buf(obj->outp_buf, buf + chars_written,
+					MIN(obj->outp_head, count - chars_written), from_user);
+			}
+		}
+
+		/* Update the pointers */
+		obj->outp_tail = (obj->outp_tail + chars_written) &
+			(CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE - 1);
+		obj->outp_count += chars_written;
+
+#ifdef DUART_SPEW
+		printk(DUART_DEBUG_PREFIX "[storedata]: tail = %d\n", obj->outp_tail);
+		printk(DUART_DEBUG_PREFIX "[storedata]: head = %d\n", obj->outp_head);
+		printk(DUART_DEBUG_PREFIX "[storedata]: written = %d\n", chars_written);
+#endif
+	}
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[storedata]: --\n");
+#endif
+
+	return chars_written;
+}
+
+/******************************************************************************
+ * REGISTER ACCESS                                                            *
+ ******************************************************************************/
+
+inline unsigned int PEEK(psmivgx_t s, unsigned int address)
+{
+    register unsigned int value = readl(s->io + address);
+    rmb();
+    return value;
+}
+
+inline void POKE(psmivgx_t s, unsigned int address, unsigned int value)
+{
+	writel(value, s->io + address);
+	wmb();
+}
+
+inline unsigned char PEEKBYTE(psmivgx_t s, unsigned int address)
+{
+    register unsigned char value = readb(s->io + address);
+    rmb();
+    return value;
+}
+
+inline void POKEBYTE(psmivgx_t s, unsigned int address, unsigned char value)
+{
+    writeb(value, s->io + address);
+    wmb();
+}
+
+
+
+
+/******************************************************************************
+ * INLINE FUNCTIONS LOCAL TO THIS MODULE                                      *
+ ******************************************************************************/
+
+/*
+ * Mask out the passed interrupt lines at the duart level.  This should be
+ * called while holding the associated outp_lock
+ */
+static inline void duart_disable_ints(psmivgx_t s,
+									  unsigned int line, unsigned char mask)
+{
+	unsigned char value;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_disable_ints]: ++(mask = 0x%02X)\n", mask);
+#endif
+
+	value = PEEKBYTE(s, UART_INTMASK_REG(line));
+	value &= ~mask;
+	POKEBYTE(s, UART_INTMASK_REG(line), value);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_disable_ints]: --\n");
+#endif
+}
+
+
+/*
+ * Unmask the passed interrupt lines at the duart level
+ */
+static inline void duart_enable_ints(psmivgx_t s,
+									 unsigned int line, unsigned char mask)
+{
+	unsigned char value;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_enable_ints]: ++(mask = 0x%02X)\n", mask);
+#endif
+
+	value = PEEKBYTE(s, UART_INTMASK_REG(line));
+	value |= mask;
+	POKEBYTE(s, UART_INTMASK_REG(line), value);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_enable_ints]: --\n");
+#endif
+}
+
+
+/*
+ * Read the status register
+ */
+static inline unsigned char get_line_status_reg(psmivgx_t s, unsigned int line)
+{
+	return PEEKBYTE(s, UART_LINE_STATUS_REG(line));
+}
+
+
+/*
+ * Read the interrupt status register
+ */
+static inline unsigned char get_int_status_reg(psmivgx_t s, unsigned int line)
+{
+	return PEEKBYTE(s, UART_INT_STATUS_REG(line));
+}
+
+
+/*
+ * Derive which uart a call is for from the passed tty line
+ */
+static inline unsigned int get_line(struct tty_struct *tty)
+{
+	unsigned int line = tty->index;
+
+	return 0;
+}
+
+
+
+
+/******************************************************************************
+ * INTERRUPT HANDLING                                                         *
+ ******************************************************************************/
+
+/*
+ * Called from smivgx_interrupt_entry with a specific
+ * UART interrupt to process
+ */
+static void smivgx_uart_interrupt(psmivgx_t s, unsigned int line)
+{
+	unsigned int int_status;
+	puart_state_t obj = &uart_states[line];
+
+//printk("int int int\n");
+	/* Read the interrupt status register */
+//	int_status = get_int_status_reg(s, line);
+
+
+	/* Receive the data first */
+//	if (TEST_FIELD(int_status, UART_0_STATUS_INTERRUPT, RX_DATA_RECEIVED) )
+	{
+
+	/* Read the interrupt status register */
+
+
+		unsigned int i;
+		unsigned char status;
+		unsigned char ch;
+		unsigned int flag;
+//printk("11111111111111\n");
+
+
+		for (i = 0; ; i++)
+		{
+			/* Make sure we have something in the buffer */
+//printk("1.55555555555555\n");
+			status = get_line_status_reg(s, line);
+//printk("222222222222222222\n");
+			if (!TEST_FIELD(status, UART_0_LINE_STATUS_DATA, READY))
+				break;
+
+			/* Read the data */
+			ch = PEEKBYTE(s, UART_DATA_REG(line));
+
+			/* Reset the error flag */
+			flag = TTY_NORMAL;
+
+
+//printk("____hex :%x  char:  %c\n",ch,ch);
+			/* Insert the character */
+			tty_insert_flip_char(obj->tty, ch, flag);
+		}
+
+
+	//	tty_flip_buffer_push(obj->tty);
+		tty_schedule_flip(obj->tty);	
+
+
+	}
+
+}
+
+
+/*
+ * Generic interrupt handler for both channels.  dev_id is a pointer
+ * to the proper uart_states structure, so from that we can derive
+ * which port interrupted
+ */
+static int smivgx_interrupt_entry(int irq, void *dev_id, struct pt_regs *regs)
+{
+	unsigned int value;
+	psmivgx_t s = (psmivgx_t)dev_id;
+
+//printk("<0>smivgx_interrupt_entry\n");
+	/* Determine which UART raised the interrupt */
+	value = PEEK(s, INTERRUPT_STATUS);
+	POKE(s,INTERRUPT_STATUS,value);
+
+	if (TEST_FIELD(value, INTERRUPT_STATUS_UART0, ACTIVE))
+		smivgx_uart_interrupt(s, 0);
+
+//	if (TEST_FIELD(value, INTERRUPT_STATUS_UART1, ACTIVE))
+//		smivgx_uart_interrupt(s, 1);
+	return 1;
+}
+
+
+/******************************************************************************
+ * ACTUAL DRIVER FUNCTIONS                                                    *
+ ******************************************************************************/
+
+/*
+ * Return the number of characters we can
+ * accomodate in a write at this instant
+ */
+static int duart_write_room(struct tty_struct *tty)
+{
+	return 1024;
+}
+
+
+/*
+ * The function enables the actual data transmission
+ */
+static void start_transmisson(unsigned int line)
+{
+	puart_state_t obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[start_transmisson]: ++(uart%d)\n", line);
+#endif
+
+	do
+	{
+		/* Make sure that the transmission
+		   has not been forced to stop */
+		if (obj->outp_stopped)
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[start_transmisson]: cannot start - duart_stop has been called\n");
+#endif
+			break;
+		}
+
+		/* If outp_count is not zero, then the
+		   transmission is in progress already */
+		if (obj->outp_transmitting)
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[start_transmisson]: already started\n");
+#endif
+			break;
+		}
+
+		/* Set the transmit fifo trigger level */
+//		set_tx_trigger(drv_data, line, TRIGGER_DEFAULT);
+
+		/* Enable transmit interrupt */
+		duart_enable_ints(drv_data, line, GET_MASK(UART_0_INTERRUPT_TX_EMPTY));
+		obj->outp_transmitting = 1;
+	}
+	while (0);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[start_transmisson]: --\n");
+#endif
+}
+
+
+/*
+ * The function waits until the transfer is complete or
+ * until the specified timeout is reached
+ */
+static int wait_until_sent(unsigned int line, int timeout)
+{
+	int result = 0;
+	uart_state_t *obj = &uart_states[line];
+	unsigned long target_time = jiffies + timeout;
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[wait_until_sent]: ++(timeout = %d, uart%d)\n",
+		timeout, line);
+#endif
+
+	while (1)
+	{
+		/* Stop if timed out */
+		if (jiffies > target_time)
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[wait_until_sent]: timed out\n");
+#endif
+			result = 1;
+			break;
+		}
+
+		/* Stop if everything is sent */
+		if (isempty(obj))
+		{
+#ifdef DUART_SPEW
+			printk(DUART_DEBUG_PREFIX "[wait_until_sent]: the buffer is empty\n");
+#endif
+			break;
+		}
+
+		/* Wait a bit */
+	 	schedule_timeout(1);
+	}
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[wait_until_sent]: --\n");
+#endif
+	return result;
+}
+
+
+/*
+ * Buffer up to count characters from buf to be written.
+ * If we don't have other characters buffered, enable the
+ * tx interrupt to start sending
+ */
+static int duart_write(struct tty_struct* tty,const unsigned char* buf, int count)
+{
+
+
+	int i;
+	int line;
+	if(!tty) return 0;
+	line = get_line(tty);
+
+
+		/* Send the data */
+	for (i = 0; i < count; i++)
+	{	
+//		printk("tx hex: %x char: %c\n",buf[i] ,buf[i]);
+		
+		while((PEEK(drv_data,UART_LINE_STATUS_REG(line))&0x20) == 0);
+		POKEBYTE(drv_data, UART_DATA_REG(line), buf[i]);
+
+	}
+
+	return count;
+}
+
+
+
+
+/*
+ * Return the number of characters in the output
+ * buffer that have yet to be written
+ */
+static int duart_chars_in_buffer(struct tty_struct *tty)
+{
+	int retval;
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t* obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_chars_in_buffer]: ++(uart%d)\n", line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&obj->outp_lock, flags);
+
+	retval = obj->outp_count;
+	if (retval == CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE)
+	{
+		obj->flags |= SD_WRITE_WAKE;
+	}
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&obj->outp_lock, flags);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_chars_in_buffer]: --(%i)\n", retval);
+#endif
+
+	return retval;
+}
+
+
+/*
+ * Kill everything we haven't yet shoved into the FIFO.
+ * Turn off the transmit interrupt since we've nothing more to transmit
+ */
+static void duart_flush_buffer(struct tty_struct *tty)
+{
+	
+}
+
+
+
+
+/*
+ * Handle notification of a termios change.
+ */
+static void duart_set_termios(struct tty_struct *tty, struct termios *old)
+{
+
+}
+
+
+/*
+ * Stop pushing stuff into the fifo, now.
+ * Do the mask under the outp_lock to avoid races
+ * involving turning the interrupt line on/off
+ */
+static void duart_start(struct tty_struct *tty)
+{
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t *obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_start]: ++(uart%d)\n", line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&obj->outp_lock, flags);
+
+	/* Reset the stop flag */
+	obj->outp_stopped = 0;
+
+	/* Enable transmission interrupt */
+	start_transmisson(line);
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&obj->outp_lock, flags);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_start]: --\n");
+#endif
+}
+
+
+/*
+ * Stop pushing stuff into the fifo, now.
+ * Do the mask under the outp_lock to avoid races
+ * involving turning the interrupt line on/off
+ */
+static void duart_stop(struct tty_struct *tty)
+{
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t *obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_stop]: ++(uart%d)\n", line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&obj->outp_lock, flags);
+
+	/* Disable transmission interrupt */
+	duart_disable_ints(drv_data, line, GET_MASK(UART_0_INTERRUPT_TX_EMPTY));
+
+	/* Set the stop flag */
+	obj->outp_stopped = 1;
+	obj->outp_transmitting = 0;
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&obj->outp_lock, flags);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_stop]: --\n");
+#endif
+}
+
+
+/*
+ * IOCTL function dispatcher
+ */
+static int duart_ioctl(struct tty_struct *tty, struct file * file,
+		       unsigned int cmd, unsigned long arg)
+{
+	int result = -ENOIOCTLCMD;
+	return result;
+}
+
+
+/*
+ * Not sure on the semantics of this; are we supposed to wait until the stuff
+ * already in the hardware FIFO drains, or are we supposed to wait until
+ * we've drained the output buffer, too?  I'm assuming the former, 'cause thats
+ * what the other drivers seem to assume
+ */
+static void duart_wait_until_sent(struct tty_struct *tty, int timeout)
+{
+	unsigned int line = get_line(tty);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_wait_until_sent]: ++(timeout = %d, uart%d)\n",
+		timeout, line);
+#endif
+
+	wait_until_sent(line, timeout);
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_wait_until_sent]: --\n");
+#endif
+}
+
+
+
+
+/*
+ * Open a tty line.  Note that this can be called multiple times,
+ * so ->open can be >1.  Only set up the tty struct if this is
+ * a "new" open, e.g. ->open was zero
+ */
+static int duart_open(struct tty_struct *tty, struct file *filp)
+{
+	uart_state_t* obj;
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+
+
+
+	/* Increase the reference counter */
+
+	tty->driver_data = NULL;
+	obj = &uart_states[line];
+	uart_states[0].tty=tty;
+	/* Enter the critical section */
+	spin_lock_irqsave(&open_lock, flags);
+	 request_irq(drv_data->irq, smivgx_interrupt_entry, SA_SHIRQ, SM501_MODULE_NAME, drv_data);
+	{ 
+			unsigned int value;
+			value = PEEK(drv_data, INTERRUPT_MASK);
+			value = SET_FIELD(value, INTERRUPT_MASK_UART0, ENABLE);
+			POKE(drv_data, INTERRUPT_MASK, value);
+	}
+	
+#ifdef	CONFIG_SMIVGX_EXT_CLOCK
+			/*set GPIO Clock as uart's input	--by boyod */	
+				value = PEEK(drv_data,MISCELLANEOUS_TIMING);
+				value = SET_FIELD(value, MISCELLANEOUS_TIMING_UART0_PLL, ENABLE);
+				POKE(drv_data,MISCELLANEOUS_TIMING, value);
+#endif
+
+
+//	duart_enable_ints(drv_data, line, 0x3);
+	duart_enable_ints(drv_data, line, 0x1);
+	spin_unlock_irqrestore(&open_lock, flags);
+
+	return 0;
+}
+
+
+/*
+ * Close a reference count out.  If reference count hits zero, null the
+ * tty, kill the interrupts.  The tty_io driver is responsible for making
+ * sure we've cleared out our internal buffers before calling close()
+ */
+static void duart_close(struct tty_struct *tty, struct file *filp)
+{
+	unsigned long flags;
+	unsigned int line = get_line(tty);
+	uart_state_t *obj = &uart_states[line];
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_close]: ++(%i (%s), uart%d)\n",
+		current->pid, current->comm, line);
+#endif
+
+	/* Enter the critical section */
+	spin_lock_irqsave(&open_lock, flags);
+
+	obj->open--;
+	ref_count--;
+
+	if (!obj->open)
+	{
+		unsigned int value;
+
+		duart_disable_ints(drv_data, line, 0xFF);
+
+		switch (line)
+		{
+		case 0:
+			value = PEEK(drv_data, INTERRUPT_MASK);
+			value = SET_FIELD(value, INTERRUPT_MASK_UART0, DISABLE);
+			POKE(drv_data, INTERRUPT_MASK, value);
+
+			value = PEEK(drv_data, GPIO_CONTROL_HIGH);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_37, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_38, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_39, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_40, GPIO);
+			POKE(drv_data, GPIO_CONTROL_HIGH, value);
+
+			value = PEEK(drv_data, CURRENT_GATE);
+			value = SET_FIELD(value, CURRENT_GATE_UART0, DISABLE);
+//			set_power(drv_data, value, PEEK(drv_data, CURRENT_CLOCK));
+			break;
+
+		case 1:
+			value = PEEK(drv_data, INTERRUPT_MASK);
+			value = SET_FIELD(value, INTERRUPT_MASK_UART1, DISABLE);
+			POKE(drv_data, INTERRUPT_MASK, value);
+
+			value = PEEK(drv_data, MISCELLANEOUS_CONTROL);
+			value = SET_FIELD(value, MISCELLANEOUS_CONTROL_UART1_SELECT, SSP);
+			POKE(drv_data, MISCELLANEOUS_CONTROL, value);
+
+			value = PEEK(drv_data, GPIO_CONTROL_HIGH);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_41, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_42, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_43, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_HIGH_44, GPIO);
+			POKE(drv_data, GPIO_CONTROL_HIGH, value);
+
+			value = PEEK(drv_data, CURRENT_GATE);
+			value = SET_FIELD(value, CURRENT_GATE_UART1, DISABLE);
+			//set_power(drv_data, value, PEEK(drv_data, CURRENT_CLOCK));
+
+			break;
+		}
+	}
+
+	/* Leave the critical section */
+	spin_unlock_irqrestore(&open_lock, flags);
+
+	/* Decrease the reference counter */
+
+#ifdef DUART_SPEW
+	printk(DUART_DEBUG_PREFIX "[duart_close]: --\n");
+#endif
+}
+
+
+/*
+ * VoyagerGX deinitialization
+ */
+static void __devinit cleanup(psmivgx_t s)
+{
+	unsigned int ret;
+	unsigned int value;
+
+
+	if (s == NULL)
+		return;
+
+
+	ret = tty_unregister_driver(&smivgx_duart_driver);
+	if (ret)
+		printk(DUART_DEBUG_PREFIX "[cleanup]: unable to unregister voyagergx duart serial driver (%d)\n", ret);
+
+	if (s->irq)
+	{
+		/* Remove interrupt service handler. */
+		synchronize_irq();
+		free_irq(s->irq, s);
+	}
+
+	if (s->io != NULL)
+	{
+		/* Disable interrupts */
+		value = PEEK(s, INTERRUPT_MASK);
+		value = SET_FIELD(value, INTERRUPT_MASK_UART0, DISABLE);
+		value = SET_FIELD(value, INTERRUPT_MASK_UART1, DISABLE);
+		POKE(s, INTERRUPT_MASK, value);
+
+		/* Disable UART0 and UART1. */
+		value = PEEK(s, CURRENT_GATE);
+		value = SET_FIELD(value, CURRENT_GATE_UART0, DISABLE);
+		value = SET_FIELD(value, CURRENT_GATE_UART1, DISABLE);
+		//set_power(s, value, PEEK(s, CURRENT_CLOCK));
+
+		/* Unmap I/O space. */
+		iounmap(s->io);
+		release_mem_region(s->phys_io, SM501_EXTENT);
+	}
+
+	/* Free state structure. */
+	kfree(s);
+
+}
+
+
+/*
+ * VoyagerGX initialization
+ */
+static int smivgx_init(struct platform_device *pdev)
+{
+	int res = -1;
+	psmivgx_t s = NULL;
+	unsigned int value;
+	struct pci_dev *pcidev=container_of(pdev->dev.parent,struct pci_dev,dev);
+
+	/* Init the pointers */
+	drv_data = NULL;
+	pci_session = -1;
+
+	/* Allocate the state structure. */
+	s = kmalloc(sizeof(smivgx_t), GFP_KERNEL);
+	if (s == NULL)
+	{
+		printk(DUART_DEBUG_PREFIX "[smivgx_init]: out of memory\n");
+		return -ENOMEM;
+	}
+	memset(s, 0, sizeof(smivgx_t));
+
+	do
+	{
+			
+		/* Enable PCI device. */
+//		res = pci_enable_device(pcidev);
+
+		drv_data = s;
+		pci_session = 0;
+		//pci_set_drvdata(pcidev, drv_data);
+
+		/* Register the driver */
+		smivgx_duart_driver.magic            = TTY_DRIVER_MAGIC;
+		smivgx_duart_driver.driver_name      = "serial";
+
+		smivgx_duart_driver.name             = "ttyS";
+		smivgx_duart_driver.major            = TTY_MAJOR;
+		smivgx_duart_driver.minor_start      = 64;
+		smivgx_duart_driver.num              = 2;
+		smivgx_duart_driver.type             = TTY_DRIVER_TYPE_SERIAL;
+		smivgx_duart_driver.subtype          = SERIAL_TYPE_NORMAL;
+		smivgx_duart_driver.init_termios     = tty_std_termios;
+		smivgx_duart_driver.flags            = TTY_DRIVER_REAL_RAW;
+		smivgx_duart_driver.refcount         = &ref_count;
+//		smivgx_duart_driver.table            = duart_table;
+		smivgx_duart_driver.termios          = duart_termios;
+		smivgx_duart_driver.termios_locked   = duart_termios_locked;
+
+		smivgx_duart_driver.ops->open             = duart_open;
+		smivgx_duart_driver.ops->close            = duart_close;
+		smivgx_duart_driver.ops->write            = duart_write;
+		smivgx_duart_driver.ops->write_room       = duart_write_room;
+		smivgx_duart_driver.ops->chars_in_buffer  = duart_chars_in_buffer;
+		smivgx_duart_driver.ops->flush_buffer     = duart_flush_buffer;
+		smivgx_duart_driver.ops->ioctl            = duart_ioctl;
+		smivgx_duart_driver.ops->set_termios      = duart_set_termios;
+		smivgx_duart_driver.ops->stop             = duart_stop;
+		smivgx_duart_driver.ops->start            = duart_start;
+		smivgx_duart_driver.ops->wait_until_sent  = duart_wait_until_sent;
+
+		/* Interrupts are now active, our ISR can be called. */
+		res = tty_register_driver(&smivgx_duart_driver);
+		if (res)
+			printk(DUART_DEBUG_PREFIX "[smivgx_init]: " \
+				"couldn't register voyagergx duart serial driver\n");
+		
+		/* Initialize state structure. */
+		s->magic   = SM501_MAGIC;
+		s->dev     = pcidev;
+		s->phys_io = (pcidev == NULL) ? io : pci_resource_start(pcidev, 1);
+		s->irq     = (pcidev == NULL) ? irq : pcidev->irq;
+
+
+		s->io = ioremap_nocache(s->phys_io, SM501_EXTENT);
+		if (s->io == NULL)
+		{
+			printk(DUART_DEBUG_PREFIX "[smivgx_init]: " \
+				"unable to map memory %08x-%08x\n",
+				s->phys_io, s->phys_io + SM501_EXTENT - 1);
+			res = -EBUSY;
+			break;
+		}
+		smivgx_serial_console_init();
+
+
+		/* Read device ID from I/O space. */
+		value = PEEK(s, DEVICE_ID);
+		s->device = GET_FIELD(value, DEVICE_ID_DEVICE);
+		s->revision = GET_FIELD(value, DEVICE_ID_REVISION);
+
+
+
+		printk(DUART_DEBUG_PREFIX "[smivgx_init]: " \
+			"found chip, device=%04x revision=%02x io=%p irq=%u\n",
+			s->device, s->revision, s->io, s->irq);
+
+		printk(DUART_DEBUG_PREFIX "[smivgx_init]: transmit buffer length = %d\n",
+			CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE);
+
+
+		return 0;
+	}
+	while (0);
+
+	/* Uninitialize anything we have done so far. */
+	cleanup(s);
+
+
+	return res;
+}
+
+
+/*
+ * VoyagerGX removal
+ */
+static void __devinit smivgx_remove(struct platform_device *pdev)
+{
+	struct pci_dev* pcidev=container_of(pdev->dev.parent,struct pci_dev,dev);
+
+
+	/* cleanup state structure pointer. */
+	cleanup((pci_session == 0)? drv_data : pci_get_drvdata(pcidev));
+
+	if (pci_session == 1)
+		pci_set_drvdata(pcidev, NULL);
+
+	pci_session = -1;
+	drv_data = NULL;
+
+}
+
+
+/*
+ * PCI initialization structures
+ */
+static struct pci_device_id id_table[] __devinitdata =
+{
+    { PCI_VENDOR_ID_SILICONMOTION, PCI_DEVICE_ID_SILICONMOTION_SM501, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
+    { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, id_table);
+
+static struct platform_driver smivgx_duart_pci_driver = {
+	.probe		= smivgx_init,
+	.remove		= smivgx_remove,
+	.driver		= {
+		.name	= "sm501-uart",
+		.owner	= THIS_MODULE,
+	},
+};
+
+
+
+/*
+ * Set up the driver and register it, register the 2 UART interrupts.
+ * This is called from tty_init, or as a part of the module init
+ */
+static int __init smivgx_duart_init(void)
+{
+	int res = -ENODEV;
+	res = platform_driver_register(&smivgx_duart_pci_driver);
+
+	return res;
+}
+
+
+/*
+ * Unload the driver.  Unregister stuff, get ready to go away
+ */
+static void __exit smivgx_duart_fini(void)
+{
+
+        platform_driver_unregister(&smivgx_duart_pci_driver);
+
+}
+
+
+/******************************************************************************
+ * MODULE ENTRY POINTS AND DESCRIPTION                                        *
+ ******************************************************************************/
+
+module_init(smivgx_duart_init);
+module_exit(smivgx_duart_fini);
+
+#ifdef CONFIG_SMIVGX_SERIAL_CONSOLE
+
+static void ser_console_write(struct console *cons, const char *str,
+                              unsigned int count)
+{
+	unsigned int i;
+	unsigned long flags;
+	unsigned int line = 0;
+
+	/* Enter the critical section */
+
+	for (i = 0; i < count; i++)
+	{
+		if (str[i] == '\n')
+		{
+			/* Expand LF -> CRLF */
+			while((PEEK(drv_data,UART_LINE_STATUS_REG(line))&0x20) == 0);
+			POKEBYTE(drv_data, UART_DATA_REG(line), '\r');
+		}
+
+		while((PEEK(drv_data,UART_LINE_STATUS_REG(line))&0x20) == 0);
+		POKEBYTE(drv_data, UART_DATA_REG(line), str[i]);
+	}
+
+}
+
+static struct tty_driver * ser_console_device(struct console *c,int *index)
+{
+	*index = c->index;
+	return &smivgx_duart_driver; 
+}
+
+static int ser_console_setup(struct console *cons, char *str)
+{
+	return 0;
+}
+
+static struct console smivgx_ser_cons =
+{
+	name:		"ttyS",
+	write:		ser_console_write,
+	device:		ser_console_device,
+	setup:		ser_console_setup,
+	flags:		CON_PRINTBUFFER,
+	index:		-1,
+};
+
+void __init smivgx_serial_console_init(void)
+{
+	register_console(&smivgx_ser_cons);
+}
+
+#endif /* CONFIG_SERIAL_CONSOLE */
+
+
diff -uNra linux-2.6.27.6/drivers/serial/sm502/smivgx.h linux-2.6.27.6.yaffs/drivers/serial/sm502/smivgx.h
--- linux-2.6.27.6/drivers/serial/sm502/smivgx.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/serial/sm502/smivgx.h	2011-05-08 18:00:02.000000000 +0800
@@ -0,0 +1,2769 @@
+/*****************************************************************************\
+ *                                                                           *
+ * Silicon Motion VoyagerGX SM501 register definitions.                      *
+ *                                                                           *
+ * This program is free software; you can redistribute it and/or modify it   *
+ * under the terms of the GNU General Public License as published by the     *
+ * Free Software Foundation; either version 2 of the License, or             *
+ * (at your option) any later version.                                       *
+ *                                                                           *
+ * This program is distributed in the hope that it will be useful, but       *
+ * WITHOUT ANY WARRANTY; without even the implied warranty of                *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.                      *
+ * See the GNU General Public License for more details.                      *
+ *                                                                           *
+ * You should have received a copy of the GNU General Public License along   *
+ * with this program; if not, write to the Free Software Foundation, Inc.,   *
+ * 675 Mass Ave, Cambridge, MA 02139, USA.                                   *
+ *                                                                           *
+\*****************************************************************************/
+
+#ifndef _SM501_H_
+#define _SM501_H_
+
+/*****************************************************************************\
+ *                                FIELD MACROS                               *
+\*****************************************************************************/
+
+#define _LSB(f)             (0 ? f)
+#define _MSB(f)             (1 ? f)
+#define _COUNT(f)           (_MSB(f) - _LSB(f) + 1)
+
+#define RAW_MASK(f)         (0xFFFFFFFF >> (32 - _COUNT(f)))
+#define GET_MASK(f)         (RAW_MASK(f) << _LSB(f))
+#define GET_FIELD(d,f)      (((d) >> _LSB(f)) & RAW_MASK(f))
+#define TEST_FIELD(d,f,v)   (GET_FIELD(d,f) == f ## _ ## v)
+#define SET_FIELD(d,f,v)    (((d) & ~GET_MASK(f)) | \
+                            (((f ## _ ## v) & RAW_MASK(f)) << _LSB(f)))
+#define SET_FIELDV(d,f,v)   (((d) & ~GET_MASK(f)) | \
+                            (((v) & RAW_MASK(f)) << _LSB(f)))
+
+/*****************************************************************************\
+ *                            SYSTEM CONFIGURATION                           *
+\*****************************************************************************/
+
+/* System Control */
+#define SYSTEM_CONTROL                                              0x000000
+#define SYSTEM_CONTROL_DPMS                                         31:30
+#define SYSTEM_CONTROL_DPMS_VPHP                                    0
+#define SYSTEM_CONTROL_DPMS_VPHN                                    1
+#define SYSTEM_CONTROL_DPMS_VNHP                                    2
+#define SYSTEM_CONTROL_DPMS_VNHN                                    3
+#define SYSTEM_CONTROL_PCI_BURST                                    29:29
+#define SYSTEM_CONTROL_PCI_BURST_DISABLE                            0
+#define SYSTEM_CONTROL_PCI_BURST_ENABLE                             1
+#define SYSTEM_CONTROL_CSC_STATUS                                   28:28
+#define SYSTEM_CONTROL_CSC_STATUS_IDLE                              0
+#define SYSTEM_CONTROL_CSC_STATUS_BUSY                              1
+#define SYSTEM_CONTROL_PCI_BUS_MASTER                               25:25
+#define SYSTEM_CONTROL_PCI_BUS_MASTER_STOP                          0
+#define SYSTEM_CONTROL_PCI_BUS_MASTER_START                         1
+#define SYSTEM_CONTROL_PCI_LATENCY_TIMER                            24:24
+#define SYSTEM_CONTROL_PCI_LATENCY_TIMER_ENABLE                     0
+#define SYSTEM_CONTROL_PCI_LATENCY_TIMER_DISABLE                    1
+#define SYSTEM_CONTROL_PANEL_STATUS                                 23:23
+#define SYSTEM_CONTROL_PANEL_STATUS_NORMAL                          0
+#define SYSTEM_CONTROL_PANEL_STATUS_FLIP_PENDING                    1
+#define SYSTEM_CONTROL_VIDEO_STATUS                                 22:22
+#define SYSTEM_CONTROL_VIDEO_STATUS_NORMAL                          0
+#define SYSTEM_CONTROL_VIDEO_STATUS_FLIP_PENDING                    1
+#define SYSTEM_CONTROL_2D_FIFO                                      20:20
+#define SYSTEM_CONTROL_2D_FIFO_NOT_EMPTY                            0
+#define SYSTEM_CONTROL_2D_FIFO_EMPTY                                1
+#define SYSTEM_CONTROL_2D_STATUS                                    19:19
+#define SYSTEM_CONTROL_2D_STATUS_IDLE                               0
+#define SYSTEM_CONTROL_2D_STATUS_BUSY                               1
+#define SYSTEM_CONTROL_CRT_STATUS                                   17:17
+#define SYSTEM_CONTROL_CRT_STATUS_NORMAL                            0
+#define SYSTEM_CONTROL_CRT_STATUS_FLIP_PENDING                      1
+#define SYSTEM_CONTROL_ZVPORT                                       16:16
+#define SYSTEM_CONTROL_ZVPORT_NORMAL                                0
+#define SYSTEM_CONTROL_ZVPORT_VERTICAL_SYNC_DETECTED                1
+#define SYSTEM_CONTROL_PCI_BURST_READ                               15:15
+#define SYSTEM_CONTROL_PCI_BURST_READ_DISABLE                       0
+#define SYSTEM_CONTROL_PCI_BURST_READ_ENABLE                        1
+#define SYSTEM_CONTROL_2D_ABORT                                     13:12
+#define SYSTEM_CONTROL_2D_ABORT_NORMAL                              0
+#define SYSTEM_CONTROL_2D_ABORT_ABORT                               3
+#define SYSTEM_CONTROL_LOCK_PCI_SUBSYSTEM                           11:11
+#define SYSTEM_CONTROL_LOCK_PCI_SUBSYSTEM_DISABLE                   0
+#define SYSTEM_CONTROL_LOCK_PCI_SUBSYSTEM_ENABLE                    1
+#define SYSTEM_CONTROL_PCI_RETRY                                    7:7
+#define SYSTEM_CONTROL_PCI_RETRY_ENABLE                             0
+#define SYSTEM_CONTROL_PCI_RETRY_DISABLE                            1
+#define SYSTEM_CONTROL_PCI_CLOCK_RUN                                6:6
+#define SYSTEM_CONTROL_PCI_CLOCK_RUN_DISABLE                        0
+#define SYSTEM_CONTROL_PCI_CLOCK_RUN_ENABLE                         1
+#define SYSTEM_CONTROL_PCI_SLAVE_BURST_READ_SIZE                    5:4
+#define SYSTEM_CONTROL_PCI_SLAVE_BURST_READ_SIZE_1                  0
+#define SYSTEM_CONTROL_PCI_SLAVE_BURST_READ_SIZE_2                  1
+#define SYSTEM_CONTROL_PCI_SLAVE_BURST_READ_SIZE_4                  2
+#define SYSTEM_CONTROL_PCI_SLAVE_BURST_READ_SIZE_8                  3
+#define SYSTEM_CONTROL_CRT_INTERFACE                                2:2
+#define SYSTEM_CONTROL_CRT_INTERFACE_NORMAL                         0
+#define SYSTEM_CONTROL_CRT_INTERFACE_TRISTATE                       1
+#define SYSTEM_CONTROL_LOCAL_MEMORY_INTERFACE                       1:1
+#define SYSTEM_CONTROL_LOCAL_MEMORY_INTERFACE_NORMAL                0
+#define SYSTEM_CONTROL_LOCAL_MEMORY_INTERFACE_TRISTATE              1
+#define SYSTEM_CONTROL_PANEL_INTERFACE                              0:0
+#define SYSTEM_CONTROL_PANEL_INTERFACE_NORMAL                       0
+#define SYSTEM_CONTROL_PANEL_INTERFACE_TRISTATE                     1
+
+/* Miscellaneous Control */
+#define MISCELLANEOUS_CONTROL                                       0x000004
+#define MISCELLANEOUS_CONTROL_PCI_PAD_DRIVE                         31:30
+#define MISCELLANEOUS_CONTROL_PCI_PAD_DRIVE_24MA                    0
+#define MISCELLANEOUS_CONTROL_PCI_PAD_DRIVE_12MA                    1
+#define MISCELLANEOUS_CONTROL_PCI_PAD_DRIVE_8MA                     2
+#define MISCELLANEOUS_CONTROL_USB_CLOCK_SELECT                      29:28
+#define MISCELLANEOUS_CONTROL_USB_CLOCK_SELECT_CRYSTAL              0
+#define MISCELLANEOUS_CONTROL_USB_CLOCK_SELECT_HOST_96              2
+#define MISCELLANEOUS_CONTROL_USB_CLOCK_SELECT_HOST_48              3
+#define MISCELLANEOUS_CONTROL_UART1_SELECT                          27:27
+#define MISCELLANEOUS_CONTROL_UART1_SELECT_UART                     0
+#define MISCELLANEOUS_CONTROL_UART1_SELECT_SSP                      1
+#define MISCELLANEOUS_CONTROL_8051_LATCH                            26:26
+#define MISCELLANEOUS_CONTROL_8051_LATCH_DISABLE                    0
+#define MISCELLANEOUS_CONTROL_8051_LATCH_ENABLE                     1
+#define MISCELLANEOUS_CONTROL_FLAT_PANEL                            25:25
+#define MISCELLANEOUS_CONTROL_FLAT_PANEL_18BIT                      0
+#define MISCELLANEOUS_CONTROL_FLAT_PANEL_24BIT                      1
+#define MISCELLANEOUS_CONTROL_CRYSTAL                               24:24
+#define MISCELLANEOUS_CONTROL_CRYSTAL_24MHZ                         0
+#define MISCELLANEOUS_CONTROL_CRYSTAL_12MHZ                         1
+#define MISCELLANEOUS_CONTROL_DRAM_REFRESH                          22:21
+#define MISCELLANEOUS_CONTROL_DRAM_REFRESH_8US                      0
+#define MISCELLANEOUS_CONTROL_DRAM_REFRESH_16US                     1
+#define MISCELLANEOUS_CONTROL_DRAM_REFRESH_32US                     2
+#define MISCELLANEOUS_CONTROL_DRAM_REFRESH_64US                     3
+#define MISCELLANEOUS_CONTROL_BUS_HOLD                              20:18
+#define MISCELLANEOUS_CONTROL_BUS_HOLD_FIFO_EMPTY                   0
+#define MISCELLANEOUS_CONTROL_BUS_HOLD_8_TRANSACTIONS               1
+#define MISCELLANEOUS_CONTROL_BUS_HOLD_16_TRANSACTIONS              2
+#define MISCELLANEOUS_CONTROL_BUS_HOLD_24_TRANSACTIONS              3
+#define MISCELLANEOUS_CONTROL_BUS_HOLD_32_TRANSACTIONS              4
+#define MISCELLANEOUS_CONTROL_HITACHI_READY                         17:17
+#define MISCELLANEOUS_CONTROL_HITACHI_READY_ACTIVE_LOW              0
+#define MISCELLANEOUS_CONTROL_HITACHI_READY_ACTIVE_HIGH             1
+#define MISCELLANEOUS_CONTROL_INTERRUPT                             16:16
+#define MISCELLANEOUS_CONTROL_INTERRUPT_NORMAL                      0
+#define MISCELLANEOUS_CONTROL_INTERRUPT_INVERTED                    1
+#define MISCELLANEOUS_CONTROL_PLL_CLOCK_COUNT                       15:15
+#define MISCELLANEOUS_CONTROL_PLL_CLOCK_COUNT_DISABLE               0
+#define MISCELLANEOUS_CONTROL_PLL_CLOCK_COUNT_ENABLE                1
+#define MISCELLANEOUS_CONTROL_DAC_BAND_GAP                          14:13
+#define MISCELLANEOUS_CONTROL_DAC_BAND_GAP_NORMAL                   0
+#define MISCELLANEOUS_CONTROL_DAC_POWER                             12:12
+#define MISCELLANEOUS_CONTROL_DAC_POWER_ENABLE                      0
+#define MISCELLANEOUS_CONTROL_DAC_POWER_DISABLE                     1
+#define MISCELLANEOUS_CONTROL_USB_SLAVE                             11:11
+#define MISCELLANEOUS_CONTROL_USB_SLAVE_CPU                         0
+#define MISCELLANEOUS_CONTROL_USB_SLAVE_8051                        1
+#define MISCELLANEOUS_CONTROL_CPU_MASTER_BURST                      10:10
+#define MISCELLANEOUS_CONTROL_CPU_MASTER_BURST_8                    0
+#define MISCELLANEOUS_CONTROL_CPU_MASTER_BURST_1                    1
+#define MISCELLANEOUS_CONTROL_USB_PORT_SELECT                       9:9
+#define MISCELLANEOUS_CONTROL_USB_PORT_SELECT_MASTER                0
+#define MISCELLANEOUS_CONTROL_USB_PORT_SELECT_SLAVE                 1
+#define MISCELLANEOUS_CONTROL_USB_LOOPBACK                          8:8
+#define MISCELLANEOUS_CONTROL_USB_LOOPBACK_NORMAL                   0
+#define MISCELLANEOUS_CONTROL_USB_LOOPBACK_INTERNAL                 1
+#define MISCELLANEOUS_CONTROL_CLOCK_DIVIDER                         7:7
+#define MISCELLANEOUS_CONTROL_CLOCK_DIVIDER_NORMAL                  0
+#define MISCELLANEOUS_CONTROL_CLOCK_DIVIDER_RESET                   1
+#define MISCELLANEOUS_CONTROL_TEST_MODE                             6:5
+#define MISCELLANEOUS_CONTROL_TEST_MODE_NORMAL                      0
+#define MISCELLANEOUS_CONTROL_TEST_MODE_DEBUGGING                   1
+#define MISCELLANEOUS_CONTROL_TEST_MODE_NAND_TREE                   2
+#define MISCELLANEOUS_CONTROL_TEST_MODE_MEMORY                      3
+#define MISCELLANEOUS_CONTROL_NEC_MEMORY_MAP                        4:4
+#define MISCELLANEOUS_CONTROL_NEC_MEMORY_MAP_30MB                   0
+#define MISCELLANEOUS_CONTROL_NEC_MEMORY_MAP_62MB                   1
+#define MISCELLANEOUS_CONTROL_CLOCK                                 3:3
+#define MISCELLANEOUS_CONTROL_CLOCK_PLL                             0
+#define MISCELLANEOUS_CONTROL_CLOCK_TEST_CLOCK                      1
+#define MISCELLANEOUS_CONTROL_HOST_BUS                              2:0
+#define MISCELLANEOUS_CONTROL_HOST_BUS_HITACHI                      0
+#define MISCELLANEOUS_CONTROL_HOST_BUS_PCI                          1
+#define MISCELLANEOUS_CONTROL_HOST_BUS_INTEL                        2
+#define MISCELLANEOUS_CONTROL_HOST_BUS_NEC                          6
+
+/* GPIO[31:0] Control */
+#define GPIO_CONTROL_LOW                                            0x000008
+#define GPIO_CONTROL_LOW_31                                         31:31
+#define GPIO_CONTROL_LOW_31_GPIO                                    0
+#define GPIO_CONTROL_LOW_31_PWM2                                    1
+#define GPIO_CONTROL_LOW_30                                         30:30
+#define GPIO_CONTROL_LOW_30_GPIO                                    0
+#define GPIO_CONTROL_LOW_30_PWM1                                    1
+#define GPIO_CONTROL_LOW_29                                         29:29
+#define GPIO_CONTROL_LOW_29_GPIO                                    0
+#define GPIO_CONTROL_LOW_29_PWM0                                    1
+#define GPIO_CONTROL_LOW_28                                         28:28
+#define GPIO_CONTROL_LOW_28_GPIO                                    0
+#define GPIO_CONTROL_LOW_28_AC97_RX_I2S                             1
+#define GPIO_CONTROL_LOW_27                                         27:27
+#define GPIO_CONTROL_LOW_27_GPIO                                    0
+#define GPIO_CONTROL_LOW_27_AC97_TX_I2S                             1
+#define GPIO_CONTROL_LOW_26                                         26:26
+#define GPIO_CONTROL_LOW_26_GPIO                                    0
+#define GPIO_CONTROL_LOW_26_AC97_CLOCK_I2S                          1
+#define GPIO_CONTROL_LOW_25                                         25:25
+#define GPIO_CONTROL_LOW_25_GPIO                                    0
+#define GPIO_CONTROL_LOW_25_AC97_SYNC_I2S                           1
+#define GPIO_CONTROL_LOW_24                                         24:24
+#define GPIO_CONTROL_LOW_24_GPIO                                    0
+#define GPIO_CONTROL_LOW_24_AC97_RESET                              1
+#define GPIO_CONTROL_LOW_23                                         23:23
+#define GPIO_CONTROL_LOW_23_GPIO                                    0
+#define GPIO_CONTROL_LOW_23_ZVPORT7                                 1
+#define GPIO_CONTROL_LOW_22                                         22:22
+#define GPIO_CONTROL_LOW_22_GPIO                                    0
+#define GPIO_CONTROL_LOW_22_ZVPORT6                                 1
+#define GPIO_CONTROL_LOW_21                                         21:21
+#define GPIO_CONTROL_LOW_21_GPIO                                    0
+#define GPIO_CONTROL_LOW_21_ZVPORT5                                 1
+#define GPIO_CONTROL_LOW_20                                         20:20
+#define GPIO_CONTROL_LOW_20_GPIO                                    0
+#define GPIO_CONTROL_LOW_20_ZVPORT4                                 1
+#define GPIO_CONTROL_LOW_19                                         19:19
+#define GPIO_CONTROL_LOW_19_GPIO                                    0
+#define GPIO_CONTROL_LOW_19_ZVPORT3                                 1
+#define GPIO_CONTROL_LOW_18                                         18:18
+#define GPIO_CONTROL_LOW_18_GPIO                                    0
+#define GPIO_CONTROL_LOW_18_ZVPORT2                                 1
+#define GPIO_CONTROL_LOW_17                                         17:17
+#define GPIO_CONTROL_LOW_17_GPIO                                    0
+#define GPIO_CONTROL_LOW_17_ZVPORT1                                 1
+#define GPIO_CONTROL_LOW_16                                         16:16
+#define GPIO_CONTROL_LOW_16_GPIO                                    0
+#define GPIO_CONTROL_LOW_16_ZVPORT0                                 1
+#define GPIO_CONTROL_LOW_15                                         15:15
+#define GPIO_CONTROL_LOW_15_GPIO                                    0
+#define GPIO_CONTROL_LOW_15_8051_A11                                1
+#define GPIO_CONTROL_LOW_14                                         14:14
+#define GPIO_CONTROL_LOW_14_GPIO                                    0
+#define GPIO_CONTROL_LOW_14_8051_A10                                1
+#define GPIO_CONTROL_LOW_13                                         13:13
+#define GPIO_CONTROL_LOW_13_GPIO                                    0
+#define GPIO_CONTROL_LOW_13_8051_A9                                 1
+#define GPIO_CONTROL_LOW_12                                         12:12
+#define GPIO_CONTROL_LOW_12_GPIO                                    0
+#define GPIO_CONTROL_LOW_12_8051_A8                                 1
+#define GPIO_CONTROL_LOW_11                                         11:11
+#define GPIO_CONTROL_LOW_11_GPIO                                    0
+#define GPIO_CONTROL_LOW_11_8051_WAIT                               1
+#define GPIO_CONTROL_LOW_10                                         10:10
+#define GPIO_CONTROL_LOW_10_GPIO                                    0
+#define GPIO_CONTROL_LOW_10_8051_ALE                                1
+#define GPIO_CONTROL_LOW_9                                          9:9
+#define GPIO_CONTROL_LOW_9_GPIO                                     0
+#define GPIO_CONTROL_LOW_9_8051_WRITE                               1
+#define GPIO_CONTROL_LOW_8                                          8:8
+#define GPIO_CONTROL_LOW_8_GPIO                                     0
+#define GPIO_CONTROL_LOW_8_8051_READ                                1
+#define GPIO_CONTROL_LOW_7                                          7:7
+#define GPIO_CONTROL_LOW_7_GPIO                                     0
+#define GPIO_CONTROL_LOW_7_8051_AD7                                 1
+#define GPIO_CONTROL_LOW_6                                          6:6
+#define GPIO_CONTROL_LOW_6_GPIO                                     0
+#define GPIO_CONTROL_LOW_6_8051_AD6                                 1
+#define GPIO_CONTROL_LOW_5                                          5:5
+#define GPIO_CONTROL_LOW_5_GPIO                                     0
+#define GPIO_CONTROL_LOW_5_8051_AD5                                 1
+#define GPIO_CONTROL_LOW_4                                          4:4
+#define GPIO_CONTROL_LOW_4_GPIO                                     0
+#define GPIO_CONTROL_LOW_4_8051_AD4                                 1
+#define GPIO_CONTROL_LOW_3                                          3:3
+#define GPIO_CONTROL_LOW_3_GPIO                                     0
+#define GPIO_CONTROL_LOW_3_8051_AD3                                 1
+#define GPIO_CONTROL_LOW_2                                          2:2
+#define GPIO_CONTROL_LOW_2_GPIO                                     0
+#define GPIO_CONTROL_LOW_2_8051_AD2                                 1
+#define GPIO_CONTROL_LOW_1                                          1:1
+#define GPIO_CONTROL_LOW_1_GPIO                                     0
+#define GPIO_CONTROL_LOW_1_8051_AD1                                 1
+#define GPIO_CONTROL_LOW_0                                          0:0
+#define GPIO_CONTROL_LOW_0_GPIO                                     0
+#define GPIO_CONTROL_LOW_0_8051_AD0                                 1
+
+/* GPIO[63:32] Control */
+#define GPIO_CONTROL_HIGH                                           0x00000C
+#define GPIO_CONTROL_HIGH_63                                        31:31
+#define GPIO_CONTROL_HIGH_63_GPIO                                   0
+#define GPIO_CONTROL_HIGH_63_CRT7_ZVPORT15                          1
+#define GPIO_CONTROL_HIGH_62                                        30:30
+#define GPIO_CONTROL_HIGH_62_GPIO                                   0
+#define GPIO_CONTROL_HIGH_62_CRT6_ZVPORT14                          1
+#define GPIO_CONTROL_HIGH_61                                        29:29
+#define GPIO_CONTROL_HIGH_61_GPIO                                   0
+#define GPIO_CONTROL_HIGH_61_CRT5_ZVPORT13_PANEL17                  1
+#define GPIO_CONTROL_HIGH_60                                        28:28
+#define GPIO_CONTROL_HIGH_60_GPIO                                   0
+#define GPIO_CONTROL_HIGH_60_CRT4_ZVPORT12_PANEL16                  1
+#define GPIO_CONTROL_HIGH_59                                        27:27
+#define GPIO_CONTROL_HIGH_59_GPIO                                   0
+#define GPIO_CONTROL_HIGH_59_CRT3_ZVPORT11_PANEL9                   1
+#define GPIO_CONTROL_HIGH_58                                        26:26
+#define GPIO_CONTROL_HIGH_58_GPIO                                   0
+#define GPIO_CONTROL_HIGH_58_CRT2_ZVPORT10_PANEL8                   1
+#define GPIO_CONTROL_HIGH_57                                        25:25
+#define GPIO_CONTROL_HIGH_57_GPIO                                   0
+#define GPIO_CONTROL_HIGH_57_CRT1_ZVPORT9_PANEL1                    1
+#define GPIO_CONTROL_HIGH_56                                        24:24
+#define GPIO_CONTROL_HIGH_56_GPIO                                   0
+#define GPIO_CONTROL_HIGH_56_CRT0_ZVPORT8_PANEL0                    1
+#define GPIO_CONTROL_HIGH_55                                        23:23
+#define GPIO_CONTROL_HIGH_55_GPIO                                   0
+#define GPIO_CONTROL_HIGH_55_CRT_CLOCK                              1
+#define GPIO_CONTROL_HIGH_47                                        15:15
+#define GPIO_CONTROL_HIGH_47_GPIO                                   0
+#define GPIO_CONTROL_HIGH_47_I2C_DATA                               1
+#define GPIO_CONTROL_HIGH_46                                        14:14
+#define GPIO_CONTROL_HIGH_46_GPIO                                   0
+#define GPIO_CONTROL_HIGH_46_I2C_CLOCK                              1
+#define GPIO_CONTROL_HIGH_45                                        13:13
+#define GPIO_CONTROL_HIGH_45_GPIO                                   0
+#define GPIO_CONTROL_HIGH_45_SSP1_CLOCK                             1
+#define GPIO_CONTROL_HIGH_44                                        12:12
+#define GPIO_CONTROL_HIGH_44_GPIO                                   0
+#define GPIO_CONTROL_HIGH_44_UART1_RTS_SSP1_OUT                     1
+#define GPIO_CONTROL_HIGH_43                                        11:11
+#define GPIO_CONTROL_HIGH_43_GPIO                                   0
+#define GPIO_CONTROL_HIGH_43_UART1_CTS_SSP1_IN                      1
+#define GPIO_CONTROL_HIGH_42                                        10:10
+#define GPIO_CONTROL_HIGH_42_GPIO                                   0
+#define GPIO_CONTROL_HIGH_42_UART1_RX_SSP1_RX                       1
+#define GPIO_CONTROL_HIGH_41                                        9:9
+#define GPIO_CONTROL_HIGH_41_GPIO                                   0
+#define GPIO_CONTROL_HIGH_41_UART1_TX_SSP1_TX                       1
+#define GPIO_CONTROL_HIGH_40                                        8:8
+#define GPIO_CONTROL_HIGH_40_GPIO                                   0
+#define GPIO_CONTROL_HIGH_40_UART0_RTS                              1
+#define GPIO_CONTROL_HIGH_39                                        7:7
+#define GPIO_CONTROL_HIGH_39_GPIO                                   0
+#define GPIO_CONTROL_HIGH_39_UART0_CTS                              1
+#define GPIO_CONTROL_HIGH_38                                        6:6
+#define GPIO_CONTROL_HIGH_38_GPIO                                   0
+#define GPIO_CONTROL_HIGH_38_UART0_RX                               1
+#define GPIO_CONTROL_HIGH_37                                        5:5
+#define GPIO_CONTROL_HIGH_37_GPIO                                   0
+#define GPIO_CONTROL_HIGH_37_UART0_TX                               1
+#define GPIO_CONTROL_HIGH_36                                        4:4
+#define GPIO_CONTROL_HIGH_36_GPIO                                   0
+#define GPIO_CONTROL_HIGH_36_SSP0_CLOCK                             1
+#define GPIO_CONTROL_HIGH_35                                        3:3
+#define GPIO_CONTROL_HIGH_35_GPIO                                   0
+#define GPIO_CONTROL_HIGH_35_SSP0_IN                                1
+#define GPIO_CONTROL_HIGH_34                                        2:2
+#define GPIO_CONTROL_HIGH_34_GPIO                                   0
+#define GPIO_CONTROL_HIGH_34_SSP0_OUT                               1
+#define GPIO_CONTROL_HIGH_33                                        1:1
+#define GPIO_CONTROL_HIGH_33_GPIO                                   0
+#define GPIO_CONTROL_HIGH_33_SSP0_RX                                1
+#define GPIO_CONTROL_HIGH_32                                        0:0
+#define GPIO_CONTROL_HIGH_32_GPIO                                   0
+#define GPIO_CONTROL_HIGH_32_SSP0_TX                                1
+
+/* DRAM Control */
+#define DRAM_CONTROL                                                0x000010
+#define DRAM_CONTROL_EMBEDDED_MEMORY                                31:31
+#define DRAM_CONTROL_EMBEDDED_MEMORY_ENABLE                         0
+#define DRAM_CONTROL_EMBEDDED_MEMORY_DISABLE                        1
+#define DRAM_CONTROL_EXTERNAL_BURST                                 30:28
+#define DRAM_CONTROL_EXTERNAL_BURST_1                               0
+#define DRAM_CONTROL_EXTERNAL_BURST_2                               1
+#define DRAM_CONTROL_EXTERNAL_BURST_4                               2
+#define DRAM_CONTROL_EXTERNAL_BURST_8                               3
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY                           27:27
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY_2                         0
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY_3                         1
+#define DRAM_CONTROL_EXTERNAL_SIZE                                  26:24
+#define DRAM_CONTROL_EXTERNAL_SIZE_2MB                              0
+#define DRAM_CONTROL_EXTERNAL_SIZE_4MB                              1
+#define DRAM_CONTROL_EXTERNAL_SIZE_64MB                             4
+#define DRAM_CONTROL_EXTERNAL_SIZE_32MB                             5
+#define DRAM_CONTROL_EXTERNAL_SIZE_16MB                             6
+#define DRAM_CONTROL_EXTERNAL_SIZE_8MB                              7
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE                           23:22
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_1024                      0
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_512                       2
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_256                       3
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE                      21:21
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE_6                    0
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE_7                    1
+#define DRAM_CONTROL_EXTERNAL                                       20:20
+#define DRAM_CONTROL_EXTERNAL_RESET                                 0
+#define DRAM_CONTROL_EXTERNAL_NORMAL                                1
+#define DRAM_CONTROL_EXTERNAL_BANKS                                 19:19
+#define DRAM_CONTROL_EXTERNAL_BANKS_2                               0
+#define DRAM_CONTROL_EXTERNAL_BANKS_4                               1
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE                       18:18
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE_2                     0
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE_1                     1
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE                              17:17
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_DISABLE                      0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_ENABLE                       1
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND                          16:16
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND_10                       0
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND_12                       1
+#define DRAM_CONTROL_LOCAL_SIZE                                     15:13
+#define DRAM_CONTROL_LOCAL_SIZE_4MB                                 0
+#define DRAM_CONTROL_LOCAL_SIZE_8MB                                 1
+#define DRAM_CONTROL_LOCAL_SIZE_16MB                                2
+#define DRAM_CONTROL_LOCAL_SIZE_32MB                                3
+#define DRAM_CONTROL_LOCAL_SIZE_64MB                                4
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE                              12:11
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_256                          0
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_512                          2
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_1024                         3
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME                         10:10
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME_1                       0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME_2                       1
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE                    9:9
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE_4                  0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE_1                  1
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE                         8:8
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE_6                       0
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE_7                       1
+#define DRAM_CONTROL_LOCAL                                          7:7
+#define DRAM_CONTROL_LOCAL_NORMAL                                   0
+#define DRAM_CONTROL_LOCAL_RESET                                    1
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE                            6:6
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE_ENABLE                     0
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE_DISABLE                    1
+#define DRAM_CONTROL_LOCAL_BANKS                                    1:1
+#define DRAM_CONTROL_LOCAL_BANKS_4                                  0
+#define DRAM_CONTROL_LOCAL_BANKS_2                                  1
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE                          0:0
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE_2                        0
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE_1                        1
+
+/* Arbitration Control */
+#define ARBITRATION_CONTROL                                         0x000014
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY                         29:29
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY_FIXED                   0
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY_REVOLVING               1
+#define ARBITRATION_CONTROL_LOCAL_MEMORY                            28:28
+#define ARBITRATION_CONTROL_LOCAL_MEMORY_FIXED                      0
+#define ARBITRATION_CONTROL_LOCAL_MEMORY_REVOLVING                  1
+#define ARBITRATION_CONTROL_USB                                     26:24
+#define ARBITRATION_CONTROL_USB_OFF                                 0
+#define ARBITRATION_CONTROL_USB_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_USB_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_USB_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_USB_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_USB_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_USB_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_USB_PRIORITY_7                          7
+#define ARBITRATION_CONTROL_PANEL                                   22:20
+#define ARBITRATION_CONTROL_PANEL_OFF                               0
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_1                        1
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_2                        2
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_3                        3
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_4                        4
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_5                        5
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_6                        6
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_7                        7
+#define ARBITRATION_CONTROL_ZVPORT                                  18:16
+#define ARBITRATION_CONTROL_ZVPORT_OFF                              0
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_1                       1
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_2                       2
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_3                       3
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_4                       4
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_5                       5
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_6                       6
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_7                       7
+#define ARBITRATION_CONTROL_COMMAND_LIST                            14:12
+#define ARBITRATION_CONTROL_COMMAND_LIST_OFF                        0
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_1                 1
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_2                 2
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_3                 3
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_4                 4
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_5                 5
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_6                 6
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_7                 7
+#define ARBITRATION_CONTROL_DMA                                     10:8
+#define ARBITRATION_CONTROL_DMA_OFF                                 0
+#define ARBITRATION_CONTROL_DMA_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_DMA_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_DMA_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_DMA_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_DMA_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_DMA_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_DMA_PRIORITY_7                          7
+#define ARBITRATION_CONTROL_VIDEO                                   6:4
+#define ARBITRATION_CONTROL_VIDEO_OFF                               0
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_1                        1
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_2                        2
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_3                        3
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_4                        4
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_5                        5
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_6                        6
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_7                        7
+#define ARBITRATION_CONTROL_CRT                                     2:0
+#define ARBITRATION_CONTROL_CRT_OFF                                 0
+#define ARBITRATION_CONTROL_CRT_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_CRT_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_CRT_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_CRT_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_CRT_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_CRT_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_CRT_PRIORITY_7                          7
+
+/* Command List Control */
+#define COMMAND_LIST_CONTROL                                        0x000018
+#define COMMAND_LIST_CONTROL_STATUS                                 31:31
+#define COMMAND_LIST_CONTROL_STATUS_STOPPED                         0
+#define COMMAND_LIST_CONTROL_STATUS_RUNNING                         1
+#define COMMAND_LIST_CONTROL_MEMORY                                 27:26
+#define COMMAND_LIST_CONTROL_MEMORY_LOCAL                           0
+#define COMMAND_LIST_CONTROL_MEMORY_EXTERNAL_CS0                    2
+#define COMMAND_LIST_CONTROL_MEMORY_EXTERNAL_CS1                    3
+#define COMMAND_LIST_CONTROL_ADDRESS                                25:0
+
+/* Command List Conditions */
+#define COMMAND_LIST_CONDITIONS                                     0x00001C
+
+/* Command List Return */
+#define COMMAND_LIST_RETURN                                         0x000020
+#define COMMAND_LIST_RETURN_MEMORY                                  27:26
+#define COMMAND_LIST_RETURN_MEMORY_LOCAL                            0
+#define COMMAND_LIST_RETURN_MEMORY_EXTERNAL_CS0                     2
+#define COMMAND_LIST_RETURN_MEMORY_EXTERNAL_CS1                     3
+#define COMMAND_LIST_RETURN_ADDRESS                                 25:0
+
+/* Command List Status */
+#define COMMAND_LIST_STATUS                                         0x000024
+#define COMMAND_LIST_STATUS_2D_MEMORY_FIFO                          20:20
+#define COMMAND_LIST_STATUS_2D_MEMORY_FIFO_NOT_EMPTY                0
+#define COMMAND_LIST_STATUS_2D_MEMORY_FIFO_EMPTY                    1
+#define COMMAND_LIST_STATUS_COMMAND_FIFO                            19:19
+#define COMMAND_LIST_STATUS_COMMAND_FIFO_NOT_EMPTY                  0
+#define COMMAND_LIST_STATUS_COMMAND_FIFO_EMPTY                      1
+#define COMMAND_LIST_STATUS_CSC                                     18:18
+#define COMMAND_LIST_STATUS_CSC_IDLE                                0
+#define COMMAND_LIST_STATUS_CSC_BUSY                                1
+#define COMMAND_LIST_STATUS_MEMORY_DMA                              17:17
+#define COMMAND_LIST_STATUS_MEMORY_DMA_IDLE                         0
+#define COMMAND_LIST_STATUS_MEMORY_DMA_BUSY                         1
+#define COMMAND_LIST_STATUS_CRT_STATUS                              16:16
+#define COMMAND_LIST_STATUS_CRT_STATUS_NORMAL                       0
+#define COMMAND_LIST_STATUS_CRT_STATUS_FLIP_PENDING                 1
+#define COMMAND_LIST_STATUS_CURRENT_FIELD                           15:15
+#define COMMAND_LIST_STATUS_CURRENT_FIELD_ODD                       0
+#define COMMAND_LIST_STATUS_CURRENT_FIELD_EVEN                      1
+#define COMMAND_LIST_STATUS_VIDEO_STATUS                            14:14
+#define COMMAND_LIST_STATUS_VIDEO_STATUS_NORMAL                     0
+#define COMMAND_LIST_STATUS_VIDEO_STATUS_FLIP_PENDING               1
+#define COMMAND_LIST_STATUS_PANEL_STATUS                            13:13
+#define COMMAND_LIST_STATUS_PANEL_STATUS_NORMAL                     0
+#define COMMAND_LIST_STATUS_PANEL_STATUS_FLIP_PENDING               1
+#define COMMAND_LIST_STATUS_CRT_VERTICAL_SYNC                       12:12
+#define COMMAND_LIST_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE            0
+#define COMMAND_LIST_STATUS_CRT_VERTICAL_SYNC_ACTIVE                1
+#define COMMAND_LIST_STATUS_PANEL_VERTICAL_SYNC                     11:11
+#define COMMAND_LIST_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE          0
+#define COMMAND_LIST_STATUS_PANEL_VERTICAL_SYNC_ACTIVE              1
+#define COMMAND_LIST_STATUS_2D_SETUP                                2:2
+#define COMMAND_LIST_STATUS_2D_SETUP_IDLE                           0
+#define COMMAND_LIST_STATUS_2D_SETUP_BUSY                           1
+#define COMMAND_LIST_STATUS_2D_FIFO                                 1:1
+#define COMMAND_LIST_STATUS_2D_FIFO_NOT_EMPTY                       0
+#define COMMAND_LIST_STATUS_2D_FIFO_EMPTY                           1
+#define COMMAND_LIST_STATUS_2D                                      0:0
+#define COMMAND_LIST_STATUS_2D_IDLE                                 0
+#define COMMAND_LIST_STATUS_2D_BUSY                                 1
+
+/* Raw Interrupt Status & Clear */
+#define RAW_INTERRUPT_STATUS                                        0x000028
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN                      5:5
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_NOT_ACTIVE           0
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_ACTIVE               1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_CLEAR                1
+#define RAW_INTERRUPT_STATUS_ZVPORT                                 4:4
+#define RAW_INTERRUPT_STATUS_ZVPORT_NOT_ACTIVE                      0
+#define RAW_INTERRUPT_STATUS_ZVPORT_ACTIVE                          1
+#define RAW_INTERRUPT_STATUS_ZVPORT_CLEAR                           1
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC                      3:3
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE           0
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_ACTIVE               1
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_CLEAR                1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE                              2:2
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_NOT_ACTIVE                   0
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_ACTIVE                       1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_CLEAR                        1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC                    1:1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE         0
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_ACTIVE             1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_CLEAR              1
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST                           0:0
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_NOT_ACTIVE                0
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_ACTIVE                    1
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_CLEAR                     1
+
+/* Interrupt Status */
+#define INTERRUPT_STATUS                                            0x00002C
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN                          31:31
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_NOT_ACTIVE               0
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_ACTIVE                   1
+#define INTERRUPT_STATUS_GPIO54                                     30:30
+#define INTERRUPT_STATUS_GPIO54_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO54_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO53                                     29:29
+#define INTERRUPT_STATUS_GPIO53_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO53_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO52                                     28:28
+#define INTERRUPT_STATUS_GPIO52_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO52_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO51                                     27:27
+#define INTERRUPT_STATUS_GPIO51_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO51_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO50                                     26:26
+#define INTERRUPT_STATUS_GPIO50_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO50_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO49                                     25:25
+#define INTERRUPT_STATUS_GPIO49_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO49_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO48                                     24:24
+#define INTERRUPT_STATUS_GPIO48_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO48_ACTIVE                              1
+#define INTERRUPT_STATUS_I2C                                        23:23
+#define INTERRUPT_STATUS_I2C_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_I2C_ACTIVE                                 1
+#define INTERRUPT_STATUS_PWM                                        22:22
+#define INTERRUPT_STATUS_PWM_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_PWM_ACTIVE                                 1
+#define INTERRUPT_STATUS_DMA                                        20:20
+#define INTERRUPT_STATUS_DMA_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_DMA_ACTIVE                                 1
+#define INTERRUPT_STATUS_PCI                                        19:19
+#define INTERRUPT_STATUS_PCI_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_PCI_ACTIVE                                 1
+#define INTERRUPT_STATUS_I2S                                        18:18
+#define INTERRUPT_STATUS_I2S_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_I2S_ACTIVE                                 1
+#define INTERRUPT_STATUS_AC97                                       17:17
+#define INTERRUPT_STATUS_AC97_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_AC97_ACTIVE                                1
+#define INTERRUPT_STATUS_USB_SLAVE                                  16:16
+#define INTERRUPT_STATUS_USB_SLAVE_NOT_ACTIVE                       0
+#define INTERRUPT_STATUS_USB_SLAVE_ACTIVE                           1
+#define INTERRUPT_STATUS_UART1                                      13:13
+#define INTERRUPT_STATUS_UART1_NOT_ACTIVE                           0
+#define INTERRUPT_STATUS_UART1_ACTIVE                               1
+#define INTERRUPT_STATUS_UART0                                      12:12
+#define INTERRUPT_STATUS_UART0_NOT_ACTIVE                           0
+#define INTERRUPT_STATUS_UART0_ACTIVE                               1
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC                          11:11
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE               0
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC_ACTIVE                   1
+#define INTERRUPT_STATUS_8051                                       10:10
+#define INTERRUPT_STATUS_8051_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_8051_ACTIVE                                1
+#define INTERRUPT_STATUS_SSP1                                       9:9
+#define INTERRUPT_STATUS_SSP1_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_SSP1_ACTIVE                                1
+#define INTERRUPT_STATUS_SSP0                                       8:8
+#define INTERRUPT_STATUS_SSP0_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_SSP0_ACTIVE                                1
+#define INTERRUPT_STATUS_USB_HOST                                   6:6
+#define INTERRUPT_STATUS_USB_HOST_NOT_ACTIVE                        0
+#define INTERRUPT_STATUS_USB_HOST_ACTIVE                            1
+#define INTERRUPT_STATUS_2D                                         3:3
+#define INTERRUPT_STATUS_2D_NOT_ACTIVE                              0
+#define INTERRUPT_STATUS_2D_ACTIVE                                  1
+#define INTERRUPT_STATUS_ZVPORT                                     2:2
+#define INTERRUPT_STATUS_ZVPORT_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_ZVPORT_ACTIVE                              1
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC                        1:1
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE             0
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_ACTIVE                 1
+#define INTERRUPT_STATUS_COMMAND_LIST                               0:0
+#define INTERRUPT_STATUS_COMMAND_LIST_NOT_ACTIVE                    0
+#define INTERRUPT_STATUS_COMMAND_LIST_ACTIVE                        1
+
+/* Interrupt Mask */
+#define INTERRUPT_MASK                                              0x000030
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN                            31:31
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN_DISABLE                    0
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN_ENABLE                     1
+#define INTERRUPT_MASK_GPIO54                                       30:30
+#define INTERRUPT_MASK_GPIO54_DISABLE                               0
+#define INTERRUPT_MASK_GPIO54_ENABLE                                1
+#define INTERRUPT_MASK_GPIO53                                       29:29
+#define INTERRUPT_MASK_GPIO53_DISABLE                               0
+#define INTERRUPT_MASK_GPIO53_ENABLE                                1
+#define INTERRUPT_MASK_GPIO52                                       28:28
+#define INTERRUPT_MASK_GPIO52_DISABLE                               0
+#define INTERRUPT_MASK_GPIO52_ENABLE                                1
+#define INTERRUPT_MASK_GPIO51                                       27:27
+#define INTERRUPT_MASK_GPIO51_DISABLE                               0
+#define INTERRUPT_MASK_GPIO51_ENABLE                                1
+#define INTERRUPT_MASK_GPIO50                                       26:26
+#define INTERRUPT_MASK_GPIO50_DISABLE                               0
+#define INTERRUPT_MASK_GPIO50_ENABLE                                1
+#define INTERRUPT_MASK_GPIO49                                       25:25
+#define INTERRUPT_MASK_GPIO49_DISABLE                               0
+#define INTERRUPT_MASK_GPIO49_ENABLE                                1
+#define INTERRUPT_MASK_GPIO48                                       24:24
+#define INTERRUPT_MASK_GPIO48_DISABLE                               0
+#define INTERRUPT_MASK_GPIO48_ENABLE                                1
+#define INTERRUPT_MASK_I2C                                          23:23
+#define INTERRUPT_MASK_I2C_DISABLE                                  0
+#define INTERRUPT_MASK_I2C_ENABLE                                   1
+#define INTERRUPT_MASK_PWM                                          22:22
+#define INTERRUPT_MASK_PWM_DISABLE                                  0
+#define INTERRUPT_MASK_PWM_ENABLE                                   1
+#define INTERRUPT_MASK_DMA                                          20:20
+#define INTERRUPT_MASK_DMA_DISABLE                                  0
+#define INTERRUPT_MASK_DMA_ENABLE                                   1
+#define INTERRUPT_MASK_PCI                                          19:19
+#define INTERRUPT_MASK_PCI_DISABLE                                  0
+#define INTERRUPT_MASK_PCI_ENABLE                                   1
+#define INTERRUPT_MASK_I2S                                          18:18
+#define INTERRUPT_MASK_I2S_DISABLE                                  0
+#define INTERRUPT_MASK_I2S_ENABLE                                   1
+#define INTERRUPT_MASK_AC97                                         17:17
+#define INTERRUPT_MASK_AC97_DISABLE                                 0
+#define INTERRUPT_MASK_AC97_ENABLE                                  1
+#define INTERRUPT_MASK_USB_SLAVE                                    16:16
+#define INTERRUPT_MASK_USB_SLAVE_DISABLE                            0
+#define INTERRUPT_MASK_USB_SLAVE_ENABLE                             1
+#define INTERRUPT_MASK_UART1                                        13:13
+#define INTERRUPT_MASK_UART1_DISABLE                                0
+#define INTERRUPT_MASK_UART1_ENABLE                                 1
+#define INTERRUPT_MASK_UART0                                        12:12
+#define INTERRUPT_MASK_UART0_DISABLE                                0
+#define INTERRUPT_MASK_UART0_ENABLE                                 1
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC                            11:11
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC_DISABLE                    0
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC_ENABLE                     1
+#define INTERRUPT_MASK_8051                                         10:10
+#define INTERRUPT_MASK_8051_DISABLE                                 0
+#define INTERRUPT_MASK_8051_ENABLE                                  1
+#define INTERRUPT_MASK_SSP1                                         9:9
+#define INTERRUPT_MASK_SSP1_DISABLE                                 0
+#define INTERRUPT_MASK_SSP1_ENABLE                                  1
+#define INTERRUPT_MASK_SSP0                                         8:8
+#define INTERRUPT_MASK_SSP0_DISABLE                                 0
+#define INTERRUPT_MASK_SSP0_ENABLE                                  1
+#define INTERRUPT_MASK_USB_HOST                                     6:6
+#define INTERRUPT_MASK_USB_HOST_DISABLE                             0
+#define INTERRUPT_MASK_USB_HOST_ENABLE                              1
+#define INTERRUPT_MASK_2D                                           3:3
+#define INTERRUPT_MASK_2D_DISABLE                                   0
+#define INTERRUPT_MASK_2D_ENABLE                                    1
+#define INTERRUPT_MASK_ZVPORT                                       2:2
+#define INTERRUPT_MASK_ZVPORT_DISABLE                               0
+#define INTERRUPT_MASK_ZVPORT_ENABLE                                1
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC                          1:1
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC_DISABLE                  0
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC_ENABLE                   1
+#define INTERRUPT_MASK_COMMAND_LIST                                 0:0
+#define INTERRUPT_MASK_COMMAND_LIST_DISABLE                         0
+#define INTERRUPT_MASK_COMMAND_LIST_ENABLE                          1
+
+/* Debug Control */
+#define DEBUG_CONTROL                                               0x000034
+#define DEBUG_CONTROL_MODULE                                        7:5
+#define DEBUG_CONTROL_PARTITION                                     4:0
+#define DEBUG_CONTROL_PARTITION_HIF                                 0
+#define DEBUG_CONTROL_PARTITION_EXTERNAL_MEMORY                     1
+#define DEBUG_CONTROL_PARTITION_PCI                                 2
+#define DEBUG_CONTROL_PARTITION_COMMAND_LIST                        3
+#define DEBUG_CONTROL_PARTITION_DISPLAY                             4
+#define DEBUG_CONTROL_PARTITION_ZVPORT                              5
+#define DEBUG_CONTROL_PARTITION_2D                                  6
+#define DEBUG_CONTROL_PARTITION_LOCAL_MEMORY                        8
+#define DEBUG_CONTROL_PARTITION_USB_HOST                            10
+#define DEBUG_CONTROL_PARTITION_SSP0                                12
+#define DEBUG_CONTROL_PARTITION_SSP1                                13
+#define DEBUG_CONTROL_PARTITION_UART0                               19
+#define DEBUG_CONTROL_PARTITION_UART1                               20
+#define DEBUG_CONTROL_PARTITION_I2C                                 21
+#define DEBUG_CONTROL_PARTITION_8051                                23
+#define DEBUG_CONTROL_PARTITION_AC97                                24
+#define DEBUG_CONTROL_PARTITION_I2S                                 25
+#define DEBUG_CONTROL_PARTITION_INTMEM                              26
+#define DEBUG_CONTROL_PARTITION_DMA                                 27
+#define DEBUG_CONTROL_PARTITION_SIMULATION                          28
+
+/* Current Gate */
+#define CURRENT_GATE                                                0x000038
+#define CURRENT_GATE_AC97_I2S                                       18:18
+#define CURRENT_GATE_AC97_I2S_DISABLE                               0
+#define CURRENT_GATE_AC97_I2S_ENABLE                                1
+#define CURRENT_GATE_8051                                           17:17
+#define CURRENT_GATE_8051_DISABLE                                   0
+#define CURRENT_GATE_8051_ENABLE                                    1
+#define CURRENT_GATE_PLL                                            16:16
+#define CURRENT_GATE_PLL_ENABLE                                     0
+#define CURRENT_GATE_PLL_DISABLE                                    1
+#define CURRENT_GATE_OSCILLATOR                                     15:15
+#define CURRENT_GATE_OSCILLATOR_ENABLE                              0
+#define CURRENT_GATE_OSCILLATOR_DISABLE                             1
+#define CURRENT_GATE_PLL_RECOVERY                                   14:13
+#define CURRENT_GATE_PLL_RECOVERY_1MS                               0
+#define CURRENT_GATE_PLL_RECOVERY_2MS                               1
+#define CURRENT_GATE_PLL_RECOVERY_3MS                               2
+#define CURRENT_GATE_PLL_RECOVERY_4MS                               3
+#define CURRENT_GATE_USB_SLAVE                                      12:12
+#define CURRENT_GATE_USB_SLAVE_DISABLE                              0
+#define CURRENT_GATE_USB_SLAVE_ENABLE                               1
+#define CURRENT_GATE_USB_HOST                                       11:11
+#define CURRENT_GATE_USB_HOST_DISABLE                               0
+#define CURRENT_GATE_USB_HOST_ENABLE                                1
+#define CURRENT_GATE_SSP                                            10:10
+#define CURRENT_GATE_SSP_DISABLE                                    0
+#define CURRENT_GATE_SSP_ENABLE                                     1
+#define CURRENT_GATE_UART1                                          8:8
+#define CURRENT_GATE_UART1_DISABLE                                  0
+#define CURRENT_GATE_UART1_ENABLE                                   1
+#define CURRENT_GATE_UART0                                          7:7
+#define CURRENT_GATE_UART0_DISABLE                                  0
+#define CURRENT_GATE_UART0_ENABLE                                   1
+#define CURRENT_GATE_GPIO_PWM_I2C                                   6:6
+#define CURRENT_GATE_GPIO_PWM_I2C_DISABLE                           0
+#define CURRENT_GATE_GPIO_PWM_I2C_ENABLE                            1
+#define CURRENT_GATE_ZVPORT                                         5:5
+#define CURRENT_GATE_ZVPORT_DISABLE                                 0
+#define CURRENT_GATE_ZVPORT_ENABLE                                  1
+#define CURRENT_GATE_CSC                                            4:4
+#define CURRENT_GATE_CSC_DISABLE                                    0
+#define CURRENT_GATE_CSC_ENABLE                                     1
+#define CURRENT_GATE_2D                                             3:3
+#define CURRENT_GATE_2D_DISABLE                                     0
+#define CURRENT_GATE_2D_ENABLE                                      1
+#define CURRENT_GATE_DISPLAY                                        2:2
+#define CURRENT_GATE_DISPLAY_DISABLE                                0
+#define CURRENT_GATE_DISPLAY_ENABLE                                 1
+#define CURRENT_GATE_MEMORY                                         1:1
+#define CURRENT_GATE_MEMORY_DISABLE                                 0
+#define CURRENT_GATE_MEMORY_ENABLE                                  1
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA                          0:0
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA_DISABLE                  0
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA_ENABLE                   1
+
+/* Current Clock */
+#define CURRENT_CLOCK                                               0x00003C
+#define CURRENT_CLOCK_P2XCLK_SELECT                                 29:29
+#define CURRENT_CLOCK_P2XCLK_SELECT_228MHZ                          0
+#define CURRENT_CLOCK_P2XCLK_SELECT_336MHZ                          1
+#define CURRENT_CLOCK_P2XCLK_DIVIDER                                28:24
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_1                              0
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_2                              1
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_4                              2
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_8                              3
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_16                             4
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_32                             5
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_64                             6
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_128                            7
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_3                              8
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_6                              9
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_12                             10
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_24                             11
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_48                             12
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_96                             13
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_192                            14
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_384                            15
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_5                              16
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_10                             17
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_20                             18
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_40                             19
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_80                             20
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_160                            21
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_320                            22
+#define CURRENT_CLOCK_P2XCLK_DIVIDER_640                            23
+#define CURRENT_CLOCK_V2XCLK_SELECT                                 20:20
+#define CURRENT_CLOCK_V2XCLK_SELECT_228MHZ                          0
+#define CURRENT_CLOCK_V2XCLK_SELECT_336MHZ                          1
+#define CURRENT_CLOCK_V2XCLK_DIVIDER                                19:16
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_1                              0
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_2                              1
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_4                              2
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_8                              3
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_16                             4
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_32                             5
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_64                             6
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_128                            7
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_3                              8
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_6                              9
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_12                             10
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_24                             11
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_48                             12
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_96                             13
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_192                            14
+#define CURRENT_CLOCK_V2XCLK_DIVIDER_384                            15
+#define CURRENT_CLOCK_MCLK_SELECT                                   12:12
+#define CURRENT_CLOCK_MCLK_SELECT_228MHZ                            0
+#define CURRENT_CLOCK_MCLK_SELECT_336MHZ                            1
+#define CURRENT_CLOCK_MCLK_DIVIDER                                  11:8
+#define CURRENT_CLOCK_MCLK_DIVIDER_1                                0
+#define CURRENT_CLOCK_MCLK_DIVIDER_2                                1
+#define CURRENT_CLOCK_MCLK_DIVIDER_4                                2
+#define CURRENT_CLOCK_MCLK_DIVIDER_8                                3
+#define CURRENT_CLOCK_MCLK_DIVIDER_16                               4
+#define CURRENT_CLOCK_MCLK_DIVIDER_32                               5
+#define CURRENT_CLOCK_MCLK_DIVIDER_64                               6
+#define CURRENT_CLOCK_MCLK_DIVIDER_128                              7
+#define CURRENT_CLOCK_MCLK_DIVIDER_3                                8
+#define CURRENT_CLOCK_MCLK_DIVIDER_6                                9
+#define CURRENT_CLOCK_MCLK_DIVIDER_12                               10
+#define CURRENT_CLOCK_MCLK_DIVIDER_24                               11
+#define CURRENT_CLOCK_MCLK_DIVIDER_48                               12
+#define CURRENT_CLOCK_MCLK_DIVIDER_96                               13
+#define CURRENT_CLOCK_MCLK_DIVIDER_192                              14
+#define CURRENT_CLOCK_MCLK_DIVIDER_384                              15
+#define CURRENT_CLOCK_M1XCLK_SELECT                                 4:4
+#define CURRENT_CLOCK_M1XCLK_SELECT_228MHZ                          0
+#define CURRENT_CLOCK_M1XCLK_SELECT_336MHZ                          1
+#define CURRENT_CLOCK_M1XCLK_DIVIDER                                3:0
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_1                              0
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_2                              1
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_4                              2
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_8                              3
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_16                             4
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_32                             5
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_64                             6
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_128                            7
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_3                              8
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_6                              9
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_12                             10
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_24                             11
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_48                             12
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_96                             13
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_192                            14
+#define CURRENT_CLOCK_M1XCLK_DIVIDER_384                            15
+
+/* Power Mode 0 Gate */
+#define POWER_MODE0_GATE                                            0x000040
+#define POWER_MODE0_GATE_AC97_I2S                                   18:18
+#define POWER_MODE0_GATE_AC97_I2S_DISABLE                           0
+#define POWER_MODE0_GATE_AC97_I2S_ENABLE                            1
+#define POWER_MODE0_GATE_8051                                       17:17
+#define POWER_MODE0_GATE_8051_DISABLE                               0
+#define POWER_MODE0_GATE_8051_ENABLE                                1
+#define POWER_MODE0_GATE_USB_SLAVE                                  12:12
+#define POWER_MODE0_GATE_USB_SLAVE_DISABLE                          0
+#define POWER_MODE0_GATE_USB_SLAVE_ENABLE                           1
+#define POWER_MODE0_GATE_USB_HOST                                   11:11
+#define POWER_MODE0_GATE_USB_HOST_DISABLE                           0
+#define POWER_MODE0_GATE_USB_HOST_ENABLE                            1
+#define POWER_MODE0_GATE_SSP                                        10:10
+#define POWER_MODE0_GATE_SSP_DISABLE                                0
+#define POWER_MODE0_GATE_SSP_ENABLE                                 1
+#define POWER_MODE0_GATE_UART1                                      8:8
+#define POWER_MODE0_GATE_UART1_DISABLE                              0
+#define POWER_MODE0_GATE_UART1_ENABLE                               1
+#define POWER_MODE0_GATE_UART0                                      7:7
+#define POWER_MODE0_GATE_UART0_DISABLE                              0
+#define POWER_MODE0_GATE_UART0_ENABLE                               1
+#define POWER_MODE0_GATE_GPIO_PWM_I2C                               6:6
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE                       0
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE                        1
+#define POWER_MODE0_GATE_ZVPORT                                     5:5
+#define POWER_MODE0_GATE_ZVPORT_DISABLE                             0
+#define POWER_MODE0_GATE_ZVPORT_ENABLE                              1
+#define POWER_MODE0_GATE_CSC                                        4:4
+#define POWER_MODE0_GATE_CSC_DISABLE                                0
+#define POWER_MODE0_GATE_CSC_ENABLE                                 1
+#define POWER_MODE0_GATE_2D                                         3:3
+#define POWER_MODE0_GATE_2D_DISABLE                                 0
+#define POWER_MODE0_GATE_2D_ENABLE                                  1
+#define POWER_MODE0_GATE_DISPLAY                                    2:2
+#define POWER_MODE0_GATE_DISPLAY_DISABLE                            0
+#define POWER_MODE0_GATE_DISPLAY_ENABLE                             1
+#define POWER_MODE0_GATE_MEMORY                                     1:1
+#define POWER_MODE0_GATE_MEMORY_DISABLE                             0
+#define POWER_MODE0_GATE_MEMORY_ENABLE                              1
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA                      0:0
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA_DISABLE              0
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA_ENABLE               1
+
+/* Power Mode 0 Clock */
+#define POWER_MODE0_CLOCK                                           0x000044
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT                             29:29
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_228MHZ                      0
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_336MHZ                      1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER                            28:24
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_1                          0
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_2                          1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_4                          2
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_8                          3
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_16                         4
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_32                         5
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_64                         6
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_128                        7
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_3                          8
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_6                          9
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_12                         10
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_24                         11
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_48                         12
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_96                         13
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_192                        14
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_384                        15
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_5                          16
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_10                         17
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_20                         18
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_40                         19
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_80                         20
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_160                        21
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_320                        22
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_640                        23
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT                             20:20
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_228MHZ                      0
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_336MHZ                      1
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER                            19:16
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_1                          0
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_2                          1
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_4                          2
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_8                          3
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_16                         4
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_32                         5
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_64                         6
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_128                        7
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_3                          8
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_6                          9
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_12                         10
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_24                         11
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_48                         12
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_96                         13
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_192                        14
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_384                        15
+#define POWER_MODE0_CLOCK_MCLK_SELECT                               12:12
+#define POWER_MODE0_CLOCK_MCLK_SELECT_228MHZ                        0
+#define POWER_MODE0_CLOCK_MCLK_SELECT_336MHZ                        1
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER                              11:8
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_1                            0
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_2                            1
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_4                            2
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_8                            3
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_16                           4
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_32                           5
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_64                           6
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_128                          7
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_3                            8
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_6                            9
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_12                           10
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_24                           11
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_48                           12
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_96                           13
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_192                          14
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_384                          15
+#define POWER_MODE0_CLOCK_M1XCLK_SELECT                             4:4
+#define POWER_MODE0_CLOCK_M1XCLK_SELECT_228MHZ                      0
+#define POWER_MODE0_CLOCK_M1XCLK_SELECT_336MHZ                      1
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER                            3:0
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_1                          0
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_2                          1
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_4                          2
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_8                          3
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_16                         4
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_32                         5
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_64                         6
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_128                        7
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_3                          8
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_6                          9
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_12                         10
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_24                         11
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_48                         12
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_96                         13
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_192                        14
+#define POWER_MODE0_CLOCK_M1XCLK_DIVIDER_384                        15
+
+/* Power Mode 1 Gate */
+#define POWER_MODE1_GATE                                            0x000048
+#define POWER_MODE1_GATE_AC97_I2S                                   18:18
+#define POWER_MODE1_GATE_AC97_I2S_DISABLE                           0
+#define POWER_MODE1_GATE_AC97_I2S_ENABLE                            1
+#define POWER_MODE1_GATE_8051                                       17:17
+#define POWER_MODE1_GATE_8051_DISABLE                               0
+#define POWER_MODE1_GATE_8051_ENABLE                                1
+#define POWER_MODE1_GATE_USB_SLAVE                                  12:12
+#define POWER_MODE1_GATE_USB_SLAVE_DISABLE                          0
+#define POWER_MODE1_GATE_USB_SLAVE_ENABLE                           1
+#define POWER_MODE1_GATE_USB_HOST                                   11:11
+#define POWER_MODE1_GATE_USB_HOST_DISABLE                           0
+#define POWER_MODE1_GATE_USB_HOST_ENABLE                            1
+#define POWER_MODE1_GATE_SSP                                        10:10
+#define POWER_MODE1_GATE_SSP_DISABLE                                0
+#define POWER_MODE1_GATE_SSP_ENABLE                                 1
+#define POWER_MODE1_GATE_UART1                                      8:8
+#define POWER_MODE1_GATE_UART1_DISABLE                              0
+#define POWER_MODE1_GATE_UART1_ENABLE                               1
+#define POWER_MODE1_GATE_UART0                                      7:7
+#define POWER_MODE1_GATE_UART0_DISABLE                              0
+#define POWER_MODE1_GATE_UART0_ENABLE                               1
+#define POWER_MODE1_GATE_GPIO_PWM_I2C                               6:6
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_DISABLE                       0
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_ENABLE                        1
+#define POWER_MODE1_GATE_ZVPORT                                     5:5
+#define POWER_MODE1_GATE_ZVPORT_DISABLE                             0
+#define POWER_MODE1_GATE_ZVPORT_ENABLE                              1
+#define POWER_MODE1_GATE_CSC                                        4:4
+#define POWER_MODE1_GATE_CSC_DISABLE                                0
+#define POWER_MODE1_GATE_CSC_ENABLE                                 1
+#define POWER_MODE1_GATE_2D                                         3:3
+#define POWER_MODE1_GATE_2D_DISABLE                                 0
+#define POWER_MODE1_GATE_2D_ENABLE                                  1
+#define POWER_MODE1_GATE_DISPLAY                                    2:2
+#define POWER_MODE1_GATE_DISPLAY_DISABLE                            0
+#define POWER_MODE1_GATE_DISPLAY_ENABLE                             1
+#define POWER_MODE1_GATE_MEMORY                                     1:1
+#define POWER_MODE1_GATE_MEMORY_DISABLE                             0
+#define POWER_MODE1_GATE_MEMORY_ENABLE                              1
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA                      0:0
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA_DISABLE              0
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA_ENABLE               1
+
+/* Power Mode 1 Clock */
+#define POWER_MODE1_CLOCK                                           0x00004C
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT                             29:29
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_228MHZ                      0
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_336MHZ                      1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER                            28:24
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_1                          0
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_2                          1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_4                          2
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_8                          3
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_16                         4
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_32                         5
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_64                         6
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_128                        7
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_3                          8
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_6                          9
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_12                         10
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_24                         11
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_48                         12
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_96                         13
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_192                        14
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_384                        15
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_5                          16
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_10                         17
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_20                         18
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_40                         19
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_80                         20
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_160                        21
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_320                        22
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_640                        23
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT                             20:20
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_228MHZ                      0
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_336MHZ                      1
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER                            19:16
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_1                          0
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_2                          1
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_4                          2
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_8                          3
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_16                         4
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_32                         5
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_64                         6
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_128                        7
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_3                          8
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_6                          9
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_12                         10
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_24                         11
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_48                         12
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_96                         13
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_192                        14
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_384                        15
+#define POWER_MODE1_CLOCK_MCLK_SELECT                               12:12
+#define POWER_MODE1_CLOCK_MCLK_SELECT_228MHZ                        0
+#define POWER_MODE1_CLOCK_MCLK_SELECT_336MHZ                        1
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER                              11:8
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_1                            0
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_2                            1
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_4                            2
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_8                            3
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_16                           4
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_32                           5
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_64                           6
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_128                          7
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_3                            8
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_6                            9
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_12                           10
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_24                           11
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_48                           12
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_96                           13
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_192                          14
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_384                          15
+#define POWER_MODE1_CLOCK_M1XCLK_SELECT                             4:4
+#define POWER_MODE1_CLOCK_M1XCLK_SELECT_228MHZ                      0
+#define POWER_MODE1_CLOCK_M1XCLK_SELECT_336MHZ                      1
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER                            3:0
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_1                          0
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_2                          1
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_4                          2
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_8                          3
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_16                         4
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_32                         5
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_64                         6
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_128                        7
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_3                          8
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_6                          9
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_12                         10
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_24                         11
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_48                         12
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_96                         13
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_192                        14
+#define POWER_MODE1_CLOCK_M1XCLK_DIVIDER_384                        15
+
+/* Sleep Mode Gate */
+#define SLEEP_MODE_GATE                                             0x000050
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK                          22:19
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_4096                     0
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_2048                     1
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_1024                     2
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_512                      3
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_256                      4
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_128                      5
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_64                       6
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_32                       7
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_16                       8
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_8                        9
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_4                        10
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_2                        11
+#define SLEEP_MODE_GATE_PLL_RECOVERY                                14:13
+#define SLEEP_MODE_GATE_PLL_RECOVERY_1MS                            0
+#define SLEEP_MODE_GATE_PLL_RECOVERY_2MS                            1
+#define SLEEP_MODE_GATE_PLL_RECOVERY_3MS                            2
+#define SLEEP_MODE_GATE_PLL_RECOVERY_4MS                            3
+
+/* Power Mode Control */
+#define POWER_MODE_CONTROL                                          0x000054
+#define POWER_MODE_CONTROL_STATUS                                   2:2
+#define POWER_MODE_CONTROL_STATUS_NOT_SLEEP                         0
+#define POWER_MODE_CONTROL_STATUS_SLEEP                             1
+#define POWER_MODE_CONTROL_MODE_SELECT                              1:0
+#define POWER_MODE_CONTROL_MODE_SELECT_MODE0                        0
+#define POWER_MODE_CONTROL_MODE_SELECT_MODE1                        1
+#define POWER_MODE_CONTROL_MODE_SELECT_SLEEP                        2
+
+/* PCI Master Base Address */
+#define PCI_MASTER_BASE                                             0x000058
+#define PCI_MASTER_BASE_ADDRESS                                     31:20
+
+/* Endian Control */
+#define ENDIAN_CONTROL                                              0x00005C
+#define ENDIAN_CONTROL_ENDIAN_SELECT                                0:0
+#define ENDIAN_CONTROL_ENDIAN_SELECT_LITTLE                         0
+#define ENDIAN_CONTROL_ENDIAN_SELECT_BIG                            1
+
+/* Device Id */
+#define DEVICE_ID                                                   0x000060
+#define DEVICE_ID_DEVICE                                            31:16
+#define DEVICE_ID_REVISION                                          7:0
+
+/* PLL Clock Count */
+#define PLL_CLOCK_COUNT                                             0x000064
+#define PLL_CLOCK_COUNT_COUNT                                       15:0
+
+/* Miscellaneous Timing */
+#define MISCELLANEOUS_TIMING                                        0x000068
+#define MISCELLANEOUS_TIMING_EXTEND                                 31:28
+#define MISCELLANEOUS_TIMING_EXTEND_NONE                            0
+#define MISCELLANEOUS_TIMING_EXTEND_16_HCLK                         1
+#define MISCELLANEOUS_TIMING_EXTEND_32_HCLK                         2
+#define MISCELLANEOUS_TIMING_EXTEND_48_HCLK                         3
+#define MISCELLANEOUS_TIMING_EXTEND_64_HCLK                         4
+#define MISCELLANEOUS_TIMING_EXTEND_80_HCLK                         5
+#define MISCELLANEOUS_TIMING_EXTEND_96_HCLK                         6
+#define MISCELLANEOUS_TIMING_EXTEND_112_HCLK                        7
+#define MISCELLANEOUS_TIMING_EXTEND_128_HCLK                        8
+#define MISCELLANEOUS_TIMING_EXTEND_144_HCLK                        9
+#define MISCELLANEOUS_TIMING_EXTEND_160_HCLK                        10
+#define MISCELLANEOUS_TIMING_EXTEND_176_HCLK                        11
+#define MISCELLANEOUS_TIMING_EXTEND_192_HCLK                        12
+#define MISCELLANEOUS_TIMING_EXTEND_208_HCLK                        13
+#define MISCELLANEOUS_TIMING_EXTEND_224_HCLK                        14
+#define MISCELLANEOUS_TIMING_EXTEND_240_HCLK                        15
+#define MISCELLANEOUS_TIMING_XSCALE                                 25:24
+#define MISCELLANEOUS_TIMING_XSCALE_PLL                             0
+#define MISCELLANEOUS_TIMING_XSCALE_HCLK                            1
+#define MISCELLANEOUS_TIMING_XSCALE_GPIO30                          2
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT                  23:23
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT_DISABLE          0
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT_ENABLE           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1              20:20
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1_288          0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1_336          1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1             19:16
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_1           0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_2           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_4           2
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_8           3
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_16          4
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_32          5
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_64          6
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_128         7
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_3           8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_6           9
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_12          10
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_24          11
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_48          12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_96          13
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_192         14
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_384         15
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0              12:12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0_288          0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0_336          1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0             11:8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_1           0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_2           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_4           2
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_8           3
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_16          4
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_32          5
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_64          6
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_128         7
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_3           8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_6           9
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_12          10
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_24          11
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_48          12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_96          13
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_192         14
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_384         15
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG                        7:7
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG_CHECK_INPUT            0
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG_CHECK_OUTPUT           1
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL                           6:6
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL_DISABLE                   0
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL_ENABLE                    1
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER                            5:4
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_336                        0
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_288                        1
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_240                        2
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_192                        3
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE                          3:3
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE_NORMAL                   0
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE_SIMULATION               1
+#define MISCELLANEOUS_TIMING_DELAY                                  2:0
+#define MISCELLANEOUS_TIMING_DELAY_NONE                             0
+#define MISCELLANEOUS_TIMING_DELAY_500PS                            1
+#define MISCELLANEOUS_TIMING_DELAY_1NS                              2
+#define MISCELLANEOUS_TIMING_DELAY_1500PS                           3
+#define MISCELLANEOUS_TIMING_DELAY_2NS                              4
+#define MISCELLANEOUS_TIMING_DELAY_2500PS                           5
+
+/* Current System SDRAM Clock */
+#define CURRENT_SYSTEM_SDRAM_CLOCK                                  0x00006C
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT                           4:4
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT_288                       0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT_336                       1
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER                          3:0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_1                        0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_2                        1
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_4                        2
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_8                        3
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_16                       4
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_32                       5
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_64                       6
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_128                      7
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_3                        8
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_6                        9
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_12                       10
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_24                       11
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_48                       12
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_96                       13
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_192                      14
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_384                      15
+
+/*****************************************************************************\
+ *                              GPIO / PWM / I2C                             *
+\*****************************************************************************/
+
+/* GPIO[31:0] Data */
+#define GPIO_DATA_LOW                                               0x010000
+
+/* GPIO[63:32] Data */
+#define GPIO_DATA_HIGH                                              0x010004
+
+/* GPIO[31:0] Data Direction */
+#define GPIO_DATA_DIRECTION_LOW                                     0x010008
+#define GPIO_DATA_DIRECTION_LOW_INPUT                               0
+#define GPIO_DATA_DIRECTION_LOW_OUTPUT                              1
+
+/* GPIO[63:32] Data Direction */
+#define GPIO_DATA_DIRECTION_HIGH                                    0x01000C
+#define GPIO_DATA_DIRECTION_HIGH_INPUT                              0
+#define GPIO_DATA_DIRECTION_HIGH_OUTPUT                             1
+
+/* GPIO Interrupt Setup */
+#define GPIO_INTERRUPT_SETUP                                        0x010010
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54                             22:22
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53                             21:21
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52                             20:20
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51                             19:19
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50                             18:18
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49                             17:17
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48                             16:16
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54                              14:14
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53                              13:13
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52                              12:12
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51                              11:11
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50                              10:10
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49                              9:9
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48                              8:8
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ENABLE_54                              6:6
+#define GPIO_INTERRUPT_SETUP_ENABLE_54_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_54_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_53                              5:5
+#define GPIO_INTERRUPT_SETUP_ENABLE_53_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_53_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_52                              4:4
+#define GPIO_INTERRUPT_SETUP_ENABLE_52_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_52_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_51                              3:3
+#define GPIO_INTERRUPT_SETUP_ENABLE_51_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_51_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_50                              2:2
+#define GPIO_INTERRUPT_SETUP_ENABLE_50_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_50_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_49                              1:1
+#define GPIO_INTERRUPT_SETUP_ENABLE_49_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_49_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_48                              0:0
+#define GPIO_INTERRUPT_SETUP_ENABLE_48_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_48_INTERRUPT                    1
+
+/* GPIO Interrupt Status & Reset */
+#define GPIO_INTERRUPT_STATUS                                       0x010014
+#define GPIO_INTERRUPT_STATUS_54                                    22:22
+#define GPIO_INTERRUPT_STATUS_54_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_54_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_54_RESET                              1
+#define GPIO_INTERRUPT_STATUS_53                                    21:21
+#define GPIO_INTERRUPT_STATUS_53_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_53_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_53_RESET                              1
+#define GPIO_INTERRUPT_STATUS_52                                    20:20
+#define GPIO_INTERRUPT_STATUS_52_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_52_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_52_RESET                              1
+#define GPIO_INTERRUPT_STATUS_51                                    19:19
+#define GPIO_INTERRUPT_STATUS_51_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_51_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_51_RESET                              1
+#define GPIO_INTERRUPT_STATUS_50                                    18:18
+#define GPIO_INTERRUPT_STATUS_50_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_50_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_50_RESET                              1
+#define GPIO_INTERRUPT_STATUS_49                                    17:17
+#define GPIO_INTERRUPT_STATUS_49_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_49_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_49_RESET                              1
+#define GPIO_INTERRUPT_STATUS_48                                    16:16
+#define GPIO_INTERRUPT_STATUS_48_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_48_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_48_RESET                              1
+
+/* PWM 0 */
+#define PWM0                                                        0x010020
+#define PWM0_HIGH_COUNTER                                           31:20
+#define PWM0_LOW_COUNTER                                            19:8
+#define PWM0_CLOCK_DIVIDE                                           7:4
+#define PWM0_CLOCK_DIVIDE_1                                         0
+#define PWM0_CLOCK_DIVIDE_2                                         1
+#define PWM0_CLOCK_DIVIDE_4                                         2
+#define PWM0_CLOCK_DIVIDE_8                                         3
+#define PWM0_CLOCK_DIVIDE_16                                        4
+#define PWM0_CLOCK_DIVIDE_32                                        5
+#define PWM0_CLOCK_DIVIDE_64                                        6
+#define PWM0_CLOCK_DIVIDE_128                                       7
+#define PWM0_CLOCK_DIVIDE_256                                       8
+#define PWM0_CLOCK_DIVIDE_512                                       9
+#define PWM0_CLOCK_DIVIDE_1024                                      10
+#define PWM0_CLOCK_DIVIDE_2048                                      11
+#define PWM0_CLOCK_DIVIDE_4096                                      12
+#define PWM0_CLOCK_DIVIDE_8192                                      13
+#define PWM0_CLOCK_DIVIDE_16384                                     14
+#define PWM0_CLOCK_DIVIDE_32768                                     15
+#define PWM0_INTERRUPT_STATUS                                       3:3
+#define PWM0_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM0_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM0_INTERRUPT_CONTROL                                      2:2
+#define PWM0_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM0_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM0_CONTROL                                                0:0
+#define PWM0_CONTROL_DISABLE                                        0
+#define PWM0_CONTROL_ENABLE                                         1
+
+/* PWM 1 */
+#define PWM1                                                        0x010024
+#define PWM1_HIGH_COUNTER                                           31:20
+#define PWM1_LOW_COUNTER                                            19:8
+#define PWM1_CLOCK_DIVIDE                                           7:4
+#define PWM1_CLOCK_DIVIDE_1                                         0
+#define PWM1_CLOCK_DIVIDE_2                                         1
+#define PWM1_CLOCK_DIVIDE_4                                         2
+#define PWM1_CLOCK_DIVIDE_8                                         3
+#define PWM1_CLOCK_DIVIDE_16                                        4
+#define PWM1_CLOCK_DIVIDE_32                                        5
+#define PWM1_CLOCK_DIVIDE_64                                        6
+#define PWM1_CLOCK_DIVIDE_128                                       7
+#define PWM1_CLOCK_DIVIDE_256                                       8
+#define PWM1_CLOCK_DIVIDE_512                                       9
+#define PWM1_CLOCK_DIVIDE_1024                                      10
+#define PWM1_CLOCK_DIVIDE_2048                                      11
+#define PWM1_CLOCK_DIVIDE_4096                                      12
+#define PWM1_CLOCK_DIVIDE_8192                                      13
+#define PWM1_CLOCK_DIVIDE_16384                                     14
+#define PWM1_CLOCK_DIVIDE_32768                                     15
+#define PWM1_INTERRUPT_STATUS                                       3:3
+#define PWM1_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM1_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM1_INTERRUPT_CONTROL                                      2:2
+#define PWM1_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM1_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM1_CONTROL                                                0:0
+#define PWM1_CONTROL_DISABLE                                        0
+#define PWM1_CONTROL_ENABLE                                         1
+
+/* PWM 2 */
+#define PWM2                                                        0x010028
+#define PWM2_HIGH_COUNTER                                           31:20
+#define PWM2_LOW_COUNTER                                            19:8
+#define PWM2_CLOCK_DIVIDE                                           7:4
+#define PWM2_CLOCK_DIVIDE_1                                         0
+#define PWM2_CLOCK_DIVIDE_2                                         1
+#define PWM2_CLOCK_DIVIDE_4                                         2
+#define PWM2_CLOCK_DIVIDE_8                                         3
+#define PWM2_CLOCK_DIVIDE_16                                        4
+#define PWM2_CLOCK_DIVIDE_32                                        5
+#define PWM2_CLOCK_DIVIDE_64                                        6
+#define PWM2_CLOCK_DIVIDE_128                                       7
+#define PWM2_CLOCK_DIVIDE_256                                       8
+#define PWM2_CLOCK_DIVIDE_512                                       9
+#define PWM2_CLOCK_DIVIDE_1024                                      10
+#define PWM2_CLOCK_DIVIDE_2048                                      11
+#define PWM2_CLOCK_DIVIDE_4096                                      12
+#define PWM2_CLOCK_DIVIDE_8192                                      13
+#define PWM2_CLOCK_DIVIDE_16384                                     14
+#define PWM2_CLOCK_DIVIDE_32768                                     15
+#define PWM2_INTERRUPT_STATUS                                       3:3
+#define PWM2_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM2_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM2_INTERRUPT_CONTROL                                      2:2
+#define PWM2_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM2_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM2_CONTROL                                                0:0
+#define PWM2_CONTROL_DISABLE                                        0
+#define PWM2_CONTROL_ENABLE                                         1
+
+/* I2C Byte Count */
+#define I2C_BYTE_COUNT                                              0x010040
+#define I2C_BYTE_COUNT_COUNT                                        3:0
+
+/* I2C Control */
+#define I2C_CONTROL                                                 0x010041
+#define I2C_CONTROL_REPEAT                                          6:6
+#define I2C_CONTROL_REPEAT_DISABLE                                  0
+#define I2C_CONTROL_REPEAT_ENABLE                                   1
+#define I2C_CONTROL_INTERRUPT                                       5:5
+#define I2C_CONTROL_INTERRUPT_NOT_ACKNOWLEDGE                       0
+#define I2C_CONTROL_INTERRUPT_ACKNOWLEDGE                           1
+#define I2C_CONTROL_INTERRUPT_CONTROL                               4:4
+#define I2C_CONTROL_INTERRUPT_CONTROL_ENABLE                        0
+#define I2C_CONTROL_INTERRUPT_CONTROL_DISABLE                       1
+#define I2C_CONTROL_STATUS                                          2:2
+#define I2C_CONTROL_STATUS_STOP                                     0
+#define I2C_CONTROL_STATUS_START                                    1
+#define I2C_CONTROL_MODE                                            1:1
+#define I2C_CONTROL_MODE_STANDARD                                   0
+#define I2C_CONTROL_MODE_FAST                                       1
+#define I2C_CONTROL_CONTROL                                         0:0
+#define I2C_CONTROL_CONTROL_DISABLE                                 0
+#define I2C_CONTROL_CONTROL_ENABLE                                  1
+
+/* I2C Status & Reset */
+#define I2C_STATUS                                                  0x010042
+#define I2C_STATUS_TRANSFER                                         3:3
+#define I2C_STATUS_TRANSFER_IN_PROGRESS                             0
+#define I2C_STATUS_TRANSFER_COMPLETED                               1
+#define I2C_STATUS_ERROR                                            2:2
+#define I2C_STATUS_ERROR_NORMAL                                     0
+#define I2C_STATUS_ERROR_BUS_ERROR                                  1
+#define I2C_STATUS_ERROR_CLEAR                                      0
+#define I2C_STATUS_ACKNOWLEDGE                                      1:1
+#define I2C_STATUS_ACKNOWLEDGE_NOT_RECEIVED                         0
+#define I2C_STATUS_ACKNOWLEDGE_RECEIVED                             1
+#define I2C_STATUS_BUSY                                             0:0
+#define I2C_STATUS_BUSY_IDLE                                        0
+#define I2C_STATUS_BUSY_BUSY                                        1
+
+/* I2C Slave Address */
+#define I2C_SLAVE_ADDRESS                                           0x010043
+#define I2C_SLAVE_ADDRESS_ADDRESS                                   7:1
+#define I2C_SLAVE_ADDRESS_ACCESS                                    0:0
+#define I2C_SLAVE_ADDRESS_ACCESS_WRITE                              0
+#define I2C_SLAVE_ADDRESS_ACCESS_READ                               1
+
+/* I2C Data */
+#define I2C_DATA_0                                                  0x010044
+#define I2C_DATA_1                                                  0x010045
+#define I2C_DATA_2                                                  0x010046
+#define I2C_DATA_3                                                  0x010047
+#define I2C_DATA_4                                                  0x010048
+#define I2C_DATA_5                                                  0x010049
+#define I2C_DATA_6                                                  0x01004A
+#define I2C_DATA_7                                                  0x01004B
+#define I2C_DATA_8                                                  0x01004C
+#define I2C_DATA_9                                                  0x01004D
+#define I2C_DATA_10                                                 0x01004E
+#define I2C_DATA_11                                                 0x01004F
+#define I2C_DATA_12                                                 0x010050
+#define I2C_DATA_13                                                 0x010051
+#define I2C_DATA_14                                                 0x010052
+#define I2C_DATA_15                                                 0x010053
+
+
+/*****************************************************************************\
+ *                                    SSP                                    *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                                UART / IRDA                                *
+\*****************************************************************************/
+/*****************************************************************************\
+ *                                                                           *
+ *     REGISTER DESCRIPTION                                                  *
+ *     |========|======|================================|==============|     *
+ *     | Offset | DLAB | Register Name                  |   Comment    |     *
+ *     |========|======|================================|==============|     *
+ *     |  0x00  |  0   | RX Buffer Register             |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x00  |  0   | TX Holding Register            |      WO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x04  |  0   | Interrupt Enable Register      |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  X   | Interrupt Identification Reg.  |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  X   | FIFO Control Register          |      WO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x0C  |  X   | Line Control Register          |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x10  |  X   | Modem Control Register         |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x14  |  X   | Line Status Register           |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x18  |  X   | Modem Status Register          | Partially RO |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x1C  |  X   | Scratch Register               |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x00  |  1   | Divisor Latch (LSB)            |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x04  |  1   | Divisor Latch (MSB)            |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  1   | Enhanced Feature Register      |              |     *
+ *     |--------|------|--------------------------------|              |     *
+ *     |  0x0C  |  1   | XON1 Register                  |      R/W     |     *
+ *     |--------|------|--------------------------------|     Only     |     *
+ *     |  0x10  |  1   | XON2 Register                  |    present   |     *
+ *     |--------|------|--------------------------------|     when     |     *
+ *     |  0x14  |  1   | XOFF1 Register                 |  LCR = 0xBF  |     *
+ *     |--------|------|--------------------------------|              |     *
+ *     |  0x18  |  1   | XOFF2 Register                 |              |     *
+ *     |========|======|================================|==============|     *
+ *                                                                           *
+ *     NOTES:                                                                *
+ *       X   = Don't Care                                                    *
+ *       RO  = Read Only                                                     *
+ *       WO  = Write Only                                                    *
+ *       R/W = Read/Write                                                    *
+ *                                                                           *
+\*****************************************************************************/
+
+
+/*****************************************************************************\
+ * UART 0                                                                    *
+\*****************************************************************************/
+
+/* UART 0 when DLAB = 0 (normal mode), LCR != 0xBF */
+
+#define UART_0_RECEIVE_BUFFER                           0x030000
+#define	UART_0_RECEIVE_BUFFER_DATA						7:0
+
+#define UART_0_TRANSMIT									0x030000
+#define UART_0_TRANSMIT_DATA							7:0
+
+#define UART_0_INTERRUPT                                0x030004
+#define UART_0_INTERRUPT_CTS                            7:7
+#define UART_0_INTERRUPT_CTS_DISABLE                    0
+#define UART_0_INTERRUPT_CTS_ENABLE                     1
+#define UART_0_INTERRUPT_RTS                            6:6
+#define UART_0_INTERRUPT_RTS_DISABLE                    0
+#define UART_0_INTERRUPT_RTS_ENABLE                     1
+#define UART_0_INTERRUPT_XOFF                           5:5
+#define UART_0_INTERRUPT_XOFF_DISABLE                   0
+#define UART_0_INTERRUPT_XOFF_ENABLE                    1
+#define UART_0_INTERRUPT_MODEM_STATUS                   3:3
+#define UART_0_INTERRUPT_MODEM_STATUS_DISABLE           0
+#define UART_0_INTERRUPT_MODEM_STATUS_ENABLE            1
+#define UART_0_INTERRUPT_LINE_STATUS                    2:2
+#define UART_0_INTERRUPT_LINE_STATUS_DISABLE            0
+#define UART_0_INTERRUPT_LINE_STATUS_ENABLE             1
+#define UART_0_INTERRUPT_TX_EMPTY                       1:1
+#define UART_0_INTERRUPT_TX_EMPTY_DISABLE               0
+#define UART_0_INTERRUPT_TX_EMPTY_ENABLE                1
+#define UART_0_INTERRUPT_RX_BUFFER                      0:0
+#define UART_0_INTERRUPT_RX_BUFFER_DISABLE              0
+#define UART_0_INTERRUPT_RX_BUFFER_ENABLE               1
+
+
+/* UART 0 when DLAB = 1 (configuration mode), LCR != 0xBF */
+
+#define	UART_0_DIVISOR_LATCH_LSB						0x030000
+#define	UART_0_DIVISOR_LATCH_LSB_VALUE					7:0
+
+#define	UART_0_DIVISOR_LATCH_MSB						0x030004
+#define	UART_0_DIVISOR_LATCH_MSB_VALUE					7:0
+
+
+/* UART 0 when DLAB = X (don't care), LCR != 0xBF */
+
+#define UART_0_STATUS                                   0x030008
+#define UART_0_STATUS_FIFO                              7:6
+#define UART_0_STATUS_FIFO_DISABLE                      0
+#define UART_0_STATUS_FIFO_ENABLE                       3
+#define UART_0_STATUS_INTERRUPT                         5:1
+#define UART_0_STATUS_INTERRUPT_MODEM_STATUS_CHANGE     0
+#define UART_0_STATUS_INTERRUPT_TX_EMPTY                1
+#define UART_0_STATUS_INTERRUPT_RX_DATA_RECEIVED        2
+#define UART_0_STATUS_INTERRUPT_LINE_STATUS             3
+#define UART_0_STATUS_INTERRUPT_RX_CHAR_TIMEOUT         6
+#define UART_0_STATUS_INTERRUPT_XOFF_RECEIVED           8
+#define UART_0_STATUS_INTERRUPT_CTS_RTS                 16
+#define UART_0_STATUS_INTERRUPT_PENDING                 1:1
+#define UART_0_STATUS_INTERRUPT_PENDING_YES             0
+#define UART_0_STATUS_INTERRUPT_PENDING_NO              1
+
+#define UART_0_FIFO                                     0x030008
+#define UART_0_FIFO_RX_TRIGGER                          7:6
+#define UART_0_FIFO_RX_TRIGGER_DEFAULT                  0
+#define UART_0_FIFO_RX_TRIGGER_QUARTER                  1
+#define UART_0_FIFO_RX_TRIGGER_HALF                     2
+#define UART_0_FIFO_RX_TRIGGER_MINUS_2                  3
+#define UART_0_FIFO_TX_TRIGGER                          5:4
+#define UART_0_FIFO_TX_TRIGGER_DEFAULT                  0
+#define UART_0_FIFO_TX_TRIGGER_QUARTER                  1
+#define UART_0_FIFO_TX_TRIGGER_HALF                     2
+#define UART_0_FIFO_TX_TRIGGER_MINUS_2                  3
+#define UART_0_FIFO_DMA_MODE                            3:3
+#define UART_0_FIFO_DMA_MODE_ZERO                       0
+#define UART_0_FIFO_DMA_MODE_ONE                        1
+#define UART_0_FIFO_TX_CLEAR                            2:2
+#define UART_0_FIFO_TX_CLEAR_NO                         0
+#define UART_0_FIFO_TX_CLEAR_CLEAR                      1
+#define UART_0_FIFO_RX_CLEAR                            1:1
+#define UART_0_FIFO_RX_CLEAR_NO                         0
+#define UART_0_FIFO_RX_CLEAR_CLEAR                      1
+#define UART_0_FIFO_ENABLE                              0:0
+#define UART_0_FIFO_ENABLE_DISABLE                      0
+#define UART_0_FIFO_ENABLE_ENABLE                       1
+
+#define UART_0_LINE_CTRL                                0x03000C
+#define	UART_0_LINE_CTRL_ENHANCED						7:0
+#define	UART_0_LINE_CTRL_ENHANCED_ENABLE				0xBF
+#define UART_0_LINE_CTRL_DLAB                           7:7
+#define UART_0_LINE_CTRL_DLAB_RESET                     0
+#define UART_0_LINE_CTRL_DLAB_SET                       1
+#define UART_0_LINE_CTRL_LINE_BREAK                     6:6
+#define UART_0_LINE_CTRL_LINE_BREAK_RESET               0
+#define UART_0_LINE_CTRL_LINE_BREAK_SET                 1
+#define UART_0_LINE_CTRL_PARITY                         5:3
+#define UART_0_LINE_CTRL_PARITY_DISABLE                 0
+#define UART_0_LINE_CTRL_PARITY_ODD                     1
+#define UART_0_LINE_CTRL_PARITY_EVEN                    3
+#define UART_0_LINE_CTRL_PARITY_MARK                    5
+#define UART_0_LINE_CTRL_PARITY_SPACE                   7
+#define UART_0_LINE_CTRL_STOPBITS                       2:2
+#define UART_0_LINE_CTRL_STOPBITS_ONE                   0
+#define UART_0_LINE_CTRL_STOPBITS_TWO                   1
+#define UART_0_LINE_CTRL_CHARSIZE                       1:0
+#define UART_0_LINE_CTRL_CHARSIZE_5                     0
+#define UART_0_LINE_CTRL_CHARSIZE_6                     1
+#define UART_0_LINE_CTRL_CHARSIZE_7                     2
+#define UART_0_LINE_CTRL_CHARSIZE_8                     3
+
+#define UART_0_MODEM_CTRL                               0x030010
+#define UART_0_MODEM_CTRL_XOFF_STATUS                   7:7
+#define UART_0_MODEM_CTRL_XOFF_STATUS_XON               0
+#define UART_0_MODEM_CTRL_XOFF_STATUS_XOFF              1
+#define UART_0_MODEM_CTRL_INFRARED                      6:6
+#define UART_0_MODEM_CTRL_INFRARED_DISABLE              0
+#define UART_0_MODEM_CTRL_INFRARED_ENABLE               1
+#define UART_0_MODEM_CTRL_LOOPBACK                      4:4
+#define UART_0_MODEM_CTRL_LOOPBACK_DISABLE              0
+#define UART_0_MODEM_CTRL_LOOPBACK_ENABLE               1
+#define UART_0_MODEM_CTRL_OUT2                          3:3
+#define UART_0_MODEM_CTRL_OUT2_RESET                    0
+#define UART_0_MODEM_CTRL_OUT2_SET                      1
+#define UART_0_MODEM_CTRL_OUT1                          2:2
+#define UART_0_MODEM_CTRL_OUT1_RESET                    0
+#define UART_0_MODEM_CTRL_OUT1_SET                      1
+#define UART_0_MODEM_CTRL_RTS                           1:1
+#define UART_0_MODEM_CTRL_RTS_RESET                     0
+#define UART_0_MODEM_CTRL_RTS_SET                       1
+#define UART_0_MODEM_CTRL_DTR                           0:0
+#define UART_0_MODEM_CTRL_DTR_RESET                     0
+#define UART_0_MODEM_CTRL_DTR_SET                       1
+
+#define UART_0_LINE_STATUS                              0x030014
+#define UART_0_LINE_STATUS_RX_FIFO                      7:7
+#define UART_0_LINE_STATUS_RX_FIFO_NO_ERROR             0
+#define UART_0_LINE_STATUS_RX_FIFO_ERROR                1
+#define UART_0_LINE_STATUS_TRANSMITTER                  6:6
+#define UART_0_LINE_STATUS_TRANSMITTER_NOT_EMPTY        0
+#define UART_0_LINE_STATUS_TRANSMITTER_EMPTY            1
+#define UART_0_LINE_STATUS_TX_HOLDING                   5:5
+#define UART_0_LINE_STATUS_TX_HOLDING_NOT_EMPTY         0
+#define UART_0_LINE_STATUS_TX_HOLDING_EMPTY             1
+#define UART_0_LINE_STATUS_BREAK                        4:4
+#define UART_0_LINE_STATUS_BREAK_NO_BREAK               0
+#define UART_0_LINE_STATUS_BREAK_BREAK                  1
+#define UART_0_LINE_STATUS_FRAME                        3:3
+#define UART_0_LINE_STATUS_FRAME_NO_ERROR               0
+#define UART_0_LINE_STATUS_FRAME_ERROR                  1
+#define UART_0_LINE_STATUS_PARITY                       2:2
+#define UART_0_LINE_STATUS_PARITY_NO_ERROR              0
+#define UART_0_LINE_STATUS_PARITY_ERROR                 1
+#define UART_0_LINE_STATUS_OVERRUN                      1:1
+#define UART_0_LINE_STATUS_OVERRUN_NO_ERROR             0
+#define UART_0_LINE_STATUS_OVERRUN_ERROR                1
+#define UART_0_LINE_STATUS_DATA                         0:0
+#define UART_0_LINE_STATUS_DATA_NOT_READY               0
+#define UART_0_LINE_STATUS_DATA_READY                   1
+
+#define UART_0_MODEM_STATUS                             0x030018
+#define UART_0_MODEM_STATUS_DCD                         7:7
+#define UART_0_MODEM_STATUS_DCD_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_DCD_DETECTED                1
+#define UART_0_MODEM_STATUS_RI                          6:6
+#define UART_0_MODEM_STATUS_RI_NOT_DETECTED             0
+#define UART_0_MODEM_STATUS_RI_DETECTED                 1
+#define UART_0_MODEM_STATUS_DSR                         5:5
+#define UART_0_MODEM_STATUS_DSR_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_DSR_DETECTED                1
+#define UART_0_MODEM_STATUS_CTS                         4:4
+#define UART_0_MODEM_STATUS_CTS_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_CTS_DETECTED                1
+#define UART_0_MODEM_STATUS_DELTA_DCD                   3:3
+#define UART_0_MODEM_STATUS_DELTA_DCD_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_DCD_CHANGE            1
+#define UART_0_MODEM_STATUS_TRAILING_RI                 2:2
+#define UART_0_MODEM_STATUS_TRAILING_RI_NO_CHANGE       0
+#define UART_0_MODEM_STATUS_TRAILING_RI_CHANGE          1
+#define UART_0_MODEM_STATUS_DELTA_DSR                   1:1
+#define UART_0_MODEM_STATUS_DELTA_DSR_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_DSR_CHANGE            1
+#define UART_0_MODEM_STATUS_DELTA_CTS                   0:0
+#define UART_0_MODEM_STATUS_DELTA_CTS_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_CTS_CHANGE            1
+
+#define UART_0_SCRATCH                                  0x03001C
+#define	UART_0_SCRATCH_DATA								7:0
+
+
+/* UART 0 when LCR = 0xBF (DLAB = 1) (configuration mode) */
+
+#define	UART_0_FEATURE									0x030008
+#define	UART_0_FEATURE_AUTO_CTS							7:7
+#define	UART_0_FEATURE_AUTO_CTS_DISABLE					0
+#define	UART_0_FEATURE_AUTO_CTS_ENABLE					1
+#define	UART_0_FEATURE_AUTO_RTS							6:6
+#define	UART_0_FEATURE_AUTO_RTS_DISABLE					0
+#define	UART_0_FEATURE_AUTO_RTS_ENABLE					1
+#define	UART_0_FEATURE_ENHANCED							4:4
+#define	UART_0_FEATURE_ENHANCED_DISABLE					0
+#define	UART_0_FEATURE_ENHANCED_ENABLE					1
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1				3:3
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2				2:2
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2_ENABLE		1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1				1:1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2				0:0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2_ENABLE		1
+
+#define	UART_0_XON1_CHAR								0x030010
+#define	UART_0_XON1_CHAR_DATA							7:0
+
+#define	UART_0_XON2_CHAR								0x030014
+#define	UART_0_XON2_CHAR_DATA							7:0
+
+#define	UART_0_XOFF1_CHAR								0x030018
+#define	UART_0_XOFF1_CHAR_DATA							7:0
+
+#define	UART_0_XOFF2_CHAR								0x03001C
+#define	UART_0_XOFF2_CHAR_DATA							7:0
+
+
+/*****************************************************************************\
+ * UART 1                                                                    *
+\*****************************************************************************/
+
+/* UART 1 when DLAB = 0 (normal mode), LCR != 0xBF */
+
+#define UART_1_RECEIVE_BUFFER                           0x030020
+#define	UART_1_RECEIVE_BUFFER_DATA						7:0
+
+#define UART_1_TRANSMIT									0x030020
+#define UART_1_TRANSMIT_DATA							7:0
+
+#define UART_1_INTERRUPT                                0x030024
+#define UART_1_INTERRUPT_CTS                            7:7
+#define UART_1_INTERRUPT_CTS_DISABLE                    0
+#define UART_1_INTERRUPT_CTS_ENABLE                     1
+#define UART_1_INTERRUPT_RTS                            6:6
+#define UART_1_INTERRUPT_RTS_DISABLE                    0
+#define UART_1_INTERRUPT_RTS_ENABLE                     1
+#define UART_1_INTERRUPT_XOFF                           5:5
+#define UART_1_INTERRUPT_XOFF_DISABLE                   0
+#define UART_1_INTERRUPT_XOFF_ENABLE                    1
+#define UART_1_INTERRUPT_MODEM_STATUS                   3:3
+#define UART_1_INTERRUPT_MODEM_STATUS_DISABLE           0
+#define UART_1_INTERRUPT_MODEM_STATUS_ENABLE            1
+#define UART_1_INTERRUPT_LINE_STATUS                    2:2
+#define UART_1_INTERRUPT_LINE_STATUS_DISABLE            0
+#define UART_1_INTERRUPT_LINE_STATUS_ENABLE             1
+#define UART_1_INTERRUPT_TX_EMPTY                       1:1
+#define UART_1_INTERRUPT_TX_EMPTY_DISABLE               0
+#define UART_1_INTERRUPT_TX_EMPTY_ENABLE                1
+#define UART_1_INTERRUPT_RX_BUFFER                      0:0
+#define UART_1_INTERRUPT_RX_BUFFER_DISABLE              0
+#define UART_1_INTERRUPT_RX_BUFFER_ENABLE               1
+
+
+/* UART 0 when DLAB = 1 (configuration mode), LCR != 0xBF */
+
+#define	UART_1_DIVISOR_LATCH_LSB						0x030020
+#define	UART_1_DIVISOR_LATCH_LSB_VALUE					7:0
+
+#define	UART_1_DIVISOR_LATCH_MSB						0x030024
+#define	UART_1_DIVISOR_LATCH_MSB_VALUE					7:0
+
+
+/* UART 1 when DLAB = X (don't care), LCR != 0xBF */
+
+#define UART_1_STATUS                                   0x030028
+#define UART_1_STATUS_FIFO                              7:6
+#define UART_1_STATUS_FIFO_DISABLE                      0
+#define UART_1_STATUS_FIFO_ENABLE                       3
+#define UART_1_STATUS_INTERRUPT                         5:1
+#define UART_1_STATUS_INTERRUPT_MODEM_STATUS_CHANGE     0
+#define UART_1_STATUS_INTERRUPT_TX_EMPTY                1
+#define UART_1_STATUS_INTERRUPT_RX_DATA_RECEIVED        2
+#define UART_1_STATUS_INTERRUPT_LINE_STATUS             3
+#define UART_1_STATUS_INTERRUPT_RX_CHAR_TIMEOUT         6
+#define UART_1_STATUS_INTERRUPT_XOFF_RECEIVED           8
+#define UART_1_STATUS_INTERRUPT_CTS_RTS                 16
+#define UART_1_STATUS_INTERRUPT_PENDING                 1:1
+#define UART_1_STATUS_INTERRUPT_PENDING_YES             0
+#define UART_1_STATUS_INTERRUPT_PENDING_NO              1
+
+#define UART_1_FIFO                                     0x030028
+#define UART_1_FIFO_RX_TRIGGER                          7:6
+#define UART_1_FIFO_RX_TRIGGER_DEFAULT                  0
+#define UART_1_FIFO_RX_TRIGGER_QUARTER                  1
+#define UART_1_FIFO_RX_TRIGGER_HALF                     2
+#define UART_1_FIFO_RX_TRIGGER_MINUS_2                  3
+#define UART_1_FIFO_TX_TRIGGER                          5:4
+#define UART_1_FIFO_TX_TRIGGER_DEFAULT                  0
+#define UART_1_FIFO_TX_TRIGGER_QUARTER                  1
+#define UART_1_FIFO_TX_TRIGGER_HALF                     2
+#define UART_1_FIFO_TX_TRIGGER_MINUS_2                  3
+#define UART_1_FIFO_DMA_MODE                            3:3
+#define UART_1_FIFO_DMA_MODE_ZERO                       0
+#define UART_1_FIFO_DMA_MODE_ONE                        1
+#define UART_1_FIFO_TX_CLEAR                            2:2
+#define UART_1_FIFO_TX_CLEAR_NO                         0
+#define UART_1_FIFO_TX_CLEAR_CLEAR                      1
+#define UART_1_FIFO_RX_CLEAR                            1:1
+#define UART_1_FIFO_RX_CLEAR_NO                         0
+#define UART_1_FIFO_RX_CLEAR_CLEAR                      1
+#define UART_1_FIFO_ENABLE                              0:0
+#define UART_1_FIFO_ENABLE_DISABLE                      0
+#define UART_1_FIFO_ENABLE_ENABLE                       1
+
+#define UART_1_LINE_CTRL                                0x03002C
+#define	UART_1_LINE_CTRL_ENHANCED						7:0
+#define	UART_1_LINE_CTRL_ENHANCED_ENABLE				0xBF
+#define UART_1_LINE_CTRL_DLAB                           7:7
+#define UART_1_LINE_CTRL_DLAB_RESET                     0
+#define UART_1_LINE_CTRL_DLAB_SET                       1
+#define UART_1_LINE_CTRL_LINE_BREAK                     6:6
+#define UART_1_LINE_CTRL_LINE_BREAK_RESET               0
+#define UART_1_LINE_CTRL_LINE_BREAK_SET                 1
+#define UART_1_LINE_CTRL_PARITY                         5:3
+#define UART_1_LINE_CTRL_PARITY_DISABLE                 0
+#define UART_1_LINE_CTRL_PARITY_ODD                     1
+#define UART_1_LINE_CTRL_PARITY_EVEN                    3
+#define UART_1_LINE_CTRL_PARITY_MARK                    5
+#define UART_1_LINE_CTRL_PARITY_SPACE                   7
+#define UART_1_LINE_CTRL_STOPBITS                       2:2
+#define UART_1_LINE_CTRL_STOPBITS_ONE                   0
+#define UART_1_LINE_CTRL_STOPBITS_TWO                   1
+#define UART_1_LINE_CTRL_CHARSIZE                       1:0
+#define UART_1_LINE_CTRL_CHARSIZE_5                     0
+#define UART_1_LINE_CTRL_CHARSIZE_6                     1
+#define UART_1_LINE_CTRL_CHARSIZE_7                     2
+#define UART_1_LINE_CTRL_CHARSIZE_8                     3
+
+#define UART_1_MODEM_CTRL                               0x030030
+#define UART_1_MODEM_CTRL_XOFF_STATUS                   7:7
+#define UART_1_MODEM_CTRL_XOFF_STATUS_XON               0
+#define UART_1_MODEM_CTRL_XOFF_STATUS_XOFF              1
+#define UART_1_MODEM_CTRL_INFRARED                      6:6
+#define UART_1_MODEM_CTRL_INFRARED_DISABLE              0
+#define UART_1_MODEM_CTRL_INFRARED_ENABLE               1
+#define UART_1_MODEM_CTRL_LOOPBACK                      4:4
+#define UART_1_MODEM_CTRL_LOOPBACK_DISABLE              0
+#define UART_1_MODEM_CTRL_LOOPBACK_ENABLE               1
+#define UART_1_MODEM_CTRL_OUT2                          3:3
+#define UART_1_MODEM_CTRL_OUT2_RESET                    0
+#define UART_1_MODEM_CTRL_OUT2_SET                      1
+#define UART_1_MODEM_CTRL_OUT1                          2:2
+#define UART_1_MODEM_CTRL_OUT1_RESET                    0
+#define UART_1_MODEM_CTRL_OUT1_SET                      1
+#define UART_1_MODEM_CTRL_RTS                           1:1
+#define UART_1_MODEM_CTRL_RTS_RESET                     0
+#define UART_1_MODEM_CTRL_RTS_SET                       1
+#define UART_1_MODEM_CTRL_DTR                           0:0
+#define UART_1_MODEM_CTRL_DTR_RESET                     0
+#define UART_1_MODEM_CTRL_DTR_SET                       1
+
+#define UART_1_LINE_STATUS                              0x030034
+#define UART_1_LINE_STATUS_RX_FIFO                      7:7
+#define UART_1_LINE_STATUS_RX_FIFO_NO_ERROR             0
+#define UART_1_LINE_STATUS_RX_FIFO_ERROR                1
+#define UART_1_LINE_STATUS_TRANSMITTER                  6:6
+#define UART_1_LINE_STATUS_TRANSMITTER_NOT_EMPTY        0
+#define UART_1_LINE_STATUS_TRANSMITTER_EMPTY            1
+#define UART_1_LINE_STATUS_TX_HOLDING                   5:5
+#define UART_1_LINE_STATUS_TX_HOLDING_NOT_EMPTY         0
+#define UART_1_LINE_STATUS_TX_HOLDING_EMPTY             1
+#define UART_1_LINE_STATUS_BREAK                        4:4
+#define UART_1_LINE_STATUS_BREAK_NO_BREAK               0
+#define UART_1_LINE_STATUS_BREAK_BREAK                  1
+#define UART_1_LINE_STATUS_FRAME                        3:3
+#define UART_1_LINE_STATUS_FRAME_NO_ERROR               0
+#define UART_1_LINE_STATUS_FRAME_ERROR                  1
+#define UART_1_LINE_STATUS_PARITY                       2:2
+#define UART_1_LINE_STATUS_PARITY_NO_ERROR              0
+#define UART_1_LINE_STATUS_PARITY_ERROR                 1
+#define UART_1_LINE_STATUS_OVERRUN                      1:1
+#define UART_1_LINE_STATUS_OVERRUN_NO_ERROR             0
+#define UART_1_LINE_STATUS_OVERRUN_ERROR                1
+#define UART_1_LINE_STATUS_DATA                         0:0
+#define UART_1_LINE_STATUS_DATA_NOT_READY               0
+#define UART_1_LINE_STATUS_DATA_READY                   1
+
+#define UART_1_MODEM_STATUS                             0x030038
+#define UART_1_MODEM_STATUS_DCD                         7:7
+#define UART_1_MODEM_STATUS_DCD_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_DCD_DETECTED                1
+#define UART_1_MODEM_STATUS_RI                          6:6
+#define UART_1_MODEM_STATUS_RI_NOT_DETECTED             0
+#define UART_1_MODEM_STATUS_RI_DETECTED                 1
+#define UART_1_MODEM_STATUS_DSR                         5:5
+#define UART_1_MODEM_STATUS_DSR_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_DSR_DETECTED                1
+#define UART_1_MODEM_STATUS_CTS                         4:4
+#define UART_1_MODEM_STATUS_CTS_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_CTS_DETECTED                1
+#define UART_1_MODEM_STATUS_DELTA_DCD                   3:3
+#define UART_1_MODEM_STATUS_DELTA_DCD_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_DCD_CHANGE            1
+#define UART_1_MODEM_STATUS_TRAILING_RI                 2:2
+#define UART_1_MODEM_STATUS_TRAILING_RI_NO_CHANGE       0
+#define UART_1_MODEM_STATUS_TRAILING_RI_CHANGE          1
+#define UART_1_MODEM_STATUS_DELTA_DSR                   1:1
+#define UART_1_MODEM_STATUS_DELTA_DSR_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_DSR_CHANGE            1
+#define UART_1_MODEM_STATUS_DELTA_CTS                   0:0
+#define UART_1_MODEM_STATUS_DELTA_CTS_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_CTS_CHANGE            1
+
+#define UART_1_SCRATCH                                  0x03003C
+#define	UART_1_SCRATCH_DATA								7:0
+
+
+/* UART 1 when LCR = 0xBF (DLAB = 1) (configuration mode) */
+
+#define	UART_1_FEATURE									0x030028
+#define	UART_1_FEATURE_AUTO_CTS							7:7
+#define	UART_1_FEATURE_AUTO_CTS_DISABLE					0
+#define	UART_1_FEATURE_AUTO_CTS_ENABLE					1
+#define	UART_1_FEATURE_AUTO_RTS							6:6
+#define	UART_1_FEATURE_AUTO_RTS_DISABLE					0
+#define	UART_1_FEATURE_AUTO_RTS_ENABLE					1
+#define	UART_1_FEATURE_ENHANCED							4:4
+#define	UART_1_FEATURE_ENHANCED_DISABLE					0
+#define	UART_1_FEATURE_ENHANCED_ENABLE					1
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1				3:3
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2				2:2
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2_ENABLE		1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1				1:1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2				0:0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2_ENABLE		1
+
+#define	UART_1_XON1_CHAR								0x030030
+#define	UART_1_XON1_CHAR_DATA							7:0
+
+#define	UART_1_XON2_CHAR								0x030034
+#define	UART_1_XON2_CHAR_DATA							7:0
+
+#define	UART_1_XOFF1_CHAR								0x030038
+#define	UART_1_XOFF1_CHAR_DATA							7:0
+
+#define	UART_1_XOFF2_CHAR								0x03003C
+#define	UART_1_XOFF2_CHAR_DATA							7:0
+
+
+/*****************************************************************************\
+ *                                 USB HOST                                  *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                                USB SLAVE                                  *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                            DISPLAY CONTROLLER                             *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                                 ZV PORT                                   *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                                AC97 / I2S                                 *
+\*****************************************************************************/
+
+/* AC97 TX Slot 0: TAG */
+#define AC97_TX_SLOT0                                               0x0A0100
+#define AC97_TX_SLOT0_VALID_FRAME_TAG                               15:15
+#define AC97_TX_SLOT0_VALID_FRAME_TAG_IGNORE                        0
+#define AC97_TX_SLOT0_VALID_FRAME_TAG_INTERPRET                     1
+#define AC97_TX_SLOT0_VALID_S1                                      14:14
+#define AC97_TX_SLOT0_VALID_S1_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S1_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S2                                      13:13
+#define AC97_TX_SLOT0_VALID_S2_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S2_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S3                                      12:12
+#define AC97_TX_SLOT0_VALID_S3_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S3_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S4                                      11:11
+#define AC97_TX_SLOT0_VALID_S4_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S4_DATA                                 1
+
+/* AC97 TX Slot 1: Command Address Port */
+#define AC97_TX_SLOT1                                               0x0A0104
+#define AC97_TX_SLOT1_READ_WRITE                                    19:19
+#define AC97_TX_SLOT1_READ_WRITE_WRITE                              0
+#define AC97_TX_SLOT1_READ_WRITE_READ                               1
+#define AC97_TX_SLOT1_CONTROL_REGISTER_INDEX                        18:12
+
+/* AC97 TX Slot 2: Command Address Port */
+#define AC97_TX_SLOT2                                               0x0A0108
+#define AC97_TX_SLOT2_DATA                                          19:4
+
+/* AC97 TX Slot 3: PCM Playback Left Channel */
+#define AC97_TX_SLOT3                                               0x0A010C
+#define AC97_TX_SLOT3_DATA                                          19:0
+
+/* AC97 TX Slot 4: PCM Playback Right Channel */
+#define AC97_TX_SLOT4                                               0x0A0110
+#define AC97_TX_SLOT4_DATA                                          19:0
+
+/* AC97 RX Slot 0: TAG */
+#define AC97_RX_SLOT0                                               0x0A0140
+#define AC97_RX_SLOT0_CODEC_READY_FLAG                              15:15
+#define AC97_RX_SLOT0_CODEC_READY_FLAG_IGNORE                       0
+#define AC97_RX_SLOT0_CODEC_READY_FLAG_READY                        1
+#define AC97_RX_SLOT0_VALID_S1                                      14:14
+#define AC97_RX_SLOT0_VALID_S1_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S1_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S2                                      13:13
+#define AC97_RX_SLOT0_VALID_S2_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S2_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S3                                      12:12
+#define AC97_RX_SLOT0_VALID_S3_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S3_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S4                                      11:11
+#define AC97_RX_SLOT0_VALID_S4_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S4_DATA                                 1
+
+/* AC97 RX Slot 1: Status Address Port */
+#define AC97_RX_SLOT1                                               0x0A0144
+#define AC97_RX_SLOT1_CONTROL_REGISTER_INDEX                        18:12
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3                             11:11
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3_SEND                        0
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3_DO_NOT_SEND                 1
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4                             10:10
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4_SEND                        0
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4_DO_NOT_SEND                 1
+
+/* AC97 RX Slot 2: Status Address Port */
+#define AC97_RX_SLOT2                                               0x0A0148
+#define AC97_RX_SLOT2_DATA                                          19:4
+
+/* AC97 RX Slot 3: PCM Record Left Channel */
+#define AC97_RX_SLOT3                                               0x0A014C
+#define AC97_RX_SLOT3_DATA                                          19:0
+
+/* AC97 RX Slot 4: PCM Record Right Channel */
+#define AC97_RX_SLOT4                                               0x0A0150
+#define AC97_RX_SLOT4_DATA                                          19:0
+
+/* AC97 Control & Status */
+#define AC97_CONTROL_STATUS                                         0x0A0180
+#define AC97_CONTROL_STATUS_DATA_DROPPED_COUNT                      15:10
+#define AC97_CONTROL_STATUS_SYNC_CONTROL                            9:9
+#define AC97_CONTROL_STATUS_SYNC_CONTROL_ENABLE                     0
+#define AC97_CONTROL_STATUS_SYNC_CONTROL_STOP                       1
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL                           8:8
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL_NOT_RUNNING               0
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL_RUNNING                   1
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST                          7:7
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST_DISABLE                  0
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST_ENABLE                   1
+#define AC97_CONTROL_STATUS_STATUS                                  5:4
+#define AC97_CONTROL_STATUS_STATUS_OFF                              0
+#define AC97_CONTROL_STATUS_STATUS_RESET                            1
+#define AC97_CONTROL_STATUS_STATUS_WAITING                          2
+#define AC97_CONTROL_STATUS_STATUS_ACTIVE                           3
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT                        3:3
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT_DISABLED               0
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT_ENABLED                1
+#define AC97_CONTROL_STATUS_WARM_RESET                              2:2
+#define AC97_CONTROL_STATUS_WARM_RESET_NORMAL                       0
+#define AC97_CONTROL_STATUS_WARM_RESET_RESET                        1
+#define AC97_CONTROL_STATUS_COLD_RESET                              1:1
+#define AC97_CONTROL_STATUS_COLD_RESET_NORMAL                       0
+#define AC97_CONTROL_STATUS_COLD_RESET_RESET                        1
+#define AC97_CONTROL_STATUS_CONTROL                                 0:0
+#define AC97_CONTROL_STATUS_CONTROL_DISABLED                        0
+#define AC97_CONTROL_STATUS_CONTROL_ENABLED                         1
+
+/* I2S TX Data Left */
+#define I2S_TX_DATA_LEFT                                            0x0A0200
+#define I2S_TX_DATA_LEFT_DATA                                       15:0
+
+/* I2S TX Data Right */
+#define I2S_TX_DATA_RIGHT                                           0x0A0204
+#define I2S_TX_DATA_RIGHT_DATA                                      15:0
+
+/* I2S RX Data Left */
+#define I2S_RX_DATA_LEFT                                            0x0A0208
+#define I2S_RX_DATA_LEFT_DATA                                       15:0
+
+/* I2S RX Data Right */
+#define I2S_RX_DATA_RIGHT                                           0x0A020C
+#define I2S_RX_DATA_RIGHT_DATA                                      15:0
+
+/* I2S Control & Status */
+#define I2S_CONTROL_STATUS                                          0x0A0210
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS                           11:11
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS_NO_ERROR                  0
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS_OVERFLOW                  1
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS                          10:10
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS_NO_ERROR                 0
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS_UNDERFLOW                1
+#define I2S_CONTROL_STATUS_CONTROL                                  2:2
+#define I2S_CONTROL_STATUS_CONTROL_DISABLED                         0
+#define I2S_CONTROL_STATUS_CONTROL_ENABLED                          1
+
+/* I2S Clock Control */
+#define I2S_CLOCK_CONTROL                                           0x0A0214
+#define I2S_CLOCK_CONTROL_MODE_SELECT                               7:7
+#define I2S_CLOCK_CONTROL_MODE_SELECT_SLAVE                         0
+#define I2S_CLOCK_CONTROL_MODE_SELECT_MASTER                        1
+#define I2S_CLOCK_CONTROL_WORD_SELECT                               6:5
+#define I2S_CLOCK_CONTROL_WORD_SELECT_16BIT                         0
+#define I2S_CLOCK_CONTROL_WORD_SELECT_24BIT                         1
+#define I2S_CLOCK_CONTROL_WORD_SELECT_32BIT                         2
+#define I2S_CLOCK_CONTROL_CLOCK_DIVIDER                             4:0
+
+/*****************************************************************************\
+ *                                    8051                                   *
+\*****************************************************************************/
+
+/* Reset */
+#define U8051_RESET                                                 0x0B0000
+#define U8051_RESET_CONTROL                                         0:0
+#define U8051_RESET_CONTROL_RESET                                   0
+#define U8051_RESET_CONTROL_ENABLE                                  1
+
+/* Mode Select */
+#define U8051_MODE_SELECT                                           0x0B0004
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE                      7:6
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_NONE                 0
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_1WS                  1
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_2WS                  2
+#define U8051_MODE_SELECT_SRAM                                      5:5
+#define U8051_MODE_SELECT_SRAM_ENABLED                              0
+#define U8051_MODE_SELECT_SRAM_DISABLED                             1
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE                        4:4
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE_12BIT                  0
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE_8BIT                   1
+#define U8051_MODE_SELECT_TEST_MODE                                 3:3
+#define U8051_MODE_SELECT_TEST_MODE_NORMAL                          0
+#define U8051_MODE_SELECT_TEST_MODE_ENABLED                         1
+#define U8051_MODE_SELECT_CODEC_SELECT                              2:2
+#define U8051_MODE_SELECT_CODEC_SELECT_AC97                         0
+#define U8051_MODE_SELECT_CODEC_SELECT_I2S                          1
+#define U8051_MODE_SELECT_DIVIDER                                   1:0
+#define U8051_MODE_SELECT_DIVIDER_2                                 0
+#define U8051_MODE_SELECT_DIVIDER_3                                 1
+#define U8051_MODE_SELECT_DIVIDER_4                                 2
+#define U8051_MODE_SELECT_DIVIDER_5                                 3
+
+/* 8051 Protocol Interrupt */
+#define U8051_8051_PROTOCOL_INTERRUPT                               0x0B0008
+#define U8051_8051_PROTOCOL_INTERRUPT_TOKEN                         31:0
+
+/* CPU Protocol Interrupt */
+#define U8051_CPU_PROTOCOL_INTERRUPT                                0x0B000C
+#define U8051_CPU_PROTOCOL_INTERRUPT_TOKEN                          31:0
+
+/* SRAM Address Space */
+#define U8051_SRAM                                                  0x0C0000
+#define U8051_SRAM_SIZE                                             0x004000
+
+
+/*****************************************************************************\
+ *                                     DMA                                   *
+\*****************************************************************************/
+
+/* DMA 0 SDRAM Address */
+#define DMA0_SDRAM                                                  0x0D0000
+#define DMA0_SDRAM_MEMORY                                           27:26
+#define DMA0_SDRAM_MEMORY_LOCAL                                     0
+#define DMA0_SDRAM_MEMORY_EXTERNAL_CS0                              2
+#define DMA0_SDRAM_MEMORY_EXTERNAL_CS1                              3
+#define DMA0_SDRAM_ADDRESS                                          25:0
+
+/* DMA 0 SRAM Address */
+#define DMA0_SRAM                                                   0x0D0004
+#define DMA0_SRAM_ADDRESS                                           15:0
+
+/* DMA 0 Size & Control */
+#define DMA0_SIZE_CONTROL                                           0x0D0008
+#define DMA0_SIZE_CONTROL_ACTIVE                                    31:31
+#define DMA0_SIZE_CONTROL_ACTIVE_IDLE                               0
+#define DMA0_SIZE_CONTROL_ACTIVE_START                              1
+#define DMA0_SIZE_CONTROL_DIRECTION                                 30:30
+#define DMA0_SIZE_CONTROL_DIRECTION_WRITE_SRAM                      0
+#define DMA0_SIZE_CONTROL_DIRECTION_READ_SRAM                       1
+#define DMA0_SIZE_CONTROL_SIZE                                      15:0
+
+/* DMA 1 Source Address */
+#define DMA1_SOURCE                                                 0x0D0010
+#define DMA1_SOURCE_MEMORY                                          27:26
+#define DMA1_SOURCE_MEMORY_LOCAL                                    0
+#define DMA1_SOURCE_MEMORY_EXTERNAL_CS0                             2
+#define DMA1_SOURCE_MEMORY_EXTERNAL_CS1                             3
+#define DMA1_SOURCE_ADDRESS                                         25:0
+
+/* DMA 1 Destination Address */
+#define DMA1_DESTINATION                                            0x0D0014
+#define DMA1_DESTINATION_MEMORY                                     27:26
+#define DMA1_DESTINATION_MEMORY_LOCAL                               0
+#define DMA1_DESTINATION_MEMORY_EXTERNAL_CS0                        2
+#define DMA1_DESTINATION_MEMORY_EXTERNAL_CS1                        3
+#define DMA1_DESTINATION_ADDRESS                                    25:0
+
+/* DMA 1 Size & Control */
+#define DMA1_SIZE_CONTROL                                           0x0D0018
+#define DMA1_SIZE_CONTROL_ACTIVE                                    31:31
+#define DMA1_SIZE_CONTROL_ACTIVE_IDLE                               0
+#define DMA1_SIZE_CONTROL_ACTIVE_START                              1
+#define DMA1_SIZE_CONTROL_SIZE                                      23:0
+
+/* DMA Abort & Interrupt */
+#define DMA_ABORT_INTERRUPT                                         0x0D0020
+#define DMA_ABORT_INTERRUPT_ABORT_1                                 5:5
+#define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE                          0
+#define DMA_ABORT_INTERRUPT_ABORT_1_ABORT                           1
+#define DMA_ABORT_INTERRUPT_ABORT_0                                 4:4
+#define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE                          0
+#define DMA_ABORT_INTERRUPT_ABORT_0_ABORT                           1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1                      1:1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1_NOT_ACTIVE           0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1_ACTIVE               1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0                      0:0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0_NOT_ACTIVE           0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0_ACTIVE               1
+
+
+/*****************************************************************************\
+ *                                  2D ENGINE                                *
+\*****************************************************************************/
+
+/* 2D Source */
+#define DE_SOURCE                                                   0x100000
+#define DE_SOURCE_WRAP                                              31:31
+#define DE_SOURCE_WRAP_DISABLE                                      0
+#define DE_SOURCE_WRAP_ENABLE                                       1
+#define DE_SOURCE_X_K1                                              29:16
+#define DE_SOURCE_Y_K2                                              15:0
+
+/* 2D Destination */
+#define DE_DESTINATION                                              0x100004
+#define DE_DESTINATION_WRAP                                         31:31
+#define DE_DESTINATION_WRAP_DISABLE                                 0
+#define DE_DESTINATION_WRAP_ENABLE                                  1
+#define DE_DESTINATION_X                                            28:16
+#define DE_DESTINATION_Y                                            15:0
+
+/* 2D Dimension */
+#define DE_DIMENSION                                                0x100008
+#define DE_DIMENSION_X_VL                                           28:16
+#define DE_DIMENSION_Y_ET                                           15:0
+
+/* 2D Control */
+#define DE_CONTROL                                                  0x10000C
+#define DE_CONTROL_STATUS                                           31:31
+#define DE_CONTROL_STATUS_STOP                                      0
+#define DE_CONTROL_STATUS_START                                     1
+#define DE_CONTROL_PATTERN_SELECT                                   30:30
+#define DE_CONTROL_PATTERN_SELECT_MONOCHROME                        0
+#define DE_CONTROL_PATTERN_SELECT_COLOR                             1
+#define DE_CONTROL_UPDATE_DESTINATION_X                             29:29
+#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE                     0
+#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE                      1
+#define DE_CONTROL_QUICK_START_CONTROL                              28:28
+#define DE_CONTROL_QUICK_START_CONTROL_DISABLE                      0
+#define DE_CONTROL_QUICK_START_CONTROL_ENABLE                       1
+#define DE_CONTROL_DIRECTION_CONTROL                                27:27
+#define DE_CONTROL_DIRECTION_CONTROL_LEFT_TO_RIGHT                  0
+#define DE_CONTROL_DIRECTION_CONTROL_RIGHT_TO_LEFT                  1
+#define DE_CONTROL_MAJOR_AXIS                                       26:26
+#define DE_CONTROL_MAJOR_AXIS_X                                     0
+#define DE_CONTROL_MAJOR_AXIS_Y                                     1
+#define DE_CONTROL_X_STEP                                           25:25
+#define DE_CONTROL_X_STEP_POSITIVE                                  0
+#define DE_CONTROL_X_STEP_NEGATIVE                                  1
+#define DE_CONTROL_Y_STEP                                           24:24
+#define DE_CONTROL_Y_STEP_POSITIVE                                  0
+#define DE_CONTROL_Y_STEP_NEGATIVE                                  1
+#define DE_CONTROL_STRETCH                                          23:23
+#define DE_CONTROL_STRETCH_DISABLE                                  0
+#define DE_CONTROL_STRETCH_ENABLE                                   1
+#define DE_CONTROL_HOST_BITBLT                                      22:22
+#define DE_CONTROL_HOST_BITBLT_COLOR                                0
+#define DE_CONTROL_HOST_BITBLT_MONOCHROME                           1
+#define DE_CONTROL_DRAW_LAST_PIXEL                                  21:21
+#define DE_CONTROL_DRAW_LAST_PIXEL_DONOT_DRAW                       0
+#define DE_CONTROL_DRAW_LAST_PIXEL_DRAW                             1
+#define DE_CONTROL_COMMAND                                          20:16
+#define DE_CONTROL_COMMAND_BITBLT                                   0
+#define DE_CONTROL_COMMAND_RECTANGLE_FILL                           1
+#define DE_CONTROL_COMMAND_DETILE                                   2
+#define DE_CONTROL_COMMAND_TRAPEZOID_FILL                           3
+#define DE_CONTROL_COMMAND_ALPHA_BLEND                              4
+#define DE_CONTROL_COMMAND_RLE_STRIP                                5
+#define DE_CONTROL_COMMAND_SHORT_STROKE                             6
+#define DE_CONTROL_COMMAND_LINE_DRAW                                7
+#define DE_CONTROL_COMMAND_HOST_WRITE                               8
+#define DE_CONTROL_COMMAND_HOST_READ                                9
+#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP                     10
+#define DE_CONTROL_COMMAND_ROTATE                                   11
+#define DE_CONTROL_COMMAND_FONT                                     12
+#define DE_CONTROL_COMMAND_TEXTURE_LOAD                             13
+#define DE_CONTROL_ROP_CONTROL                                      15:15
+#define DE_CONTROL_ROP_CONTROL_ROP2                                 0
+#define DE_CONTROL_ROP_CONTROL_ROP3                                 1
+#define DE_CONTROL_ROP2_CONTROL                                     14:14
+#define DE_CONTROL_ROP2_CONTROL_BITMAP                              0
+#define DE_CONTROL_ROP2_CONTROL_PATTERN                             1
+#define DE_CONTROL_MONOCHROME_PACK_CONTROL                          13:12
+#define DE_CONTROL_MONOCHROME_PACK_CONTROL_NOT_PACKED               0
+#define DE_CONTROL_MONOCHROME_PACK_CONTROL_8_BIT                    1
+#define DE_CONTROL_MONOCHROME_PACK_CONTROL_16_BIT                   2
+#define DE_CONTROL_MONOCHROME_PACK_CONTROL_32_BIT                   3
+#define DE_CONTROL_REPEAT_ROTATION                                  11:11
+#define DE_CONTROL_REPEAT_ROTATION_DISABLE                          0
+#define DE_CONTROL_REPEAT_ROTATION_ENABLE                           1
+#define DE_CONTROL_TRANSPARENCY_MATCH_SELECT                        10:10
+#define DE_CONTROL_TRANSPARENCY_MATCH_SELECT_OPAQUE                 0
+#define DE_CONTROL_TRANSPARENCY_MATCH_SELECT_TRANSPARENT            1
+#define DE_CONTROL_TRANSPARENCY_SELECT                              9:9
+#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE                       0
+#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION                  1
+#define DE_CONTROL_TRANSPARENCY_CONTROL                             8:8
+#define DE_CONTROL_TRANSPARENCY_CONTROL_DISABLE                     0
+#define DE_CONTROL_TRANSPARENCY_CONTROL_ENABLE                      1
+#define DE_CONTROL_ROP                                              7:0
+
+/* 2D Pitch */
+#define DE_PITCH                                                    0x100010
+#define DE_PITCH_DESTINATION                                        28:16
+#define DE_PITCH_SOURCE                                             12:0
+
+/* 2D Foreground */
+#define DE_FOREGROUND                                               0x100014
+
+/* 2D Background */
+#define DE_BACKGROUND                                               0x100018
+
+/* 2D Stretch & Format */
+#define DE_STRETCH_FORMAT                                           0x10001C
+#define DE_STRETCH_FORMAT_PATTERN_XY                                30:30
+#define DE_STRETCH_FORMAT_PATTERN_XY_LINEAR                         0
+#define DE_STRETCH_FORMAT_PATTERN_XY_LINEAR_AND_XY                  1
+#define DE_STRETCH_FORMAT_PATTERN_Y_ORIGIN                          29:27
+#define DE_STRETCH_FORMAT_PATTERN_X_ORIGIN                          25:23
+#define DE_STRETCH_FORMAT_FORMAT                                    21:20
+#define DE_STRETCH_FORMAT_FORMAT_8BPP                               0
+#define DE_STRETCH_FORMAT_FORMAT_16BPP                              1
+#define DE_STRETCH_FORMAT_FORMAT_32BPP                              2
+#define DE_STRETCH_FORMAT_ADRESSING                                 19:16
+#define DE_STRETCH_FORMAT_ADRESSING_XY                              0
+#define DE_STRETCH_FORMAT_ADRESSING_LINEAR                          15
+#define DE_STRETCH_FORMAT_HEIGHT                                    11:0
+
+/* 2D Color Compare */
+#define DE_COLOR_COMPARE                                            0x100020
+#define DE_COLOR_COMPARE_COLOR                                      23:0
+
+/* 2D Color Compare Mask */
+#define DE_COLOR_COMPARE_MASK                                       0x100024
+#define DE_COLOR_COMPARE_MASK_MASK                                  23:0
+
+/* 2D Mask */
+#define DE_MASK                                                     0x100028
+#define DE_MASK_BYTE                                                31:16
+#define DE_MASK_BIT                                                 15:0
+
+/* 2D Clip TL */
+#define DE_CLIP_TL                                                  0x10002C
+#define DE_CLIP_TL_TOP                                              31:16
+#define DE_CLIP_TL_CONTROL                                          13:13
+#define DE_CLIP_TL_CONTROL_DISABLE                                  0
+#define DE_CLIP_TL_CONTROL_ENABLE                                   
+#define DE_CLIP_TL_SELECT                                           12:12
+#define DE_CLIP_TL_SELECT_INTERIOR                                  0
+#define DE_CLIP_TL_SELECT_EXTERIOR                                  1
+#define DE_CLIP_TL_LEFT                                             11:0
+
+/* 2D Clip BR */
+#define DE_CLIP_BR                                                  0x100030
+#define DE_CLIP_BR_BOTTOM                                           31:16
+#define DE_CLIP_BR_RIGHT                                            12:0
+
+/* 2D Mono Pattern Low */
+#define DE_MONO_PATTERN_LOW                                         0x100034
+
+/* 2D Mono Pattern High */
+#define DE_MONO_PATTERN_HIGH                                        0x100038
+
+/* 2D Window Width */
+#define DE_WINDOW_WIDTH                                             0x10003C
+#define DE_WINDOW_WIDTH_DESTINATION                                 28:16
+#define DE_WINDOW_WIDTH_SOURCE                                      12:0
+
+/* 2D Source Base */
+#define DE_SOURCE_BASE                                              0x100040
+#define DE_SOURCE_BASE_MEMORY                                       27:26
+#define DE_SOURCE_BASE_MEMORY_LOCAL                                 0
+#define DE_SOURCE_BASE_MEMORY_EXTERNAL_CS0                          2
+#define DE_SOURCE_BASE_MEMORY_EXTERNAL_CS1                          3
+#define DE_SOURCE_BASE_ADDRESS                                      25:0
+
+/* 2D Destination Base */
+#define DE_DESTINATION_BASE                                         0x100044
+#define DE_DESTINATION_BASE_MEMORY                                  27:26
+#define DE_DESTINATION_BASE_MEMORY_LOCAL                            0
+#define DE_DESTINATION_BASE_MEMORY_EXTERNAL_CS0                     2
+#define DE_DESTINATION_BASE_MEMORY_EXTERNAL_CS1                     3
+#define DE_DESTINATION_BASE_ADDRESS                                 25:0
+
+/* 2D Alpha */
+#define DE_ALPHA                                                    0x100048
+#define DE_ALPHA_ALPHA                                              7:0
+
+/* 2D Wrap */
+#define DE_WRAP                                                     0x10004C
+#define DE_WRAP_WIDTH                                               31:16
+#define DE_WRAP_HEIGHT                                              15:0
+
+/* 2D Status */
+#define DE_STATUS                                                   0x100050
+#define DE_STATUS_CSC                                               1:1
+#define DE_STATUS_CSC_NO_INTERRUPT                                  0
+#define DE_STATUS_CSC_INTERRUPT                                     1
+#define DE_STATUS_2D                                                0:0
+#define DE_STATUS_2D_NO_INTERRUPT                                   0
+#define DE_STATUS_2D_INTERRUPT                                      1
+
+/* CSC Y Source Base */
+#define CSC_Y_SOURCE_BASE                                           0x1000C8
+#define CSC_Y_SOURCE_BASE_MEMORY                                    27:26
+#define CSC_Y_SOURCE_BASE_MEMORY_LOCAL                              0
+#define CSC_Y_SOURCE_BASE_MEMORY_EXTERNAL_CS0                       2
+#define CSC_Y_SOURCE_BASE_MEMORY_EXTERNAL_CS1                       3
+#define CSC_Y_SOURCE_BASE_ADDRESS                                   25:0
+
+/* CSC Constants */
+#define CSC_CONSTANTS                                               0x1000CC
+#define CSC_CONSTANTS_Y                                             31:24
+#define CSC_CONSTANTS_R                                             23:16
+#define CSC_CONSTANTS_G                                             15:8
+#define CSC_CONSTANTS_B                                             7:0
+
+/* CSC Y Source X */
+#define CSC_Y_SOURCE_X                                              0x1000D0
+#define CSC_Y_SOURCE_X_INTEGER                                      27:16
+#define CSC_Y_SOURCE_X_FRACTIONAL                                   15:3
+
+/* CSC Y Source Y */
+#define CSC_Y_SOURCE_Y                                              0x1000D4
+#define CSC_Y_SOURCE_Y_INTEGER                                      27:16
+#define CSC_Y_SOURCE_Y_FRACTIONAL                                   15:3
+
+/* CSC U Source Base */
+#define CSC_U_SOURCE_BASE                                           0x1000D8
+#define CSC_U_SOURCE_BASE_MEMORY                                    27:26
+#define CSC_U_SOURCE_BASE_MEMORY_LOCAL                              0
+#define CSC_U_SOURCE_BASE_MEMORY_EXTERNAL_CS0                       2
+#define CSC_U_SOURCE_BASE_MEMORY_EXTERNAL_CS1                       3
+#define CSC_U_SOURCE_BASE_ADDRESS                                   25:0
+
+/* CSC V Source Base */
+#define CSC_V_SOURCE_BASE                                           0x1000DC
+#define CSC_V_SOURCE_BASE_MEMORY                                    27:26
+#define CSC_V_SOURCE_BASE_MEMORY_LOCAL                              0
+#define CSC_V_SOURCE_BASE_MEMORY_EXTERNAL_CS0                       2
+#define CSC_V_SOURCE_BASE_MEMORY_EXTERNAL_CS1                       3
+#define CSC_V_SOURCE_BASE_ADDRESS                                   25:0
+
+/* CSC Source Dimension */
+#define CSC_SOURCE_DIMENSION                                        0x1000E0
+#define CSC_SOURCE_DIMENSION_WIDTH                                  31:16
+#define CSC_SOURCE_DIMENSION_HEIGHT                                 15:0
+
+/* CSC Source Pitch */
+#define CSC_SOURCE_PITCH                                            0x1000E4
+#define CSC_SOURCE_PITCH_Y                                          31:16
+#define CSC_SOURCE_PITCH_UV                                         15:0
+
+/* CSC Destination */
+#define CSC_DESTINATION                                             0x1000E8
+#define CSC_DESTINATION_WRAP                                        31:31
+#define CSC_DESTINATION_WRAP_DISABLE                                0
+#define CSC_DESTINATION_WRAP_ENABLE                                 1
+#define CSC_DESTINATION_X                                           27:16
+#define CSC_DESTINATION_Y                                           11:0
+
+/* CSC Destination Dimension */
+#define CSC_DESTINATION_DIMENSION                                   0x1000EC
+#define CSC_DESTINATION_DIMENSION_WIDTH                             31:16
+#define CSC_DESTINATION_DIMENSION_HEIGHT                            15:0
+
+/* CSC Destination Pitch */
+#define CSC_DESTINATION_PITCH                                       0x1000F0
+#define CSC_DESTINATION_PITCH_X                                     31:16
+#define CSC_DESTINATION_PITCH_Y                                     15:0
+
+/* CSC Scale Factor */
+#define CSC_SCALE_FACTOR                                            0x1000F4
+#define CSC_SCALE_FACTOR_X                                          31:16
+#define CSC_SCALE_FACTOR_Y                                          15:0
+
+/* CSC Destination Base */
+#define CSC_DESTINATION_BASE                                        0x1000F8
+#define CSC_DESTINATION_BASE_MEMORY                                 27:26
+#define CSC_DESTINATION_BASE_MEMORY_LOCAL                           0
+#define CSC_DESTINATION_BASE_MEMORY_EXTERNAL_CS0                    2
+#define CSC_DESTINATION_BASE_MEMORY_EXTERNAL_CS1                    3
+#define CSC_DESTINATION_BASE_ADDRESS                                25:0
+
+/* CSC Control */
+#define CSC_CONTROL                                                 0x1000FC
+#define CSC_CONTROL_STATUS                                          31:31
+#define CSC_CONTROL_STATUS_STOP                                     0
+#define CSC_CONTROL_STATUS_START                                    1
+#define CSC_CONTROL_SOURCE_FORMAT                                   30:28
+#define CSC_CONTROL_SOURCE_FORMAT_YUV422                            0
+#define CSC_CONTROL_SOURCE_FORMAT_YUV420I                           1
+#define CSC_CONTROL_SOURCE_FORMAT_YUV420                            2
+#define CSC_CONTROL_SOURCE_FORMAT_RGB565                            6
+#define CSC_CONTROL_SOURCE_FORMAT_RGBX888                           7
+#define CSC_CONTROL_DESTINATION_FORMAT                              27:26
+#define CSC_CONTROL_DESTINATION_FORMAT_RGB565                       0
+#define CSC_CONTROL_DESTINATION_FORMAT_RGBX888                      1
+#define CSC_CONTROL_HORIZONTAL_LINEAR_CONTROL                       25:25
+#define CSC_CONTROL_HORIZONTAL_LINEAR_CONTROL_DISABLE               0
+#define CSC_CONTROL_HORIZONTAL_LINEAR_CONTROL_ENABLE                1
+#define CSC_CONTROL_VERTICAL_LINEAR_CONTROL                         24:24
+#define CSC_CONTROL_VERTICAL_LINEAR_CONTROL_DISABLE                 0
+#define CSC_CONTROL_VERTICAL_LINEAR_CONTROL_ENABLE                  1
+#define CSC_CONTROL_BYTE_ORDER                                      23:23
+#define CSC_CONTROL_BYTE_ORDER_YUYV_UVUV                            0
+#define CSC_CONTROL_BYTE_ORDER_UYVY_VUVU                            1
+
+/*****************************************************************************\
+ *                             2D ENGINE DATA PORT                           *
+\*****************************************************************************/
+
+#define DE_DATA_PORT                                                0x110000
+#define DE_DATA_PORT_SIZE                                           0x040000
+
+#endif /* _SM501_H_ */
diff -uNra linux-2.6.27.6/drivers/usb/core/hcd.c linux-2.6.27.6.yaffs/drivers/usb/core/hcd.c
--- linux-2.6.27.6/drivers/usb/core/hcd.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/core/hcd.c	2011-05-08 18:00:30.000000000 +0800
@@ -1310,6 +1310,7 @@
 	 * (which will control it).  HCD guarantees that it either returns
 	 * an error or calls giveback(), but not both.
 	 */
+//			printk("--1----%s-----------------\n",__func__);
 	usb_get_urb(urb);
 	atomic_inc(&urb->use_count);
 	atomic_inc(&urb->dev->urbnum);
@@ -1429,6 +1430,8 @@
  */
 void usb_hcd_giveback_urb(struct usb_hcd *hcd, struct urb *urb, int status)
 {
+
+//	printk("-------%s---------\n",__func__);
 	urb->hcpriv = NULL;
 	if (unlikely(urb->unlinked))
 		status = urb->unlinked;
diff -uNra linux-2.6.27.6/drivers/usb/core/quirks.c linux-2.6.27.6.yaffs/drivers/usb/core/quirks.c
--- linux-2.6.27.6/drivers/usb/core/quirks.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/core/quirks.c	2011-05-08 18:00:30.000000000 +0800
@@ -80,7 +80,10 @@
 	for (; id->idVendor || id->bDeviceClass || id->bInterfaceClass ||
 			id->driver_info; id++) {
 		if (usb_match_device(udev, id))
+		{
 			return id;
+			printk("---mj--quirks-----------\n");
+		}
 	}
 	return NULL;
 }
diff -uNra linux-2.6.27.6/drivers/usb/core/urb.c linux-2.6.27.6.yaffs/drivers/usb/core/urb.c
--- linux-2.6.27.6/drivers/usb/core/urb.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/core/urb.c	2011-05-08 18:00:30.000000000 +0800
@@ -444,7 +444,7 @@
 			return -EINVAL;
 		}
 		/* Round down to a power of 2, no more than max */
-		urb->interval = min(max, 1 << ilog2(urb->interval));
+		urb->interval = min(max, 1 << __ilog2_u64(urb->interval));
 	}
 
 	return usb_hcd_submit_urb(urb, mem_flags);
diff -uNra linux-2.6.27.6/drivers/usb/host/ohci-sm501.c linux-2.6.27.6.yaffs/drivers/usb/host/ohci-sm501.c
--- linux-2.6.27.6/drivers/usb/host/ohci-sm501.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/host/ohci-sm501.c	2011-05-08 18:00:29.000000000 +0800
@@ -18,6 +18,9 @@
 #include <linux/sm501.h>
 #include <linux/sm501-regs.h>
 
+extern unsigned long sm501_modify_reg(struct device *dev,unsigned long reg,unsigned long set,unsigned long clear);
+extern int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to);
+
 static int ohci_sm501_init(struct usb_hcd *hcd)
 {
 	return ohci_init(hcd_to_ohci(hcd));
diff -uNra linux-2.6.27.6/drivers/usb/host/uhci-hcd.c linux-2.6.27.6.yaffs/drivers/usb/host/uhci-hcd.c
--- linux-2.6.27.6/drivers/usb/host/uhci-hcd.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/host/uhci-hcd.c	2011-05-08 18:00:29.000000000 +0800
@@ -264,6 +264,7 @@
 	int int_enable, egsm_enable, wakeup_enable;
 	struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub;
 
+//	printk("--->>>----%s---------\n",__func__);
 	auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
 	dev_dbg(&rhdev->dev, "%s%s\n", __func__,
 			(auto_stop ? " (auto-stop)" : ""));
@@ -349,6 +350,7 @@
 
 	uhci_scan_schedule(uhci);
 	uhci_fsbr_off(uhci);
+//	printk("---<<<----%s---------\n",__func__);
 }
 
 static void start_rh(struct uhci_hcd *uhci)
@@ -417,6 +419,7 @@
 	 * interrupt cause.  Contrary to the UHCI specification, the
 	 * "HC Halted" status bit is persistent: it is RO, not R/WC.
 	 */
+//	printk("--->>>----%s---------\n",__func__);
 	status = inw(uhci->io_addr + USBSTS);
 	if (!(status & ~USBSTS_HCH))	/* shared interrupt, not mine */
 		return IRQ_NONE;
@@ -452,13 +455,18 @@
 	}
 
 	if (status & USBSTS_RD)
+	{
+//	printk("--1----%s---------\n",__func__);
 		usb_hcd_poll_rh_status(hcd);
+	}
 	else {
+//	printk("--2----%s---------\n",__func__);
 		spin_lock(&uhci->lock);
 		uhci_scan_schedule(uhci);
 		spin_unlock(&uhci->lock);
 	}
 
+//	printk("---<<<----%s---------\n",__func__);
 	return IRQ_HANDLED;
 }
 
diff -uNra linux-2.6.27.6/drivers/usb/host/uhci-hub.c linux-2.6.27.6.yaffs/drivers/usb/host/uhci-hub.c
--- linux-2.6.27.6/drivers/usb/host/uhci-hub.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/host/uhci-hub.c	2011-05-08 18:00:29.000000000 +0800
@@ -187,6 +187,7 @@
 	unsigned long flags;
 	int status = 0;
 
+//	printk("--->>>----%s---------\n",__func__);
 	spin_lock_irqsave(&uhci->lock, flags);
 
 	uhci_scan_schedule(uhci);
@@ -230,6 +231,7 @@
 		break;
 	}
 
+//	printk("---<<<----%s---------\n",__func__);
 done:
 	spin_unlock_irqrestore(&uhci->lock, flags);
 	return status;
diff -uNra linux-2.6.27.6/drivers/usb/host/uhci-q.c linux-2.6.27.6.yaffs/drivers/usb/host/uhci-q.c
--- linux-2.6.27.6/drivers/usb/host/uhci-q.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/usb/host/uhci-q.c	2011-05-08 18:00:29.000000000 +0800
@@ -1718,6 +1718,7 @@
 	int i;
 	struct uhci_qh *qh;
 
+//	printk("--->>>>>----%s- :--------\n",__func__);
 	/* Don't allow re-entrant calls */
 	if (uhci->scan_in_progress) {
 		uhci->need_rescan = 1;
@@ -1743,6 +1744,15 @@
 			if (uhci_advance_check(uhci, qh)) {
 				uhci_scan_qh(uhci, qh);
 				if (qh->state == QH_STATE_ACTIVE) {
+#if 0  //mj
+					unsigned char * c;
+					int i;
+					c=(unsigned char *)(((struct uhci_td *)(qh->link))->buffer);
+					printk("\n");
+				for(i=0;i<8;i++)	
+					printk("%02x ",c[i]);
+					printk("----%s------------\n",__func__);
+#endif 
 					uhci_urbp_wants_fsbr(uhci,
 	list_entry(qh->queue.next, struct urb_priv, node));
 				}
@@ -1765,4 +1775,5 @@
 		uhci_clear_next_interrupt(uhci);
 	else
 		uhci_set_next_interrupt(uhci);
+//	printk("---<<<<<<----%s- :--------\n",__func__);
 }
diff -uNra linux-2.6.27.6/drivers/video/Kconfig linux-2.6.27.6.yaffs/drivers/video/Kconfig
--- linux-2.6.27.6/drivers/video/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/video/Kconfig	2011-05-08 18:00:50.000000000 +0800
@@ -1899,6 +1899,38 @@
 	  Turn on debugging messages. Note that you can set/unset at run time
 	  through sysfs
 
+config FB_SILICONMOTION
+	bool "Silicon Motion Display Support"
+	depends on FB
+	select FB_CFB_COPYAREA
+	select FB_CFB_FILLRECT
+	select FB_CFB_IMAGEBLIT
+	---help---
+	  Frame Buffer driver for the Silicon Motion serial graphic card.
+
+config FB_SM7XX
+	bool "Silicon Motion SM7XX Frame Buffer Support"
+	depends on FB_SILICONMOTION
+	depends on FB
+ 	select FB_CFB_FILLRECT
+ 	select FB_CFB_COPYAREA
+ 	select FB_CFB_IMAGEBLIT
+	---help---
+	  Frame Buffer driver for the Silicon Motion SM7XX serial graphic card.
+
+config FB_SM7XX_ACCEL
+	bool "Siliconmotion Acceleration functions (EXPERIMENTAL)"
+	depends on FB_SM7XX && EXPERIMENTAL
+	---help---
+	This will compile the Trident frame buffer device with
+	acceleration functions.
+
+config FB_SM7XX_DUALHEAD
+	bool "SM7XX dualhead display support"
+	depends on FB_SM7XX
+	---help---
+	  Say Y here if you want to use a secondary head display.
+
 config FB_SM501
 	tristate "Silicon Motion SM501 framebuffer support"
 	depends on FB && MFD_SM501
diff -uNra linux-2.6.27.6/drivers/video/Makefile linux-2.6.27.6.yaffs/drivers/video/Makefile
--- linux-2.6.27.6/drivers/video/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/video/Makefile	2011-05-08 18:00:53.000000000 +0800
@@ -71,6 +71,7 @@
 obj-$(CONFIG_FB_TCX)              += tcx.o sbuslib.o
 obj-$(CONFIG_FB_LEO)              += leo.o sbuslib.o
 obj-$(CONFIG_FB_SGIVW)            += sgivwfb.o
+obj-$(CONFIG_FB_SILICONMOTION)	  += smi/
 obj-$(CONFIG_FB_ACORN)            += acornfb.o
 obj-$(CONFIG_FB_ATARI)            += atafb.o c2p.o atafb_mfb.o \
                                      atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o
diff -uNra linux-2.6.27.6/drivers/video/sis/sis_main.c linux-2.6.27.6.yaffs/drivers/video/sis/sis_main.c
--- linux-2.6.27.6/drivers/video/sis/sis_main.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/video/sis/sis_main.c	2011-05-08 18:00:51.000000000 +0800
@@ -1980,6 +1980,9 @@
 		case 0x02:
 			ivideo->video_size += (ivideo->video_size/2);
 		}
+#if defined(CONFIG_LEMOTE_LOONGSON2F)
+		ivideo->video_size = 0x2000 << 10;
+#endif
 		break;
 	case SIS_330:
 		inSISIDXREG(SISSR, 0x14, reg);
diff -uNra linux-2.6.27.6/drivers/video/sm2d.c linux-2.6.27.6.yaffs/drivers/video/sm2d.c
--- linux-2.6.27.6/drivers/video/sm2d.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/video/sm2d.c	2011-05-08 18:00:52.000000000 +0800
@@ -0,0 +1,1877 @@
+/*
+ *  linux/drivers/video/smtc2d.c -- Silicon Motion SM501 and SM7xx 2D drawing engine functions.
+ *
+ *      Copyright (C) 2010 Silicon Motion Technology Corp.
+ *      Ge Wang, gewang@siliconmotion.com
+ *      Boyod.yang,  <boyod.yang@siliconmotion.com.cn>
+ *      Teddy.wang  <teddy.wang@siliconmotion.com.cn>
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License version 2 or later as published by the Free Software Foundation.  
+ */
+
+ 
+#include <linux/kernel.h>
+#include <linux/errno.h>
+
+#define RGB(r, g, b) ((unsigned long)(((r) << 16) | ((g) << 8) | (b)))
+
+// Transparent info definition
+typedef struct
+{
+    unsigned long match;    // Matching pixel is OPAQUE/TRANSPARENT
+	unsigned long select;   // Transparency controlled by SOURCE/DESTINATION
+	unsigned long control;  // ENABLE/DISABLE transparency
+	unsigned long color;    // Transparent color
+} Transparent, *pTransparent;
+
+#define PIXEL_DEPTH_1_BP		0		// 1 bit per pixel
+#define PIXEL_DEPTH_8_BPP		1		// 8 bits per pixel
+#define PIXEL_DEPTH_16_BPP		2		// 16 bits per pixel
+#define PIXEL_DEPTH_32_BPP		3		// 32 bits per pixel
+#define PIXEL_DEPTH_YUV422		8		// 16 bits per pixel YUV422
+#define PIXEL_DEPTH_YUV420		9		// 16 bits per pixel YUV420
+
+#define PATTERN_WIDTH           8
+#define PATTERN_HEIGHT          8
+
+#define	TOP_TO_BOTTOM			0
+#define	BOTTOM_TO_TOP			1
+#define RIGHT_TO_LEFT			BOTTOM_TO_TOP
+#define LEFT_TO_RIGHT			TOP_TO_BOTTOM
+
+// Constants used in Transparent structure
+#define MATCH_OPAQUE            0x00000000
+#define MATCH_TRANSPARENT       0x00000400
+#define SOURCE                  0x00000000
+#define DESTINATION             0x00000200
+
+#define DE_DATA_PORT_501                                0x110000
+#define DE_DATA_PORT_712                                0x400000
+#define DE_DATA_PORT_722                                0x6000
+
+unsigned char sm_accel_busy = 0;
+
+void SmWrite2D(unsigned long nOffset, unsigned long nData)
+{
+    SmWrite32(DE_BASE_ADDRESS+nOffset, nData);
+}
+
+ulong SmRead2D(ulong offset)
+{
+	return SmRead32(DE_BASE_ADDRESS+offset);
+}
+
+
+void SmWrite2D_DataPort(unsigned long nOffset, unsigned long nData)
+{
+    SmWrite32(DE_DATA_PORT+nOffset, nData);
+}
+
+/* sm501fb_Wait_IDLE()
+ *
+ * This call is mainly for wait 2D idle.
+*/
+void sm501fb_Wait_Idle(void)
+{
+	unsigned long i = 0x1000000;
+	unsigned long dwVal =0;
+	smdbg("In W_Idle\n");
+	while (i--)
+	{
+        dwVal = SmRead32(SYS_CTRL);
+        if ((FIELD_GET(dwVal, SYS_CTRL, 2D_ENGINE_STATUS)      == SYS_CTRL_2D_ENGINE_STATUS_IDLE) &&
+            (FIELD_GET(dwVal, SYS_CTRL, 2D_FIFO)        == SYS_CTRL_2D_FIFO_EMPTY) &&
+            (FIELD_GET(dwVal, SYS_CTRL, CSC_STATUS)     == SYS_CTRL_CSC_STATUS_IDLE) &&
+            (FIELD_GET(dwVal, SYS_CTRL, 2D_MEMORY_FIFO) == SYS_CTRL_2D_MEMORY_FIFO_EMPTY))
+            break;
+	}
+    	//sm_accel_busy = 0;
+}
+
+/*
+ * This function gets the transparency status from DE_CONTROL register.
+ * It returns a double word with the transparent fields properly set,
+ * while other fields are 0.
+ */
+unsigned long deGetTransparency()
+{
+    unsigned long de_ctrl;
+
+    de_ctrl = SmRead2D(DE_CONTROL);
+
+    de_ctrl &= 
+        FIELD_MASK(DE_CONTROL_TRANSPARENCY_MATCH) | 
+        FIELD_MASK(DE_CONTROL_TRANSPARENCY_SELECT)| 
+        FIELD_MASK(DE_CONTROL_TRANSPARENCY);
+
+    return de_ctrl;
+}
+
+long deSetTransparency(
+unsigned long enable,     /* 0 = disable, 1 = enable transparency feature */
+unsigned long tSelect,    /* 0 = compare source, 1 = compare destination */
+unsigned long tMatch,     /* 0 = Opaque mode, 1 = transparent mode */
+unsigned long ulColor)    /* Color to compare. */
+{
+    unsigned long de_ctrl;
+
+    
+    /* Set mask */
+    if (enable)
+    {
+        SmWrite2D(DE_COLOR_COMPARE_MASK, 0x00ffffff);
+
+        /* Set compare color */
+        SmWrite2D(DE_COLOR_COMPARE, ulColor);
+    }
+    else
+    {
+        SmWrite2D(DE_COLOR_COMPARE_MASK, 0x0);
+        SmWrite2D(DE_COLOR_COMPARE, 0x0);
+    }
+
+    /* Set up transparency control, without affecting other bits
+       Note: There are two operatiing modes: Transparent and Opague.
+       We only use transparent mode because Opaque mode may have bug.
+    */
+    de_ctrl = SmRead2D(DE_CONTROL)
+              & FIELD_CLEAR(DE_CONTROL, TRANSPARENCY)
+              & FIELD_CLEAR(DE_CONTROL, TRANSPARENCY_MATCH)
+              & FIELD_CLEAR(DE_CONTROL, TRANSPARENCY_SELECT);
+
+    /* For DE_CONTROL_TRANSPARENCY_MATCH bit, always set it
+       to TRANSPARENT mode, OPAQUE mode don't seem working.
+    */
+    de_ctrl |=
+    ((enable)?
+      FIELD_SET(0, DE_CONTROL, TRANSPARENCY, ENABLE)
+    : FIELD_SET(0, DE_CONTROL, TRANSPARENCY, DISABLE))        |
+    ((tMatch)?
+      FIELD_SET(0, DE_CONTROL, TRANSPARENCY_MATCH, TRANSPARENT)
+    : FIELD_SET(0, DE_CONTROL, TRANSPARENCY_MATCH, OPAQUE)) |
+    ((tSelect)?
+      FIELD_SET(0, DE_CONTROL, TRANSPARENCY_SELECT, DESTINATION)
+    : FIELD_SET(0, DE_CONTROL, TRANSPARENCY_SELECT, SOURCE));
+
+    SmWrite2D(DE_CONTROL, de_ctrl);
+
+    return 0;
+}
+
+
+/**********************************************************************
+ *
+ * deInit
+ *
+ * Purpose
+ *    Drawing engine initialization.
+ *
+ **********************************************************************/
+ void deInit(unsigned int nModeWidth, unsigned int nModeHeight, unsigned int bpp)
+{
+	// Get current power configuration.
+	unsigned int gate, clock;
+
+	gate  = SmRead32(CURRENT_GATE);
+
+	// Enable 2D Drawing Engine
+	gate = FIELD_SET(gate, CURRENT_GATE, 2D, ENABLE);
+	sm501_set_gate(gate);
+	
+	SmWrite2D(DE_CLIP_TL,
+		FIELD_VALUE(0, DE_CLIP_TL, TOP,     0)       |
+		FIELD_SET  (0, DE_CLIP_TL, STATUS,  DISABLE) |
+		FIELD_SET  (0, DE_CLIP_TL, INHIBIT, OUTSIDE) |
+		FIELD_VALUE(0, DE_CLIP_TL, LEFT,    0));
+/*
+    SmWrite2D(DE_PITCH,
+		FIELD_VALUE(0, DE_PITCH, DESTINATION, nModeWidth) |
+		FIELD_VALUE(0, DE_PITCH, SOURCE,      nModeWidth));
+
+    SmWrite2D(DE_WINDOW_WIDTH,
+		FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, nModeWidth) |
+		FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      nModeWidth));
+*/
+
+   if ((bpp>=24)&&(bpp<=32))
+   	bpp = 32;
+   
+    switch (bpp)
+    {
+    case 8:
+        SmWrite2D(DE_STRETCH_FORMAT,
+            FIELD_SET  (0, DE_STRETCH_FORMAT, PATTERN_XY,    NORMAL) |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_Y,     0)      |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X,     0)      |
+            FIELD_SET  (0, DE_STRETCH_FORMAT, PIXEL_FORMAT,  8)      |
+            FIELD_SET  (0, DE_STRETCH_FORMAT, ADDRESSING,	 XY)     |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, SOURCE_HEIGHT, 3));
+        break;
+    case 16:
+        SmWrite2D(DE_STRETCH_FORMAT,
+            FIELD_SET  (0, DE_STRETCH_FORMAT, PATTERN_XY,    NORMAL) |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_Y,     0)      |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X,     0)      |
+            FIELD_SET  (0, DE_STRETCH_FORMAT, PIXEL_FORMAT,  16)     |
+            FIELD_SET  (0, DE_STRETCH_FORMAT, ADDRESSING,	 XY)     |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, SOURCE_HEIGHT, 3));
+        break;
+    case 32:
+        SmWrite2D(DE_STRETCH_FORMAT,
+            FIELD_SET  (0, DE_STRETCH_FORMAT, PATTERN_XY,    NORMAL) |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_Y,     0)      |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X,     0)      |
+            FIELD_SET  (0, DE_STRETCH_FORMAT, PIXEL_FORMAT,  32)     |
+            FIELD_SET  (0, DE_STRETCH_FORMAT, ADDRESSING,	 XY)     |
+            FIELD_VALUE(0, DE_STRETCH_FORMAT, SOURCE_HEIGHT, 3));
+       break;
+   default:
+		BUG();
+
+    }
+
+	SmWrite2D(DE_MASKS,
+		FIELD_VALUE(0, DE_MASKS, BYTE_MASK, 0xFFFF) |
+		FIELD_VALUE(0, DE_MASKS, BIT_MASK,  0xFFFF));
+	SmWrite2D(DE_COLOR_COMPARE_MASK,
+		FIELD_VALUE(0, DE_COLOR_COMPARE_MASK, MASKS, 0xFFFFFF));
+	SmWrite2D(DE_COLOR_COMPARE,
+		FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, 0xFFFFFF));
+
+	/* disable transparency first */
+	deSetTransparency(0,0,0,0);
+}
+
+
+#if 0
+/**********************************************************************
+ *
+ * deSetClipRectangle
+ *
+ * Purpose
+ *    Set drawing engine clip rectangle.
+ *
+ * Remarks
+ *       Caller need to pass in valid rectangle parameter in device coordinate.
+ **********************************************************************/
+void deSetClipRectangle(int left, int top, int right, int bottom)
+{
+    /* Top left of clipping rectangle cannot be negative */
+    if (top < 0)
+    {
+        top = 0;
+    }
+    
+    if (left < 0)
+    {
+        left = 0;
+    }
+    
+    SmWrite2D(DE_CLIP_TL,
+        FIELD_VALUE(0, DE_CLIP_TL, TOP,     top) |
+        FIELD_SET  (0, DE_CLIP_TL, STATUS,  ENABLE)         |
+        FIELD_SET  (0, DE_CLIP_TL, INHIBIT, OUTSIDE)        |
+        FIELD_VALUE(0, DE_CLIP_TL, LEFT,    left));
+    SmWrite2D(DE_CLIP_BR,
+        FIELD_VALUE(0, DE_CLIP_BR, BOTTOM, bottom) |
+        FIELD_VALUE(0, DE_CLIP_BR, RIGHT,  right));
+}
+
+
+void deVerticalLine(unsigned long dst_base,
+                    unsigned long dst_pitch, 
+                    unsigned long nX, 
+                    unsigned long nY, 
+                    unsigned long dst_height, 
+                    unsigned long nColor)
+{
+    sm501fb_Wait_Idle();
+
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+
+	SmWrite2D(DE_PITCH,
+		FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+		FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+    
+	SmWrite2D(DE_WINDOW_WIDTH,
+		FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+		FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+
+    SmWrite2D(DE_FOREGROUND,
+        FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor));
+
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    nX)      |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    nY));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    1) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+
+    SmWrite2D(DE_CONTROL,
+        FIELD_SET  (0, DE_CONTROL, STATUS,     START)         |
+        FIELD_SET  (0, DE_CONTROL, DIRECTION,  LEFT_TO_RIGHT) |
+        FIELD_SET  (0, DE_CONTROL, MAJOR,      Y)             |
+        FIELD_SET  (0, DE_CONTROL, STEP_X,     NEGATIVE)      |
+        FIELD_SET  (0, DE_CONTROL, STEP_Y,     POSITIVE)      |
+        FIELD_SET  (0, DE_CONTROL, LAST_PIXEL, OFF)           |
+        FIELD_SET  (0, DE_CONTROL, COMMAND,    SHORT_STROKE)  |
+        FIELD_SET  (0, DE_CONTROL, ROP_SELECT, ROP2)          |
+        FIELD_VALUE(0, DE_CONTROL, ROP,        0x0C));
+    
+    sm_accel_busy = 1;
+}
+
+void deHorizontalLine(unsigned long dst_base,
+                      unsigned long dst_pitch, 
+                      unsigned long nX, 
+                      unsigned long nY, 
+                      unsigned long dst_width, 
+                      unsigned long nColor)
+{
+    sm501fb_Wait_Idle();
+    
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+    
+    SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+    
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+    SmWrite2D(DE_FOREGROUND,
+        FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor));
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    nX)      |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    nY));
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, 1));
+    SmWrite2D(DE_CONTROL,
+        FIELD_SET  (0, DE_CONTROL, STATUS,     START)         |
+        FIELD_SET  (0, DE_CONTROL, DIRECTION,  RIGHT_TO_LEFT) |
+        FIELD_SET  (0, DE_CONTROL, MAJOR,      X)             |
+        FIELD_SET  (0, DE_CONTROL, STEP_X,     POSITIVE)      |
+        FIELD_SET  (0, DE_CONTROL, STEP_Y,     NEGATIVE)      |
+        FIELD_SET  (0, DE_CONTROL, LAST_PIXEL, OFF)           |
+        FIELD_SET  (0, DE_CONTROL, COMMAND,    SHORT_STROKE)  |
+        FIELD_SET  (0, DE_CONTROL, ROP_SELECT, ROP2)          |
+        FIELD_VALUE(0, DE_CONTROL, ROP,        0x0C));
+
+    sm_accel_busy = 1;
+}
+
+
+void deLine(unsigned long dst_base,
+            unsigned long dst_pitch,  
+            unsigned long nX1, 
+            unsigned long nY1, 
+            unsigned long nX2, 
+            unsigned long nY2, 
+            unsigned long nColor)
+{
+    unsigned long nCommand =
+        FIELD_SET  (0, DE_CONTROL, STATUS,     START)         |
+        FIELD_SET  (0, DE_CONTROL, DIRECTION,  LEFT_TO_RIGHT) |
+        FIELD_SET  (0, DE_CONTROL, MAJOR,      X)             |
+        FIELD_SET  (0, DE_CONTROL, STEP_X,     POSITIVE)      |
+        FIELD_SET  (0, DE_CONTROL, STEP_Y,     POSITIVE)      |
+        FIELD_SET  (0, DE_CONTROL, LAST_PIXEL, OFF)           |
+        FIELD_SET  (0, DE_CONTROL, ROP_SELECT, ROP2)          |
+        FIELD_VALUE(0, DE_CONTROL, ROP,        0x0C);
+    unsigned long DeltaX;
+    unsigned long DeltaY;
+    
+    /* Calculate delta X */
+    if (nX1 <= nX2)
+    {
+        DeltaX = nX2 - nX1;
+    }
+    else
+    {
+        DeltaX = nX1 - nX2;
+        nCommand = FIELD_SET(nCommand, DE_CONTROL, STEP_X, NEGATIVE);
+    }
+    
+    /* Calculate delta Y */
+    if (nY1 <= nY2)
+    {
+        DeltaY = nY2 - nY1;
+    }
+    else
+    {
+        DeltaY = nY1 - nY2;
+        nCommand = FIELD_SET(nCommand, DE_CONTROL, STEP_Y, NEGATIVE);
+    }
+    
+    /* Determine the major axis */
+    if (DeltaX < DeltaY)
+    {
+        nCommand = FIELD_SET(nCommand, DE_CONTROL, MAJOR, Y);
+    }
+    
+    /* Vertical line? */
+    if (nX1 == nX2)
+        deVerticalLine(dst_base, dst_pitch, nX1, nY1, DeltaY, nColor);
+    
+    /* Horizontal line? */
+    else if (nY1 == nY2)
+        deHorizontalLine(dst_base, dst_pitch, nX1, nY1, DeltaX, nColor);
+    
+    /* Diagonal line? */
+    else if (DeltaX == DeltaY)
+    {
+        sm501fb_Wait_Idle();
+        
+        SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+        
+        SmWrite2D(DE_PITCH,
+            FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+        
+        SmWrite2D(DE_WINDOW_WIDTH,
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+        
+        SmWrite2D(DE_FOREGROUND,
+            FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor));
+        
+        SmWrite2D(DE_DESTINATION,
+            FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_DESTINATION, X,    1)       |
+            FIELD_VALUE(0, DE_DESTINATION, Y,    nY1));
+        
+        SmWrite2D(DE_DIMENSION,
+            FIELD_VALUE(0, DE_DIMENSION, X,    1) |
+            FIELD_VALUE(0, DE_DIMENSION, Y_ET, DeltaX));
+        
+        SmWrite2D(DE_CONTROL,
+            FIELD_SET(nCommand, DE_CONTROL, COMMAND, SHORT_STROKE));
+    }
+    
+    /* Generic line */
+    else
+    {
+        unsigned int k1, k2, et, w;
+        if (DeltaX < DeltaY)
+        {
+            k1 = 2 * DeltaX;
+            et = k1 - DeltaY;
+            k2 = et - DeltaY;
+            w  = DeltaY + 1;
+        } 
+        else 
+        {
+            k1 = 2 * DeltaY;
+            et = k1 - DeltaX;
+            k2 = et - DeltaX;
+            w  = DeltaX + 1;
+        }
+        
+        sm501fb_Wait_Idle();
+        
+        SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+        
+        SmWrite2D(DE_PITCH,
+            FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+        
+        SmWrite2D(DE_WINDOW_WIDTH,
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+        
+        SmWrite2D(DE_FOREGROUND,
+            FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor));
+        
+        SmWrite2D(DE_SOURCE,
+            FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_SOURCE, X_K1, k1)      |
+            FIELD_VALUE(0, DE_SOURCE, Y_K2, k2));
+        
+        SmWrite2D(DE_DESTINATION,
+            FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_DESTINATION, X,    nX1)     |
+            FIELD_VALUE(0, DE_DESTINATION, Y,    nY1));
+        
+        SmWrite2D(DE_DIMENSION,
+            FIELD_VALUE(0, DE_DIMENSION, X,    w) |
+            FIELD_VALUE(0, DE_DIMENSION, Y_ET, et));
+        
+        SmWrite2D(DE_CONTROL,
+            FIELD_SET(nCommand, DE_CONTROL, COMMAND, LINE_DRAW));
+    }
+
+    sm_accel_busy = 1;
+}
+#endif
+
+
+
+#if 1
+/*
+ * This function uses 2D engine to fill a rectangular area with a specific color.
+ * The filled area includes the starting points.
+ */
+long deRectFill( /*resolution_t resolution, point_t p0, point_t p1, unsigned long color, unsigned long rop2)*/
+unsigned long dBase,  /* Base address of destination surface counted from beginning of video frame buffer */
+unsigned long dPtich, /* Pitch value of destination surface in BYTES */
+unsigned long bpp,    /* Color depth of destination surface: 8, 16 or 32 */
+unsigned long x,
+unsigned long y,      /* Upper left corner (X, Y) of rectangle in pixel value */
+unsigned long width, 
+unsigned long height, /* width and height of rectange in pixel value */
+unsigned long color,  /* Color to be filled */
+unsigned long rop2)   /* ROP value */
+{
+	unsigned long de_ctrl, bytePerPixel;
+
+    	bytePerPixel = bpp/8;
+    
+	sm501fb_Wait_Idle();
+
+	ulong regvalue=SmRead2D(DE_STRETCH_FORMAT);
+	switch(bpp)
+	{
+		case 8:
+			FIELD_SET(regvalue,DE_STRETCH_FORMAT,PIXEL_FORMAT,8);
+			break;
+		case 16:
+			FIELD_SET(regvalue,DE_STRETCH_FORMAT,PIXEL_FORMAT,16);
+			break;
+		case 32:	
+			FIELD_SET(regvalue,DE_STRETCH_FORMAT,PIXEL_FORMAT,32);
+			break;
+	}
+	SmWrite2D(DE_STRETCH_FORMAT, regvalue);
+
+
+    /* 2D Destination Base.
+       It is an address offset (128 bit aligned) from the beginning of frame buffer.
+    */
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, dBase);
+
+    /* Program pitch (distance between the 1st points of two adjacent lines).
+       Note that input pitch is BYTE value, but the 2D Pitch register uses
+       pixel values. Need Byte to pixel convertion.
+    */
+    SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, (dPtich/bytePerPixel)) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      (dPtich/bytePerPixel)));
+
+    /* Screen Window width in Pixels.
+       2D engine uses this value to calculate the linear address in frame buffer for a given point.
+    */
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, (dPtich/bytePerPixel)) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      (dPtich/bytePerPixel)));
+
+    SmWrite2D(DE_FOREGROUND, color);
+
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    x)       |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    y));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, height));
+
+	/*
+		because bpp had been set by deInit routine, we do not need reset again
+		but,if dual mode need support ,  bpp should by set each time cuz CRT may 
+		get a different bpp to PANEL and deInit may only set 2d engine bpp filed to
+		be the same as PANEL layer
+	*/
+	
+
+    de_ctrl = 
+        FIELD_SET  (0, DE_CONTROL,  STATUS,     START)          |
+        FIELD_SET  (0, DE_CONTROL,  DIRECTION,  LEFT_TO_RIGHT)  |
+        FIELD_SET  (0, DE_CONTROL,LAST_PIXEL, ON)            |
+        FIELD_SET  (0, DE_CONTROL,  COMMAND,    RECTANGLE_FILL) |
+        FIELD_SET  (0, DE_CONTROL,  ROP_SELECT, ROP2)           |
+        FIELD_VALUE(0, DE_CONTROL,  ROP,        rop2);
+	
+	sm501fb_Wait_Idle();
+
+#if 0
+    POKE_32(DE_CONTROL, de_ctrl | deGetTransparency());
+#else	
+	SmWrite2D(DE_CONTROL,de_ctrl);
+#endif
+
+    return 0;
+}
+#else
+void deFillRect(unsigned long dst_base,
+                unsigned long dst_pitch,  
+                unsigned long dst_X, 
+                unsigned long dst_Y, 
+                unsigned long dst_width, 
+                unsigned long dst_height, 
+                unsigned long nColor)
+{
+    sm501fb_Wait_Idle();
+
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+    
+    if (dst_pitch)
+    {
+        SmWrite2D(DE_PITCH,
+            FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+        
+        SmWrite2D(DE_WINDOW_WIDTH,
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+    }
+
+    SmWrite2D(DE_FOREGROUND,
+        FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor));
+
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dst_X)     |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dst_Y));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+
+    SmWrite2D(DE_CONTROL,
+        FIELD_SET  (0, DE_CONTROL, STATUS,     START)          |
+        FIELD_SET  (0, DE_CONTROL, DIRECTION,  LEFT_TO_RIGHT)  |
+        FIELD_SET  (0, DE_CONTROL, LAST_PIXEL, OFF)            |
+        FIELD_SET  (0, DE_CONTROL, COMMAND,    RECTANGLE_FILL) |
+        FIELD_SET  (0, DE_CONTROL, ROP_SELECT, ROP2)           |
+        FIELD_VALUE(0, DE_CONTROL, ROP,        0x0C));
+
+    //sm_accel_busy = 1;
+}
+#endif
+#if 0
+/**********************************************************************
+ *
+ * deRotatePattern
+ *
+ * Purpose
+ *    Rotate the given pattern if necessary
+ *
+ * Parameters
+ *    [in]
+ *        pPattern  - Pointer to DE_SURFACE structure containing
+ *                    pattern attributes
+ *        patternX  - X position (0-7) of pattern origin
+ *        patternY  - Y position (0-7) of pattern origin
+ *
+ *    [out]
+ *        pattern_dstaddr - Pointer to pre-allocated buffer containing rotated pattern
+ *
+ *
+ **********************************************************************/
+void deRotatePattern(unsigned char* pattern_dstaddr,
+                     unsigned long pattern_src_addr,
+                     unsigned long pattern_BPP,
+                     unsigned long pattern_stride,
+                     int patternX,
+                     int patternY)
+{
+    unsigned int i;
+    unsigned long pattern_read_addr;
+    unsigned long pattern[PATTERN_WIDTH * PATTERN_HEIGHT];
+    unsigned int x, y;
+	unsigned char* pjPatByte;
+
+    if (pattern_dstaddr != NULL)
+    {
+        sm501fb_Wait_Idle();
+        
+        /* Load pattern from local video memory into pattern array */
+        pattern_read_addr = pattern_src_addr;
+        
+        for (i = 0; i < (pattern_BPP * 2); i++)
+        {
+//            pattern[i] = SmRead32m(pattern_read_addr);          bug
+            pattern_read_addr += 4;
+        }
+        
+        if (patternX || patternY)
+        {
+            /* Rotate pattern */
+            pjPatByte = (unsigned char*)pattern;
+            
+            switch (pattern_BPP)
+            {
+            case 8:
+                {
+                    for (y = 0; y < 8; y++)
+                    {
+                        unsigned char* pjBuffer = pattern_dstaddr + ((patternY + y) & 7) * 8;
+                        for (x = 0; x < 8; x++)
+                        {
+                            pjBuffer[(patternX + x) & 7] = pjPatByte[x];
+                        }
+                        pjPatByte += pattern_stride;
+                    }
+                    break;
+                }
+                
+            case 16:
+                {
+                    for (y = 0; y < 8; y++)
+                    {
+                        unsigned short* pjBuffer = (unsigned short*) pattern_dstaddr + ((patternY + y) & 7) * 8;
+                        for (x = 0; x < 8; x++)
+                        {
+                            pjBuffer[(patternX + x) & 7] = ((unsigned short*) pjPatByte)[x];
+                        }
+                        pjPatByte += pattern_stride;
+                    }
+                    break;
+                }
+                
+            case 32:
+                {
+                    for (y = 0; y < 8; y++)
+                    {
+                        unsigned long* pjBuffer = (unsigned long*) pattern_dstaddr + ((patternY + y) & 7) * 8;
+                        for (x = 0; x < 8; x++)
+                        {
+                            pjBuffer[(patternX + x) & 7] = ((unsigned long*) pjPatByte)[x];
+                        }
+                        pjPatByte += pattern_stride;
+                    }
+                    break;
+                }
+            }
+        }
+        else
+        {
+            /* Don't rotate, just copy pattern into pattern_dstaddr */
+            for (i = 0; i < (pattern_BPP * 2); i++)
+            {
+                ((unsigned long *)pattern_dstaddr)[i] = pattern[i];
+            }
+        }
+        
+    }
+}
+
+
+/**********************************************************************
+ *
+ * deMonoPatternFill
+ *
+ * Purpose
+ *    Copy the specified monochrome pattern into the destination surface
+ *
+ * Remarks
+ *       Pattern size must be 8x8 pixel. 
+ *       Pattern color depth must be same as destination bitmap or monochrome.
+**********************************************************************/
+void deMonoPatternFill(unsigned long dst_base,
+                       unsigned long dst_pitch,  
+                       unsigned long dst_BPP,
+                       unsigned long dstX, 
+                       unsigned long dstY,
+                       unsigned long dst_width,
+                       unsigned long dst_height,
+                       unsigned long pattern_FGcolor,
+                       unsigned long pattern_BGcolor,
+                       unsigned long pattern_low, 
+                       unsigned long pattern_high)
+{
+    sm501fb_Wait_Idle();
+    
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+    
+    SmWrite2D(DE_PITCH, FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |  FIELD_VALUE(0, DE_PITCH, SOURCE, dst_pitch));
+    
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+
+    SmWrite2D(DE_FOREGROUND,
+        FIELD_VALUE(0, DE_FOREGROUND, COLOR, pattern_FGcolor));
+
+    SmWrite2D(DE_BACKGROUND,
+        FIELD_VALUE(0, DE_BACKGROUND, COLOR, pattern_BGcolor));
+
+    SmWrite2D(DE_MONO_PATTERN_LOW,
+        FIELD_VALUE(0, DE_MONO_PATTERN_LOW, PATTERN, pattern_low));
+
+    SmWrite2D(DE_MONO_PATTERN_HIGH,
+        FIELD_VALUE(0, DE_MONO_PATTERN_HIGH, PATTERN, pattern_high));
+    
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dstX)      |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dstY));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+    
+    SmWrite2D(DE_CONTROL, 
+        FIELD_VALUE(0, DE_CONTROL, ROP, 0xF0) |
+        FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) |
+        FIELD_SET(0, DE_CONTROL, PATTERN, MONO)  |
+        FIELD_SET(0, DE_CONTROL, STATUS, START));
+
+    sm_accel_busy = 1;
+} /* deMonoPatternFill() */
+
+/**********************************************************************
+ *
+ * deColorPatternFill
+ *
+ * Purpose
+ *    Copy the specified pattern into the destination surface
+ *
+ * Parameters
+ *    [in]
+ *        pDestSurface   - Pointer to DE_SURFACE structure containing
+ *                         destination surface attributes
+ *        nX             - X coordinate of destination surface to be filled
+ *        nY             - Y coordinate of destination surface to be filled
+ *        dst_width         - Width (in pixels) of area to be filled
+ *        dst_height        - Height (in lines) of area to be filled
+ *        pPattern       - Pointer to DE_SURFACE structure containing
+ *                         pattern attributes
+ *        pPatternOrigin - Pointer to Point structure containing pattern origin
+ *        pMonoInfo      - Pointer to mono_pattern_info structure
+ *        pClipRect      - Pointer to Rect structure describing clipping
+ *                         rectangle; NULL if no clipping required
+ *
+ *    [out]
+ *        None
+ *
+ * Remarks
+ *       Pattern size must be 8x8 pixel. 
+ *       Pattern color depth must be same as destination bitmap.
+**********************************************************************/
+void deColorPatternFill(unsigned long dst_base,
+                        unsigned long dst_pitch,  
+                        unsigned long dst_BPP,  
+                        unsigned long dst_X, 
+                        unsigned long dst_Y, 
+                        unsigned long dst_width,
+                        unsigned long dst_height,
+                        unsigned long pattern_src_addr,
+                        unsigned long pattern_stride,
+                        int PatternOriginX,
+                        int PatternOriginY)
+{
+    unsigned int i;
+    unsigned long de_data_port_write_addr;
+    unsigned char ajPattern[PATTERN_WIDTH * PATTERN_HEIGHT * 4];
+    unsigned long de_ctrl = 0;
+    
+    sm501fb_Wait_Idle();
+    
+    de_ctrl = FIELD_SET(0, DE_CONTROL, PATTERN, COLOR);
+    
+    SmWrite2D(DE_CONTROL, de_ctrl);
+    
+    /* Rotate pattern if necessary */
+    deRotatePattern(ajPattern, pattern_src_addr, dst_BPP, pattern_stride, PatternOriginX, PatternOriginY);
+    
+    /* Load pattern to 2D Engine Data Port */
+    de_data_port_write_addr = 0;
+    
+    for (i = 0; i < (dst_BPP * 2); i++)
+    {
+        SmWrite2D_DataPort(de_data_port_write_addr, ((unsigned long *)ajPattern)[i]);
+        de_data_port_write_addr += 4;
+    }
+    
+    sm501fb_Wait_Idle();
+
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+ 
+    SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dst_X)      |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dst_Y));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+    
+    SmWrite2D(DE_CONTROL, 
+        FIELD_VALUE(0, DE_CONTROL, ROP, 0xF0) |
+        FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) |
+        FIELD_SET(0, DE_CONTROL, PATTERN, COLOR) |
+        FIELD_SET(0, DE_CONTROL, STATUS, START));
+
+    sm_accel_busy = 1;
+} /* deColorPatternFill() */
+#endif
+
+#if 0
+/**********************************************************************
+ *
+ * deCopy
+ *
+ * Purpose
+ *    Copy a rectangular area of the source surface to a destination surface
+ *
+ * Remarks
+ *       Source bitmap must have the same color depth (BPP) as the destination bitmap.
+ *
+**********************************************************************/
+void deCopy(unsigned long dst_base,
+            unsigned long dst_pitch,  
+            unsigned long dst_BPP,  
+            unsigned long dst_X, 
+            unsigned long dst_Y, 
+            unsigned long dst_width,
+            unsigned long dst_height,
+            unsigned long src_base, 
+            unsigned long src_pitch,  
+            unsigned long src_X, 
+            unsigned long src_Y, 
+            pTransparent pTransp,
+            unsigned char nROP2)
+{
+    unsigned long nDirection = 0;
+    unsigned long nTransparent = 0;
+    unsigned long opSign = 1;    // Direction of ROP2 operation: 1 = Left to Right, (-1) = Right to Left
+    unsigned long xWidth = 192 / (dst_BPP / 8); // xWidth is in pixels
+    unsigned long de_ctrl = 0;
+    
+    sm501fb_Wait_Idle();
+
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+
+    SmWrite2D(DE_WINDOW_SOURCE_BASE, FIELD_VALUE(0, DE_WINDOW_SOURCE_BASE, ADDRESS, src_base));
+
+    if (dst_pitch && src_pitch)
+    {
+        SmWrite2D(DE_PITCH,
+            FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_PITCH, SOURCE,      src_pitch));
+        
+        SmWrite2D(DE_WINDOW_WIDTH,
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+            FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      src_pitch));
+    }
+    
+    /* Set transparent bits if necessary */
+    if (pTransp != NULL)
+    {
+        nTransparent = pTransp->match | pTransp->select | pTransp->control;
+        
+        /* Set color compare register */
+        SmWrite2D(DE_COLOR_COMPARE,
+            FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, pTransp->color));
+    }
+    
+    /* Determine direction of operation */
+    if (src_Y < dst_Y)
+    {
+    /* +----------+
+    |S         |
+    |   +----------+
+    |   |      |   |
+    |   |      |   |
+    +---|------+   |
+    |         D|
+        +----------+ */
+        
+        nDirection = BOTTOM_TO_TOP;
+    }
+    else if (src_Y > dst_Y)
+    {
+    /* +----------+
+    |D         |
+    |   +----------+
+    |   |      |   |
+    |   |      |   |
+    +---|------+   |
+    |         S|
+        +----------+ */
+        
+        nDirection = TOP_TO_BOTTOM;
+    }
+    else
+    {
+        /* src_Y == dst_Y */
+        
+        if (src_X <= dst_X)
+        {
+        /* +------+---+------+
+        |S     |   |     D|
+        |      |   |      |
+        |      |   |      |
+        |      |   |      |
+            +------+---+------+ */
+            
+            nDirection = RIGHT_TO_LEFT;
+        }
+        else
+        {
+            /* src_X > dst_X */
+            
+            /* +------+---+------+
+            |D     |   |     S|
+            |      |   |      |
+            |      |   |      |
+            |      |   |      |
+            +------+---+------+ */
+            
+            nDirection = LEFT_TO_RIGHT;
+        }
+    }
+    
+    if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT))
+    {
+        src_X += dst_width - 1;
+        src_Y += dst_height - 1;
+        dst_X += dst_width - 1;
+        dst_Y += dst_height - 1;
+        opSign = (-1);
+    }
+    
+    /* Workaround for 192 byte hw bug */
+    if ((nROP2 != 0x0C) && ((dst_width * (dst_BPP / 8)) >= 192))
+    {
+        /* Perform the ROP2 operation in chunks of (xWidth * dst_height) */
+        while (1)
+        {
+            sm501fb_Wait_Idle();
+            SmWrite2D(DE_SOURCE,
+                FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE) |
+                FIELD_VALUE(0, DE_SOURCE, X_K1, src_X)   |
+                FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y));
+            SmWrite2D(DE_DESTINATION,
+                FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+                FIELD_VALUE(0, DE_DESTINATION, X,    dst_X)  |
+                FIELD_VALUE(0, DE_DESTINATION, Y,    dst_Y));
+            SmWrite2D(DE_DIMENSION,
+                FIELD_VALUE(0, DE_DIMENSION, X,    xWidth) |
+                FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+            de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, nROP2) |
+                nTransparent |
+                FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) |
+                FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) |
+                ((nDirection == 1) ? FIELD_SET(0, DE_CONTROL, DIRECTION, RIGHT_TO_LEFT)
+                : FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT)) |
+                FIELD_SET(0, DE_CONTROL, STATUS, START);
+            SmWrite2D(DE_CONTROL, de_ctrl);
+            
+            src_X += (opSign * xWidth);
+            dst_X += (opSign * xWidth);
+            dst_width -= xWidth;
+            
+            if (dst_width <= 0)
+            {
+                /* ROP2 operation is complete */
+                break;
+            }
+            
+            if (xWidth > dst_width)
+            {
+                xWidth = dst_width;
+            }
+        }
+    }
+    else
+    {
+        sm501fb_Wait_Idle();
+        SmWrite2D(DE_SOURCE,
+            FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_SOURCE, X_K1, src_X)   |
+            FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y));
+        SmWrite2D(DE_DESTINATION,
+            FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_DESTINATION, X,    dst_X)  |
+            FIELD_VALUE(0, DE_DESTINATION, Y,    dst_Y));
+        SmWrite2D(DE_DIMENSION,
+            FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+            FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+        de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, nROP2) |
+            nTransparent |
+            FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) |
+            FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) |
+            ((nDirection == 1) ? FIELD_SET(0, DE_CONTROL, DIRECTION, RIGHT_TO_LEFT)
+            : FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT)) |
+            FIELD_SET(0, DE_CONTROL, STATUS, START);
+        SmWrite2D(DE_CONTROL, de_ctrl);
+    }
+
+    sm_accel_busy = 1;
+}
+#endif
+#if 0
+/**********************************************************************
+ *
+ * deSrcCopyHost
+ *
+ * Purpose
+ *    Copy a rectangular area of the source surface in system memory to
+ *    a destination surface in video memory
+ *
+ * Remarks
+ *       Source bitmap must have the same color depth (BPP) as the destination bitmap.
+ *
+**********************************************************************/
+void deSrcCopyHost(unsigned long dst_base, 
+                   unsigned long dst_pitch,  
+                   unsigned long dst_BPP,  
+                   unsigned long dst_X, 
+                   unsigned long dst_Y,
+                   unsigned long dst_width, 
+                   unsigned long dst_height, 
+                   unsigned long src_base, 
+                   unsigned long src_stride,  
+                   unsigned long src_X, 
+                   unsigned long src_Y,
+                   pTransparent pTransp,
+                   unsigned char nROP2)
+{
+    int nBytes_per_scan;
+    int nBytes8_per_scan;
+    int nBytes_remain;
+    int nLong;
+    unsigned long nTransparent = 0;
+    unsigned long de_ctrl = 0;
+    unsigned long i;
+    int j;
+    unsigned long ulSrc;
+    unsigned long de_data_port_write_addr;
+    unsigned char abyRemain[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+    unsigned char *pSrcBuffer;
+    
+    pSrcBuffer = (unsigned char*)(src_base + src_Y * src_stride + src_X * (dst_BPP / 8));
+
+    nBytes_per_scan = dst_width * (dst_BPP / 8);
+    nBytes8_per_scan = (nBytes_per_scan + 7) & ~7;
+    nBytes_remain = nBytes_per_scan & 7;
+    nLong = nBytes_per_scan & ~7;
+    
+    /* Program 2D Drawing Engine */
+    sm501fb_Wait_Idle();
+
+    /* Set transparent bits if necessary */
+    if (pTransp != NULL)
+    {
+        nTransparent = pTransp->match | pTransp->select | pTransp->control;
+        
+        /* Set color compare register */
+        SmWrite2D(DE_COLOR_COMPARE,
+            FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, pTransp->color));
+    }
+    
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+    
+    SmWrite2D(DE_WINDOW_SOURCE_BASE, FIELD_VALUE(0, DE_WINDOW_SOURCE_BASE, ADDRESS, 0));
+    
+    SmWrite2D(DE_SOURCE,
+        FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_SOURCE, X_K1, 0)       |
+        FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y));
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dst_X)  |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dst_Y));
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+    SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_width) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_width));
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_width) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_width));
+    de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, nROP2) |
+        nTransparent |
+        FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) |
+        FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) |
+        FIELD_SET(0, DE_CONTROL, STATUS, START);
+    SmWrite2D(DE_CONTROL, de_ctrl);
+    
+    /* Write bitmap/image data (line by line) to 2D Engine data port */
+    de_data_port_write_addr = 0;
+    
+    for (i = 1; i < dst_height; i++)
+    {
+        for (j = 0; j < (nBytes8_per_scan / 4); j++)
+        {
+            memcpy(&ulSrc, (pSrcBuffer + (j * 4)), 4);
+            SmWrite2D_DataPort(de_data_port_write_addr, ulSrc);
+        }
+        
+        pSrcBuffer += src_stride;
+    }
+    
+    /* Special handling for last line of bitmap */
+    if (nLong)
+    {
+        for (j = 0; j < (nLong / 4); j++)
+        {
+            memcpy(&ulSrc, (pSrcBuffer + (j * 4)), 4);
+            SmWrite2D_DataPort(de_data_port_write_addr, ulSrc);
+        }
+    }
+    
+    if (nBytes_remain)
+    {
+        memcpy(abyRemain, (pSrcBuffer + nLong), nBytes_remain);
+        SmWrite2D_DataPort(de_data_port_write_addr, *(unsigned long*)abyRemain);
+        SmWrite2D_DataPort(de_data_port_write_addr, *(unsigned long*)(abyRemain + 4));
+    }
+
+    sm_accel_busy = 1;
+}
+
+
+/**********************************************************************
+ *
+ * deMonoSrcCopyHost
+ *
+ * Purpose
+ *    Copy a rectangular area of the monochrome source surface in 
+ *    system memory to a destination surface in video memory
+ *
+ * Parameters
+ *    [in]
+ *        pSrcSurface  - Pointer to DE_SURFACE structure containing
+ *                       source surface attributes
+ *        pSrcBuffer   - Pointer to source buffer (system memory)
+ *                       containing monochrome image
+ *        src_X        - X coordinate of source surface
+ *        src_Y        - Y coordinate of source surface
+ *        pDestSurface - Pointer to DE_SURFACE structure containing
+ *                       destination surface attributes
+ *        dst_X       - X coordinate of destination surface
+ *        dst_Y       - Y coordinate of destination surface
+ *        dst_width       - Width (in pixels) of the area to be copied
+ *        dst_height      - Height (in lines) of the area to be copied
+ *        nFgColor     - Foreground color
+ *        nBgColor     - Background color
+ *        pClipRect    - Pointer to Rect structure describing clipping
+ *                       rectangle; NULL if no clipping required
+ *        pTransp      - Pointer to Transparent structure containing
+ *                       transparency settings; NULL if no transparency
+ *                       required
+ *
+ *    [out]
+ *        None
+ *
+ * Returns
+ *    DDK_OK                      - function is successful
+ *    DDK_ERROR_NULL_PSRCSURFACE  - pSrcSurface is NULL
+ *    DDK_ERROR_NULL_PDESTSURFACE - pDestSurface is NULL
+ *
+**********************************************************************/
+void deMonoSrcCopyHost(unsigned long dst_base, 
+                      unsigned long dst_pitch,  
+                      unsigned long dst_BPP,  
+                      unsigned long dst_X, 
+                      unsigned long dst_Y,
+                      unsigned long dst_width, 
+                      unsigned long dst_height, 
+                      unsigned long src_base, 
+                      unsigned long src_stride,  
+                      unsigned long src_X, 
+                      unsigned long src_Y,
+                      unsigned long nFgColor, 
+                      unsigned long nBgColor,
+                      pTransparent pTransp)
+{
+    int nLeft_bits_off;
+    int nBytes_per_scan;
+    int nBytes4_per_scan;
+    int nBytes_remain;
+    int nLong;
+    unsigned long nTransparent = 0;
+    unsigned long de_ctrl = 0;
+    unsigned long de_data_port_write_addr;
+    unsigned long i;
+    int j;
+	unsigned long ulSrc;
+    unsigned char * pSrcBuffer;
+
+    pSrcBuffer = (unsigned char *)src_base+(src_Y * src_stride) + (src_X / 8);
+    nLeft_bits_off = (src_X & 0x07);
+    nBytes_per_scan = (dst_width + nLeft_bits_off + 7) / 8;
+    nBytes4_per_scan = (nBytes_per_scan + 3) & ~3;
+    nBytes_remain = nBytes_per_scan & 3;
+    nLong = nBytes_per_scan & ~3;
+
+    sm501fb_Wait_Idle();
+    
+    /* Set transparent bits if necessary */
+    if (pTransp != NULL)
+    {
+        nTransparent = pTransp->match | pTransp->select | pTransp->control;
+        
+        /* Set color compare register */
+        SmWrite2D(DE_COLOR_COMPARE,
+            FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, pTransp->color));
+    }
+    
+    /* Program 2D Drawing Engine */
+
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, dst_base));
+
+    SmWrite2D(DE_WINDOW_SOURCE_BASE, FIELD_VALUE(0, DE_WINDOW_SOURCE_BASE, ADDRESS, 0));
+
+    SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      dst_pitch));
+    
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, dst_pitch) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      dst_pitch));
+
+    SmWrite2D(DE_SOURCE,
+        FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE)        |
+        FIELD_VALUE(0, DE_SOURCE, X_K1, nLeft_bits_off) |
+        FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y));
+
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dst_X)  |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dst_Y));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    dst_width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height));
+
+    SmWrite2D(DE_FOREGROUND,
+        FIELD_VALUE(0, DE_FOREGROUND, COLOR, nFgColor));
+
+    SmWrite2D(DE_BACKGROUND,
+        FIELD_VALUE(0, DE_BACKGROUND, COLOR, nBgColor));
+    
+    de_ctrl = 0x0000000C |
+        FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) |
+        FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) |
+        FIELD_SET(0, DE_CONTROL, HOST, MONO) |
+        nTransparent |
+        FIELD_SET(0, DE_CONTROL, STATUS, START);
+    SmWrite2D(DE_CONTROL, de_ctrl);
+    
+    /* Write bitmap/image data (line by line) to 2D Engine data port */
+    de_data_port_write_addr = 0;
+    
+    for (i = 1; i < dst_height; i++)
+    {
+        for (j = 0; j < (nBytes4_per_scan / 4); j++)
+        {
+            memcpy(&ulSrc, (pSrcBuffer + (j * 4)), 4);
+            SmWrite2D_DataPort(de_data_port_write_addr, ulSrc);
+        }
+        
+        pSrcBuffer += src_stride;
+    }
+    
+    /* Special handling for last line of bitmap */
+    if (nLong)
+    {
+        for (j = 0; j < (nLong / 4); j++)
+        {
+            memcpy(&ulSrc, (pSrcBuffer + (j * 4)), 4);
+            SmWrite2D_DataPort(de_data_port_write_addr, ulSrc);
+        }
+    }
+    
+    if (nBytes_remain)
+    {
+        memcpy(&ulSrc, (pSrcBuffer + nLong), nBytes_remain);
+        SmWrite2D_DataPort(de_data_port_write_addr, ulSrc);
+    }
+
+    sm_accel_busy = 1;
+}
+/**********************************************************************
+*
+ * Misc. functions
+ *
+ **********************************************************************/
+// Load 8x8 pattern into local video memory
+void deLoadPattern(unsigned char* pattern, unsigned long write_addr)
+{
+    int i;
+
+    for (i = 0; i < (8 * 8 * 2); i += 4)
+    {
+//        SmWrite32m(write_addr, *(unsigned long*)(&pattern[i]));    bug
+        write_addr += 4;
+    }
+}
+#endif
+
+/*
+ * System memory to Video memory monochrome expansion.
+ * Source is monochrome image in system memory.
+ * This function expands the monochrome data to color image in video memory.
+ */
+long deSystemMem2VideoMemMonoBlt(
+unsigned char *pSrcbuf, /* pointer to start of source buffer in system memory */
+long srcDelta,          /* Pitch value (in bytes) of the source buffer, +ive means top down and -ive mean button up */
+unsigned long startBit, /* Mono data can start at any bit in a byte, this value should be 0 to 7 */
+unsigned long dBase,    /* Address of destination: offset in frame buffer */
+unsigned long dPitch,   /* Pitch value of destination surface in BYTE */
+unsigned long bpp,      /* Color depth of destination surface */
+unsigned long dx,
+unsigned long dy,       /* Starting coordinate of destination surface */
+unsigned long width, 
+unsigned long height,   /* width and height of rectange in pixel value */
+unsigned long fColor,   /* Foreground color (corresponding to a 1 in the monochrome data */
+unsigned long bColor,   /* Background color (corresponding to a 0 in the monochrome data */
+unsigned long rop2)     /* ROP value */
+{
+    unsigned long bytePerPixel;
+    unsigned long ulBytesPerScan;
+    unsigned long ul4BytesPerScan;
+    unsigned long ulBytesRemain;
+    unsigned long de_ctrl = 0;
+    unsigned char ajRemain[4];
+    long i, j;
+
+    bytePerPixel = bpp/8;
+
+    startBit &= 7; /* Just make sure the start bit is within legal range */
+    ulBytesPerScan = (width + startBit + 7) / 8;
+    ul4BytesPerScan = ulBytesPerScan & ~3;
+    ulBytesRemain = ulBytesPerScan & 3;
+
+
+	sm501fb_Wait_Idle();
+    
+    /* 2D Source Base.
+       Use 0 for HOST Blt.
+    */
+    SmWrite2D(DE_WINDOW_SOURCE_BASE, 0);
+
+    /* 2D Destination Base.
+       It is an address offset (128 bit aligned) from the beginning of frame buffer.
+    */
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, dBase);
+
+    /* Program pitch (distance between the 1st points of two adjacent lines).
+       Note that input pitch is BYTE value, but the 2D Pitch register uses
+       pixel values. Need Byte to pixel convertion.
+    */
+
+#if 1
+    	SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, dPitch/bytePerPixel) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      dPitch/bytePerPixel));
+#else
+    	SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, width*bpp/8) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,     width/8));
+#endif
+    /* Screen Window width in Pixels.
+       2D engine uses this value to calculate the linear address in frame buffer for a given point.
+    */
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, (dPitch/bytePerPixel)) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      (dPitch/bytePerPixel)));
+
+    /* Note: For 2D Source in Host Write, only X_K1 field is needed, and Y_K2 field is not used.
+             For mono bitmap, use startBit for X_K1. */
+    SmWrite2D(DE_SOURCE,
+        FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE)  |
+        FIELD_VALUE(0, DE_SOURCE, X_K1, startBit) |
+        FIELD_VALUE(0, DE_SOURCE, Y_K2, 0));
+
+    SmWrite2D(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dx)    |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dy));
+
+    SmWrite2D(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, height));
+
+    SmWrite2D(DE_FOREGROUND, fColor);
+    SmWrite2D(DE_BACKGROUND, bColor);
+    
+
+	
+    de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, rop2)         |
+              FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2)    |
+              FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) |
+              FIELD_SET(0, DE_CONTROL, HOST, MONO)          |
+              FIELD_SET(0, DE_CONTROL, STATUS, START);
+
+    SmWrite2D(DE_CONTROL, de_ctrl);
+
+    /* Write MONO data (line by line) to 2D Engine data port */
+    for (i=0; i<height; i++)
+    {
+        /* For each line, send the data in chunks of 4 bytes */
+        for (j=0; j<(ul4BytesPerScan/4); j++)
+        {
+            SmWrite32(DE_DATA_PORT, *(unsigned long *)(pSrcbuf + (j * 4)));
+        }
+
+        if (ulBytesRemain)
+        {
+            memcpy(ajRemain, pSrcbuf+ul4BytesPerScan, ulBytesRemain);
+            SmWrite32(DE_DATA_PORT, *(unsigned long *)ajRemain);
+        }
+
+        pSrcbuf += srcDelta;
+    }
+	
+    	return 0;
+}
+
+/* 
+ * System memory to Video memory data transfer
+ * Note: 
+ *         We also call it HOST Blt.
+ *        This function is a one to one transfer without stretching or 
+ *        mono expansion.
+ */
+ #if 0
+long deSystemMem2VideoMemBlt(
+unsigned char *pSrcbuf, /* pointer to source data in system memory */
+long srcDelta,          /* width (in Bytes) of the source data, +ive means top down and -ive mean button up */
+unsigned long dBase,    /* Address of destination: offset in frame buffer */
+unsigned long dPitch,   /* Pitch value of destination surface in BYTE */
+unsigned long bpp,      /* Color depth of destination surface */
+unsigned long dx,
+unsigned long dy,       /* Starting coordinate of destination surface */
+unsigned long width, 
+unsigned long height,   /* width and height of rectange in pixel value */
+unsigned long rop2)     /* ROP value */
+{
+    unsigned long bytePerPixel;
+    unsigned long ulBytesPerScan;
+    unsigned long ul8BytesPerScan;
+    unsigned long ulBytesRemain;
+    unsigned long de_ctrl = 0;
+    unsigned char ajRemain[8];
+    long i, j;
+
+    bytePerPixel = bpp/8;
+
+    /* HOST blt data port must take multiple of 8 bytes as input.
+       If the source width does not match that requirement,
+       we need to split it into two portions. The first portion
+       is 8 byte multiple. The 2nd portion is the remaining bytes.
+       The remaining bytes will be buffered to an 8 byte array and
+       and send it to the host blt data port.
+    */
+    ulBytesPerScan = width * bpp / 8;
+    ul8BytesPerScan = ulBytesPerScan & ~7;
+    ulBytesRemain = ulBytesPerScan & 7;
+
+    /* Program 2D Drawing Engine */
+    if (deWaitForNotBusy() != 0)
+    {
+        /* The 2D engine is always busy for some unknown reason.
+           Application can choose to return ERROR, or reset it and
+           continue the operation.
+        */
+
+        return -1;
+
+        /* or */
+        /* deReset(); */
+    }
+
+    /* 2D Source Base.
+       Use 0 for HOST Blt.
+    */
+    POKE_32(DE_WINDOW_SOURCE_BASE, 0);
+
+    /* 2D Destination Base.
+       It is an address offset (128 bit aligned) from the beginning of frame buffer.
+    */
+    POKE_32(DE_WINDOW_DESTINATION_BASE, dBase);
+
+    /* Program pitch (distance between the 1st points of two adjacent lines).
+       Note that input pitch is BYTE value, but the 2D Pitch register uses
+       pixel values. Need Byte to pixel convertion.
+    */
+    POKE_32(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, dPitch/bytePerPixel) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      dPitch/bytePerPixel));
+
+    /* Screen Window width in Pixels.
+       2D engine uses this value to calculate the linear address in frame buffer for a given point.
+    */
+    POKE_32(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, (dPitch/bytePerPixel)) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      (dPitch/bytePerPixel)));
+
+    /* Note: For 2D Source in Host Write, only X_K1 field is needed, and Y_K2 field is not used.
+             For 1 to 1 bitmap transfer, use 0 for X_K1 means source alignment from byte 0. */
+    POKE_32(DE_SOURCE,
+        FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_SOURCE, X_K1, 0)       |
+        FIELD_VALUE(0, DE_SOURCE, Y_K2, 0));
+
+    POKE_32(DE_DESTINATION,
+        FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+        FIELD_VALUE(0, DE_DESTINATION, X,    dx)    |
+        FIELD_VALUE(0, DE_DESTINATION, Y,    dy));
+
+    POKE_32(DE_DIMENSION,
+        FIELD_VALUE(0, DE_DIMENSION, X,    width) |
+        FIELD_VALUE(0, DE_DIMENSION, Y_ET, height));
+        
+    /* Set the pixel format of the destination */
+    deSetPixelFormat(bpp);
+
+   
+        FIELD_VALUE(0, DE_CONTROL, ROP, rop2)         |
+        FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2)    |
+        FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) |
+        FIELD_SET(0, DE_CONTROL, HOST, COLOR)         |
+        FIELD_SET(0, DE_CONTROL, STATUS, START);
+
+    POKE_32(DE_CONTROL, de_ctrl | deGetTransparency());
+
+    /* Write bitmap/image data (line by line) to 2D Engine data port */
+    for (i = 0; i < height; i++)
+    {
+        /* For each line, send the data in chunks of 4 bytes. */
+        for (j=0; j < (ul8BytesPerScan/4);  j++)
+            POKE_32(DE_DATA_PORT, *(unsigned long *)(pSrcbuf + (j * 4)));
+
+        if (ulBytesRemain)
+        {
+            memcpy(ajRemain, pSrcbuf+ul8BytesPerScan, ulBytesRemain);
+            POKE_32(DE_DATA_PORT, *(unsigned long *)ajRemain);
+            POKE_32(DE_DATA_PORT, *(unsigned long *)(ajRemain+4));
+        }
+
+        pSrcbuf += srcDelta;
+    }
+
+    return 0;
+}
+#endif
+
+#if 0
+void sm_imageblt(struct fb_info *info, const struct fb_image *image)
+{
+	ulong fgcolor,bgcolor;
+	struct sm501fb_par *p = (struct sm501fb_par*)info->par;
+
+	//if (info->state != FBINFO_STATE_RUNNING)
+	//	return;
+	
+	//if (info->fbops->fb_sync)
+	//	info->fbops->fb_sync(info);
+
+	sm501fb_Wait_Idle();
+	
+
+	if(image->depth==1)
+	{
+		if (info->fix.visual == FB_VISUAL_TRUECOLOR ||info->fix.visual == FB_VISUAL_DIRECTCOLOR) 
+		{
+			fgcolor = ((u32*)(info->pseudo_palette))[image->fg_color];
+			bgcolor = ((u32*)(info->pseudo_palette))[image->bg_color];
+		} 
+		else
+		{
+			fgcolor = image->fg_color;
+			bgcolor = image->bg_color;
+		}	
+		 deSystemMem2VideoMemMonoBlt(	
+		 	image->data,                                                 /* pointer to start of source buffer in system memory */
+		 	image->width/8,                                            /* Pitch value (in bytes) of the source buffer, +ive means top down and -ive mean button up */
+		 	0,                                                                     /* Mono data can start at any bit in a byte, this value should be 0 to 7 */				
+		 	p->screen.sm_addr,                                       /* Address of destination: offset in frame buffer */			 	
+		 	info->fix.line_length,                                   /* Pitch value of destination surface in BYTE */
+		 	info->var.bits_per_pixel,                                /* Color depth of destination surface */				
+		 	image->dx,		                                        /* Starting coordinate of destination surface */
+		 	image->dy,                   				
+		 	image->width, 	                                        /* width and height of rectange in pixel value */		
+		 	image->height,             				
+		 	fgcolor,                                                              /* Foreground color (corresponding to a 1 in the monochrome data */				
+		 	bgcolor,                                                             /* Background color (corresponding to a 0 in the monochrome data */				
+		 	0x0C		 	
+		 	);		 
+	}
+	else
+	{
+		cfb_imageblit(info,image);
+	}
+	sm_accel_busy = 1;	
+}
+#endif
+
+
+/*
+ * Video Memory to Video Memory data transfer.
+ * Note: 
+ *        It works whether the Video Memroy is off-screeen or on-screen.
+ *        This function is a one to one transfer without stretching or 
+ *        mono expansion.
+ */
+long deVideoMem2VideoMemBlt(
+unsigned long sBase,  /* Address of source: offset in frame buffer */
+unsigned long sPitch, /* Pitch value of source surface in BYTE */
+unsigned long sx,
+unsigned long sy,     /* Starting coordinate of source surface */
+unsigned long dBase,  /* Address of destination: offset in frame buffer */
+unsigned long dPitch, /* Pitch value of destination surface in BYTE */
+unsigned long bpp,    /* Color depth of destination surface */
+unsigned long dx,
+unsigned long dy,     /* Starting coordinate of destination surface */
+unsigned long width, 
+unsigned long height, /* width and height of rectangle in pixel value */
+unsigned long rop2)   /* ROP value */
+{
+    unsigned long nDirection, de_ctrl, bytePerPixel;
+    long opSign;
+
+
+    nDirection = LEFT_TO_RIGHT;
+    opSign = 1;    /* Direction of ROP2 operation: 1 = Left to Right, (-1) = Right to Left */
+    bytePerPixel = bpp/8;
+    de_ctrl = 0;
+
+    /* If source and destination are the same surface, need to check for overlay cases */
+    if (sBase == dBase && sPitch == dPitch)
+    {
+        /* Determine direction of operation */
+        if (sy < dy)
+        {
+            /* +----------+
+               |S         |
+               |   +----------+
+               |   |      |   |
+               |   |      |   |
+               +---|------+   |
+                   |         D|
+                   +----------+ */
+    
+            nDirection = BOTTOM_TO_TOP;
+        }
+        else if (sy > dy)
+        {
+            /* +----------+
+               |D         |
+               |   +----------+
+               |   |      |   |
+               |   |      |   |
+               +---|------+   |
+                   |         S|
+                   +----------+ */
+    
+            nDirection = TOP_TO_BOTTOM;
+        }
+        else
+        {
+            /* sy == dy */
+    
+            if (sx <= dx)
+            {
+                /* +------+---+------+
+                   |S     |   |     D|
+                   |      |   |      |
+                   |      |   |      |
+                   |      |   |      |
+                   +------+---+------+ */
+    
+                nDirection = RIGHT_TO_LEFT;
+            }
+            else
+            {
+                /* sx > dx */
+    
+                /* +------+---+------+
+                   |D     |   |     S|
+                   |      |   |      |
+                   |      |   |      |
+                   |      |   |      |
+                   +------+---+------+ */
+    
+                nDirection = LEFT_TO_RIGHT;
+            }
+        }
+    }
+
+    if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT))
+    {
+        sx += width - 1;
+        sy += height - 1;
+        dx += width - 1;
+        dy += height - 1;
+        opSign = (-1);
+    }
+
+    /* Note:
+       DE_FOREGROUND are DE_BACKGROUND are don't care.
+       DE_COLOR_COMPARE and DE_COLOR_COMPARE_MAKS are set by set deSetTransparency().
+    */
+
+    /* 2D Source Base.
+       It is an address offset (128 bit aligned) from the beginning of frame buffer.
+    */
+    SmWrite2D(DE_WINDOW_SOURCE_BASE, sBase);
+
+    /* 2D Destination Base.
+       It is an address offset (128 bit aligned) from the beginning of frame buffer.
+    */
+    SmWrite2D(DE_WINDOW_DESTINATION_BASE, dBase);
+
+    /* Program pitch (distance between the 1st points of two adjacent lines).
+       Note that input pitch is BYTE value, but the 2D Pitch register uses
+       pixel values. Need Byte to pixel convertion.
+    */
+    SmWrite2D(DE_PITCH,
+        FIELD_VALUE(0, DE_PITCH, DESTINATION, (dPitch/bytePerPixel)) |
+        FIELD_VALUE(0, DE_PITCH, SOURCE,      (sPitch/bytePerPixel)));
+
+    /* Screen Window width in Pixels.
+       2D engine uses this value to calculate the linear address in frame buffer for a given point.
+    */
+    SmWrite2D(DE_WINDOW_WIDTH,
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, (dPitch/bytePerPixel)) |
+        FIELD_VALUE(0, DE_WINDOW_WIDTH, SOURCE,      (sPitch/bytePerPixel)));
+
+	sm501fb_Wait_Idle();
+
+        SmWrite2D(DE_SOURCE,
+            FIELD_SET  (0, DE_SOURCE, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_SOURCE, X_K1, sx)   |
+            FIELD_VALUE(0, DE_SOURCE, Y_K2, sy));
+        SmWrite2D(DE_DESTINATION,
+            FIELD_SET  (0, DE_DESTINATION, WRAP, DISABLE) |
+            FIELD_VALUE(0, DE_DESTINATION, X,    dx)  |
+            FIELD_VALUE(0, DE_DESTINATION, Y,    dy));
+        SmWrite2D(DE_DIMENSION,
+            FIELD_VALUE(0, DE_DIMENSION, X,    width) |
+            FIELD_VALUE(0, DE_DIMENSION, Y_ET, height));
+
+        de_ctrl = 
+            FIELD_VALUE(0, DE_CONTROL, ROP, rop2) |
+            FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) |
+            FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) |
+            ((nDirection == RIGHT_TO_LEFT) ? 
+            FIELD_SET(0, DE_CONTROL, DIRECTION, RIGHT_TO_LEFT)
+            : FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT)) |
+            FIELD_SET(0, DE_CONTROL, STATUS, START);
+		
+		SmWrite2D(DE_CONTROL,de_ctrl);
+
+    	return 0;
+}
+
+
diff -uNra linux-2.6.27.6/drivers/video/sm501fb.c linux-2.6.27.6.yaffs/drivers/video/sm501fb.c
--- linux-2.6.27.6/drivers/video/sm501fb.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/drivers/video/sm501fb.c	2011-05-08 18:00:52.000000000 +0800
@@ -1,16 +1,27 @@
 /* linux/drivers/video/sm501fb.c
  *
+ * Copyright (C) 2010 SiliconMotion Inc.
  * Copyright (c) 2006 Simtec Electronics
  *	Vincent Sanders <vince@simtec.co.uk>
  *	Ben Dooks <ben@simtec.co.uk>
+ *	Boyod.yang,  <boyod.yang@siliconmotion.com.cn>
+ *    Teddy.wang,  <teddy.wang@siliconmotion.com>
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public
+ * License version 2 or later as published by the Free Software Foundation.  
  *
- * Framebuffer driver for the Silicon Motion SM501
+ * Framebuffer driver for the Silicon Motion SM50X/SM107
  */
 
+// #define DEBUG
+
+#ifdef DEBUG
+#define smdbg(format, arg...)	printk(KERN_DEBUG format , ## arg)
+#else
+#define smdbg(format, arg...)
+#endif
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
@@ -38,25 +49,221 @@
 #include <linux/pm.h>
 #endif
 
+#include <linux/screen_info.h>
+
 #include <linux/sm501.h>
-#include <linux/sm501-regs.h>
+#include <linux/sm501_regs.h>
+
+#define SM501_MEMF_CURSOR		(1)
+#define SM501_MEMF_PANEL		(2)
+#define SM501_MEMF_CRT			(4)
+#define SM501_MEMF_ACCEL		(8)
+
+#define DEFAULT_MODE "1368x768-16@60"
+
+
+/*
+ * globals
+ */
+ 
+static char *mode_option __devinitdata = DEFAULT_MODE;
+static int noaccel = 0;
+static int nofr = 0;
+static int noca = 0;
+static int noib = 0;
+static int mirror = 0;
+static int dcolor = 0;
+static int nomtrr = 1;
+static int gen = 0;
+
+typedef enum _spolarity_t
+{
+    POS, /* positive */
+    NEG, /* negative */
+}
+spolarity_t;
+
+typedef struct _mode_parameter_t
+{
+    /* Horizontal timing. */
+    unsigned long horizontal_total;
+    unsigned long horizontal_display_end;
+    unsigned long horizontal_sync_start;
+    unsigned long horizontal_sync_width;
+    spolarity_t horizontal_sync_polarity;
+
+    /* Vertical timing. */
+    unsigned long vertical_total;
+    unsigned long vertical_display_end;
+    unsigned long vertical_sync_start;
+    unsigned long vertical_sync_height;
+    spolarity_t vertical_sync_polarity;
+
+    /* Refresh timing. */
+    unsigned long pixel_clock;
+    unsigned long horizontal_frequency;
+    unsigned long vertical_frequency;
+    
+    /* Clock Phase. This clock phase only applies to Panel. */
+    spolarity_t clock_phase_polarity;
+}mode_parameter_t;
+
+#include "sm2d.c"
+
+/*
+ *  Timing parameter for some popular modes.
+ *  Note that this table is made according to standard VESA parameters for the
+ *  popular modes.
+ */
+static mode_parameter_t gModeParamTable[] =
+{
+/* 320 x 240 */
+ { 352, 320, 335,  8, NEG, 265, 240, 254, 2, NEG,  5600000, 15909, 60, NEG},
+
+/* 400 x 300 */
+ { 528, 400, 420, 64, NEG, 314, 300, 301, 2, NEG,  9960000, 18864, 60, NEG},
+
+/* 640 x 480  [4:3] */
+ { 800, 640, 656, 96, NEG, 525, 480, 490, 2, NEG, 25175000, 31500, 60, NEG},
+ { 840, 640, 680, 64, NEG, 500, 480, 481, 3, NEG, 31500000, 37500, 75, NEG},
+ { 832, 640, 700, 56, NEG, 509, 480, 481, 3, NEG, 36000000, 43269, 85, NEG},
+
+/* 720 x 480  [3:2] */
+ { 889, 720, 738,108, POS, 525, 480, 490, 2, NEG, 28000000, 31496, 60, NEG},
+
+/* 720 x 540  [4:3] */
+ { 886, 720, 740, 96, POS, 576, 540, 545, 2, POS, 30600000, 34537, 60, NEG},
+
+/* 800 x 480  [5:3] */
+ { 973, 800, 822, 56, POS, 524, 480, 490, 2, NEG, 30600000, 31449, 60, NEG},
+
+/* 800 x 600  [4:3] */
+ {1062, 800, 840,128, POS, 628, 600, 601, 4, POS, 40000000, 37665, 60, NEG},
+ {1056, 800, 816, 80, POS, 625, 600, 601, 3, POS, 49500000, 46875, 75, NEG},
+ {1054, 800, 842, 64, POS, 625, 600, 601, 3, POS, 56000000, 53131, 85, NEG},
+
+/* 960 x 720  [4:3] */
+ {1245, 960, 992, 64, POS, 750, 720, 721, 3, POS, 56000000, 44980, 60, NEG},
+      
+/* 1024 x 600  [16:9] 1.7 */
+ {1313,1024,1064,104, POS, 622, 600, 601, 3, POS, 49000000, 37319, 60, NEG},
+     
+/* 1024 x 768  [4:3] */
+ {1340,1024,1060,136, NEG, 809, 768, 772, 6, NEG, 65000000, 48507, 60, NEG},
+ {1337,1024,1072, 96, NEG, 808, 768, 780, 3, NEG, 81000000, 60583, 75, POS},
+ {1376,1024,1070, 96, POS, 808, 768, 769, 3, POS, 94500000, 68677, 85, POS},
+  
+/* 1152 x 864  [4:3] */
+ {1475,1152,1208, 96, NEG, 888, 864, 866, 3, NEG, 78600000, 53288, 60, POS},
+
+/* 1280 x 768  [5:3] */
+ {1678,1280,1350,136, POS, 795, 768, 769, 3, POS, 80000000, 47676, 60, POS},
+
+/* 1280 x 800  [8:5] */
+ {1650,1280,1344,136, NEG, 824, 800, 800, 3, NEG, 81600000, 49455, 60, POS},
+
+/* 1280 x 960  [4:3] */
+ {1618,1280,1330, 96, NEG, 977, 960, 960, 2, NEG, 94500000, 59259, 60, POS},
+    
+/* 1280 x 1024 [5:4] */
+ {1626,1280,1332,112, POS,1046,1024,1024, 2, POS,102000000, 62731, 60, POS},
+
+/* 1366 x 768  [16:9] */
+ {1722,1366,1424,112, NEG, 784, 768, 769, 3, NEG, 81000000, 47038, 60, POS},
+
+/* 1600 x 1200 [4:3] */
+/* Not supported yet.
+ {2160,1600,1724,112, NEG,1220,1200,1200, 2, NEG,158000000, 73148, 60, POS},
+ */
+
+/* End of table. */
+ { 0, 0, 0, 0, NEG, 0, 0, 0, 0, NEG, 0, 0, 0, NEG},
+};
+
+static struct fb_var_screeninfo __devinitdata sm50xfb_default_var = {
+	.xres = 640,
+	.yres = 480,
+	.xres_virtual = 640,
+	.yres_virtual = 480,
+	.bits_per_pixel = 8,
+	.red = {0, 8, 0},
+	.green = {0, 8, 0},
+	.blue = {0, 8, 0},
+	.transp = {0, 0, 0},
+	.activate = FB_ACTIVATE_NOW,
+	.height = -1,
+	.width = -1,
+	.pixclock = 39721,
+	.left_margin = 40,
+	.right_margin = 24,
+	.upper_margin = 32,
+	.lower_margin = 11,
+	.hsync_len = 96,
+	.vsync_len = 2,
+	.vmode = FB_VMODE_NONINTERLACED
+};
+
+
+static const struct fb_videomode SM501modedb[] = {	
+	/* 10 800x600-75 VESA */  /*added by caesar*/
+	{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+	/* 15 1024x768-75 VESA */	/*added by caesar*/
+	{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 2, 96, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+	/* 16 1024x768-85 VESA */
+	{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+	  /* 20 1280x1024-60 VESA */
+	{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,  //9259
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+	  /* 21 1280x1024-75 VESA */
+	{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+	/* 22 1280x1024-85 VESA */
+	{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+	
+        /* 34 1024x600-60 VESA */
+        {NULL,  60, 1024, 600, 20423, 144,  40, 18, 1, 104, 3,
+         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+        /*35 1024x600-70 VESA */
+        {NULL,  70, 1024, 600, 17211, 152,  48, 21, 1, 104, 3,
+         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+        /* 36 1024x600-75 VESA */
+        {NULL,  75, 1024, 600, 15822, 160,  56, 23, 1, 104, 3,
+         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+        /* 37 1024x600-85 VESA */
+        {NULL,  85, 1024, 600, 13730, 168,  56, 26, 1, 112, 3,
+         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+	 /*720x480*/
+        {NULL, 60,  720,  480,  37427, 88,   16, 13, 1,   72,  3,
+        FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+	/* 1368 x 768  Pixel Clock=75hz for lemote*/     
+        {NULL, 60,  1368,  768,  13333, 216, 72, 23, 1,   144,  3,
+        FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},        
+
+};
+
 
 #define NR_PALETTE	256
+#define PANEL_CRT_ADDR	0x400000
 
 enum sm501_controller {
 	HEAD_CRT	= 0,
 	HEAD_PANEL	= 1,
 };
 
-/* SM501 memory address.
- *
- * This structure is used to track memory usage within the SM501 framebuffer
- * allocation. The sm_addr field is stored as an offset as it is often used
- * against both the physical and mapped addresses.
- */
+/* SM501 memory adress */
 struct sm501_mem {
 	unsigned long	 size;
-	unsigned long	 sm_addr;	/* offset from base of sm501 fb. */
+	unsigned long	 sm_addr;
 	void __iomem	*k_addr;
 };
 
@@ -71,7 +278,6 @@
 	unsigned long		 pm_crt_ctrl;	/* pm: crt ctrl save */
 
 	int			 irq;
-	int			 swap_endian;	/* set to swap rgb=>bgr */
 	void __iomem		*regs;		/* remapped registers */
 	void __iomem		*fbmem;		/* remapped framebuffer */
 	size_t			 fbmem_len;	/* length of remapped region */
@@ -106,6 +312,35 @@
 		var->lower_margin + var->vsync_len;
 }
 
+/*
+ *  Locate in-stock parameter table for the requested mode.
+ *  Success: return a pointer to the mode_parameter_t entry.
+ *  Fail: a NULL pointer.
+ *
+ */
+mode_parameter_t *findVesaModeParam(
+unsigned long width, 
+unsigned long height, 
+unsigned long refresh_rate)
+{
+    mode_parameter_t *mode_table = gModeParamTable;
+
+    /* Walk the entire mode table. */
+    while (mode_table->pixel_clock != 0)
+    {
+        if ((mode_table->horizontal_display_end == width)
+        && (mode_table->vertical_display_end == height)
+        && (mode_table->vertical_frequency == refresh_rate))
+        {
+            return(mode_table);
+        }
+        mode_table++; /* Next entry */
+    }
+
+    /* No match, return NULL pointer */
+    return((mode_parameter_t *)0);
+}
+
 /* sm501fb_sync_regs()
  *
  * This call is mainly for PCI bus systems where we need to
@@ -115,9 +350,10 @@
 
 static inline void sm501fb_sync_regs(struct sm501fb_info *info)
 {
-	readl(info->regs);
+	SmRead32(0);
 }
 
+
 /* sm501_alloc_mem
  *
  * This is an attempt to lay out memory for the two framebuffers and
@@ -139,76 +375,36 @@
  *
  */
 
-#define SM501_MEMF_CURSOR		(1)
-#define SM501_MEMF_PANEL		(2)
-#define SM501_MEMF_CRT			(4)
-#define SM501_MEMF_ACCEL		(8)
-
 static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
 			   unsigned int why, size_t size)
 {
-	struct sm501fb_par *par;
-	struct fb_info *fbi;
-	unsigned int ptr;
-	unsigned int end;
+	unsigned int ptr = 0;
 
 	switch (why) {
 	case SM501_MEMF_CURSOR:
 		ptr = inf->fbmem_len - size;
-		inf->fbmem_len = ptr;	/* adjust available memory. */
+		inf->fbmem_len = ptr;
 		break;
 
 	case SM501_MEMF_PANEL:
+/*
 		ptr = inf->fbmem_len - size;
-		fbi = inf->fb[HEAD_CRT];
-
-		/* round down, some programs such as directfb do not draw
-		 * 0,0 correctly unless the start is aligned to a page start.
-		 */
-
-		if (ptr > 0)
-			ptr &= ~(PAGE_SIZE - 1);
-
-		if (fbi && ptr < fbi->fix.smem_len)
-			return -ENOMEM;
-
-		if (ptr < 0)
+		if (ptr < inf->fb[0]->fix.smem_len)
 			return -ENOMEM;
-
+*/		ptr = 0x0;
 		break;
 
 	case SM501_MEMF_CRT:
-		ptr = 0;
-
-		/* check to see if we have panel memory allocated
-		 * which would put an limit on available memory. */
-
-		fbi = inf->fb[HEAD_PANEL];
-		if (fbi) {
-			par = fbi->par;
-			end = par->screen.k_addr ? par->screen.sm_addr : inf->fbmem_len;
-		} else
-			end = inf->fbmem_len;
-
-		if ((ptr + size) > end)
-			return -ENOMEM;
+		ptr = PANEL_CRT_ADDR;
 
 		break;
 
 	case SM501_MEMF_ACCEL:
-		fbi = inf->fb[HEAD_CRT];
-		ptr = fbi ? fbi->fix.smem_len : 0;
-
-		fbi = inf->fb[HEAD_PANEL];
-		if (fbi) {
-			par = fbi->par;
-			end = par->screen.sm_addr;
-		} else
-			end = inf->fbmem_len;
+		ptr = inf->fb[0]->fix.smem_len;
 
-		if ((ptr + size) > end)
+		if ((ptr + size) >
+		    (inf->fb[1]->fix.smem_start - inf->fbmem_res->start))
 			return -ENOMEM;
-
 		break;
 
 	default:
@@ -219,12 +415,26 @@
 	mem->sm_addr = ptr;
 	mem->k_addr  = inf->fbmem + ptr;
 
-	dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
+	dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %08lx\n",
 		__func__, mem->sm_addr, mem->k_addr, why, size);
 
 	return 0;
 }
 
+
+
+#ifdef CONFIG_MTRR
+
+extern void sm501fb_set_mtrr(struct device *dev);
+
+extern void sm501fb_unset_mtrr(struct device *dev);
+
+#else
+#define sm501fb_set_mtrr(x) do {smdbg("MTRR is disabled in the kernel\n");} while (0)
+
+#define sm501fb_unset_mtrr(x) do { } while (0)
+#endif /* CONFIG_MTRR */
+
 /* sm501fb_ps_to_hz
  *
  * Converts a period in picoseconds to Hz.
@@ -235,7 +445,7 @@
 
 static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
 {
-	unsigned long long numerator=1000000000000ULL;
+	unsigned long long numerator=1000*1000*1000*1000ULL;
 
 	/* 10^12 / picosecond period gives frequency in Hz */
 	do_div(numerator, psvalue);
@@ -246,6 +456,35 @@
 
 #define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
 
+
+static void sm501fb_wait_panelvsnc(int vsync_count)
+{
+	unsigned long status;
+
+	while (vsync_count-- > 0)
+	{
+		// Wait for end of vsync.
+		do
+		{
+			status = FIELD_GET(SmRead32(SYS_CTRL),
+							   SYS_CTRL,
+							   PANEL_SYNC);
+		}
+		while (status == SYS_CTRL_PANEL_SYNC_ACTIVE);
+
+		// Wait for start of vsync.
+		do
+		{
+			status = FIELD_GET(SmRead32(SYS_CTRL),
+							   SYS_CTRL, 
+							   PANEL_SYNC);
+		}
+		while (status == SYS_CTRL_PANEL_SYNC_INACTIVE);
+	}
+	smdbg("w_panelvsync\n");
+
+}
+
 /* sm501fb_setup_gamma
  *
  * Programs a linear 1.0 gamma ramp in case the gamma
@@ -260,7 +499,7 @@
 
 	/* set gamma values */
 	for (offset = 0; offset < 256 * 4; offset += 4) {
-		writel(value, fbi->regs + palette + offset);
+		SmWrite32(palette + offset, value);
 		value += 0x010101; 	/* Advance RGB by 1,1,1.*/
 	}
 }
@@ -294,12 +533,16 @@
 
 	if (h_total(var) > 4096 || v_total(var) > 2048)
 		return -EINVAL;
+        /* Commented out by Jason 08/04/2009
+         * to enable vesa_modes that are not 128 bit aligned 
+         * since we've got the workaround with these modes */
 
 	/* check our line length is going to be 128 bit aligned */
 
-	tmp = (var->xres * var->bits_per_pixel) / 8;
+	/* tmp = (var->xres * var->bits_per_pixel) / 8;
 	if ((tmp & 15) != 0)
 		return -EINVAL;
+        */
 
 	/* check the virtual size */
 
@@ -330,40 +573,29 @@
 		break;
 
 	case 16:
-		if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
-			var->blue.offset	= 11;
-			var->green.offset	= 5;
-			var->red.offset		= 0;
-		} else {
-			var->red.offset		= 11;
-			var->green.offset	= 5;
-			var->blue.offset	= 0;
-		}
-		var->transp.offset	= 0;
+		var->red.offset		= 11;
+		var->blue.offset	= 0;
+		var->green.offset	= 5;
 
-		var->red.length		= 5;
+		var->red.length	= 5;
 		var->green.length	= 6;
 		var->blue.length	= 5;
+
+		var->transp.offset	= 0;
 		var->transp.length	= 0;
+		
 		break;
 
 	case 32:
-		if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
-			var->transp.offset	= 0;
-			var->red.offset		= 8;
-			var->green.offset	= 16;
-			var->blue.offset	= 24;
-		} else {
-			var->transp.offset	= 24;
-			var->red.offset		= 16;
-			var->green.offset	= 8;
-			var->blue.offset	= 0;
-		}
+		var->transp.offset	= 24;
+		var->red.offset		= 16;
+		var->green.offset	= 8;
+		var->blue.offset	= 0;
 
 		var->red.length		= 8;
 		var->green.length	= 8;
 		var->blue.length	= 8;
-		var->transp.length	= 0;
+		var->transp.length	= 8;
 		break;
 
 	default:
@@ -398,6 +630,160 @@
 	return sm501fb_check_var(var, info);
 }
 
+
+static int my_atoi(const char *name)
+{
+    int val = 0;
+
+    for (;; name++) {
+	switch (*name) {
+	    case '0' ... '9':
+		val = 10*val+(*name-'0');
+		break;
+	    default:
+		return val;
+	}
+    }
+}
+
+/* Perform a rounded division. */
+long roundedDiv(long num, long denom)
+{
+    /* n / d + 1 / 2 = (2n + d) / 2d */
+    return (2 * num + denom) / (2 * denom);
+}
+
+
+static int sm501_get_refresh(char * mode)
+{
+	int refresh;
+	char *tmp;
+	if(mode == NULL)
+	{
+		return 60;
+	}
+	tmp = strstr(mode, "@");
+	refresh = my_atoi(tmp + 1);
+	return refresh;
+}
+
+
+/*
+ *  Locate in-stock parameter table for the requested mode.
+ *  Success: return a pointer to the mode_parameter_t entry.
+ *  Fail: a NULL pointer.
+ *
+ */
+mode_parameter_t *find_vesamode(
+unsigned long width, 
+unsigned long height, 
+unsigned long refresh_rate)
+{
+    mode_parameter_t *mode_table = gModeParamTable;
+
+    /* Walk the entire mode table. */
+    while (mode_table->pixel_clock != 0)
+    {
+        if ((mode_table->horizontal_display_end == width)
+        && (mode_table->vertical_display_end == height)
+        && (mode_table->vertical_frequency == refresh_rate))
+        {
+            return(mode_table);
+        }
+        mode_table++; /* Next entry */
+    }
+
+    /* No match, return NULL pointer */
+    return((mode_parameter_t *)0);
+}
+
+/*
+ *  Convert the VESA timing into possible Voyager timing.
+ *  If actual pixel clock is not equal to Vesa timing pixel clock.
+ *  other parameter like horizontal total and sync have to be changed.
+ */
+long sm501fb_adjust_vesamode(struct fb_info *info,
+				     	struct fb_var_screeninfo *var)
+{
+
+    	unsigned long blank_width, sync_start, sync_width, refresh, pixclock;
+	unsigned long horizontal_total, horizontal_sync_start, horizontal_sync_width; 
+	unsigned long reg;
+	mode_parameter_t *pVesaMode; /* physical parameters for the mode */
+	struct sm501fb_par  *par = info->par;
+
+	refresh = sm501_get_refresh(mode_option);
+
+	pVesaMode = find_vesamode(var->xres, var->yres, refresh);
+	if(pVesaMode == NULL)
+	{
+		return -1;
+	}
+	
+	pixclock = sm501fb_ps_to_hz(var->pixclock);
+	if(pixclock == pVesaMode->pixel_clock)
+	{
+		return 0;
+	}
+	
+    	/* Calculate the sync percentages of the VESA mode. */
+	blank_width = pVesaMode->horizontal_total - pVesaMode->horizontal_display_end;
+    	sync_start = roundedDiv((pVesaMode->horizontal_sync_start -
+                       pVesaMode->horizontal_display_end) * 100, blank_width);
+    	sync_width = roundedDiv(pVesaMode->horizontal_sync_width * 100, blank_width);
+
+     	/* Calculate the horizontal total based on the actual pixel clock and VESA line frequency. */
+    	horizontal_total = roundedDiv(pixclock,
+                                    pVesaMode->horizontal_frequency);
+
+    	/* Calculate the sync start and width based on the VESA percentages. */
+    	blank_width = horizontal_total - pVesaMode->horizontal_display_end;
+    	horizontal_sync_start = pVesaMode->horizontal_display_end + roundedDiv(blank_width * sync_start, 100);
+    	horizontal_sync_width = roundedDiv(blank_width * sync_width, 100);
+
+
+	/* program horizontal total */
+	reg = 0;
+	if (par->head == HEAD_CRT)
+	{
+		reg = FIELD_VALUE(reg, CRT_HORIZONTAL_TOTAL, TOTAL, horizontal_total - 1)  | 
+			  FIELD_VALUE(reg, CRT_HORIZONTAL_TOTAL, DISPLAY_END, pVesaMode->horizontal_display_end - 1);
+		SmWrite32(CRT_HORIZONTAL_TOTAL, reg);
+	}
+	#if 0
+	else
+	{
+		reg = FIELD_VALUE(reg, PANEL_HORIZONTAL_TOTAL, TOTAL, horizontal_total - 1) |
+			  FIELD_VALUE(reg, PANEL_HORIZONTAL_TOTAL, TOTAL, pVesaMode->horizontal_display_end - 1);
+		SmWrite32(PANEL_HORIZONTAL_TOTAL, reg);
+	}
+	#endif
+	
+	
+
+	/* program horizontal sync */	
+	reg = 0;
+	if (par->head == HEAD_CRT)	
+	{
+		reg = FIELD_VALUE(reg, CRT_HORIZONTAL_SYNC, WIDTH, horizontal_sync_width) |
+			  FIELD_VALUE(reg, CRT_HORIZONTAL_SYNC, START, horizontal_sync_start - 1);	
+		SmWrite32(CRT_HORIZONTAL_SYNC, reg);
+	}
+	#if 0
+	else
+	{
+		reg = FIELD_VALUE(reg, PANEL_HORIZONTAL_SYNC, WIDTH, horizontal_sync_width) |
+			  FIELD_VALUE(reg, PANEL_HORIZONTAL_SYNC, START, horizontal_sync_start - 1) ;	
+		SmWrite32(PANEL_HORIZONTAL_SYNC, reg);
+	}
+	#endif
+
+	
+	
+    	return 0;
+
+}
+
 /* sm501fb_set_par_common
  *
  * set common registers for framebuffers
@@ -408,8 +794,8 @@
 {
 	struct sm501fb_par  *par = info->par;
 	struct sm501fb_info *fbi = par->info;
-	unsigned long pixclock;      /* pixelclock in Hz */
-	unsigned long sm501pixclock; /* pixelclock the 501 can achive in Hz */
+	unsigned long pixclock=0;      /* pixelclock in Hz */
+	unsigned long sm501pixclock=0; /* pixelclock the 501 can achive in Hz */
 	unsigned int mem_type;
 	unsigned int clock_type;
 	unsigned int head_addr;
@@ -422,13 +808,13 @@
 	case HEAD_CRT:
 		mem_type = SM501_MEMF_CRT;
 		clock_type = SM501_CLOCK_V2XCLK;
-		head_addr = SM501_DC_CRT_FB_ADDR;
+		head_addr = CRT_FB_ADDRESS;
 		break;
 
 	case HEAD_PANEL:
 		mem_type = SM501_MEMF_PANEL;
 		clock_type = SM501_CLOCK_P2XCLK;
-		head_addr = SM501_DC_PANEL_FB_ADDR;
+		head_addr = PANEL_FB_ADDRESS;
 		break;
 
 	default:
@@ -443,46 +829,60 @@
 		break;
 
 	case 16:
-		info->fix.visual = FB_VISUAL_TRUECOLOR;
-		break;
-
 	case 32:
-		info->fix.visual = FB_VISUAL_TRUECOLOR;
+		if (info->var.nonstd)
+			info->fix.visual = FB_VISUAL_DIRECTCOLOR;
+		else
+			info->fix.visual = FB_VISUAL_TRUECOLOR;
+	    	break;
 		break;
 	}
-
 	/* allocate fb memory within 501 */
-	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
-	info->fix.smem_len    = info->fix.line_length * var->yres_virtual;
+/*#if 1 // Cheok(7/26/2007):	*/
+        /* Jason(08/05/2009):
+         * to enable the workaround for resolutions that are not 16 pixel aligned
+         */
 
+#if 0 // Cheok(7/26/2007):	
+	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
+#else
+	// Cheok(7/26/2007)
+	// Take care cases that screen width is not 16 pixel aligned, which is
+	// a requirement for Direct Draw and the hardware.
+	// Note that standard resolutions: 320, 640., 800, 1024 and 1280 are all
+	// 16 pixel aligned and don't need this adjustment. 
+	// However, new resolution, 1366, has to be adjusted.
+        // fb_width (or Pitch value) has to be 32 byte aligned.
+        {
+                int tmpWidth = var->xres_virtual;
+                tmpWidth = (tmpWidth + 15) & ~15; //This calculation has no effect on 640, 800, 1024 and 1280.
+                info->fix.line_length =( tmpWidth  * var->bits_per_pixel)/8;
+        }
+#endif	
+	info->fix.smem_len  = info->fix.line_length * var->yres_virtual;
 	dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
 		info->fix.line_length);
-
 	if (sm501_alloc_mem(fbi, &par->screen, mem_type,
 			    info->fix.smem_len)) {
 		dev_err(fbi->dev, "no memory available\n");
 		return -ENOMEM;
 	}
-
 	info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
 
 	info->screen_base = fbi->fbmem + par->screen.sm_addr;
 	info->screen_size = info->fix.smem_len;
-
 	/* set start of framebuffer to the screen */
 
-	writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr);
-
+	SmWrite32(PANEL_FB_ADDRESS, 
+					FIELD_VALUE(0,PANEL_FB_ADDRESS, ADDRESS, par->screen.sm_addr) |
+					FIELD_SET(0, PANEL_FB_ADDRESS, STATUS, FLIP));
+	
 	/* program CRT clock  */
-
 	pixclock = sm501fb_ps_to_hz(var->pixclock);
-
-	sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
-					pixclock);
-
+	sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type, pixclock);
 	/* update fb layer with actual clock used */
 	var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
-
+	
 	dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz)  = %lu, "
 	       "sm501pixclock = %lu,  error = %ld%%\n",
 	       __func__, var->pixclock, pixclock, sm501pixclock,
@@ -501,48 +901,63 @@
 {
 	struct sm501fb_par  *par = info->par;
 	struct sm501fb_info *fbi = par->info;
-	void __iomem *base = fbi->regs;
+	unsigned long  base;
 	unsigned long reg;
 
 	if (par->head == HEAD_CRT)
-		base += SM501_DC_CRT_H_TOT;
+		base = CRT_HORIZONTAL_TOTAL;
 	else
-		base += SM501_DC_PANEL_H_TOT;
+		base = PANEL_HORIZONTAL_TOTAL;
 
 	/* set framebuffer width and display width */
 
 	reg = info->fix.line_length;
-	reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
-
-	writel(reg, fbi->regs + (par->head == HEAD_CRT ?
-		    SM501_DC_CRT_FB_OFFSET :  SM501_DC_PANEL_FB_OFFSET));
+	if (par->head == HEAD_CRT)
+		reg = FIELD_VALUE(reg, CRT_FB_WIDTH, WIDTH, (var->xres * var->bits_per_pixel)/8) ;
+	else
+		reg = FIELD_VALUE(reg, PANEL_FB_WIDTH, WIDTH, (var->xres * var->bits_per_pixel)/8) ;
+	SmWrite32((par->head == HEAD_CRT ? CRT_FB_WIDTH :  PANEL_FB_WIDTH), reg);
 
 	/* program horizontal total */
 
-	reg  = (h_total(var) - 1) << 16;
-	reg |= (var->xres - 1);
-
-	writel(reg, base + SM501_OFF_DC_H_TOT);
+	reg = (var->xres - 1);
+	if (par->head == HEAD_CRT)
+		reg = FIELD_VALUE(reg, CRT_HORIZONTAL_TOTAL, TOTAL, (h_total(var) - 1) ) ;
+	else
+		reg = FIELD_VALUE(reg, PANEL_HORIZONTAL_TOTAL, TOTAL, (h_total(var) - 1) ) ;
+	SmWrite32(base+SM501_OFF_DC_H_TOT, reg);
 
 	/* program horizontal sync */
 
-	reg  = var->hsync_len << 16;
-	reg |= var->xres + var->right_margin - 1;
+	reg = var->xres + var->right_margin - 1;
+	if (par->head == HEAD_CRT)
+		reg = FIELD_VALUE(reg, CRT_HORIZONTAL_SYNC, WIDTH, var->hsync_len);
+	else
+		reg = FIELD_VALUE(reg, PANEL_HORIZONTAL_SYNC, WIDTH, var->hsync_len);
 
-	writel(reg, base + SM501_OFF_DC_H_SYNC);
+	SmWrite32(base + SM501_OFF_DC_H_SYNC, reg);
 
 	/* program vertical total */
 
-	reg  = (v_total(var) - 1) << 16;
-	reg |= (var->yres - 1);
-
-	writel(reg, base + SM501_OFF_DC_V_TOT);
+	reg = (var->yres - 1);
+	if (par->head == HEAD_CRT)
+		reg  = FIELD_VALUE(reg, CRT_VERTICAL_TOTAL, TOTAL, (v_total(var) - 1));
+	else
+		reg  = FIELD_VALUE(reg, PANEL_VERTICAL_TOTAL, TOTAL, (v_total(var) - 1));
+	
+	SmWrite32(base + SM501_OFF_DC_V_TOT, reg);
 
 	/* program vertical sync */
-	reg  = var->vsync_len << 16;
-	reg |= var->yres + var->lower_margin - 1;
+	reg  = var->yres + var->lower_margin - 1;
+	if (par->head == HEAD_CRT)
+		reg  = FIELD_VALUE(reg, CRT_VERTICAL_SYNC, HEIGHT, var->vsync_len);
+	else
+		reg  = FIELD_VALUE(reg, PANEL_VERTICAL_SYNC, HEIGHT, var->vsync_len);
+	SmWrite32(base + SM501_OFF_DC_V_SYNC, reg);
+	
+	/*adjust the timing when using dule mode.added by caesar*/
+	sm501fb_adjust_vesamode(info, var);		
 
-	writel(reg, base + SM501_OFF_DC_V_SYNC);
 }
 
 /* sm501fb_pan_crt
@@ -561,15 +976,14 @@
 
 	xoffs = var->xoffset * bytes_pixel;
 
-	reg = readl(fbi->regs + SM501_DC_CRT_CONTROL);
-
-	reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
-	reg |= ((xoffs & 15) / bytes_pixel) << 4;
-	writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
-
-	reg = (par->screen.sm_addr + xoffs +
-	       var->yoffset * info->fix.line_length);
-	writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
+	reg = SmRead32(CRT_DISPLAY_CTRL);
+	reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, PIXEL, (xoffs & 15) / bytes_pixel);
+	
+	SmWrite32(CRT_DISPLAY_CTRL, reg);
+
+	reg = (par->screen.sm_addr + xoffs + var->yoffset * info->fix.line_length);
+	reg = FIELD_SET(reg, CRT_FB_ADDRESS, STATUS , PENDING);
+	SmWrite32(CRT_FB_ADDRESS, reg);
 
 	sm501fb_sync_regs(fbi);
 	return 0;
@@ -587,11 +1001,13 @@
 	struct sm501fb_info *fbi = par->info;
 	unsigned long reg;
 
-	reg = var->xoffset | (var->xres_virtual << 16);
-	writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
-
-	reg = var->yoffset | (var->yres_virtual << 16);
-	writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
+	reg = FIELD_VALUE(reg, PANEL_WINDOW_WIDTH, X, var->xoffset);
+	reg = FIELD_VALUE(reg, PANEL_WINDOW_WIDTH, WIDTH, var->xres_virtual);
+	SmWrite32(PANEL_WINDOW_WIDTH, reg);
+
+	reg = FIELD_VALUE(reg, PANEL_WINDOW_HEIGHT, Y, var->yoffset);
+	reg = FIELD_VALUE(reg, PANEL_WINDOW_HEIGHT, HEIGHT, var->yres_virtual);
+	SmWrite32(PANEL_WINDOW_HEIGHT, reg);
 
 	sm501fb_sync_regs(fbi);
 	return 0;
@@ -615,28 +1031,21 @@
 	dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
 
 	/* enable CRT DAC - note 0 is on!*/
-	sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
-
-	control = readl(fbi->regs + SM501_DC_CRT_CONTROL);
-
-	control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
-		    SM501_DC_CRT_CONTROL_GAMMA |
-		    SM501_DC_CRT_CONTROL_BLANK |
-		    SM501_DC_CRT_CONTROL_SEL |
-		    SM501_DC_CRT_CONTROL_CP |
-		    SM501_DC_CRT_CONTROL_TVP);
+	control = SmRead32(MISC_CTRL);
+	SmWrite32(MISC_CTRL, FIELD_SET(control, MISC_CTRL, DAC_POWER, ENABLE) );
+	
+	control = SmRead32(CRT_DISPLAY_CTRL);
 
 	/* set the sync polarities before we check data source  */
 
 	if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
-		control |= SM501_DC_CRT_CONTROL_HSP;
+		control = FIELD_SET(control, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW);
 
 	if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
-		control |= SM501_DC_CRT_CONTROL_VSP;
+		control = FIELD_SET(control, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW);
 
-	if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
+	if ( FIELD_GET(control, CRT_DISPLAY_CTRL, SELECT)== CRT_DISPLAY_CTRL_SELECT_PANEL) {
 		/* the head is displaying panel data... */
-
 		sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0);
 		goto out_update;
 	}
@@ -650,122 +1059,117 @@
 	sm501fb_pan_crt(var, info);
 	sm501fb_set_par_geometry(info, var);
 
-	control |= SM501_FIFO_3;	/* fill if >3 free slots */
-
+	dev_dbg(fbi->dev, "CRT pixel:%d\n",var->bits_per_pixel);
+	control = FIELD_SET(control, CRT_DISPLAY_CTRL, FIFO, 3);
+	
 	switch(var->bits_per_pixel) {
 	case 8:
-		control |= SM501_DC_CRT_CONTROL_8BPP;
+		control = FIELD_SET(control, CRT_DISPLAY_CTRL, FORMAT,  8);
 		break;
-
 	case 16:
-		control |= SM501_DC_CRT_CONTROL_16BPP;
-		sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
+		control = FIELD_SET(control, CRT_DISPLAY_CTRL, FORMAT,  16);
+		sm501fb_setup_gamma(fbi, CRT_PALETTE_RAM);
 		break;
-
 	case 32:
-		control |= SM501_DC_CRT_CONTROL_32BPP;
-		sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
+		control = FIELD_SET(control, CRT_DISPLAY_CTRL, FORMAT,  32);
+		sm501fb_setup_gamma(fbi, CRT_PALETTE_RAM);
 		break;
-
 	default:
 		BUG();
 	}
 
-	control |= SM501_DC_CRT_CONTROL_SEL;	/* CRT displays CRT data */
-	control |= SM501_DC_CRT_CONTROL_TE;	/* enable CRT timing */
-	control |= SM501_DC_CRT_CONTROL_ENABLE;	/* enable CRT plane */
-
+#ifdef CONFIG_FB_SM501_DUAL_HEAD
+	control = FIELD_SET(control, CRT_DISPLAY_CTRL, SELECT,  CRT);
+#else
+	control = FIELD_SET(control, CRT_DISPLAY_CTRL, SELECT,  PANEL);
+#endif
+	control = FIELD_SET(control, CRT_DISPLAY_CTRL, TIMING,  ENABLE);
+	control = FIELD_SET(control, CRT_DISPLAY_CTRL, PLANE, ENABLE);
+	
  out_update:
 	dev_dbg(fbi->dev, "new control is %08lx\n", control);
 
-	writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
+	SmWrite32(CRT_DISPLAY_CTRL, control);
 	sm501fb_sync_regs(fbi);
 
 	return 0;
 }
 
-static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
+
+/* sm501fb_panel_power
+ *
+ * Set power of panel
+*/
+static void sm501fb_panel_power(panel_state_t on_off, int vsync_delay)
 {
-	unsigned long control;
-	void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
-	struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl;
+	unsigned long panelControl = SmRead32(PANEL_DISPLAY_CTRL);
 
-	control = readl(ctrl_reg);
+	if (on_off == PANEL_ON)
+	{
+		// Turn on FPVDDEN.
+		panelControl = FIELD_SET(panelControl,
+								 PANEL_DISPLAY_CTRL, FPVDDEN, HIGH);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
 
-	if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
-		/* enable panel power */
+		sm501fb_wait_panelvsnc(vsync_delay);
 
-		control |= SM501_DC_PANEL_CONTROL_VDD;	/* FPVDDEN */
-		writel(control, ctrl_reg);
-		sm501fb_sync_regs(fbi);
-		mdelay(10);
+		// Turn on FPDATA.
+		panelControl = FIELD_SET(panelControl, 
+								 PANEL_DISPLAY_CTRL, DATA, ENABLE);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
 
-		control |= SM501_DC_PANEL_CONTROL_DATA;	/* DATA */
-		writel(control, ctrl_reg);
-		sm501fb_sync_regs(fbi);
-		mdelay(10);
+		sm501fb_wait_panelvsnc(vsync_delay);
 
-		/* VBIASEN */
+		// Turn on FPVBIAS.
+		panelControl = FIELD_SET(panelControl, 
+								 PANEL_DISPLAY_CTRL, VBIASEN, HIGH);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
 
-		if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
-			if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
-				control &= ~SM501_DC_PANEL_CONTROL_BIAS;
-			else
-				control |= SM501_DC_PANEL_CONTROL_BIAS;
+		sm501fb_wait_panelvsnc(vsync_delay);
 
-			writel(control, ctrl_reg);
-			sm501fb_sync_regs(fbi);
-			mdelay(10);
-		}
+		// Turn on FPEN.
+		panelControl = FIELD_SET(panelControl, 
+								 PANEL_DISPLAY_CTRL, FPEN, HIGH);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
+	}
 
-		if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
-			if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
-				control &= ~SM501_DC_PANEL_CONTROL_FPEN;
-			else
-				control |= SM501_DC_PANEL_CONTROL_FPEN;
+	else
+	{
+		// Turn off FPEN.
+		panelControl = FIELD_SET(panelControl,
+								 PANEL_DISPLAY_CTRL, FPEN, LOW);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
 
-			writel(control, ctrl_reg);
-			sm501fb_sync_regs(fbi);
-			mdelay(10);
-		}
-	} else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
-		/* disable panel power */
-		if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
-			if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
-				control |= SM501_DC_PANEL_CONTROL_FPEN;
-			else
-				control &= ~SM501_DC_PANEL_CONTROL_FPEN;
+		sm501fb_wait_panelvsnc(vsync_delay);
 
-			writel(control, ctrl_reg);
-			sm501fb_sync_regs(fbi);
-			mdelay(10);
-		}
 
-		if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
-			if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
-				control |= SM501_DC_PANEL_CONTROL_BIAS;
-			else
-				control &= ~SM501_DC_PANEL_CONTROL_BIAS;
+		// Turn off FPVBIASEN.
+		panelControl = FIELD_SET(panelControl, 
+								 PANEL_DISPLAY_CTRL, VBIASEN, LOW);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
 
-			writel(control, ctrl_reg);
-			sm501fb_sync_regs(fbi);
-			mdelay(10);
-		}
+		sm501fb_wait_panelvsnc(vsync_delay);
+
+
+		// Turn off FPDATA.
+		panelControl = FIELD_SET(panelControl, 
+								 PANEL_DISPLAY_CTRL, DATA, DISABLE);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
+
+		sm501fb_wait_panelvsnc(vsync_delay);
 
-		control &= ~SM501_DC_PANEL_CONTROL_DATA;
-		writel(control, ctrl_reg);
-		sm501fb_sync_regs(fbi);
-		mdelay(10);
-
-		control &= ~SM501_DC_PANEL_CONTROL_VDD;
-		writel(control, ctrl_reg);
-		sm501fb_sync_regs(fbi);
-		mdelay(10);
+
+		// Turn off FPVDDEN.
+		panelControl = FIELD_SET(panelControl, 
+								 PANEL_DISPLAY_CTRL, FPVDDEN, LOW);
+		SmWrite32(PANEL_DISPLAY_CTRL, panelControl);
 	}
+	
 
-	sm501fb_sync_regs(fbi);
 }
 
+
+
 /* sm501fb_set_par_pnl
  *
  * Set the panel video mode from the fb_info structure
@@ -793,72 +1197,60 @@
 
 	/* update control register */
 
-	control = readl(fbi->regs + SM501_DC_PANEL_CONTROL);
-	control &= (SM501_DC_PANEL_CONTROL_GAMMA |
-		    SM501_DC_PANEL_CONTROL_VDD  |
-		    SM501_DC_PANEL_CONTROL_DATA |
-		    SM501_DC_PANEL_CONTROL_BIAS |
-		    SM501_DC_PANEL_CONTROL_FPEN |
-		    SM501_DC_PANEL_CONTROL_CP |
-		    SM501_DC_PANEL_CONTROL_CK |
-		    SM501_DC_PANEL_CONTROL_HP |
-		    SM501_DC_PANEL_CONTROL_VP |
-		    SM501_DC_PANEL_CONTROL_HPD |
-		    SM501_DC_PANEL_CONTROL_VPD);
+	control = SmRead32(PANEL_DISPLAY_CTRL);
 
-	control |= SM501_FIFO_3;	/* fill if >3 free slots */
+	control = FIELD_SET(control, PANEL_DISPLAY_CTRL, FIFO, 3);	
+
+	dev_dbg(fbi->dev, "PANEL pixel:%d\n",var->bits_per_pixel);
 
 	switch(var->bits_per_pixel) {
 	case 8:
-		control |= SM501_DC_PANEL_CONTROL_8BPP;
+		control = FIELD_SET(control, PANEL_DISPLAY_CTRL, FORMAT,  8);
 		break;
-
 	case 16:
-		control |= SM501_DC_PANEL_CONTROL_16BPP;
-		sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
+		control = FIELD_SET(control, PANEL_DISPLAY_CTRL, FORMAT,  16);
+		sm501fb_setup_gamma(fbi, PANEL_PALETTE_RAM);
 		break;
-
 	case 32:
-		control |= SM501_DC_PANEL_CONTROL_32BPP;
-		sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
+		control = FIELD_SET(control, PANEL_DISPLAY_CTRL, FORMAT,  32);
+		sm501fb_setup_gamma(fbi, PANEL_PALETTE_RAM);
 		break;
-
 	default:
 		BUG();
 	}
 
-	writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
+	SmWrite32(PANEL_PAN_CTRL, 0x0);
 
 	/* panel plane top left and bottom right location */
 
-	writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
+	SmWrite32(PANEL_PLANE_TL, 0x0);
 
 	reg  = var->xres - 1;
 	reg |= (var->yres - 1) << 16;
-
-	writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
+	SmWrite32( PANEL_PLANE_BR, reg);
 
 	/* program panel control register */
 
-	control |= SM501_DC_PANEL_CONTROL_TE;	/* enable PANEL timing */
-	control |= SM501_DC_PANEL_CONTROL_EN;	/* enable PANEL gfx plane */
+	control = FIELD_SET(control, PANEL_DISPLAY_CTRL, TIMING, ENABLE);	/* DATA */
+	control = FIELD_SET(control, PANEL_DISPLAY_CTRL, PLANE, ENABLE);	/* DATA */
 
 	if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
-		control |= SM501_DC_PANEL_CONTROL_HSP;
+		control = FIELD_SET(control, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW);	/* DATA */
 
 	if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
-		control |= SM501_DC_PANEL_CONTROL_VSP;
-
-	writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
-	sm501fb_sync_regs(fbi);
+		control = FIELD_SET(control, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW);	/* DATA */
 
-	/* ensure the panel interface is not tristated at this point */
+	dev_dbg(fbi->dev, "%s H:%d  V:%d\n", __func__, var->sync, var->sync);
 
-	sm501_modify_reg(fbi->dev->parent, SM501_SYSTEM_CONTROL,
-			 0, SM501_SYSCTRL_PANEL_TRISTATE);
+	SmWrite32(PANEL_DISPLAY_CTRL, control);
+	sm501fb_wait_panelvsnc(4);
 
 	/* power the panel up */
-	sm501fb_panel_power(fbi, 1);
+
+	sm501fb_panel_power(PANEL_ON, 4);
+
+	deInit(info->var.xres, info->var.yres, info->var.bits_per_pixel);
+
 	return 0;
 }
 
@@ -889,40 +1281,63 @@
 {
 	struct sm501fb_par  *par = info->par;
 	struct sm501fb_info *fbi = par->info;
-	void __iomem *base = fbi->regs;
+	unsigned long base;
 	unsigned int val;
+	u32 *pal = par->pseudo_palette;
 
+	if (regno > 255)
+		return 1;
+	
 	if (par->head == HEAD_CRT)
-		base += SM501_DC_CRT_PALETTE;
+		base = CRT_PALETTE_RAM;
 	else
-		base += SM501_DC_PANEL_PALETTE;
+		base = PANEL_PALETTE_RAM;
+
+	if(info->var.grayscale)
+		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 
 	switch (info->fix.visual) {
+	case FB_VISUAL_DIRECTCOLOR:
 	case FB_VISUAL_TRUECOLOR:
-		/* true-colour, use pseuo-palette */
-
-		if (regno < 16) {
-			u32 *pal = par->pseudo_palette;
-
-			val  = chan_to_field(red,   &info->var.red);
-			val |= chan_to_field(green, &info->var.green);
-			val |= chan_to_field(blue,  &info->var.blue);
-
-			pal[regno] = val;
+		/* 16/32 bit true-colour, use pseuo-palette for 16 base color*/
+		if (regno < 16) 
+		{			
+			if (info->var.bits_per_pixel==16)
+			{				
+				val  = chan_to_field(red,   &info->var.red);
+				val |= chan_to_field(green, &info->var.green);
+				val |= chan_to_field(blue,  &info->var.blue);
+#ifdef __BIG_ENDIAN
+				 pal[regno] =( (red & 0xf800) >> 8) |
+				 			((green & 0xe000) >> 13) |
+				 			((green & 0x1c00) << 3) |
+				 			((blue & 0xf800) >> 3);
+#else
+				pal[regno] = val;
+#endif
+			}
+			else
+			{				
+				val  = chan_to_field(red,   &info->var.red);
+				val |= chan_to_field(green, &info->var.green);
+				val |= chan_to_field(blue,  &info->var.blue);
+#ifdef __BIG_ENDIAN				
+				pal[regno] = ((val & 0x00ff)<<24)|
+							((val & 0xff00)<<8)|
+							((val & 0xff0000)>>8);				
+#else
+				pal[regno] = val;
+#endif
+			}
 		}
 		break;
-
 	case FB_VISUAL_PSEUDOCOLOR:
-		if (regno < 256) {
-			val = (red >> 8) << 16;
-			val |= (green >> 8) << 8;
-			val |= blue >> 8;
-
-			writel(val, base + (regno * 4));
-		}
-
+		/* color depth 8 bit*/
+			val = ((red >> 8) <<16 )|
+				((green >> 8) <<8)|
+				((blue >> 8));		
+			SmWrite32(base + (regno * 4), val);
 		break;
-
 	default:
 		return 1;   /* unknown type */
 	}
@@ -930,76 +1345,116 @@
 	return 0;
 }
 
-/* sm501fb_blank_pnl
+
+/* field_to_chan
  *
- * Blank or un-blank the panel interface
+ * convert  a field position intoa colour value
+ *
+ * from pxafb.c
 */
 
-static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
+static inline u16 field_to_chan(unsigned int chan,
+					 struct fb_bitfield *bf)
 {
-	struct sm501fb_par  *par = info->par;
-	struct sm501fb_info *fbi = par->info;
+	chan >>= bf->offset;
+	chan &=( (1<<bf->length)-1);
+	chan <<= 16 - bf->length;	
+	return chan &0xffff;
+}
 
-	dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
+int sm501fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info)
+{
+	int i, start, rc = 0;
+	u16 *red, *green, *blue, *transp;
+	u_int hred, hgreen, hblue, htransp= 0xffff;
+	unsigned int val;
 
-	switch (blank_mode) {
-	case FB_BLANK_POWERDOWN:
-		sm501fb_panel_power(fbi, 0);
-		break;
+	red = cmap->red;
+	green = cmap->green;
+	blue = cmap->blue;
+	transp = cmap->transp;
+	start = cmap->start;
 
-	case FB_BLANK_UNBLANK:
-		sm501fb_panel_power(fbi, 1);
-		break;
+	if (start < 0 || (!info->fbops->fb_setcolreg))
+		return -EINVAL;
 
-	case FB_BLANK_NORMAL:
-	case FB_BLANK_VSYNC_SUSPEND:
-	case FB_BLANK_HSYNC_SUSPEND:
-	default:
-		return 1;
-	}
+		for (i = 0; i < cmap->len; i++) {
+#if 1
+			val  = chan_to_field(red[i],   &info->var.red);
+			val |= chan_to_field(green[i], &info->var.green);
+			val |= chan_to_field(blue[i],  &info->var.blue);
+			
+			if (transp){
+				val |= chan_to_field(transp[i],  &info->var.transp);
+			}
 
-	return 0;
+			val = (val& 0xff00ff00>>8)|(val& 0x00ff00ff<<8);
+			
+			red[i] |= field_to_chan(val,&info->var.red);
+			green[i] |= field_to_chan(val,&info->var.green);
+			blue[i] |= field_to_chan(val,&info->var.blue);
+
+			if (transp)
+				transp[i] |= field_to_chan(val,&info->var.transp);
+#else
+
+		           red[i] = i*65535/((1<<info->var.red.length)-1);
+	 	           green[i] = i*65535/((1<<info->var.green.length)-1);
+	 	           blue[i] = i*65535/((1<<info->var.blue.length)-1);
+	 	           transp[i] = 0;
+#endif			   
+			if (info->fbops->fb_setcolreg(start++,
+						      red[i], green[i], blue[i],
+						      transp[i], info))
+			break;
+		}
+		
+	if (rc == 0)
+		fb_copy_cmap(cmap, &info->cmap);
+
+	return rc;
 }
 
-/* sm501fb_blank_crt
+/* sm501fb_blank
  *
  * Blank or un-blank the crt interface
 */
 
-static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
+static int sm501fb_blank(int blank_mode, struct fb_info *info)
 {
 	struct sm501fb_par  *par = info->par;
 	struct sm501fb_info *fbi = par->info;
-	unsigned long ctrl;
+	unsigned long ctrl, misc_value;
 
 	dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
 
-	ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL);
+	ctrl = SmRead32(SYSTEM_CTRL);
 
 	switch (blank_mode) {
 	case FB_BLANK_POWERDOWN:
-		ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
-		sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
-
+		ctrl = FIELD_SET(ctrl, SYSTEM_CTRL, DPMS, VNHN);
+		
 	case FB_BLANK_NORMAL:
-		ctrl |= SM501_DC_CRT_CONTROL_BLANK;
+		ctrl = FIELD_SET(ctrl, SYSTEM_CTRL, DPMS, VPHP);
 		break;
 
 	case FB_BLANK_UNBLANK:
-		ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
-		ctrl |=  SM501_DC_CRT_CONTROL_ENABLE;
-		sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
+		ctrl = FIELD_SET(ctrl, SYSTEM_CTRL, DPMS, VPHP);
 		break;
 
 	case FB_BLANK_VSYNC_SUSPEND:
+		ctrl = FIELD_SET(ctrl, SYSTEM_CTRL, DPMS, VNHP);
+		break;		
 	case FB_BLANK_HSYNC_SUSPEND:
+		ctrl = FIELD_SET(ctrl, SYSTEM_CTRL, DPMS, VPHN);
+		break;
 	default:
 		return 1;
 
 	}
 
-	writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
-	sm501fb_sync_regs(fbi);
+	SmWrite32(SYSTEM_CTRL, ctrl);
+	sm501fb_wait_panelvsnc(4);
 
 	return 0;
 }
@@ -1013,16 +1468,16 @@
 {
 	struct sm501fb_par  *par = info->par;
 	struct sm501fb_info *fbi = par->info;
-	void __iomem *base = fbi->regs;
+	unsigned long base;
 	unsigned long hwc_addr;
 	unsigned long fg, bg;
 
-	dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
+//	dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
 
 	if (par->head == HEAD_CRT)
-		base += SM501_DC_CRT_HWC_BASE;
+		base = CRT_HWC_ADDRESS;
 	else
-		base += SM501_DC_PANEL_HWC_BASE;
+		base = PANEL_HWC_ADDRESS;
 
 	/* check not being asked to exceed capabilities */
 
@@ -1035,12 +1490,12 @@
 	if (cursor->image.depth > 1)
 		return -EINVAL;
 
-	hwc_addr = readl(base + SM501_OFF_HWC_ADDR);
+	hwc_addr = SmRead32(base + SM501_OFF_HWC_ADDR);
 
 	if (cursor->enable)
-		writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
+		SmWrite32( base + SM501_OFF_HWC_ADDR, hwc_addr | SM501_HWC_EN);
 	else
-		writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
+		SmWrite32(base + SM501_OFF_HWC_ADDR, hwc_addr & ~SM501_HWC_EN );
 
 	/* set data */
 	if (cursor->set & FB_CUR_SETPOS) {
@@ -1050,11 +1505,11 @@
 		if (x >= 2048 || y >= 2048 )
 			return -EINVAL;
 
-		dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
+//		dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
 
 		//y += cursor->image.height;
 
-		writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
+		SmWrite32(base + SM501_OFF_HWC_LOC, x | (y << 16));
 	}
 
 	if (cursor->set & FB_CUR_SETCMAP) {
@@ -1072,10 +1527,10 @@
 			((info->cmap.green[fg_col] & 0xFC) << 3) |
 			((info->cmap.blue[fg_col] & 0xF8) >> 3);
 
-		dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
+		dev_dbg(fbi->dev, "fgcol %08x, bgcol %08x\n", fg, bg);
 
-		writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
-		writel(fg, base + SM501_OFF_HWC_COLOR_3);
+		SmWrite32(base + SM501_OFF_HWC_COLOR_1_2, bg);
+		SmWrite32(base + SM501_OFF_HWC_COLOR_3, fg);
 	}
 
 	if (cursor->set & FB_CUR_SETSIZE ||
@@ -1092,15 +1547,16 @@
 		unsigned char  dmsk = 0;
 		unsigned int   op;
 
-		dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
-			__func__, cursor->image.width, cursor->image.height);
+//		dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n", __func__, cursor->image.width, cursor->image.height);
 
 		for (op = 0; op < (64*64*2)/8; op+=4)
 			writel(0x0, dst + op);
 
 		for (y = 0; y < cursor->image.height; y++) {
-			for (x = 0; x < cursor->image.width; x++) {
-				if ((x % 8) == 0) {
+			for (x = 0; x < cursor->image.width; x++) 
+			{
+				if ((x % 8) == 0) 
+				{
 					dcol = *pcol++;
 					dmsk = *pmsk++;
 				} else {
@@ -1108,7 +1564,8 @@
 					dmsk >>= 1;
 				}
 
-				if (dmsk & 1) {
+				if (dmsk & 1) 
+				{
 					op = (dcol & 1) ? 1 : 3;
 					op <<= ((x % 4) * 2);
 
@@ -1124,10 +1581,182 @@
 	return 0;
 }
 
-/* sm501fb_crtsrc_show
- *
- * device attribute code to show where the crt output is sourced from
-*/
+
+static ssize_t
+sm501fb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
+{
+	unsigned long p = *ppos;
+	struct inode *inode = file->f_path.dentry->d_inode;
+	int fbidx = iminor(inode);
+	struct fb_info *info = registered_fb[fbidx];
+	u32 *buffer, *dst;
+	u32 __iomem *src;
+	int c, i, cnt = 0, err = 0;
+	unsigned long total_size;
+
+	if (!info || ! info->screen_base)
+		return -ENODEV;
+
+	if (info->state != FBINFO_STATE_RUNNING)
+		return -EPERM;
+
+	total_size = info->screen_size;
+
+	if (total_size == 0)
+		total_size = info->fix.smem_len;
+
+	if (p >= total_size)
+		return 0;
+
+	if (count >= total_size)
+		count = total_size;
+
+	if (count + p > total_size)
+		count = total_size - p;
+
+	buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
+			 GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	src = (u32 __iomem *) (info->screen_base + p);
+
+	if (info->fbops->fb_sync)
+		info->fbops->fb_sync(info);
+
+	while (count) {
+		c  = (count > PAGE_SIZE) ? PAGE_SIZE : count;
+		dst = buffer;
+		for (i = c >> 2; i--; ){
+			*dst = fb_readl(src++);
+			*dst  = (*dst & 0xff00ff00>>8)|(*dst & 0x00ff00ff<<8);
+			dst++;
+			}
+		if (c & 3) {
+			u8 *dst8 = (u8 *) dst;
+			u8 __iomem *src8 = (u8 __iomem *) src;
+
+			for (i = c & 3; i--;){
+				if (i&1){
+				*dst8++ = fb_readb(++src8);
+				}
+				else{
+				*dst8++ = fb_readb(--src8);
+				src8 +=2;
+				}
+			}
+			src = (u32 __iomem *) src8;
+		}
+
+		if (copy_to_user(buf, buffer, c)) {
+			err = -EFAULT;
+			break;
+		}
+		*ppos += c;
+		buf += c;
+		cnt += c;
+		count -= c;
+	}
+
+	kfree(buffer);
+
+	return (err) ? err : cnt;
+}
+
+static ssize_t
+sm501fb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
+{
+	unsigned long p = *ppos;
+	struct inode *inode = file->f_path.dentry->d_inode;
+	int fbidx = iminor(inode);
+	struct fb_info *info = registered_fb[fbidx];
+	u32 *buffer, *src;
+	u32 __iomem *dst;
+	int c, i, cnt = 0, err = 0;
+	unsigned long total_size;
+
+	if (!info || !info->screen_base)
+		return -ENODEV;
+
+	if (info->state != FBINFO_STATE_RUNNING)
+		return -EPERM;
+
+	
+	total_size = info->screen_size;
+
+	if (total_size == 0)
+		total_size = info->fix.smem_len;
+
+	if (p > total_size)
+		return -EFBIG;
+
+	if (count > total_size) {
+		err = -EFBIG;
+		count = total_size;
+	}
+
+	if (count + p > total_size) {
+		if (!err)
+			err = -ENOSPC;
+
+		count = total_size - p;
+	}
+
+	buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
+			 GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	dst = (u32 __iomem *) (info->screen_base + p);
+
+	if (info->fbops->fb_sync)
+		info->fbops->fb_sync(info);
+
+	while (count) {
+		c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
+		src = buffer;
+
+		if (copy_from_user(src, buf, c)) {
+			err = -EFAULT;
+			break;
+		}
+
+		for (i = c >> 2; i--; ){
+			fb_writel( (*src& 0xff00ff00>>8)|(*src& 0x00ff00ff<<8), dst++);
+			src++;
+		}
+		if (c & 3) {
+			u8 *src8 = (u8 *) src;
+			u8 __iomem *dst8 = (u8 __iomem *) dst;
+
+			for (i = c & 3; i--; ){
+				if (i&1){
+				fb_writeb(*src8++, ++dst8);
+				}
+				else{
+				fb_writeb(*src8++, --dst8);
+				dst8 +=2;
+				}
+			}
+			dst = (u32 __iomem *) dst8;
+		}
+
+		*ppos += c;
+		buf += c;
+		cnt += c;
+		count -= c;
+	}
+
+	kfree(buffer);
+
+	return (cnt) ? cnt : err;
+}
+
+
+/* sm501fb_crtsrc_show
+ *
+ * device attribute code to show where the crt output is sourced from
+*/
 
 static ssize_t sm501fb_crtsrc_show(struct device *dev,
 			       struct device_attribute *attr, char *buf)
@@ -1135,8 +1764,8 @@
 	struct sm501fb_info *info = dev_get_drvdata(dev);
 	unsigned long ctrl;
 
-	ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
-	ctrl &= SM501_DC_CRT_CONTROL_SEL;
+	ctrl = SmRead32(CRT_DISPLAY_CTRL);
+	ctrl = FIELD_GET(ctrl, CRT_DISPLAY_CTRL, SELECT);
 
 	return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel");
 }
@@ -1166,19 +1795,24 @@
 
 	dev_info(dev, "setting crt source to head %d\n", head);
 
-	ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
+	ctrl = SmRead32(CRT_DISPLAY_CTRL);
 
 	if (head == HEAD_CRT) {
-		ctrl |= SM501_DC_CRT_CONTROL_SEL;
-		ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
-		ctrl |= SM501_DC_CRT_CONTROL_TE;
+
+#ifdef CONFIG_FB_SM501_DUAL_HEAD
+		ctrl = FIELD_SET(ctrl, CRT_DISPLAY_CTRL, SELECT, CRT)||
+#else
+		ctrl = FIELD_SET(ctrl, CRT_DISPLAY_CTRL, SELECT, PANEL)||
+#endif
+			FIELD_SET(ctrl, CRT_DISPLAY_CTRL, PLANE, ENABLE)||
+				FIELD_SET(ctrl, CRT_DISPLAY_CTRL, TIMING, ENABLE);
 	} else {
-		ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
-		ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
-		ctrl &= ~SM501_DC_CRT_CONTROL_TE;
+		ctrl = FIELD_SET(ctrl, CRT_DISPLAY_CTRL, SELECT, PANEL)||
+			FIELD_SET(ctrl, CRT_DISPLAY_CTRL, PLANE, DISABLE)||
+				FIELD_SET(ctrl, CRT_DISPLAY_CTRL, TIMING, DISABLE);
 	}
-
-	writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
+	SmWrite32(CRT_DISPLAY_CTRL, ctrl);
+	
 	sm501fb_sync_regs(info);
 
 	return len;
@@ -1194,12 +1828,11 @@
 static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
 			     unsigned int start, unsigned int len)
 {
-	void __iomem *mem = info->regs;
 	char *buf = ptr;
 	unsigned int reg;
 
 	for (reg = start; reg < (len + start); reg += 4)
-		ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg));
+		ptr += sprintf(ptr, "%08x = %08x\n", reg, SmRead32(reg));
 
 	return ptr - buf;
 }
@@ -1215,8 +1848,8 @@
 	struct sm501fb_info *info = dev_get_drvdata(dev);
 	char *ptr = buf;
 
-	ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
-	ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
+	ptr += sm501fb_show_regs(info, ptr, CRT_DISPLAY_CTRL, 0x40);
+	ptr += sm501fb_show_regs(info, ptr, CRT_HWC_ADDRESS, 0x10);
 
 	return ptr - buf;
 }
@@ -1234,12 +1867,184 @@
 	struct sm501fb_info *info = dev_get_drvdata(dev);
 	char *ptr = buf;
 
-	ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
-	ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
+	ptr += sm501fb_show_regs(info, ptr, PANEL_DISPLAY_CTRL, 0x40);
+	ptr += sm501fb_show_regs(info, ptr, PANEL_HWC_ADDRESS, 0x10);
 
 	return ptr - buf;
 }
 
+
+
+void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
+{
+	struct sm501fb_par *p = (struct sm501fb_par*)info->par;
+	ulong ulreg;
+	if(noca)
+		goto soft;
+ 
+    if (!noaccel)
+    {
+    	if (!area->width || !area->height)
+            return;
+	/*
+       	deCopy(p->screen.sm_addr , 0, info->var.bits_per_pixel,  
+            area->dx, area->dy, area->width, area->height, 
+            p->screen.sm_addr, 0, area->sx, area->sy, 0, 0xC);
+        */
+
+	ulreg=SmRead32(DE_BASE_ADDRESS+DE_STRETCH_FORMAT);	
+	switch (info->var.bits_per_pixel)
+	{
+		case 8:
+			ulreg=FIELD_SET(ulreg,DE_STRETCH_FORMAT,PIXEL_FORMAT,8);
+			break;
+		case 16:
+			ulreg=FIELD_SET(ulreg,DE_STRETCH_FORMAT,PIXEL_FORMAT,16);
+			break;
+		case 24:
+		case 32:		
+			ulreg=FIELD_SET(ulreg,DE_STRETCH_FORMAT,PIXEL_FORMAT,32);
+			break;
+	}
+	SmWrite2D( DE_STRETCH_FORMAT, ulreg);
+        
+	deVideoMem2VideoMemBlt(p->screen.sm_addr, info->fix.line_length,area->sx, area->sy,
+							p->screen.sm_addr,info->fix.line_length,info->var.bits_per_pixel,
+							area->dx,area->dy,area->width,area->height,0xc);
+	
+    }
+    else
+    {
+soft:    
+        cfb_copyarea(info, area);
+    }
+}
+void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+{
+    	struct sm501fb_par *p = (struct sm501fb_par*)info->par;
+	ulong rop,color,bpp;
+	ulong color32[4]={0xffffff,0xFF0000,0xFF00,0xFF};
+	ulong color16[4]={0x001f,0x07e0,0xf800,0xffff};
+	ulong x,y;
+	
+	
+	if(nofr)
+		goto soft;
+ 
+	if (!noaccel)
+    	{
+       		 if (!rect->width || !rect->height)
+            		return;
+
+		if(info->var.bits_per_pixel == 8)
+			color = rect->color;
+		else
+			color = ((u32*)(info->pseudo_palette))[rect->color];
+	
+		if(rect->rop == ROP_COPY)
+			rop = 0xc;
+		else
+			rop = 0x6;
+		
+	       	
+		deRectFill(p->screen.sm_addr,info->fix.line_length,info->var.bits_per_pixel,
+			 rect->dx, rect->dy, rect->width, rect->height, color,rop);
+		return;
+			
+		if(rect->width != 800 || rect->height != 8)
+		{
+			deRectFill(p->screen.sm_addr,info->fix.line_length,info->var.bits_per_pixel,
+			 rect->dx, rect->dy, rect->width, rect->height, color,rop);
+		}
+		else
+		{
+			gen = gen %4;
+			if(info->var.bits_per_pixel == 16){
+				bpp=16;
+				color=color16[gen];	
+				x=0;
+				y=592;
+			}
+			else{	
+				bpp=32;
+				color=color32[gen];
+				x=400;
+				y=592;
+			}		
+			deRectFill(p->screen.sm_addr,info->fix.line_length,bpp,
+				 x, y, 400,8, color,rop);
+			printk("bpp=%d,color=%08x pos = [%d,%d]\n ",bpp,color,x,y);
+			gen++;
+		}
+	}
+	else
+	{	
+soft:	
+        	cfb_fillrect(info, rect);
+	}
+}
+
+void sm501fb_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+	ulong fgcol,bgcol;	
+	struct sm501fb_par *p = (struct sm501fb_par*)info->par;
+	if(noib)
+		goto soft;
+	
+#if 0
+    {
+	if(sm_accel_busy)
+		sm501fb_Wait_Idle();
+	cfb_imageblit(info, image);
+    }
+#else
+
+	ulong regvalue=SmRead2D(DE_STRETCH_FORMAT);
+	switch(info->var.bits_per_pixel)
+	{
+		case 8:
+			regvalue = FIELD_SET(regvalue,DE_STRETCH_FORMAT,PIXEL_FORMAT,8);
+			break;
+		case 16:
+			regvalue = FIELD_SET(regvalue,DE_STRETCH_FORMAT,PIXEL_FORMAT,16);
+			break;
+		case 32:	
+			regvalue = FIELD_SET(regvalue,DE_STRETCH_FORMAT,PIXEL_FORMAT,32);
+			break;
+	}
+
+	SmWrite2D(DE_STRETCH_FORMAT, regvalue);
+	
+	if(!noaccel && image->depth == 1)		
+	{
+	
+			if(info->fix.visual == FB_VISUAL_TRUECOLOR ||info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+			{
+				fgcol = ((u32*)info->pseudo_palette)[image->fg_color];
+				bgcol = ((u32*)info->pseudo_palette)[image->bg_color];		
+			}
+			else
+			{
+				fgcol = image->fg_color;
+				bgcol = image->bg_color;
+			}
+			deSystemMem2VideoMemMonoBlt(image->data,image->width/8,0,p->screen.sm_addr,
+									info->fix.line_length,info->var.bits_per_pixel,
+									image->dx,image->dy,image->width,image->height,fgcol,bgcol,
+									0xc);		
+		
+	}
+	else
+	{
+soft:	
+		cfb_imageblit(info,image);
+	}
+#endif
+}
+
+
+
+	
 static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
 
 /* framebuffer ops */
@@ -1248,13 +2053,18 @@
 	.owner		= THIS_MODULE,
 	.fb_check_var	= sm501fb_check_var_crt,
 	.fb_set_par	= sm501fb_set_par_crt,
-	.fb_blank	= sm501fb_blank_crt,
+	.fb_blank	= sm501fb_blank,
 	.fb_setcolreg	= sm501fb_setcolreg,
 	.fb_pan_display	= sm501fb_pan_crt,
 	.fb_cursor	= sm501fb_cursor,
-	.fb_fillrect	= cfb_fillrect,
-	.fb_copyarea	= cfb_copyarea,
-	.fb_imageblit	= cfb_imageblit,
+	.fb_fillrect	= sm501fb_fillrect,
+	.fb_copyarea	= sm501fb_copyarea,
+	.fb_imageblit	= sm501fb_imageblit,
+#ifdef __BIG_ENDIAN	
+//	.fb_setcmap = sm501fb_set_cmap,
+	.fb_write = sm501fb_write,
+	.fb_read = sm501fb_read,
+#endif
 };
 
 static struct fb_ops sm501fb_ops_pnl = {
@@ -1262,14 +2072,52 @@
 	.fb_check_var	= sm501fb_check_var_pnl,
 	.fb_set_par	= sm501fb_set_par_pnl,
 	.fb_pan_display	= sm501fb_pan_pnl,
-	.fb_blank	= sm501fb_blank_pnl,
+	.fb_blank	= sm501fb_blank,
 	.fb_setcolreg	= sm501fb_setcolreg,
 	.fb_cursor	= sm501fb_cursor,
-	.fb_fillrect	= cfb_fillrect,
-	.fb_copyarea	= cfb_copyarea,
-	.fb_imageblit	= cfb_imageblit,
+	.fb_fillrect	= sm501fb_fillrect,
+	.fb_copyarea	= sm501fb_copyarea,
+	.fb_imageblit	= sm501fb_imageblit,
+#ifdef __BIG_ENDIAN	
+//	.fb_setcmap = sm501fb_set_cmap,
+	.fb_write = sm501fb_write,
+	.fb_read = sm501fb_read,
+#endif
 };
 
+/* sm501fb_info_alloc
+ *
+ * creates and initialises an sm501fb_info structure
+*/
+
+static struct sm501fb_info *sm501fb_info_alloc(struct fb_info *fbinfo_crt,
+					       struct fb_info *fbinfo_pnl)
+{
+	struct sm501fb_info *info;
+	struct sm501fb_par  *par;
+
+	info = kzalloc(sizeof(struct sm501fb_info), GFP_KERNEL);
+	if (info) {
+		/* set the references back */
+
+		par = fbinfo_crt->par;
+		par->info = info;
+		par->head = HEAD_CRT;
+		fbinfo_crt->pseudo_palette = &par->pseudo_palette;
+
+		par = fbinfo_pnl->par;
+		par->info = info;
+		par->head = HEAD_PANEL;
+		fbinfo_pnl->pseudo_palette = &par->pseudo_palette;
+
+		/* store the two fbs into our info */
+		info->fb[HEAD_CRT] = fbinfo_crt;
+		info->fb[HEAD_PANEL] = fbinfo_pnl;
+	}
+
+	return info;
+}
+
 /* sm501_init_cursor
  *
  * initialise hw cursor parameters
@@ -1277,17 +2125,11 @@
 
 static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
 {
-	struct sm501fb_par *par;
-	struct sm501fb_info *info;
+	struct sm501fb_par *par = fbi->par;
+	struct sm501fb_info *info = par->info;
 	int ret;
 
-	if (fbi == NULL)
-		return 0;
-
-	par = fbi->par;
-	info = par->info;
-
-	par->cursor_regs = info->regs + reg_base;
+	par->cursor_regs = reg_base;
 
 	ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024);
 	if (ret < 0)
@@ -1295,11 +2137,11 @@
 
 	/* initialise the colour registers */
 
-	writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR);
+	SmWrite32(par->cursor_regs + SM501_OFF_HWC_ADDR, par->cursor.sm_addr);
 
-	writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
-	writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
-	writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
+	SmWrite32(par->cursor_regs + SM501_OFF_HWC_LOC, 0x0);
+	SmWrite32(par->cursor_regs + SM501_OFF_HWC_COLOR_1_2, 0x0);
+	SmWrite32(par->cursor_regs + SM501_OFF_HWC_COLOR_3, 0x0);
 	sm501fb_sync_regs(info);
 
 	return 0;
@@ -1314,9 +2156,11 @@
 			 struct platform_device *pdev)
 {
 	struct resource	*res;
-	struct device *dev = &pdev->dev;
-	int k;
-	int ret;
+	struct device *dev;
+	int ret, value;
+
+	info->dev = dev = &pdev->dev;
+	platform_set_drvdata(pdev, info);
 
 	info->irq = ret = platform_get_irq(pdev, 0);
 	if (ret < 0) {
@@ -1324,31 +2168,6 @@
 		dev_warn(dev, "no irq for device\n");
 	}
 
-	/* allocate, reserve and remap resources for registers */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res == NULL) {
-		dev_err(dev, "no resource definition for registers\n");
-		ret = -ENOENT;
-		goto err_release;
-	}
-
-	info->regs_res = request_mem_region(res->start,
-					    res->end - res->start,
-					    pdev->name);
-
-	if (info->regs_res == NULL) {
-		dev_err(dev, "cannot claim registers\n");
-		ret = -ENXIO;
-		goto err_release;
-	}
-
-	info->regs = ioremap(res->start, (res->end - res->start)+1);
-	if (info->regs == NULL) {
-		dev_err(dev, "cannot remap registers\n");
-		ret = -ENXIO;
-		goto err_regs_res;
-	}
-
 	/* allocate, reserve resources for framebuffer */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 	if (res == NULL) {
@@ -1360,6 +2179,7 @@
 	info->fbmem_res = request_mem_region(res->start,
 					     (res->end - res->start)+1,
 					     pdev->name);
+	
 	if (info->fbmem_res == NULL) {
 		dev_err(dev, "cannot claim framebuffer\n");
 		ret = -ENXIO;
@@ -1373,21 +2193,15 @@
 	}
 
 	info->fbmem_len = (res->end - res->start)+1;
-
-	/* clear framebuffer memory - avoids garbage data on unused fb */
-	memset(info->fbmem, 0, info->fbmem_len);
-
-	/* clear palette ram - undefined at power on */
-	for (k = 0; k < (256 * 3); k++)
-		writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
-
+		
 	/* enable display controller */
-	sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
+	value = SmRead32(CURRENT_GATE);
+	sm501_set_gate(FIELD_SET(value,POWER_MODE0_GATE, DISPLAY, ENABLE) );
 
 	/* setup cursors */
 
-	sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
-	sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
+	sm501_init_cursor(info->fb[HEAD_CRT], CRT_HWC_ADDRESS);
+	sm501_init_cursor(info->fb[HEAD_PANEL], PANEL_HWC_ADDRESS);
 
 	return 0; /* everything is setup */
 
@@ -1408,16 +2222,54 @@
 
 static void sm501fb_stop(struct sm501fb_info *info)
 {
+	int value;
 	/* disable display controller */
-	sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
+	value = SmRead32(CURRENT_GATE);
+	sm501_set_gate(FIELD_SET(value,POWER_MODE0_GATE, DISPLAY, DISABLE) );
 
 	iounmap(info->fbmem);
 	release_resource(info->fbmem_res);
 	kfree(info->fbmem_res);
 
-	iounmap(info->regs);
-	release_resource(info->regs_res);
-	kfree(info->regs_res);
+}
+
+static void sm501fb_info_release(struct sm501fb_info *info)
+{
+	kfree(info);
+}
+
+
+void sm501fb_cmap_swap(struct fb_cmap *cmap, struct fb_info *info)
+{
+	int i, start = 0;
+	u16 *red, *green, *blue, *transp;
+	unsigned int val;
+
+	red = cmap->red;
+	green = cmap->green;
+	blue = cmap->blue;
+	transp = cmap->transp;
+	start = cmap->start;
+
+		for (i = 0; i < cmap->len; i++) {
+			val  = chan_to_field(red[i],   &info->var.red);
+			val |= chan_to_field(green[i], &info->var.green);
+			val |= chan_to_field(blue[i],  &info->var.blue);
+		
+			if (transp){
+				val |= chan_to_field(transp[i],  &info->var.transp);
+			}
+			val = (val& 0xff00ff00>>8)|(val& 0x00ff00ff<<8);
+
+			red[i] = field_to_chan(val,&info->var.red);
+			green[i] = field_to_chan(val,&info->var.green);
+			blue[i] = field_to_chan(val,&info->var.blue);
+
+			if (transp+i)
+				transp[i] |= field_to_chan(val,&info->var.transp);
+		}
+
+	return ;
 }
 
 static int sm501fb_init_fb(struct fb_info *fb,
@@ -1430,25 +2282,31 @@
 	unsigned long ctrl;
 	unsigned int enable;
 	int ret;
-
+	
+	
 	switch (head) {
 	case HEAD_CRT:
-		pd = info->pdata->fb_crt;
-		ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
-		enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
 
+		pd = info->pdata->fb_crt;
+		ctrl = SmRead32(CRT_DISPLAY_CTRL);
+		enable = FIELD_GET(ctrl, CRT_DISPLAY_CTRL, PLANE);
 		/* ensure we set the correct source register */
 		if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
-			ctrl |= SM501_DC_CRT_CONTROL_SEL;
-			writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
+#ifdef CONFIG_FB_SM501_DUAL_HEAD
+		printk("monk config_fb_sm501_dual_head \n");
+		ctrl = FIELD_SET(ctrl, CRT_DISPLAY_CTRL, SELECT, CRT);
+#else
+		ctrl = FIELD_SET(ctrl, CRT_DISPLAY_CTRL, SELECT, PANEL/*CRT*/);
+#endif
+			SmWrite32(CRT_DISPLAY_CTRL, ctrl);
 		}
-
 		break;
 
 	case HEAD_PANEL:
 		pd = info->pdata->fb_pnl;
-		ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL);
-		enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
+		ctrl = SmRead32(PANEL_DISPLAY_CTRL);
+		enable =FIELD_GET(ctrl, PANEL_DISPLAY_CTRL, PLANE);
+
 		break;
 
 	default:
@@ -1458,14 +2316,18 @@
 		BUG();
 	}
 
+
+
 	dev_info(info->dev, "fb %s %sabled at start\n",
 		 fbname, enable ? "en" : "dis");
 
 	/* check to see if our routing allows this */
 
+
+	
 	if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
-		ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
-		writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
+		ctrl = FIELD_SET(ctrl, CRT_DISPLAY_CTRL, SELECT, PANEL);
+		SmWrite32(CRT_DISPLAY_CTRL, ctrl);
 		enable = 0;
 	}
 
@@ -1474,12 +2336,12 @@
 	memcpy(&par->ops,
 	       (head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
 	       sizeof(struct fb_ops));
-
+		
 	/* update ops dependant on what we've been passed */
 
 	if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
 		par->ops.fb_cursor = NULL;
-
+	
 	fb->fbops = &par->ops;
 	fb->flags = FBINFO_FLAG_DEFAULT |
 		FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
@@ -1495,15 +2357,20 @@
 
 	/* screenmode */
 
-	fb->var.nonstd		= 0;
+	if (dcolor)
+		fb->var.nonstd = 1;
 	fb->var.activate	= FB_ACTIVATE_NOW;
 	fb->var.accel_flags	= 0;
 	fb->var.vmode		= FB_VMODE_NONINTERLACED;
 	fb->var.bits_per_pixel  = 16;
 
-	if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
-		/* TODO read the mode from the current display */
-
+	if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE)&&0) {
+/*		fb->var.xres = screen_info.lfb_width;
+		fb->var.yres = screen_info.lfb_height;
+		fb->var.bits_per_pixel = screen_info.lfb_depth;
+		fb->var.xres_virtual = fb->var.xres;
+		fb->var.yres_virtual = fb->var.yres;
+*/
 	} else {
 		if (pd->def_mode) {
 			dev_info(info->dev, "using supplied mode\n");
@@ -1513,9 +2380,11 @@
 			fb->var.xres_virtual = fb->var.xres;
 			fb->var.yres_virtual = fb->var.yres;
 		} else {
-			ret = fb_find_mode(&fb->var, fb,
-					   NULL, NULL, 0, NULL, 8);
-
+			ret = fb_find_mode(&fb->var, fb, mode_option, SM501modedb, ARRAY_SIZE(SM501modedb), NULL, 16);
+			if(ret != 1)
+			{
+			ret = fb_find_mode(&fb->var, fb, mode_option, NULL, 0, NULL, 16);
+			}
 			if (ret == 0 || ret == 4) {
 				dev_err(info->dev,
 					"failed to get initial mode\n");
@@ -1523,9 +2392,10 @@
 			}
 		}
 	}
-
+	
 	/* initialise and set the palette */
 	fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0);
+//	sm501fb_cmap_swap(&fb->cmap, fb);
 	fb_set_cmap(&fb->cmap, fb);
 
 	ret = (fb->fbops->fb_check_var)(&fb->var, fb);
@@ -1540,7 +2410,14 @@
 
 /* default platform data if none is supplied (ie, PCI device) */
 
+static struct fb_videomode default_mode = {
+	/* 640x480 @ 60 Hz, 31.5 kHz hsync */
+	NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
+	0, FB_VMODE_NONINTERLACED
+};
+
 static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
+//	.def_mode	= &default_mode;
 	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
 			   SM501FB_FLAG_USE_HWCURSOR |
 			   SM501FB_FLAG_USE_HWACCEL |
@@ -1549,6 +2426,7 @@
 };
 
 static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
+//	.def_mode	= &default_mode;
 	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
 			   SM501FB_FLAG_USE_HWCURSOR |
 			   SM501FB_FLAG_USE_HWACCEL |
@@ -1564,185 +2442,150 @@
 static char driver_name_crt[] = "sm501fb-crt";
 static char driver_name_pnl[] = "sm501fb-panel";
 
-static int __devinit sm501fb_probe_one(struct sm501fb_info *info,
-				       enum sm501_controller head)
+static int __init sm501fb_probe(struct platform_device *pdev)
 {
-	unsigned char *name = (head == HEAD_CRT) ? "crt" : "panel";
-	struct sm501_platdata_fbsub *pd;
-	struct sm501fb_par *par;
-	struct fb_info *fbi;
-
-	pd = (head == HEAD_CRT) ? info->pdata->fb_crt : info->pdata->fb_pnl;
+	struct sm501fb_info *info;
+	struct device	    *dev = &pdev->dev;
+	struct fb_info	    *fbinfo_crt;
+	struct fb_info	    *fbinfo_pnl;
+	int		     ret;
 
-	/* Do not initialise if we've not been given any platform data */
-	if (pd == NULL) {
-		dev_info(info->dev, "no data for fb %s (disabled)\n", name);
-		return 0;
-	}
+	/* allocate our framebuffers */
 
-	fbi = framebuffer_alloc(sizeof(struct sm501fb_par), info->dev);
-	if (fbi == NULL) {
-		dev_err(info->dev, "cannot allocate %s framebuffer\n", name);
+	fbinfo_crt = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
+	if (fbinfo_crt == NULL) {
+		dev_err(dev, "cannot allocate crt framebuffer\n");
 		return -ENOMEM;
 	}
 
-	par = fbi->par;
-	par->info = info;
-	par->head = head;
-	fbi->pseudo_palette = &par->pseudo_palette;
-
-	info->fb[head] = fbi;
-
-	return 0;
-}
-
-/* Free up anything allocated by sm501fb_init_fb */
-
-static void sm501_free_init_fb(struct sm501fb_info *info,
-				enum sm501_controller head)
-{
-	struct fb_info *fbi = info->fb[head];
-
-	fb_dealloc_cmap(&fbi->cmap);
-}
-
-static int __devinit sm501fb_start_one(struct sm501fb_info *info,
-				       enum sm501_controller head,
-				       const char *drvname)
-{
-	struct fb_info *fbi = info->fb[head];
-	int ret;
-
-	if (!fbi)
-		return 0;
-
-	ret = sm501fb_init_fb(info->fb[head], head, drvname);
-	if (ret) {
-		dev_err(info->dev, "cannot initialise fb %s\n", drvname);
-		return ret;
+	fbinfo_pnl = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
+	if (fbinfo_pnl == NULL) {
+		dev_err(dev, "cannot allocate panel framebuffer\n");
+		ret = -ENOMEM;
+		goto fbinfo_crt_alloc_fail;
 	}
 
-	ret = register_framebuffer(info->fb[head]);
-	if (ret) {
-		dev_err(info->dev, "failed to register fb %s\n", drvname);
-		sm501_free_init_fb(info, head);
-		return ret;
+	info = sm501fb_info_alloc(fbinfo_crt, fbinfo_pnl);
+	if (info == NULL) {
+		dev_err(dev, "cannot allocate par\n");
+		ret = -ENOMEM;
+		goto sm501fb_alloc_fail;
 	}
 
-	dev_info(info->dev, "fb%d: %s frame buffer\n", fbi->node, fbi->fix.id);
-
-	return 0;
-}
-
-static int __devinit sm501fb_probe(struct platform_device *pdev)
-{
-	struct sm501fb_info *info;
-	struct device *dev = &pdev->dev;
-	int ret;
-
-	/* allocate our framebuffers */
-
-	info = kzalloc(sizeof(struct sm501fb_info), GFP_KERNEL);
-	if (!info) {
-		dev_err(dev, "failed to allocate state\n");
-		return -ENOMEM;
-	}
-
-	info->dev = dev = &pdev->dev;
-	platform_set_drvdata(pdev, info);
-
 	if (dev->parent->platform_data) {
 		struct sm501_platdata *pd = dev->parent->platform_data;
 		info->pdata = pd->fb;
 	}
 
 	if (info->pdata == NULL) {
-		dev_info(dev, "using default configuration data\n");
+		dev_dbg(dev, "using default configuration data\n");
 		info->pdata = &sm501fb_def_pdata;
 	}
 
-	/* probe for the presence of each panel */
+	if (!nomtrr)
+		sm501fb_set_mtrr(info->dev->parent);
+	
+	/* start the framebuffers */
 
-	ret = sm501fb_probe_one(info, HEAD_CRT);
-	if (ret < 0) {
-		dev_err(dev, "failed to probe CRT\n");
-		goto err_alloc;
+	ret = sm501fb_start(info, pdev);
+	if (ret) {
+		dev_err(dev, "cannot initialise SM501\n");
+		goto sm501fb_start_fail;
 	}
 
-	ret = sm501fb_probe_one(info, HEAD_PANEL);
-	if (ret < 0) {
-		dev_err(dev, "failed to probe PANEL\n");
-		goto err_probed_crt;
-	}
 
-	if (info->fb[HEAD_PANEL] == NULL &&
-	    info->fb[HEAD_CRT] == NULL) {
-		dev_err(dev, "no framebuffers found\n");
-		goto err_alloc;
+	memset(info->fbmem,0,info->fbmem_len); //Teddy:Clease screen before set timing registers.
+	
+	/* CRT framebuffer setup */
+
+	ret = sm501fb_init_fb(fbinfo_crt, HEAD_CRT, driver_name_crt);
+	if (ret) {
+		dev_err(dev, "cannot initialise CRT fb\n");
+		goto sm501fb_start_fail;
 	}
 
-	/* get the resources for both of the framebuffers */
+	/* Panel framebuffer setup */
 
-	ret = sm501fb_start(info, pdev);
+	ret = sm501fb_init_fb(fbinfo_pnl, HEAD_PANEL, driver_name_pnl);
 	if (ret) {
-		dev_err(dev, "cannot initialise SM501\n");
-		goto err_probed_panel;
+		dev_err(dev, "cannot initialise Panel fb\n");
+		goto sm501fb_start_fail;
 	}
 
-	ret = sm501fb_start_one(info, HEAD_CRT, driver_name_crt);
-	if (ret) {
-		dev_err(dev, "failed to start CRT\n");
-		goto err_started;
+	/* Init sm501 drawing engine */
+	if(!noaccel)
+       	{
+       		//deInit(fbinfo_crt->var.xres, fbinfo_crt->var.yres, fbinfo_crt->var.bits_per_pixel); 
+		printk("2d accel enabled\n");			
+	}
+	else
+	{
+		printk("2d accel disabled\n");
 	}
 
-	ret = sm501fb_start_one(info, HEAD_PANEL, driver_name_pnl);
-	if (ret) {
-		dev_err(dev, "failed to start Panel\n");
-		goto err_started_crt;
+	
+	
+	
+	/* register framebuffers */
+
+	ret = register_framebuffer(fbinfo_pnl);
+	if (ret < 0) {
+		dev_err(dev, "failed to register panel fb (%d)\n", ret);
+		goto register_pnl_fail;
 	}
 
-	/* create device files */
+	ret = register_framebuffer(fbinfo_crt);
+	if (ret < 0) {
+		dev_err(dev, "failed to register CRT fb (%d)\n", ret);
+		goto register_crt_fail;
+	}
+	
+
+	dev_dbg(dev, "accel: x:%dx%d bit_pixel: %d\n", fbinfo_crt->var.xres, fbinfo_crt->var.yres, fbinfo_crt->var.bits_per_pixel);	
+	
+	dev_dbg(dev, "fb%d: %s frame buffer device\n",
+		 fbinfo_crt->node, fbinfo_crt->fix.id);
+
+	dev_dbg(dev, "fb%d: %s frame buffer device\n",
+	       fbinfo_pnl->node, fbinfo_pnl->fix.id);
 
+	/* create device files */
 	ret = device_create_file(dev, &dev_attr_crt_src);
 	if (ret)
-		goto err_started_panel;
-
+		goto crtsrc_fail;
 	ret = device_create_file(dev, &dev_attr_fbregs_pnl);
 	if (ret)
-		goto err_attached_crtsrc_file;
-
+		goto fbregs_pnl_fail;
 	ret = device_create_file(dev, &dev_attr_fbregs_crt);
 	if (ret)
-		goto err_attached_pnlregs_file;
+		goto fbregs_crt_fail;
 
 	/* we registered, return ok */
 	return 0;
 
-err_attached_pnlregs_file:
+ fbregs_crt_fail:
 	device_remove_file(dev, &dev_attr_fbregs_pnl);
 
-err_attached_crtsrc_file:
+ fbregs_pnl_fail:
 	device_remove_file(dev, &dev_attr_crt_src);
 
-err_started_panel:
-	unregister_framebuffer(info->fb[HEAD_PANEL]);
-	sm501_free_init_fb(info, HEAD_PANEL);
-
-err_started_crt:
-	unregister_framebuffer(info->fb[HEAD_CRT]);
-	sm501_free_init_fb(info, HEAD_CRT);
+ crtsrc_fail:
+	unregister_framebuffer(fbinfo_pnl);
+
+ register_pnl_fail:
+	unregister_framebuffer(fbinfo_crt);
 
-err_started:
+ register_crt_fail:
 	sm501fb_stop(info);
 
-err_probed_panel:
-	framebuffer_release(info->fb[HEAD_PANEL]);
+ sm501fb_start_fail:
+	sm501fb_info_release(info);
 
-err_probed_crt:
-	framebuffer_release(info->fb[HEAD_CRT]);
+ sm501fb_alloc_fail:
+	framebuffer_release(fbinfo_pnl);
 
-err_alloc:
-	kfree(info);
+ fbinfo_crt_alloc_fail:
+	framebuffer_release(fbinfo_crt);
 
 	return ret;
 }
@@ -1761,14 +2604,12 @@
 	device_remove_file(&pdev->dev, &dev_attr_fbregs_pnl);
 	device_remove_file(&pdev->dev, &dev_attr_crt_src);
 
-	sm501_free_init_fb(info, HEAD_CRT);
-	sm501_free_init_fb(info, HEAD_PANEL);
-
-	unregister_framebuffer(fbinfo_crt);
 	unregister_framebuffer(fbinfo_pnl);
-
+	unregister_framebuffer(fbinfo_crt);
+	if (!nomtrr)
+		sm501fb_unset_mtrr(info->dev->parent);
 	sm501fb_stop(info);
-	kfree(info);
+	sm501fb_info_release(info);
 
 	framebuffer_release(fbinfo_pnl);
 	framebuffer_release(fbinfo_crt);
@@ -1795,7 +2636,6 @@
 	acquire_console_sem();
 	fb_set_suspend(fbi, 1);
 	release_console_sem();
-
 	/* backup copies in case chip is powered down over suspend */
 
 	par->store_fb = vmalloc(par->screen.size);
@@ -1810,9 +2650,6 @@
 		goto err_nocursor;
 	}
 
-	dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
-	dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
-
 	memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
 	memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
 
@@ -1866,36 +2703,28 @@
 {
 	struct sm501fb_info *info = platform_get_drvdata(pdev);
 
-	/* store crt control to resume with */
-	info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
-
 	sm501fb_suspend_fb(info, HEAD_CRT);
 	sm501fb_suspend_fb(info, HEAD_PANEL);
 
 	/* turn off the clocks, in case the device is not powered down */
-	sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
+
+	int value = SmRead32(CURRENT_GATE);
+	sm501_set_gate(FIELD_SET(value,POWER_MODE0_GATE, DISPLAY,DISABLE)&
+		FIELD_SET(value, POWER_MODE0_GATE, 2D, DISABLE)&
+		FIELD_SET(value, POWER_MODE0_GATE, CSC, DISABLE) );
 
 	return 0;
 }
 
-#define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP |        \
-			     SM501_DC_CRT_CONTROL_SEL)
-
-
 static int sm501fb_resume(struct platform_device *pdev)
 {
 	struct sm501fb_info *info = platform_get_drvdata(pdev);
-	unsigned long crt_ctrl;
-
-	sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
-
-	/* restore the items we want to be saved for crt control */
-
-	crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
-	crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
-	crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
-	writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
 
+	int value = SmRead32(CURRENT_GATE);
+	sm501_set_gate(FIELD_SET(value, POWER_MODE0_GATE, DISPLAY, ENABLE)|
+		FIELD_SET(value, POWER_MODE0_GATE, 2D, ENABLE)|
+		FIELD_SET(value, POWER_MODE0_GATE, CSC, ENABLE) );
+	
 	sm501fb_resume_fb(info, HEAD_CRT);
 	sm501fb_resume_fb(info, HEAD_PANEL);
 
@@ -1910,7 +2739,7 @@
 static struct platform_driver sm501fb_driver = {
 	.probe		= sm501fb_probe,
 	.remove		= sm501fb_remove,
-	.suspend	= sm501fb_suspend,
+	.suspend		= sm501fb_suspend,
 	.resume		= sm501fb_resume,
 	.driver		= {
 		.name	= "sm501-fb",
@@ -1918,8 +2747,54 @@
 	},
 };
 
+/*
+ * Interface to the world
+ */
+static int  __devinit sm501fb_setup(char *options)
+{
+	char *this_opt;
+
+	if (!options || !*options)
+		return 0;
+
+	while ((this_opt = strsep(&options, ",")) != NULL) {
+		if (!*this_opt) continue;
+
+		smdbg("option %s\n", this_opt);
+
+		if (!strncmp(this_opt,"noaccel",7))
+			noaccel = 1;
+		else	if (!strncmp(this_opt,"dcolor",6))
+			dcolor = 1;
+		else if(!strncmp(this_opt,"nofr",4))
+			nofr=1;
+		else if(!strncmp(this_opt,"noca",4))
+			noca=1;
+		else if(!strncmp(this_opt,"noib",4))
+			noib=1;
+		else
+			mode_option = this_opt;
+		//noaccel = 0;
+	}
+	return 0;
+}
+
+
 static int __devinit sm501fb_init(void)
 {
+	char *option = NULL;
+
+        /* Jason (08/05/2009):
+         * if there are params passed using modprobe, use those
+         * if not, use the booting vesa params.
+         */
+#ifdef MODULE
+        option = mode_option;
+#else
+        if (fb_get_options("sm501fb", &option))
+            return -ENODEV;
+#endif
+	sm501fb_setup(option);
 	return platform_driver_register(&sm501fb_driver);
 }
 
@@ -1931,6 +2806,18 @@
 module_init(sm501fb_init);
 module_exit(sm501fb_cleanup);
 
-MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
-MODULE_DESCRIPTION("SM501 Framebuffer driver");
+module_param(mode_option, charp, 0);
+MODULE_PARM_DESC(mode_option, "Initial mode (default=" DEFAULT_MODE ")");
+module_param(noaccel, bool, 0);
+MODULE_PARM_DESC(noaccel, "bool: Disable acceleration support (0 or 1=disabled) (default=0)");
+module_param(mirror, bool, 0);
+MODULE_PARM_DESC(mirror, "bool: Mirror the display to both monitors");
+module_param(dcolor, bool, 0);
+MODULE_PARM_DESC(dcolor, "bool: Enable Direct color.");
+
+module_param(nomtrr, bool, 1);
+MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
+
+MODULE_AUTHOR("Boyod Yang, Ben Dooks, Vincent Sanders");
+MODULE_DESCRIPTION("SM50x Framebuffer driver");
 MODULE_LICENSE("GPL v2");
diff -uNra linux-2.6.27.6/fs/compat_ioctl.c linux-2.6.27.6.yaffs/fs/compat_ioctl.c
--- linux-2.6.27.6/fs/compat_ioctl.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/compat_ioctl.c	2011-05-08 18:01:20.000000000 +0800
@@ -723,6 +723,8 @@
 	void __user *dxferp;
 	int err;
 
+	//printk("wgl : function = %s, file = %s\n", __func__, __FILE__);
+
 	sgio32 = compat_ptr(arg);
 	if (get_user(iovec_count, &sgio32->iovec_count))
 		return -EFAULT;
diff -uNra linux-2.6.27.6/fs/Kconfig linux-2.6.27.6.yaffs/fs/Kconfig
--- linux-2.6.27.6/fs/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/Kconfig	2011-05-08 18:01:06.000000000 +0800
@@ -1136,6 +1136,10 @@
 	  To compile the EFS file system support as a module, choose M here: the
 	  module will be called efs.
 
+
+# Patched by YAFFS
+source "fs/yaffs2/Kconfig"
+
 config JFFS2_FS
 	tristate "Journalling Flash File System v2 (JFFS2) support"
 	select CRC32
diff -uNra linux-2.6.27.6/fs/Kconfig.pre.yaffs linux-2.6.27.6.yaffs/fs/Kconfig.pre.yaffs
--- linux-2.6.27.6/fs/Kconfig.pre.yaffs	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/Kconfig.pre.yaffs	2011-05-08 18:01:12.000000000 +0800
@@ -0,0 +1,2096 @@
+#
+# File system configuration
+#
+
+menu "File systems"
+
+if BLOCK
+
+config EXT2_FS
+	tristate "Second extended fs support"
+	help
+	  Ext2 is a standard Linux file system for hard disks.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called ext2.
+
+	  If unsure, say Y.
+
+config EXT2_FS_XATTR
+	bool "Ext2 extended attributes"
+	depends on EXT2_FS
+	help
+	  Extended attributes are name:value pairs associated with inodes by
+	  the kernel or by users (see the attr(5) manual page, or visit
+	  <http://acl.bestbits.at/> for details).
+
+	  If unsure, say N.
+
+config EXT2_FS_POSIX_ACL
+	bool "Ext2 POSIX Access Control Lists"
+	depends on EXT2_FS_XATTR
+	select FS_POSIX_ACL
+	help
+	  Posix Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the Posix ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N
+
+config EXT2_FS_SECURITY
+	bool "Ext2 Security Labels"
+	depends on EXT2_FS_XATTR
+	help
+	  Security labels support alternative access control models
+	  implemented by security modules like SELinux.  This option
+	  enables an extended attribute handler for file security
+	  labels in the ext2 filesystem.
+
+	  If you are not using a security module that requires using
+	  extended attributes for file security labels, say N.
+
+config EXT2_FS_XIP
+	bool "Ext2 execute in place support"
+	depends on EXT2_FS && MMU
+	help
+	  Execute in place can be used on memory-backed block devices. If you
+	  enable this option, you can select to mount block devices which are
+	  capable of this feature without using the page cache.
+
+	  If you do not use a block device that is capable of using this,
+	  or if unsure, say N.
+
+config FS_XIP
+# execute in place
+	bool
+	depends on EXT2_FS_XIP
+	default y
+
+config EXT3_FS
+	tristate "Ext3 journalling file system support"
+	select JBD
+	help
+	  This is the journalling version of the Second extended file system
+	  (often called ext3), the de facto standard Linux file system
+	  (method to organize files on a storage device) for hard disks.
+
+	  The journalling code included in this driver means you do not have
+	  to run e2fsck (file system checker) on your file systems after a
+	  crash.  The journal keeps track of any changes that were being made
+	  at the time the system crashed, and can ensure that your file system
+	  is consistent without the need for a lengthy check.
+
+	  Other than adding the journal to the file system, the on-disk format
+	  of ext3 is identical to ext2.  It is possible to freely switch
+	  between using the ext3 driver and the ext2 driver, as long as the
+	  file system has been cleanly unmounted, or e2fsck is run on the file
+	  system.
+
+	  To add a journal on an existing ext2 file system or change the
+	  behavior of ext3 file systems, you can use the tune2fs utility ("man
+	  tune2fs").  To modify attributes of files and directories on ext3
+	  file systems, use chattr ("man chattr").  You need to be using
+	  e2fsprogs version 1.20 or later in order to create ext3 journals
+	  (available at <http://sourceforge.net/projects/e2fsprogs/>).
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called ext3.
+
+config EXT3_FS_XATTR
+	bool "Ext3 extended attributes"
+	depends on EXT3_FS
+	default y
+	help
+	  Extended attributes are name:value pairs associated with inodes by
+	  the kernel or by users (see the attr(5) manual page, or visit
+	  <http://acl.bestbits.at/> for details).
+
+	  If unsure, say N.
+
+	  You need this for POSIX ACL support on ext3.
+
+config EXT3_FS_POSIX_ACL
+	bool "Ext3 POSIX Access Control Lists"
+	depends on EXT3_FS_XATTR
+	select FS_POSIX_ACL
+	help
+	  Posix Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the Posix ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N
+
+config EXT3_FS_SECURITY
+	bool "Ext3 Security Labels"
+	depends on EXT3_FS_XATTR
+	help
+	  Security labels support alternative access control models
+	  implemented by security modules like SELinux.  This option
+	  enables an extended attribute handler for file security
+	  labels in the ext3 filesystem.
+
+	  If you are not using a security module that requires using
+	  extended attributes for file security labels, say N.
+
+config EXT4DEV_FS
+	tristate "Ext4dev/ext4 extended fs support development (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	select JBD2
+	select CRC16
+	help
+	  Ext4dev is a predecessor filesystem of the next generation
+	  extended fs ext4, based on ext3 filesystem code. It will be
+	  renamed ext4 fs later, once ext4dev is mature and stabilized.
+
+	  Unlike the change from ext2 filesystem to ext3 filesystem,
+	  the on-disk format of ext4dev is not the same as ext3 any more:
+	  it is based on extent maps and it supports 48-bit physical block
+	  numbers. These combined on-disk format changes will allow
+	  ext4dev/ext4 to handle more than 16 TB filesystem volumes --
+	  a hard limit that ext3 cannot overcome without changing the
+	  on-disk format.
+
+	  Other than extent maps and 48-bit block numbers, ext4dev also is
+	  likely to have other new features such as persistent preallocation,
+	  high resolution time stamps, and larger file support etc.  These
+	  features will be added to ext4dev gradually.
+
+	  To compile this file system support as a module, choose M here. The
+	  module will be called ext4dev.
+
+	  If unsure, say N.
+
+config EXT4DEV_FS_XATTR
+	bool "Ext4dev extended attributes"
+	depends on EXT4DEV_FS
+	default y
+	help
+	  Extended attributes are name:value pairs associated with inodes by
+	  the kernel or by users (see the attr(5) manual page, or visit
+	  <http://acl.bestbits.at/> for details).
+
+	  If unsure, say N.
+
+	  You need this for POSIX ACL support on ext4dev/ext4.
+
+config EXT4DEV_FS_POSIX_ACL
+	bool "Ext4dev POSIX Access Control Lists"
+	depends on EXT4DEV_FS_XATTR
+	select FS_POSIX_ACL
+	help
+	  POSIX Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the POSIX ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N
+
+config EXT4DEV_FS_SECURITY
+	bool "Ext4dev Security Labels"
+	depends on EXT4DEV_FS_XATTR
+	help
+	  Security labels support alternative access control models
+	  implemented by security modules like SELinux.  This option
+	  enables an extended attribute handler for file security
+	  labels in the ext4dev/ext4 filesystem.
+
+	  If you are not using a security module that requires using
+	  extended attributes for file security labels, say N.
+
+config JBD
+	tristate
+	help
+	  This is a generic journalling layer for block devices.  It is
+	  currently used by the ext3 and OCFS2 file systems, but it could
+	  also be used to add journal support to other file systems or block
+	  devices such as RAID or LVM.
+
+	  If you are using the ext3 or OCFS2 file systems, you need to
+	  say Y here. If you are not using ext3 OCFS2 then you will probably
+	  want to say N.
+
+	  To compile this device as a module, choose M here: the module will be
+	  called jbd.  If you are compiling ext3 or OCFS2 into the kernel,
+	  you cannot compile this code as a module.
+
+config JBD_DEBUG
+	bool "JBD (ext3) debugging support"
+	depends on JBD && DEBUG_FS
+	help
+	  If you are using the ext3 journaled file system (or potentially any
+	  other file system/device using JBD), this option allows you to
+	  enable debugging output while the system is running, in order to
+	  help track down any problems you are having.  By default the
+	  debugging output will be turned off.
+
+	  If you select Y here, then you will be able to turn on debugging
+	  with "echo N > /sys/kernel/debug/jbd/jbd-debug", where N is a
+	  number between 1 and 5, the higher the number, the more debugging
+	  output is generated.  To turn debugging off again, do
+	  "echo 0 > /sys/kernel/debug/jbd/jbd-debug".
+
+config JBD2
+	tristate
+	select CRC32
+	help
+	  This is a generic journaling layer for block devices that support
+	  both 32-bit and 64-bit block numbers.  It is currently used by
+	  the ext4dev/ext4 filesystem, but it could also be used to add
+	  journal support to other file systems or block devices such
+	  as RAID or LVM.
+
+	  If you are using ext4dev/ext4, you need to say Y here. If you are not
+	  using ext4dev/ext4 then you will probably want to say N.
+
+	  To compile this device as a module, choose M here. The module will be
+	  called jbd2.  If you are compiling ext4dev/ext4 into the kernel,
+	  you cannot compile this code as a module.
+
+config JBD2_DEBUG
+	bool "JBD2 (ext4dev/ext4) debugging support"
+	depends on JBD2 && DEBUG_FS
+	help
+	  If you are using the ext4dev/ext4 journaled file system (or
+	  potentially any other filesystem/device using JBD2), this option
+	  allows you to enable debugging output while the system is running,
+	  in order to help track down any problems you are having.
+	  By default, the debugging output will be turned off.
+
+	  If you select Y here, then you will be able to turn on debugging
+	  with "echo N > /sys/kernel/debug/jbd2/jbd2-debug", where N is a
+	  number between 1 and 5. The higher the number, the more debugging
+	  output is generated.  To turn debugging off again, do
+	  "echo 0 > /sys/kernel/debug/jbd2/jbd2-debug".
+
+config FS_MBCACHE
+# Meta block cache for Extended Attributes (ext2/ext3/ext4)
+	tristate
+	depends on EXT2_FS_XATTR || EXT3_FS_XATTR || EXT4DEV_FS_XATTR
+	default y if EXT2_FS=y || EXT3_FS=y || EXT4DEV_FS=y
+	default m if EXT2_FS=m || EXT3_FS=m || EXT4DEV_FS=m
+
+config REISERFS_FS
+	tristate "Reiserfs support"
+	help
+	  Stores not just filenames but the files themselves in a balanced
+	  tree.  Uses journalling.
+
+	  Balanced trees are more efficient than traditional file system
+	  architectural foundations.
+
+	  In general, ReiserFS is as fast as ext2, but is very efficient with
+	  large directories and small files.  Additional patches are needed
+	  for NFS and quotas, please see <http://www.namesys.com/> for links.
+
+	  It is more easily extended to have features currently found in
+	  database and keyword search systems than block allocation based file
+	  systems are.  The next version will be so extended, and will support
+	  plugins consistent with our motto ``It takes more than a license to
+	  make source code open.''
+
+	  Read <http://www.namesys.com/> to learn more about reiserfs.
+
+	  Sponsored by Threshold Networks, Emusic.com, and Bigstorage.com.
+
+	  If you like it, you can pay us to add new features to it that you
+	  need, buy a support contract, or pay us to port it to another OS.
+
+config REISERFS_CHECK
+	bool "Enable reiserfs debug mode"
+	depends on REISERFS_FS
+	help
+	  If you set this to Y, then ReiserFS will perform every check it can
+	  possibly imagine of its internal consistency throughout its
+	  operation.  It will also go substantially slower.  More than once we
+	  have forgotten that this was on, and then gone despondent over the
+	  latest benchmarks.:-) Use of this option allows our team to go all
+	  out in checking for consistency when debugging without fear of its
+	  effect on end users.  If you are on the verge of sending in a bug
+	  report, say Y and you might get a useful error message.  Almost
+	  everyone should say N.
+
+config REISERFS_PROC_INFO
+	bool "Stats in /proc/fs/reiserfs"
+	depends on REISERFS_FS && PROC_FS
+	help
+	  Create under /proc/fs/reiserfs a hierarchy of files, displaying
+	  various ReiserFS statistics and internal data at the expense of
+	  making your kernel or module slightly larger (+8 KB). This also
+	  increases the amount of kernel memory required for each mount.
+	  Almost everyone but ReiserFS developers and people fine-tuning
+	  reiserfs or tracing problems should say N.
+
+config REISERFS_FS_XATTR
+	bool "ReiserFS extended attributes"
+	depends on REISERFS_FS
+	help
+	  Extended attributes are name:value pairs associated with inodes by
+	  the kernel or by users (see the attr(5) manual page, or visit
+	  <http://acl.bestbits.at/> for details).
+
+	  If unsure, say N.
+
+config REISERFS_FS_POSIX_ACL
+	bool "ReiserFS POSIX Access Control Lists"
+	depends on REISERFS_FS_XATTR
+	select FS_POSIX_ACL
+	help
+	  Posix Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the Posix ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N
+
+config REISERFS_FS_SECURITY
+	bool "ReiserFS Security Labels"
+	depends on REISERFS_FS_XATTR
+	help
+	  Security labels support alternative access control models
+	  implemented by security modules like SELinux.  This option
+	  enables an extended attribute handler for file security
+	  labels in the ReiserFS filesystem.
+
+	  If you are not using a security module that requires using
+	  extended attributes for file security labels, say N.
+
+config JFS_FS
+	tristate "JFS filesystem support"
+	select NLS
+	help
+	  This is a port of IBM's Journaled Filesystem .  More information is
+	  available in the file <file:Documentation/filesystems/jfs.txt>.
+
+	  If you do not intend to use the JFS filesystem, say N.
+
+config JFS_POSIX_ACL
+	bool "JFS POSIX Access Control Lists"
+	depends on JFS_FS
+	select FS_POSIX_ACL
+	help
+	  Posix Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the Posix ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N
+
+config JFS_SECURITY
+	bool "JFS Security Labels"
+	depends on JFS_FS
+	help
+	  Security labels support alternative access control models
+	  implemented by security modules like SELinux.  This option
+	  enables an extended attribute handler for file security
+	  labels in the jfs filesystem.
+
+	  If you are not using a security module that requires using
+	  extended attributes for file security labels, say N.
+
+config JFS_DEBUG
+	bool "JFS debugging"
+	depends on JFS_FS
+	help
+	  If you are experiencing any problems with the JFS filesystem, say
+	  Y here.  This will result in additional debugging messages to be
+	  written to the system log.  Under normal circumstances, this
+	  results in very little overhead.
+
+config JFS_STATISTICS
+	bool "JFS statistics"
+	depends on JFS_FS
+	help
+	  Enabling this option will cause statistics from the JFS file system
+	  to be made available to the user in the /proc/fs/jfs/ directory.
+
+config FS_POSIX_ACL
+# Posix ACL utility routines (for now, only ext2/ext3/jfs/reiserfs/nfs4)
+#
+# NOTE: you can implement Posix ACLs without these helpers (XFS does).
+# 	Never use this symbol for ifdefs.
+#
+	bool
+	default n
+
+source "fs/xfs/Kconfig"
+source "fs/gfs2/Kconfig"
+
+config OCFS2_FS
+	tristate "OCFS2 file system support"
+	depends on NET && SYSFS
+	select CONFIGFS_FS
+	select JBD
+	select CRC32
+	help
+	  OCFS2 is a general purpose extent based shared disk cluster file
+	  system with many similarities to ext3. It supports 64 bit inode
+	  numbers, and has automatically extending metadata groups which may
+	  also make it attractive for non-clustered use.
+
+	  You'll want to install the ocfs2-tools package in order to at least
+	  get "mount.ocfs2".
+
+	  Project web page:    http://oss.oracle.com/projects/ocfs2
+	  Tools web page:      http://oss.oracle.com/projects/ocfs2-tools
+	  OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/
+
+	  For more information on OCFS2, see the file
+	  <file:Documentation/filesystems/ocfs2.txt>.
+
+config OCFS2_FS_O2CB
+	tristate "O2CB Kernelspace Clustering"
+	depends on OCFS2_FS
+	default y
+	help
+	  OCFS2 includes a simple kernelspace clustering package, the OCFS2
+	  Cluster Base.  It only requires a very small userspace component
+	  to configure it. This comes with the standard ocfs2-tools package.
+	  O2CB is limited to maintaining a cluster for OCFS2 file systems.
+	  It cannot manage any other cluster applications.
+
+	  It is always safe to say Y here, as the clustering method is
+	  run-time selectable.
+
+config OCFS2_FS_USERSPACE_CLUSTER
+	tristate "OCFS2 Userspace Clustering"
+	depends on OCFS2_FS && DLM
+	default y
+	help
+	  This option will allow OCFS2 to use userspace clustering services
+	  in conjunction with the DLM in fs/dlm.  If you are using a
+	  userspace cluster manager, say Y here.
+
+	  It is safe to say Y, as the clustering method is run-time
+	  selectable.
+
+config OCFS2_FS_STATS
+	bool "OCFS2 statistics"
+	depends on OCFS2_FS
+	default y
+	help
+	  This option allows some fs statistics to be captured. Enabling
+	  this option may increase the memory consumption.
+
+config OCFS2_DEBUG_MASKLOG
+	bool "OCFS2 logging support"
+	depends on OCFS2_FS
+	default y
+	help
+	  The ocfs2 filesystem has an extensive logging system.  The system
+	  allows selection of events to log via files in /sys/o2cb/logmask/.
+	  This option will enlarge your kernel, but it allows debugging of
+	  ocfs2 filesystem issues.
+
+config OCFS2_DEBUG_FS
+	bool "OCFS2 expensive checks"
+	depends on OCFS2_FS
+	default n
+	help
+	  This option will enable expensive consistency checks. Enable
+	  this option for debugging only as it is likely to decrease
+	  performance of the filesystem.
+
+endif # BLOCK
+
+config DNOTIFY
+	bool "Dnotify support"
+	default y
+	help
+	  Dnotify is a directory-based per-fd file change notification system
+	  that uses signals to communicate events to user-space.  There exist
+	  superior alternatives, but some applications may still rely on
+	  dnotify.
+
+	  If unsure, say Y.
+
+config INOTIFY
+	bool "Inotify file change notification support"
+	default y
+	---help---
+	  Say Y here to enable inotify support.  Inotify is a file change
+	  notification system and a replacement for dnotify.  Inotify fixes
+	  numerous shortcomings in dnotify and introduces several new features
+	  including multiple file events, one-shot support, and unmount
+	  notification.
+
+	  For more information, see <file:Documentation/filesystems/inotify.txt>
+
+	  If unsure, say Y.
+
+config INOTIFY_USER
+	bool "Inotify support for userspace"
+	depends on INOTIFY
+	default y
+	---help---
+	  Say Y here to enable inotify support for userspace, including the
+	  associated system calls.  Inotify allows monitoring of both files and
+	  directories via a single open fd.  Events are read from the file
+	  descriptor, which is also select()- and poll()-able.
+
+	  For more information, see <file:Documentation/filesystems/inotify.txt>
+
+	  If unsure, say Y.
+
+config QUOTA
+	bool "Quota support"
+	help
+	  If you say Y here, you will be able to set per user limits for disk
+	  usage (also called disk quotas). Currently, it works for the
+	  ext2, ext3, and reiserfs file system. ext3 also supports journalled
+	  quotas for which you don't need to run quotacheck(8) after an unclean
+	  shutdown.
+	  For further details, read the Quota mini-HOWTO, available from
+	  <http://www.tldp.org/docs.html#howto>, or the documentation provided
+	  with the quota tools. Probably the quota support is only useful for
+	  multi user systems. If unsure, say N.
+
+config QUOTA_NETLINK_INTERFACE
+	bool "Report quota messages through netlink interface"
+	depends on QUOTA && NET
+	help
+	  If you say Y here, quota warnings (about exceeding softlimit, reaching
+	  hardlimit, etc.) will be reported through netlink interface. If unsure,
+	  say Y.
+
+config PRINT_QUOTA_WARNING
+	bool "Print quota warnings to console (OBSOLETE)"
+	depends on QUOTA
+	default y
+	help
+	  If you say Y here, quota warnings (about exceeding softlimit, reaching
+	  hardlimit, etc.) will be printed to the process' controlling terminal.
+	  Note that this behavior is currently deprecated and may go away in
+	  future. Please use notification via netlink socket instead.
+
+config QFMT_V1
+	tristate "Old quota format support"
+	depends on QUOTA
+	help
+	  This quota format was (is) used by kernels earlier than 2.4.22. If
+	  you have quota working and you don't want to convert to new quota
+	  format say Y here.
+
+config QFMT_V2
+	tristate "Quota format v2 support"
+	depends on QUOTA
+	help
+	  This quota format allows using quotas with 32-bit UIDs/GIDs. If you
+	  need this functionality say Y here.
+
+config QUOTACTL
+	bool
+	depends on XFS_QUOTA || QUOTA
+	default y
+
+config AUTOFS_FS
+	tristate "Kernel automounter support"
+	help
+	  The automounter is a tool to automatically mount remote file systems
+	  on demand. This implementation is partially kernel-based to reduce
+	  overhead in the already-mounted case; this is unlike the BSD
+	  automounter (amd), which is a pure user space daemon.
+
+	  To use the automounter you need the user-space tools from the autofs
+	  package; you can find the location in <file:Documentation/Changes>.
+	  You also want to answer Y to "NFS file system support", below.
+
+	  If you want to use the newer version of the automounter with more
+	  features, say N here and say Y to "Kernel automounter v4 support",
+	  below.
+
+	  To compile this support as a module, choose M here: the module will be
+	  called autofs.
+
+	  If you are not a part of a fairly large, distributed network, you
+	  probably do not need an automounter, and can say N here.
+
+config AUTOFS4_FS
+	tristate "Kernel automounter version 4 support (also supports v3)"
+	help
+	  The automounter is a tool to automatically mount remote file systems
+	  on demand. This implementation is partially kernel-based to reduce
+	  overhead in the already-mounted case; this is unlike the BSD
+	  automounter (amd), which is a pure user space daemon.
+
+	  To use the automounter you need the user-space tools from
+	  <ftp://ftp.kernel.org/pub/linux/daemons/autofs/v4/>; you also
+	  want to answer Y to "NFS file system support", below.
+
+	  To compile this support as a module, choose M here: the module will be
+	  called autofs4.  You will need to add "alias autofs autofs4" to your
+	  modules configuration file.
+
+	  If you are not a part of a fairly large, distributed network or
+	  don't have a laptop which needs to dynamically reconfigure to the
+	  local network, you probably do not need an automounter, and can say
+	  N here.
+
+config FUSE_FS
+	tristate "Filesystem in Userspace support"
+	help
+	  With FUSE it is possible to implement a fully functional filesystem
+	  in a userspace program.
+
+	  There's also companion library: libfuse.  This library along with
+	  utilities is available from the FUSE homepage:
+	  <http://fuse.sourceforge.net/>
+
+	  See <file:Documentation/filesystems/fuse.txt> for more information.
+	  See <file:Documentation/Changes> for needed library/utility version.
+
+	  If you want to develop a userspace FS, or if you want to use
+	  a filesystem based on FUSE, answer Y or M.
+
+config GENERIC_ACL
+	bool
+	select FS_POSIX_ACL
+
+if BLOCK
+menu "CD-ROM/DVD Filesystems"
+
+config ISO9660_FS
+	tristate "ISO 9660 CDROM file system support"
+	help
+	  This is the standard file system used on CD-ROMs.  It was previously
+	  known as "High Sierra File System" and is called "hsfs" on other
+	  Unix systems.  The so-called Rock-Ridge extensions which allow for
+	  long Unix filenames and symbolic links are also supported by this
+	  driver.  If you have a CD-ROM drive and want to do more with it than
+	  just listen to audio CDs and watch its LEDs, say Y (and read
+	  <file:Documentation/filesystems/isofs.txt> and the CD-ROM-HOWTO,
+	  available from <http://www.tldp.org/docs.html#howto>), thereby
+	  enlarging your kernel by about 27 KB; otherwise say N.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called isofs.
+
+config JOLIET
+	bool "Microsoft Joliet CDROM extensions"
+	depends on ISO9660_FS
+	select NLS
+	help
+	  Joliet is a Microsoft extension for the ISO 9660 CD-ROM file system
+	  which allows for long filenames in unicode format (unicode is the
+	  new 16 bit character code, successor to ASCII, which encodes the
+	  characters of almost all languages of the world; see
+	  <http://www.unicode.org/> for more information).  Say Y here if you
+	  want to be able to read Joliet CD-ROMs under Linux.
+
+config ZISOFS
+	bool "Transparent decompression extension"
+	depends on ISO9660_FS
+	select ZLIB_INFLATE
+	help
+	  This is a Linux-specific extension to RockRidge which lets you store
+	  data in compressed form on a CD-ROM and have it transparently
+	  decompressed when the CD-ROM is accessed.  See
+	  <http://www.kernel.org/pub/linux/utils/fs/zisofs/> for the tools
+	  necessary to create such a filesystem.  Say Y here if you want to be
+	  able to read such compressed CD-ROMs.
+
+config UDF_FS
+	tristate "UDF file system support"
+	select CRC_ITU_T
+	help
+	  This is the new file system used on some CD-ROMs and DVDs. Say Y if
+	  you intend to mount DVD discs or CDRW's written in packet mode, or
+	  if written to by other UDF utilities, such as DirectCD.
+	  Please read <file:Documentation/filesystems/udf.txt>.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called udf.
+
+	  If unsure, say N.
+
+config UDF_NLS
+	bool
+	default y
+	depends on (UDF_FS=m && NLS) || (UDF_FS=y && NLS=y)
+
+endmenu
+endif # BLOCK
+
+if BLOCK
+menu "DOS/FAT/NT Filesystems"
+
+config FAT_FS
+	tristate
+	select NLS
+	help
+	  If you want to use one of the FAT-based file systems (the MS-DOS and
+	  VFAT (Windows 95) file systems), then you must say Y or M here
+	  to include FAT support. You will then be able to mount partitions or
+	  diskettes with FAT-based file systems and transparently access the
+	  files on them, i.e. MSDOS files will look and behave just like all
+	  other Unix files.
+
+	  This FAT support is not a file system in itself, it only provides
+	  the foundation for the other file systems. You will have to say Y or
+	  M to at least one of "MSDOS fs support" or "VFAT fs support" in
+	  order to make use of it.
+
+	  Another way to read and write MSDOS floppies and hard drive
+	  partitions from within Linux (but not transparently) is with the
+	  mtools ("man mtools") program suite. You don't need to say Y here in
+	  order to do that.
+
+	  If you need to move large files on floppies between a DOS and a
+	  Linux box, say Y here, mount the floppy under Linux with an MSDOS
+	  file system and use GNU tar's M option. GNU tar is a program
+	  available for Unix and DOS ("man tar" or "info tar").
+
+	  The FAT support will enlarge your kernel by about 37 KB. If unsure,
+	  say Y.
+
+	  To compile this as a module, choose M here: the module will be called
+	  fat.  Note that if you compile the FAT support as a module, you
+	  cannot compile any of the FAT-based file systems into the kernel
+	  -- they will have to be modules as well.
+
+config MSDOS_FS
+	tristate "MSDOS fs support"
+	select FAT_FS
+	help
+	  This allows you to mount MSDOS partitions of your hard drive (unless
+	  they are compressed; to access compressed MSDOS partitions under
+	  Linux, you can either use the DOS emulator DOSEMU, described in the
+	  DOSEMU-HOWTO, available from
+	  <http://www.tldp.org/docs.html#howto>, or try dmsdosfs in
+	  <ftp://ibiblio.org/pub/Linux/system/filesystems/dosfs/>. If you
+	  intend to use dosemu with a non-compressed MSDOS partition, say Y
+	  here) and MSDOS floppies. This means that file access becomes
+	  transparent, i.e. the MSDOS files look and behave just like all
+	  other Unix files.
+
+	  If you have Windows 95 or Windows NT installed on your MSDOS
+	  partitions, you should use the VFAT file system (say Y to "VFAT fs
+	  support" below), or you will not be able to see the long filenames
+	  generated by Windows 95 / Windows NT.
+
+	  This option will enlarge your kernel by about 7 KB. If unsure,
+	  answer Y. This will only work if you said Y to "DOS FAT fs support"
+	  as well. To compile this as a module, choose M here: the module will
+	  be called msdos.
+
+config VFAT_FS
+	tristate "VFAT (Windows-95) fs support"
+	select FAT_FS
+	help
+	  This option provides support for normal Windows file systems with
+	  long filenames.  That includes non-compressed FAT-based file systems
+	  used by Windows 95, Windows 98, Windows NT 4.0, and the Unix
+	  programs from the mtools package.
+
+	  The VFAT support enlarges your kernel by about 10 KB and it only
+	  works if you said Y to the "DOS FAT fs support" above.  Please read
+	  the file <file:Documentation/filesystems/vfat.txt> for details.  If
+	  unsure, say Y.
+
+	  To compile this as a module, choose M here: the module will be called
+	  vfat.
+
+config FAT_DEFAULT_CODEPAGE
+	int "Default codepage for FAT"
+	depends on MSDOS_FS || VFAT_FS
+	default 437
+	help
+	  This option should be set to the codepage of your FAT filesystems.
+	  It can be overridden with the "codepage" mount option.
+	  See <file:Documentation/filesystems/vfat.txt> for more information.
+
+config FAT_DEFAULT_IOCHARSET
+	string "Default iocharset for FAT"
+	depends on VFAT_FS
+	default "iso8859-1"
+	help
+	  Set this to the default input/output character set you'd
+	  like FAT to use. It should probably match the character set
+	  that most of your FAT filesystems use, and can be overridden
+	  with the "iocharset" mount option for FAT filesystems.
+	  Note that "utf8" is not recommended for FAT filesystems.
+	  If unsure, you shouldn't set "utf8" here.
+	  See <file:Documentation/filesystems/vfat.txt> for more information.
+
+config NTFS_FS
+	tristate "NTFS file system support"
+	select NLS
+	help
+	  NTFS is the file system of Microsoft Windows NT, 2000, XP and 2003.
+
+	  Saying Y or M here enables read support.  There is partial, but
+	  safe, write support available.  For write support you must also
+	  say Y to "NTFS write support" below.
+
+	  There are also a number of user-space tools available, called
+	  ntfsprogs.  These include ntfsundelete and ntfsresize, that work
+	  without NTFS support enabled in the kernel.
+
+	  This is a rewrite from scratch of Linux NTFS support and replaced
+	  the old NTFS code starting with Linux 2.5.11.  A backport to
+	  the Linux 2.4 kernel series is separately available as a patch
+	  from the project web site.
+
+	  For more information see <file:Documentation/filesystems/ntfs.txt>
+	  and <http://www.linux-ntfs.org/>.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called ntfs.
+
+	  If you are not using Windows NT, 2000, XP or 2003 in addition to
+	  Linux on your computer it is safe to say N.
+
+config NTFS_DEBUG
+	bool "NTFS debugging support"
+	depends on NTFS_FS
+	help
+	  If you are experiencing any problems with the NTFS file system, say
+	  Y here.  This will result in additional consistency checks to be
+	  performed by the driver as well as additional debugging messages to
+	  be written to the system log.  Note that debugging messages are
+	  disabled by default.  To enable them, supply the option debug_msgs=1
+	  at the kernel command line when booting the kernel or as an option
+	  to insmod when loading the ntfs module.  Once the driver is active,
+	  you can enable debugging messages by doing (as root):
+	  echo 1 > /proc/sys/fs/ntfs-debug
+	  Replacing the "1" with "0" would disable debug messages.
+
+	  If you leave debugging messages disabled, this results in little
+	  overhead, but enabling debug messages results in very significant
+	  slowdown of the system.
+
+	  When reporting bugs, please try to have available a full dump of
+	  debugging messages while the misbehaviour was occurring.
+
+config NTFS_RW
+	bool "NTFS write support"
+	depends on NTFS_FS
+	help
+	  This enables the partial, but safe, write support in the NTFS driver.
+
+	  The only supported operation is overwriting existing files, without
+	  changing the file length.  No file or directory creation, deletion or
+	  renaming is possible.  Note only non-resident files can be written to
+	  so you may find that some very small files (<500 bytes or so) cannot
+	  be written to.
+
+	  While we cannot guarantee that it will not damage any data, we have
+	  so far not received a single report where the driver would have
+	  damaged someones data so we assume it is perfectly safe to use.
+
+	  Note:  While write support is safe in this version (a rewrite from
+	  scratch of the NTFS support), it should be noted that the old NTFS
+	  write support, included in Linux 2.5.10 and before (since 1997),
+	  is not safe.
+
+	  This is currently useful with TopologiLinux.  TopologiLinux is run
+	  on top of any DOS/Microsoft Windows system without partitioning your
+	  hard disk.  Unlike other Linux distributions TopologiLinux does not
+	  need its own partition.  For more information see
+	  <http://topologi-linux.sourceforge.net/>
+
+	  It is perfectly safe to say N here.
+
+endmenu
+endif # BLOCK
+
+menu "Pseudo filesystems"
+
+source "fs/proc/Kconfig"
+
+config SYSFS
+	bool "sysfs file system support" if EMBEDDED
+	default y
+	help
+	The sysfs filesystem is a virtual filesystem that the kernel uses to
+	export internal kernel objects, their attributes, and their
+	relationships to one another.
+
+	Users can use sysfs to ascertain useful information about the running
+	kernel, such as the devices the kernel has discovered on each bus and
+	which driver each is bound to. sysfs can also be used to tune devices
+	and other kernel subsystems.
+
+	Some system agents rely on the information in sysfs to operate.
+	/sbin/hotplug uses device and object attributes in sysfs to assist in
+	delegating policy decisions, like persistently naming devices.
+
+	sysfs is currently used by the block subsystem to mount the root
+	partition.  If sysfs is disabled you must specify the boot device on
+	the kernel boot command line via its major and minor numbers.  For
+	example, "root=03:01" for /dev/hda1.
+
+	Designers of embedded systems may wish to say N here to conserve space.
+
+config TMPFS
+	bool "Virtual memory file system support (former shm fs)"
+	help
+	  Tmpfs is a file system which keeps all files in virtual memory.
+
+	  Everything in tmpfs is temporary in the sense that no files will be
+	  created on your hard drive. The files live in memory and swap
+	  space. If you unmount a tmpfs instance, everything stored therein is
+	  lost.
+
+	  See <file:Documentation/filesystems/tmpfs.txt> for details.
+
+config TMPFS_POSIX_ACL
+	bool "Tmpfs POSIX Access Control Lists"
+	depends on TMPFS
+	select GENERIC_ACL
+	help
+	  POSIX Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the POSIX ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N.
+
+config HUGETLBFS
+	bool "HugeTLB file system support"
+	depends on X86 || IA64 || PPC64 || SPARC64 || (SUPERH && MMU) || \
+		   (S390 && 64BIT) || BROKEN
+	help
+	  hugetlbfs is a filesystem backing for HugeTLB pages, based on
+	  ramfs. For architectures that support it, say Y here and read
+	  <file:Documentation/vm/hugetlbpage.txt> for details.
+
+	  If unsure, say N.
+
+config HUGETLB_PAGE
+	def_bool HUGETLBFS
+
+config CONFIGFS_FS
+	tristate "Userspace-driven configuration filesystem"
+	depends on SYSFS
+	help
+	  configfs is a ram-based filesystem that provides the converse
+	  of sysfs's functionality. Where sysfs is a filesystem-based
+	  view of kernel objects, configfs is a filesystem-based manager
+	  of kernel objects, or config_items.
+
+	  Both sysfs and configfs can and should exist together on the
+	  same system. One is not a replacement for the other.
+
+endmenu
+
+menu "Miscellaneous filesystems"
+
+config ADFS_FS
+	tristate "ADFS file system support (EXPERIMENTAL)"
+	depends on BLOCK && EXPERIMENTAL
+	help
+	  The Acorn Disc Filing System is the standard file system of the
+	  RiscOS operating system which runs on Acorn's ARM-based Risc PC
+	  systems and the Acorn Archimedes range of machines. If you say Y
+	  here, Linux will be able to read from ADFS partitions on hard drives
+	  and from ADFS-formatted floppy discs. If you also want to be able to
+	  write to those devices, say Y to "ADFS write support" below.
+
+	  The ADFS partition should be the first partition (i.e.,
+	  /dev/[hs]d?1) on each of your drives. Please read the file
+	  <file:Documentation/filesystems/adfs.txt> for further details.
+
+	  To compile this code as a module, choose M here: the module will be
+	  called adfs.
+
+	  If unsure, say N.
+
+config ADFS_FS_RW
+	bool "ADFS write support (DANGEROUS)"
+	depends on ADFS_FS
+	help
+	  If you say Y here, you will be able to write to ADFS partitions on
+	  hard drives and ADFS-formatted floppy disks. This is experimental
+	  codes, so if you're unsure, say N.
+
+config AFFS_FS
+	tristate "Amiga FFS file system support (EXPERIMENTAL)"
+	depends on BLOCK && EXPERIMENTAL
+	help
+	  The Fast File System (FFS) is the common file system used on hard
+	  disks by Amiga(tm) systems since AmigaOS Version 1.3 (34.20).  Say Y
+	  if you want to be able to read and write files from and to an Amiga
+	  FFS partition on your hard drive.  Amiga floppies however cannot be
+	  read with this driver due to an incompatibility of the floppy
+	  controller used in an Amiga and the standard floppy controller in
+	  PCs and workstations. Read <file:Documentation/filesystems/affs.txt>
+	  and <file:fs/affs/Changes>.
+
+	  With this driver you can also mount disk files used by Bernd
+	  Schmidt's Un*X Amiga Emulator
+	  (<http://www.freiburg.linux.de/~uae/>).
+	  If you want to do this, you will also need to say Y or M to "Loop
+	  device support", above.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called affs.  If unsure, say N.
+
+config ECRYPT_FS
+	tristate "eCrypt filesystem layer support (EXPERIMENTAL)"
+	depends on EXPERIMENTAL && KEYS && CRYPTO && NET
+	help
+	  Encrypted filesystem that operates on the VFS layer.  See
+	  <file:Documentation/filesystems/ecryptfs.txt> to learn more about
+	  eCryptfs.  Userspace components are required and can be
+	  obtained from <http://ecryptfs.sf.net>.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called ecryptfs.
+
+config HFS_FS
+	tristate "Apple Macintosh file system support (EXPERIMENTAL)"
+	depends on BLOCK && EXPERIMENTAL
+	select NLS
+	help
+	  If you say Y here, you will be able to mount Macintosh-formatted
+	  floppy disks and hard drive partitions with full read-write access.
+	  Please read <file:Documentation/filesystems/hfs.txt> to learn about
+	  the available mount options.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called hfs.
+
+config HFSPLUS_FS
+	tristate "Apple Extended HFS file system support"
+	depends on BLOCK
+	select NLS
+	select NLS_UTF8
+	help
+	  If you say Y here, you will be able to mount extended format
+	  Macintosh-formatted hard drive partitions with full read-write access.
+
+	  This file system is often called HFS+ and was introduced with
+	  MacOS 8. It includes all Mac specific filesystem data such as
+	  data forks and creator codes, but it also has several UNIX
+	  style features such as file ownership and permissions.
+
+config BEFS_FS
+	tristate "BeOS file system (BeFS) support (read only) (EXPERIMENTAL)"
+	depends on BLOCK && EXPERIMENTAL
+	select NLS
+	help
+	  The BeOS File System (BeFS) is the native file system of Be, Inc's
+	  BeOS. Notable features include support for arbitrary attributes
+	  on files and directories, and database-like indices on selected
+	  attributes. (Also note that this driver doesn't make those features
+	  available at this time). It is a 64 bit filesystem, so it supports
+	  extremely large volumes and files.
+
+	  If you use this filesystem, you should also say Y to at least one
+	  of the NLS (native language support) options below.
+
+	  If you don't know what this is about, say N.
+
+	  To compile this as a module, choose M here: the module will be
+	  called befs.
+
+config BEFS_DEBUG
+	bool "Debug BeFS"
+	depends on BEFS_FS
+	help
+	  If you say Y here, you can use the 'debug' mount option to enable
+	  debugging output from the driver.
+
+config BFS_FS
+	tristate "BFS file system support (EXPERIMENTAL)"
+	depends on BLOCK && EXPERIMENTAL
+	help
+	  Boot File System (BFS) is a file system used under SCO UnixWare to
+	  allow the bootloader access to the kernel image and other important
+	  files during the boot process.  It is usually mounted under /stand
+	  and corresponds to the slice marked as "STAND" in the UnixWare
+	  partition.  You should say Y if you want to read or write the files
+	  on your /stand slice from within Linux.  You then also need to say Y
+	  to "UnixWare slices support", below.  More information about the BFS
+	  file system is contained in the file
+	  <file:Documentation/filesystems/bfs.txt>.
+
+	  If you don't know what this is about, say N.
+
+	  To compile this as a module, choose M here: the module will be called
+	  bfs.  Note that the file system of your root partition (the one
+	  containing the directory /) cannot be compiled as a module.
+
+
+
+config EFS_FS
+	tristate "EFS file system support (read only) (EXPERIMENTAL)"
+	depends on BLOCK && EXPERIMENTAL
+	help
+	  EFS is an older file system used for non-ISO9660 CD-ROMs and hard
+	  disk partitions by SGI's IRIX operating system (IRIX 6.0 and newer
+	  uses the XFS file system for hard disk partitions however).
+
+	  This implementation only offers read-only access. If you don't know
+	  what all this is about, it's safe to say N. For more information
+	  about EFS see its home page at <http://aeschi.ch.eu.org/efs/>.
+
+	  To compile the EFS file system support as a module, choose M here: the
+	  module will be called efs.
+
+config JFFS2_FS
+	tristate "Journalling Flash File System v2 (JFFS2) support"
+	select CRC32
+	depends on MTD
+	help
+	  JFFS2 is the second generation of the Journalling Flash File System
+	  for use on diskless embedded devices. It provides improved wear
+	  levelling, compression and support for hard links. You cannot use
+	  this on normal block devices, only on 'MTD' devices.
+
+	  Further information on the design and implementation of JFFS2 is
+	  available at <http://sources.redhat.com/jffs2/>.
+
+config JFFS2_FS_DEBUG
+	int "JFFS2 debugging verbosity (0 = quiet, 2 = noisy)"
+	depends on JFFS2_FS
+	default "0"
+	help
+	  This controls the amount of debugging messages produced by the JFFS2
+	  code. Set it to zero for use in production systems. For evaluation,
+	  testing and debugging, it's advisable to set it to one. This will
+	  enable a few assertions and will print debugging messages at the
+	  KERN_DEBUG loglevel, where they won't normally be visible. Level 2
+	  is unlikely to be useful - it enables extra debugging in certain
+	  areas which at one point needed debugging, but when the bugs were
+	  located and fixed, the detailed messages were relegated to level 2.
+
+	  If reporting bugs, please try to have available a full dump of the
+	  messages at debug level 1 while the misbehaviour was occurring.
+
+config JFFS2_FS_WRITEBUFFER
+	bool "JFFS2 write-buffering support"
+	depends on JFFS2_FS
+	default y
+	help
+	  This enables the write-buffering support in JFFS2.
+
+	  This functionality is required to support JFFS2 on the following
+	  types of flash devices:
+	    - NAND flash
+	    - NOR flash with transparent ECC
+	    - DataFlash
+
+config JFFS2_FS_WBUF_VERIFY
+	bool "Verify JFFS2 write-buffer reads"
+	depends on JFFS2_FS_WRITEBUFFER
+	default n
+	help
+	  This causes JFFS2 to read back every page written through the
+	  write-buffer, and check for errors.
+
+config JFFS2_SUMMARY
+	bool "JFFS2 summary support (EXPERIMENTAL)"
+	depends on JFFS2_FS && EXPERIMENTAL
+	default n
+	help
+	  This feature makes it possible to use summary information
+	  for faster filesystem mount.
+
+	  The summary information can be inserted into a filesystem image
+	  by the utility 'sumtool'.
+
+	  If unsure, say 'N'.
+
+config JFFS2_FS_XATTR
+	bool "JFFS2 XATTR support (EXPERIMENTAL)"
+	depends on JFFS2_FS && EXPERIMENTAL
+	default n
+	help
+	  Extended attributes are name:value pairs associated with inodes by
+	  the kernel or by users (see the attr(5) manual page, or visit
+	  <http://acl.bestbits.at/> for details).
+
+	  If unsure, say N.
+
+config JFFS2_FS_POSIX_ACL
+	bool "JFFS2 POSIX Access Control Lists"
+	depends on JFFS2_FS_XATTR
+	default y
+	select FS_POSIX_ACL
+	help
+	  Posix Access Control Lists (ACLs) support permissions for users and
+	  groups beyond the owner/group/world scheme.
+
+	  To learn more about Access Control Lists, visit the Posix ACLs for
+	  Linux website <http://acl.bestbits.at/>.
+
+	  If you don't know what Access Control Lists are, say N
+
+config JFFS2_FS_SECURITY
+	bool "JFFS2 Security Labels"
+	depends on JFFS2_FS_XATTR
+	default y
+	help
+	  Security labels support alternative access control models
+	  implemented by security modules like SELinux.  This option
+	  enables an extended attribute handler for file security
+	  labels in the jffs2 filesystem.
+
+	  If you are not using a security module that requires using
+	  extended attributes for file security labels, say N.
+
+config JFFS2_COMPRESSION_OPTIONS
+	bool "Advanced compression options for JFFS2"
+	depends on JFFS2_FS
+	default n
+	help
+	  Enabling this option allows you to explicitly choose which
+	  compression modules, if any, are enabled in JFFS2. Removing
+	  compressors can mean you cannot read existing file systems,
+	  and enabling experimental compressors can mean that you
+	  write a file system which cannot be read by a standard kernel.
+
+	  If unsure, you should _definitely_ say 'N'.
+
+config JFFS2_ZLIB
+	bool "JFFS2 ZLIB compression support" if JFFS2_COMPRESSION_OPTIONS
+	select ZLIB_INFLATE
+	select ZLIB_DEFLATE
+	depends on JFFS2_FS
+	default y
+	help
+	  Zlib is designed to be a free, general-purpose, legally unencumbered,
+	  lossless data-compression library for use on virtually any computer
+	  hardware and operating system. See <http://www.gzip.org/zlib/> for
+	  further information.
+
+	  Say 'Y' if unsure.
+
+config JFFS2_LZO
+	bool "JFFS2 LZO compression support" if JFFS2_COMPRESSION_OPTIONS
+	select LZO_COMPRESS
+	select LZO_DECOMPRESS
+	depends on JFFS2_FS
+	default n
+	help
+	  minilzo-based compression. Generally works better than Zlib.
+
+	  This feature was added in July, 2007. Say 'N' if you need
+	  compatibility with older bootloaders or kernels.
+
+config JFFS2_RTIME
+	bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS
+	depends on JFFS2_FS
+	default y
+	help
+	  Rtime does manage to recompress already-compressed data. Say 'Y' if unsure.
+
+config JFFS2_RUBIN
+	bool "JFFS2 RUBIN compression support" if JFFS2_COMPRESSION_OPTIONS
+	depends on JFFS2_FS
+	default n
+	help
+	  RUBINMIPS and DYNRUBIN compressors. Say 'N' if unsure.
+
+choice
+	prompt "JFFS2 default compression mode" if JFFS2_COMPRESSION_OPTIONS
+	default JFFS2_CMODE_PRIORITY
+	depends on JFFS2_FS
+	help
+	  You can set here the default compression mode of JFFS2 from
+	  the available compression modes. Don't touch if unsure.
+
+config JFFS2_CMODE_NONE
+	bool "no compression"
+	help
+	  Uses no compression.
+
+config JFFS2_CMODE_PRIORITY
+	bool "priority"
+	help
+	  Tries the compressors in a predefined order and chooses the first
+	  successful one.
+
+config JFFS2_CMODE_SIZE
+	bool "size (EXPERIMENTAL)"
+	help
+	  Tries all compressors and chooses the one which has the smallest
+	  result.
+
+config JFFS2_CMODE_FAVOURLZO
+	bool "Favour LZO"
+	help
+	  Tries all compressors and chooses the one which has the smallest
+	  result but gives some preference to LZO (which has faster
+	  decompression) at the expense of size.
+
+endchoice
+
+# UBIFS File system configuration
+source "fs/ubifs/Kconfig"
+
+config CRAMFS
+	tristate "Compressed ROM file system support (cramfs)"
+	depends on BLOCK
+	select ZLIB_INFLATE
+	help
+	  Saying Y here includes support for CramFs (Compressed ROM File
+	  System).  CramFs is designed to be a simple, small, and compressed
+	  file system for ROM based embedded systems.  CramFs is read-only,
+	  limited to 256MB file systems (with 16MB files), and doesn't support
+	  16/32 bits uid/gid, hard links and timestamps.
+
+	  See <file:Documentation/filesystems/cramfs.txt> and
+	  <file:fs/cramfs/README> for further information.
+
+	  To compile this as a module, choose M here: the module will be called
+	  cramfs.  Note that the root file system (the one containing the
+	  directory /) cannot be compiled as a module.
+
+	  If unsure, say N.
+
+config VXFS_FS
+	tristate "FreeVxFS file system support (VERITAS VxFS(TM) compatible)"
+	depends on BLOCK
+	help
+	  FreeVxFS is a file system driver that support the VERITAS VxFS(TM)
+	  file system format.  VERITAS VxFS(TM) is the standard file system
+	  of SCO UnixWare (and possibly others) and optionally available
+	  for Sunsoft Solaris, HP-UX and many other operating systems.
+	  Currently only readonly access is supported.
+
+	  NOTE: the file system type as used by mount(1), mount(2) and
+	  fstab(5) is 'vxfs' as it describes the file system format, not
+	  the actual driver.
+
+	  To compile this as a module, choose M here: the module will be
+	  called freevxfs.  If unsure, say N.
+
+config MINIX_FS
+	tristate "Minix file system support"
+	depends on BLOCK
+	help
+	  Minix is a simple operating system used in many classes about OS's.
+	  The minix file system (method to organize files on a hard disk
+	  partition or a floppy disk) was the original file system for Linux,
+	  but has been superseded by the second extended file system ext2fs.
+	  You don't want to use the minix file system on your hard disk
+	  because of certain built-in restrictions, but it is sometimes found
+	  on older Linux floppy disks.  This option will enlarge your kernel
+	  by about 28 KB. If unsure, say N.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called minix.  Note that the file system of your root
+	  partition (the one containing the directory /) cannot be compiled as
+	  a module.
+
+config OMFS_FS
+	tristate "SonicBlue Optimized MPEG File System support"
+	depends on BLOCK
+	select CRC_ITU_T
+	help
+	  This is the proprietary file system used by the Rio Karma music
+	  player and ReplayTV DVR.  Despite the name, this filesystem is not
+	  more efficient than a standard FS for MPEG files, in fact likely
+	  the opposite is true.  Say Y if you have either of these devices
+	  and wish to mount its disk.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called omfs.  If unsure, say N.
+
+config HPFS_FS
+	tristate "OS/2 HPFS file system support"
+	depends on BLOCK
+	help
+	  OS/2 is IBM's operating system for PC's, the same as Warp, and HPFS
+	  is the file system used for organizing files on OS/2 hard disk
+	  partitions. Say Y if you want to be able to read files from and
+	  write files to an OS/2 HPFS partition on your hard drive. OS/2
+	  floppies however are in regular MSDOS format, so you don't need this
+	  option in order to be able to read them. Read
+	  <file:Documentation/filesystems/hpfs.txt>.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called hpfs.  If unsure, say N.
+
+
+config QNX4FS_FS
+	tristate "QNX4 file system support (read only)"
+	depends on BLOCK
+	help
+	  This is the file system used by the real-time operating systems
+	  QNX 4 and QNX 6 (the latter is also called QNX RTP).
+	  Further information is available at <http://www.qnx.com/>.
+	  Say Y if you intend to mount QNX hard disks or floppies.
+	  Unless you say Y to "QNX4FS read-write support" below, you will
+	  only be able to read these file systems.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called qnx4.
+
+	  If you don't know whether you need it, then you don't need it:
+	  answer N.
+
+config QNX4FS_RW
+	bool "QNX4FS write support (DANGEROUS)"
+	depends on QNX4FS_FS && EXPERIMENTAL && BROKEN
+	help
+	  Say Y if you want to test write support for QNX4 file systems.
+
+	  It's currently broken, so for now:
+	  answer N.
+
+config ROMFS_FS
+	tristate "ROM file system support"
+	depends on BLOCK
+	---help---
+	  This is a very small read-only file system mainly intended for
+	  initial ram disks of installation disks, but it could be used for
+	  other read-only media as well.  Read
+	  <file:Documentation/filesystems/romfs.txt> for details.
+
+	  To compile this file system support as a module, choose M here: the
+	  module will be called romfs.  Note that the file system of your
+	  root partition (the one containing the directory /) cannot be a
+	  module.
+
+	  If you don't know whether you need it, then you don't need it:
+	  answer N.
+
+
+config SYSV_FS
+	tristate "System V/Xenix/V7/Coherent file system support"
+	depends on BLOCK
+	help
+	  SCO, Xenix and Coherent are commercial Unix systems for Intel
+	  machines, and Version 7 was used on the DEC PDP-11. Saying Y
+	  here would allow you to read from their floppies and hard disk
+	  partitions.
+
+	  If you have floppies or hard disk partitions like that, it is likely
+	  that they contain binaries from those other Unix systems; in order
+	  to run these binaries, you will want to install linux-abi which is
+	  a set of kernel modules that lets you run SCO, Xenix, Wyse,
+	  UnixWare, Dell Unix and System V programs under Linux.  It is
+	  available via FTP (user: ftp) from
+	  <ftp://ftp.openlinux.org/pub/people/hch/linux-abi/>).
+	  NOTE: that will work only for binaries from Intel-based systems;
+	  PDP ones will have to wait until somebody ports Linux to -11 ;-)
+
+	  If you only intend to mount files from some other Unix over the
+	  network using NFS, you don't need the System V file system support
+	  (but you need NFS file system support obviously).
+
+	  Note that this option is generally not needed for floppies, since a
+	  good portable way to transport files and directories between unixes
+	  (and even other operating systems) is given by the tar program ("man
+	  tar" or preferably "info tar").  Note also that this option has
+	  nothing whatsoever to do with the option "System V IPC". Read about
+	  the System V file system in
+	  <file:Documentation/filesystems/sysv-fs.txt>.
+	  Saying Y here will enlarge your kernel by about 27 KB.
+
+	  To compile this as a module, choose M here: the module will be called
+	  sysv.
+
+	  If you haven't heard about all of this before, it's safe to say N.
+
+
+config UFS_FS
+	tristate "UFS file system support (read only)"
+	depends on BLOCK
+	help
+	  BSD and derivate versions of Unix (such as SunOS, FreeBSD, NetBSD,
+	  OpenBSD and NeXTstep) use a file system called UFS. Some System V
+	  Unixes can create and mount hard disk partitions and diskettes using
+	  this file system as well. Saying Y here will allow you to read from
+	  these partitions; if you also want to write to them, say Y to the
+	  experimental "UFS file system write support", below. Please read the
+	  file <file:Documentation/filesystems/ufs.txt> for more information.
+
+          The recently released UFS2 variant (used in FreeBSD 5.x) is
+          READ-ONLY supported.
+
+	  Note that this option is generally not needed for floppies, since a
+	  good portable way to transport files and directories between unixes
+	  (and even other operating systems) is given by the tar program ("man
+	  tar" or preferably "info tar").
+
+	  When accessing NeXTstep files, you may need to convert them from the
+	  NeXT character set to the Latin1 character set; use the program
+	  recode ("info recode") for this purpose.
+
+	  To compile the UFS file system support as a module, choose M here: the
+	  module will be called ufs.
+
+	  If you haven't heard about all of this before, it's safe to say N.
+
+config UFS_FS_WRITE
+	bool "UFS file system write support (DANGEROUS)"
+	depends on UFS_FS && EXPERIMENTAL
+	help
+	  Say Y here if you want to try writing to UFS partitions. This is
+	  experimental, so you should back up your UFS partitions beforehand.
+
+config UFS_DEBUG
+	bool "UFS debugging"
+	depends on UFS_FS
+	help
+	  If you are experiencing any problems with the UFS filesystem, say
+	  Y here.  This will result in _many_ additional debugging messages to be
+	  written to the system log.
+
+endmenu
+
+menuconfig NETWORK_FILESYSTEMS
+	bool "Network File Systems"
+	default y
+	depends on NET
+	---help---
+	  Say Y here to get to see options for network filesystems and
+	  filesystem-related networking code, such as NFS daemon and
+	  RPCSEC security modules.
+
+	  This option alone does not add any kernel code.
+
+	  If you say N, all options in this submenu will be skipped and
+	  disabled; if unsure, say Y here.
+
+if NETWORK_FILESYSTEMS
+
+config NFS_FS
+	tristate "NFS client support"
+	depends on INET
+	select LOCKD
+	select SUNRPC
+	select NFS_ACL_SUPPORT if NFS_V3_ACL
+	help
+	  Choose Y here if you want to access files residing on other
+	  computers using Sun's Network File System protocol.  To compile
+	  this file system support as a module, choose M here: the module
+	  will be called nfs.
+
+	  To mount file systems exported by NFS servers, you also need to
+	  install the user space mount.nfs command which can be found in
+	  the Linux nfs-utils package, available from http://linux-nfs.org/.
+	  Information about using the mount command is available in the
+	  mount(8) man page.  More detail about the Linux NFS client
+	  implementation is available via the nfs(5) man page.
+
+	  Below you can choose which versions of the NFS protocol are
+	  available in the kernel to mount NFS servers.  Support for NFS
+	  version 2 (RFC 1094) is always available when NFS_FS is selected.
+
+	  To configure a system which mounts its root file system via NFS
+	  at boot time, say Y here, select "Kernel level IP
+	  autoconfiguration" in the NETWORK menu, and select "Root file
+	  system on NFS" below.  You cannot compile this file system as a
+	  module in this case.
+
+	  If unsure, say N.
+
+config NFS_V3
+	bool "NFS client support for NFS version 3"
+	depends on NFS_FS
+	help
+	  This option enables support for version 3 of the NFS protocol
+	  (RFC 1813) in the kernel's NFS client.
+
+	  If unsure, say Y.
+
+config NFS_V3_ACL
+	bool "NFS client support for the NFSv3 ACL protocol extension"
+	depends on NFS_V3
+	help
+	  Some NFS servers support an auxiliary NFSv3 ACL protocol that
+	  Sun added to Solaris but never became an official part of the
+	  NFS version 3 protocol.  This protocol extension allows
+	  applications on NFS clients to manipulate POSIX Access Control
+	  Lists on files residing on NFS servers.  NFS servers enforce
+	  ACLs on local files whether this protocol is available or not.
+
+	  Choose Y here if your NFS server supports the Solaris NFSv3 ACL
+	  protocol extension and you want your NFS client to allow
+	  applications to access and modify ACLs on files on the server.
+
+	  Most NFS servers don't support the Solaris NFSv3 ACL protocol
+	  extension.  You can choose N here or specify the "noacl" mount
+	  option to prevent your NFS client from trying to use the NFSv3
+	  ACL protocol.
+
+	  If unsure, say N.
+
+config NFS_V4
+	bool "NFS client support for NFS version 4 (EXPERIMENTAL)"
+	depends on NFS_FS && EXPERIMENTAL
+	select RPCSEC_GSS_KRB5
+	help
+	  This option enables support for version 4 of the NFS protocol
+	  (RFC 3530) in the kernel's NFS client.
+
+	  To mount NFS servers using NFSv4, you also need to install user
+	  space programs which can be found in the Linux nfs-utils package,
+	  available from http://linux-nfs.org/.
+
+	  If unsure, say N.
+
+config ROOT_NFS
+	bool "Root file system on NFS"
+	depends on NFS_FS=y && IP_PNP
+	help
+	  If you want your system to mount its root file system via NFS,
+	  choose Y here.  This is common practice for managing systems
+	  without local permanent storage.  For details, read
+	  <file:Documentation/filesystems/nfsroot.txt>.
+
+	  Most people say N here.
+
+config NFSD
+	tristate "NFS server support"
+	depends on INET
+	select LOCKD
+	select SUNRPC
+	select EXPORTFS
+	select NFS_ACL_SUPPORT if NFSD_V2_ACL
+	help
+	  Choose Y here if you want to allow other computers to access
+	  files residing on this system using Sun's Network File System
+	  protocol.  To compile the NFS server support as a module,
+	  choose M here: the module will be called nfsd.
+
+	  You may choose to use a user-space NFS server instead, in which
+	  case you can choose N here.
+
+	  To export local file systems using NFS, you also need to install
+	  user space programs which can be found in the Linux nfs-utils
+	  package, available from http://linux-nfs.org/.  More detail about
+	  the Linux NFS server implementation is available via the
+	  exports(5) man page.
+
+	  Below you can choose which versions of the NFS protocol are
+	  available to clients mounting the NFS server on this system.
+	  Support for NFS version 2 (RFC 1094) is always available when
+	  CONFIG_NFSD is selected.
+
+	  If unsure, say N.
+
+config NFSD_V2_ACL
+	bool
+	depends on NFSD
+
+config NFSD_V3
+	bool "NFS server support for NFS version 3"
+	depends on NFSD
+	help
+	  This option enables support in your system's NFS server for
+	  version 3 of the NFS protocol (RFC 1813).
+
+	  If unsure, say Y.
+
+config NFSD_V3_ACL
+	bool "NFS server support for the NFSv3 ACL protocol extension"
+	depends on NFSD_V3
+	select NFSD_V2_ACL
+	help
+	  Solaris NFS servers support an auxiliary NFSv3 ACL protocol that
+	  never became an official part of the NFS version 3 protocol.
+	  This protocol extension allows applications on NFS clients to
+	  manipulate POSIX Access Control Lists on files residing on NFS
+	  servers.  NFS servers enforce POSIX ACLs on local files whether
+	  this protocol is available or not.
+
+	  This option enables support in your system's NFS server for the
+	  NFSv3 ACL protocol extension allowing NFS clients to manipulate
+	  POSIX ACLs on files exported by your system's NFS server.  NFS
+	  clients which support the Solaris NFSv3 ACL protocol can then
+	  access and modify ACLs on your NFS server.
+
+	  To store ACLs on your NFS server, you also need to enable ACL-
+	  related CONFIG options for your local file systems of choice.
+
+	  If unsure, say N.
+
+config NFSD_V4
+	bool "NFS server support for NFS version 4 (EXPERIMENTAL)"
+	depends on NFSD && PROC_FS && EXPERIMENTAL
+	select NFSD_V3
+	select FS_POSIX_ACL
+	select RPCSEC_GSS_KRB5
+	help
+	  This option enables support in your system's NFS server for
+	  version 4 of the NFS protocol (RFC 3530).
+
+	  To export files using NFSv4, you need to install additional user
+	  space programs which can be found in the Linux nfs-utils package,
+	  available from http://linux-nfs.org/.
+
+	  If unsure, say N.
+
+config LOCKD
+	tristate
+
+config LOCKD_V4
+	bool
+	depends on NFSD_V3 || NFS_V3
+	default y
+
+config EXPORTFS
+	tristate
+
+config NFS_ACL_SUPPORT
+	tristate
+	select FS_POSIX_ACL
+
+config NFS_COMMON
+	bool
+	depends on NFSD || NFS_FS
+	default y
+
+config SUNRPC
+	tristate
+
+config SUNRPC_GSS
+	tristate
+
+config SUNRPC_XPRT_RDMA
+	tristate
+	depends on SUNRPC && INFINIBAND && EXPERIMENTAL
+	default SUNRPC && INFINIBAND
+	help
+	  This option enables an RPC client transport capability that
+	  allows the NFS client to mount servers via an RDMA-enabled
+	  transport.
+
+	  To compile RPC client RDMA transport support as a module,
+	  choose M here: the module will be called xprtrdma.
+
+	  If unsure, say N.
+
+config RPCSEC_GSS_KRB5
+	tristate "Secure RPC: Kerberos V mechanism (EXPERIMENTAL)"
+	depends on SUNRPC && EXPERIMENTAL
+	select SUNRPC_GSS
+	select CRYPTO
+	select CRYPTO_MD5
+	select CRYPTO_DES
+	select CRYPTO_CBC
+	help
+	  Choose Y here to enable Secure RPC using the Kerberos version 5
+	  GSS-API mechanism (RFC 1964).
+
+	  Secure RPC calls with Kerberos require an auxiliary user-space
+	  daemon which may be found in the Linux nfs-utils package
+	  available from http://linux-nfs.org/.  In addition, user-space
+	  Kerberos support should be installed.
+
+	  If unsure, say N.
+
+config RPCSEC_GSS_SPKM3
+	tristate "Secure RPC: SPKM3 mechanism (EXPERIMENTAL)"
+	depends on SUNRPC && EXPERIMENTAL
+	select SUNRPC_GSS
+	select CRYPTO
+	select CRYPTO_MD5
+	select CRYPTO_DES
+	select CRYPTO_CAST5
+	select CRYPTO_CBC
+	help
+	  Choose Y here to enable Secure RPC using the SPKM3 public key
+	  GSS-API mechansim (RFC 2025).
+
+	  Secure RPC calls with SPKM3 require an auxiliary userspace
+	  daemon which may be found in the Linux nfs-utils package
+	  available from http://linux-nfs.org/.
+
+	  If unsure, say N.
+
+config SMB_FS
+	tristate "SMB file system support (OBSOLETE, please use CIFS)"
+	depends on INET
+	select NLS
+	help
+	  SMB (Server Message Block) is the protocol Windows for Workgroups
+	  (WfW), Windows 95/98, Windows NT and OS/2 Lan Manager use to share
+	  files and printers over local networks.  Saying Y here allows you to
+	  mount their file systems (often called "shares" in this context) and
+	  access them just like any other Unix directory.  Currently, this
+	  works only if the Windows machines use TCP/IP as the underlying
+	  transport protocol, and not NetBEUI.  For details, read
+	  <file:Documentation/filesystems/smbfs.txt> and the SMB-HOWTO,
+	  available from <http://www.tldp.org/docs.html#howto>.
+
+	  Note: if you just want your box to act as an SMB *server* and make
+	  files and printing services available to Windows clients (which need
+	  to have a TCP/IP stack), you don't need to say Y here; you can use
+	  the program SAMBA (available from <ftp://ftp.samba.org/pub/samba/>)
+	  for that.
+
+	  General information about how to connect Linux, Windows machines and
+	  Macs is on the WWW at <http://www.eats.com/linux_mac_win.html>.
+
+	  To compile the SMB support as a module, choose M here:
+	  the module will be called smbfs.  Most people say N, however.
+
+config SMB_NLS_DEFAULT
+	bool "Use a default NLS"
+	depends on SMB_FS
+	help
+	  Enabling this will make smbfs use nls translations by default. You
+	  need to specify the local charset (CONFIG_NLS_DEFAULT) in the nls
+	  settings and you need to give the default nls for the SMB server as
+	  CONFIG_SMB_NLS_REMOTE.
+
+	  The nls settings can be changed at mount time, if your smbmount
+	  supports that, using the codepage and iocharset parameters.
+
+	  smbmount from samba 2.2.0 or later supports this.
+
+config SMB_NLS_REMOTE
+	string "Default Remote NLS Option"
+	depends on SMB_NLS_DEFAULT
+	default "cp437"
+	help
+	  This setting allows you to specify a default value for which
+	  codepage the server uses. If this field is left blank no
+	  translations will be done by default. The local codepage/charset
+	  default to CONFIG_NLS_DEFAULT.
+
+	  The nls settings can be changed at mount time, if your smbmount
+	  supports that, using the codepage and iocharset parameters.
+
+	  smbmount from samba 2.2.0 or later supports this.
+
+config CIFS
+	tristate "CIFS support (advanced network filesystem, SMBFS successor)"
+	depends on INET
+	select NLS
+	help
+	  This is the client VFS module for the Common Internet File System
+	  (CIFS) protocol which is the successor to the Server Message Block 
+	  (SMB) protocol, the native file sharing mechanism for most early
+	  PC operating systems.  The CIFS protocol is fully supported by 
+	  file servers such as Windows 2000 (including Windows 2003, NT 4  
+	  and Windows XP) as well by Samba (which provides excellent CIFS
+	  server support for Linux and many other operating systems). Limited
+	  support for OS/2 and Windows ME and similar servers is provided as
+	  well.
+
+	  The cifs module provides an advanced network file system
+	  client for mounting to CIFS compliant servers.  It includes
+	  support for DFS (hierarchical name space), secure per-user
+	  session establishment via Kerberos or NTLM or NTLMv2,
+	  safe distributed caching (oplock), optional packet
+	  signing, Unicode and other internationalization improvements.
+	  If you need to mount to Samba or Windows from this machine, say Y.
+
+config CIFS_STATS
+        bool "CIFS statistics"
+        depends on CIFS
+        help
+          Enabling this option will cause statistics for each server share
+	  mounted by the cifs client to be displayed in /proc/fs/cifs/Stats
+
+config CIFS_STATS2
+	bool "Extended statistics"
+	depends on CIFS_STATS
+	help
+	  Enabling this option will allow more detailed statistics on SMB
+	  request timing to be displayed in /proc/fs/cifs/DebugData and also
+	  allow optional logging of slow responses to dmesg (depending on the
+	  value of /proc/fs/cifs/cifsFYI, see fs/cifs/README for more details).
+	  These additional statistics may have a minor effect on performance
+	  and memory utilization.
+
+	  Unless you are a developer or are doing network performance analysis
+	  or tuning, say N.
+
+config CIFS_WEAK_PW_HASH
+	bool "Support legacy servers which use weaker LANMAN security"
+	depends on CIFS
+	help
+	  Modern CIFS servers including Samba and most Windows versions
+	  (since 1997) support stronger NTLM (and even NTLMv2 and Kerberos)
+	  security mechanisms. These hash the password more securely
+	  than the mechanisms used in the older LANMAN version of the
+	  SMB protocol but LANMAN based authentication is needed to
+	  establish sessions with some old SMB servers.
+
+	  Enabling this option allows the cifs module to mount to older
+	  LANMAN based servers such as OS/2 and Windows 95, but such
+	  mounts may be less secure than mounts using NTLM or more recent
+	  security mechanisms if you are on a public network.  Unless you
+	  have a need to access old SMB servers (and are on a private
+	  network) you probably want to say N.  Even if this support
+	  is enabled in the kernel build, LANMAN authentication will not be
+	  used automatically. At runtime LANMAN mounts are disabled but
+	  can be set to required (or optional) either in
+	  /proc/fs/cifs (see fs/cifs/README for more detail) or via an
+	  option on the mount command. This support is disabled by
+	  default in order to reduce the possibility of a downgrade
+	  attack.
+
+	  If unsure, say N.
+
+config CIFS_UPCALL
+	  bool "Kerberos/SPNEGO advanced session setup"
+	  depends on CIFS && KEYS
+	  help
+	    Enables an upcall mechanism for CIFS which accesses
+	    userspace helper utilities to provide SPNEGO packaged (RFC 4178)
+	    Kerberos tickets which are needed to mount to certain secure servers
+	    (for which more secure Kerberos authentication is required). If
+	    unsure, say N.
+
+config CIFS_XATTR
+        bool "CIFS extended attributes"
+        depends on CIFS
+        help
+          Extended attributes are name:value pairs associated with inodes by
+          the kernel or by users (see the attr(5) manual page, or visit
+          <http://acl.bestbits.at/> for details).  CIFS maps the name of
+          extended attributes beginning with the user namespace prefix
+          to SMB/CIFS EAs. EAs are stored on Windows servers without the
+          user namespace prefix, but their names are seen by Linux cifs clients
+          prefaced by the user namespace prefix. The system namespace
+          (used by some filesystems to store ACLs) is not supported at
+          this time.
+
+          If unsure, say N.
+
+config CIFS_POSIX
+        bool "CIFS POSIX Extensions"
+        depends on CIFS_XATTR
+        help
+          Enabling this option will cause the cifs client to attempt to
+	  negotiate a newer dialect with servers, such as Samba 3.0.5
+	  or later, that optionally can handle more POSIX like (rather
+	  than Windows like) file behavior.  It also enables
+	  support for POSIX ACLs (getfacl and setfacl) to servers
+	  (such as Samba 3.10 and later) which can negotiate
+	  CIFS POSIX ACL support.  If unsure, say N.
+
+config CIFS_DEBUG2
+	bool "Enable additional CIFS debugging routines"
+	depends on CIFS
+	help
+	   Enabling this option adds a few more debugging routines
+	   to the cifs code which slightly increases the size of
+	   the cifs module and can cause additional logging of debug
+	   messages in some error paths, slowing performance. This
+	   option can be turned off unless you are debugging
+	   cifs problems.  If unsure, say N.
+
+config CIFS_EXPERIMENTAL
+	  bool "CIFS Experimental Features (EXPERIMENTAL)"
+	  depends on CIFS && EXPERIMENTAL
+	  help
+	    Enables cifs features under testing. These features are
+	    experimental and currently include DFS support and directory 
+	    change notification ie fcntl(F_DNOTIFY), as well as the upcall
+	    mechanism which will be used for Kerberos session negotiation
+	    and uid remapping.  Some of these features also may depend on 
+	    setting a value of 1 to the pseudo-file /proc/fs/cifs/Experimental
+	    (which is disabled by default). See the file fs/cifs/README 
+	    for more details.  If unsure, say N.
+
+config CIFS_DFS_UPCALL
+	  bool "DFS feature support (EXPERIMENTAL)"
+	  depends on CIFS_EXPERIMENTAL
+	  depends on KEYS
+	  help
+	    Enables an upcall mechanism for CIFS which contacts userspace
+	    helper utilities to provide server name resolution (host names to
+	    IP addresses) which is needed for implicit mounts of DFS junction
+	    points. If unsure, say N.
+
+config NCP_FS
+	tristate "NCP file system support (to mount NetWare volumes)"
+	depends on IPX!=n || INET
+	help
+	  NCP (NetWare Core Protocol) is a protocol that runs over IPX and is
+	  used by Novell NetWare clients to talk to file servers.  It is to
+	  IPX what NFS is to TCP/IP, if that helps.  Saying Y here allows you
+	  to mount NetWare file server volumes and to access them just like
+	  any other Unix directory.  For details, please read the file
+	  <file:Documentation/filesystems/ncpfs.txt> in the kernel source and
+	  the IPX-HOWTO from <http://www.tldp.org/docs.html#howto>.
+
+	  You do not have to say Y here if you want your Linux box to act as a
+	  file *server* for Novell NetWare clients.
+
+	  General information about how to connect Linux, Windows machines and
+	  Macs is on the WWW at <http://www.eats.com/linux_mac_win.html>.
+
+	  To compile this as a module, choose M here: the module will be called
+	  ncpfs.  Say N unless you are connected to a Novell network.
+
+source "fs/ncpfs/Kconfig"
+
+config CODA_FS
+	tristate "Coda file system support (advanced network fs)"
+	depends on INET
+	help
+	  Coda is an advanced network file system, similar to NFS in that it
+	  enables you to mount file systems of a remote server and access them
+	  with regular Unix commands as if they were sitting on your hard
+	  disk.  Coda has several advantages over NFS: support for
+	  disconnected operation (e.g. for laptops), read/write server
+	  replication, security model for authentication and encryption,
+	  persistent client caches and write back caching.
+
+	  If you say Y here, your Linux box will be able to act as a Coda
+	  *client*.  You will need user level code as well, both for the
+	  client and server.  Servers are currently user level, i.e. they need
+	  no kernel support.  Please read
+	  <file:Documentation/filesystems/coda.txt> and check out the Coda
+	  home page <http://www.coda.cs.cmu.edu/>.
+
+	  To compile the coda client support as a module, choose M here: the
+	  module will be called coda.
+
+config AFS_FS
+	tristate "Andrew File System support (AFS) (EXPERIMENTAL)"
+	depends on INET && EXPERIMENTAL
+	select AF_RXRPC
+	help
+	  If you say Y here, you will get an experimental Andrew File System
+	  driver. It currently only supports unsecured read-only AFS access.
+
+	  See <file:Documentation/filesystems/afs.txt> for more information.
+
+	  If unsure, say N.
+
+config AFS_DEBUG
+	bool "AFS dynamic debugging"
+	depends on AFS_FS
+	help
+	  Say Y here to make runtime controllable debugging messages appear.
+
+	  See <file:Documentation/filesystems/afs.txt> for more information.
+
+	  If unsure, say N.
+
+config 9P_FS
+	tristate "Plan 9 Resource Sharing Support (9P2000) (Experimental)"
+	depends on INET && NET_9P && EXPERIMENTAL
+	help
+	  If you say Y here, you will get experimental support for
+	  Plan 9 resource sharing via the 9P2000 protocol.
+
+	  See <http://v9fs.sf.net> for more information.
+
+	  If unsure, say N.
+
+endif # NETWORK_FILESYSTEMS
+
+if BLOCK
+menu "Partition Types"
+
+source "fs/partitions/Kconfig"
+
+endmenu
+endif
+
+source "fs/nls/Kconfig"
+source "fs/dlm/Kconfig"
+
+endmenu
diff -uNra linux-2.6.27.6/fs/Makefile linux-2.6.27.6.yaffs/fs/Makefile
--- linux-2.6.27.6/fs/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/Makefile	2011-05-08 18:01:21.000000000 +0800
@@ -122,3 +122,6 @@
 obj-$(CONFIG_DEBUG_FS)		+= debugfs/
 obj-$(CONFIG_OCFS2_FS)		+= ocfs2/
 obj-$(CONFIG_GFS2_FS)           += gfs2/
+
+# Patched by YAFFS
+obj-$(CONFIG_YAFFS_FS)		+= yaffs2/
diff -uNra linux-2.6.27.6/fs/Makefile.pre.yaffs linux-2.6.27.6.yaffs/fs/Makefile.pre.yaffs
--- linux-2.6.27.6/fs/Makefile.pre.yaffs	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/Makefile.pre.yaffs	2011-05-08 18:01:10.000000000 +0800
@@ -0,0 +1,124 @@
+#
+# Makefile for the Linux filesystems.
+#
+# 14 Sep 2000, Christoph Hellwig <hch@infradead.org>
+# Rewritten to use lists instead of if-statements.
+# 
+
+obj-y :=	open.o read_write.o file_table.o super.o \
+		char_dev.o stat.o exec.o pipe.o namei.o fcntl.o \
+		ioctl.o readdir.o select.o fifo.o locks.o dcache.o inode.o \
+		attr.o bad_inode.o file.o filesystems.o namespace.o aio.o \
+		seq_file.o xattr.o libfs.o fs-writeback.o \
+		pnode.o drop_caches.o splice.o sync.o utimes.o \
+		stack.o
+
+ifeq ($(CONFIG_BLOCK),y)
+obj-y +=	buffer.o bio.o block_dev.o direct-io.o mpage.o ioprio.o
+else
+obj-y +=	no-block.o
+endif
+
+obj-$(CONFIG_BLK_DEV_INTEGRITY) += bio-integrity.o
+obj-$(CONFIG_INOTIFY)		+= inotify.o
+obj-$(CONFIG_INOTIFY_USER)	+= inotify_user.o
+obj-$(CONFIG_EPOLL)		+= eventpoll.o
+obj-$(CONFIG_ANON_INODES)	+= anon_inodes.o
+obj-$(CONFIG_SIGNALFD)		+= signalfd.o
+obj-$(CONFIG_TIMERFD)		+= timerfd.o
+obj-$(CONFIG_EVENTFD)		+= eventfd.o
+obj-$(CONFIG_COMPAT)		+= compat.o compat_ioctl.o
+
+nfsd-$(CONFIG_NFSD)		:= nfsctl.o
+obj-y				+= $(nfsd-y) $(nfsd-m)
+
+obj-$(CONFIG_BINFMT_AOUT)	+= binfmt_aout.o
+obj-$(CONFIG_BINFMT_EM86)	+= binfmt_em86.o
+obj-$(CONFIG_BINFMT_MISC)	+= binfmt_misc.o
+
+# binfmt_script is always there
+obj-y				+= binfmt_script.o
+
+obj-$(CONFIG_BINFMT_ELF)	+= binfmt_elf.o
+obj-$(CONFIG_COMPAT_BINFMT_ELF)	+= compat_binfmt_elf.o
+obj-$(CONFIG_BINFMT_ELF_FDPIC)	+= binfmt_elf_fdpic.o
+obj-$(CONFIG_BINFMT_SOM)	+= binfmt_som.o
+obj-$(CONFIG_BINFMT_FLAT)	+= binfmt_flat.o
+
+obj-$(CONFIG_FS_MBCACHE)	+= mbcache.o
+obj-$(CONFIG_FS_POSIX_ACL)	+= posix_acl.o xattr_acl.o
+obj-$(CONFIG_NFS_COMMON)	+= nfs_common/
+obj-$(CONFIG_GENERIC_ACL)	+= generic_acl.o
+
+obj-$(CONFIG_QUOTA)		+= dquot.o
+obj-$(CONFIG_QFMT_V1)		+= quota_v1.o
+obj-$(CONFIG_QFMT_V2)		+= quota_v2.o
+obj-$(CONFIG_QUOTACTL)		+= quota.o
+
+obj-$(CONFIG_DNOTIFY)		+= dnotify.o
+
+obj-$(CONFIG_PROC_FS)		+= proc/
+obj-y				+= partitions/
+obj-$(CONFIG_SYSFS)		+= sysfs/
+obj-$(CONFIG_CONFIGFS_FS)	+= configfs/
+obj-y				+= devpts/
+
+obj-$(CONFIG_PROFILING)		+= dcookies.o
+obj-$(CONFIG_DLM)		+= dlm/
+ 
+# Do not add any filesystems before this line
+obj-$(CONFIG_REISERFS_FS)	+= reiserfs/
+obj-$(CONFIG_EXT3_FS)		+= ext3/ # Before ext2 so root fs can be ext3
+obj-$(CONFIG_EXT4DEV_FS)	+= ext4/ # Before ext2 so root fs can be ext4dev
+obj-$(CONFIG_JBD)		+= jbd/
+obj-$(CONFIG_JBD2)		+= jbd2/
+obj-$(CONFIG_EXT2_FS)		+= ext2/
+obj-$(CONFIG_CRAMFS)		+= cramfs/
+obj-y				+= ramfs/
+obj-$(CONFIG_HUGETLBFS)		+= hugetlbfs/
+obj-$(CONFIG_CODA_FS)		+= coda/
+obj-$(CONFIG_MINIX_FS)		+= minix/
+obj-$(CONFIG_FAT_FS)		+= fat/
+obj-$(CONFIG_MSDOS_FS)		+= msdos/
+obj-$(CONFIG_VFAT_FS)		+= vfat/
+obj-$(CONFIG_BFS_FS)		+= bfs/
+obj-$(CONFIG_ISO9660_FS)	+= isofs/
+obj-$(CONFIG_HFSPLUS_FS)	+= hfsplus/ # Before hfs to find wrapped HFS+
+obj-$(CONFIG_HFS_FS)		+= hfs/
+obj-$(CONFIG_ECRYPT_FS)		+= ecryptfs/
+obj-$(CONFIG_VXFS_FS)		+= freevxfs/
+obj-$(CONFIG_NFS_FS)		+= nfs/
+obj-$(CONFIG_EXPORTFS)		+= exportfs/
+obj-$(CONFIG_NFSD)		+= nfsd/
+obj-$(CONFIG_LOCKD)		+= lockd/
+obj-$(CONFIG_NLS)		+= nls/
+obj-$(CONFIG_SYSV_FS)		+= sysv/
+obj-$(CONFIG_SMB_FS)		+= smbfs/
+obj-$(CONFIG_CIFS)		+= cifs/
+obj-$(CONFIG_NCP_FS)		+= ncpfs/
+obj-$(CONFIG_HPFS_FS)		+= hpfs/
+obj-$(CONFIG_NTFS_FS)		+= ntfs/
+obj-$(CONFIG_UFS_FS)		+= ufs/
+obj-$(CONFIG_EFS_FS)		+= efs/
+obj-$(CONFIG_JFFS2_FS)		+= jffs2/
+obj-$(CONFIG_UBIFS_FS)		+= ubifs/
+obj-$(CONFIG_AFFS_FS)		+= affs/
+obj-$(CONFIG_ROMFS_FS)		+= romfs/
+obj-$(CONFIG_QNX4FS_FS)		+= qnx4/
+obj-$(CONFIG_AUTOFS_FS)		+= autofs/
+obj-$(CONFIG_AUTOFS4_FS)	+= autofs4/
+obj-$(CONFIG_ADFS_FS)		+= adfs/
+obj-$(CONFIG_FUSE_FS)		+= fuse/
+obj-$(CONFIG_UDF_FS)		+= udf/
+obj-$(CONFIG_SUN_OPENPROMFS)	+= openpromfs/
+obj-$(CONFIG_OMFS_FS)		+= omfs/
+obj-$(CONFIG_JFS_FS)		+= jfs/
+obj-$(CONFIG_XFS_FS)		+= xfs/
+obj-$(CONFIG_9P_FS)		+= 9p/
+obj-$(CONFIG_AFS_FS)		+= afs/
+obj-$(CONFIG_BEFS_FS)		+= befs/
+obj-$(CONFIG_HOSTFS)		+= hostfs/
+obj-$(CONFIG_HPPFS)		+= hppfs/
+obj-$(CONFIG_DEBUG_FS)		+= debugfs/
+obj-$(CONFIG_OCFS2_FS)		+= ocfs2/
+obj-$(CONFIG_GFS2_FS)           += gfs2/
diff -uNra linux-2.6.27.6/fs/yaffs2/devextras.h linux-2.6.27.6.yaffs/fs/yaffs2/devextras.h
--- linux-2.6.27.6/fs/yaffs2/devextras.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/devextras.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,196 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/*
+ * This file is just holds extra declarations of macros that would normally
+ * be providesd in the Linux kernel. These macros have been written from
+ * scratch but are functionally equivalent to the Linux ones.
+ *
+ */
+
+#ifndef __EXTRAS_H__
+#define __EXTRAS_H__
+
+
+#if !(defined __KERNEL__)
+
+/* Definition of types */
+typedef unsigned char __u8;
+typedef unsigned short __u16;
+typedef unsigned __u32;
+
+#endif
+
+/*
+ * This is a simple doubly linked list implementation that matches the
+ * way the Linux kernel doubly linked list implementation works.
+ */
+
+struct ylist_head {
+	struct ylist_head *next; /* next in chain */
+	struct ylist_head *prev; /* previous in chain */
+};
+
+
+/* Initialise a static list */
+#define YLIST_HEAD(name) \
+struct ylist_head name = { &(name), &(name)}
+
+
+
+/* Initialise a list head to an empty list */
+#define YINIT_LIST_HEAD(p) \
+do { \
+	(p)->next = (p);\
+	(p)->prev = (p); \
+} while (0)
+
+
+/* Add an element to a list */
+static __inline__ void ylist_add(struct ylist_head *newEntry,
+				struct ylist_head *list)
+{
+	struct ylist_head *listNext = list->next;
+
+	list->next = newEntry;
+	newEntry->prev = list;
+	newEntry->next = listNext;
+	listNext->prev = newEntry;
+
+}
+
+static __inline__ void ylist_add_tail(struct ylist_head *newEntry,
+				 struct ylist_head *list)
+{
+	struct ylist_head *listPrev = list->prev;
+
+	list->prev = newEntry;
+	newEntry->next = list;
+	newEntry->prev = listPrev;
+	listPrev->next = newEntry;
+
+}
+
+
+/* Take an element out of its current list, with or without
+ * reinitialising the links.of the entry*/
+static __inline__ void ylist_del(struct ylist_head *entry)
+{
+	struct ylist_head *listNext = entry->next;
+	struct ylist_head *listPrev = entry->prev;
+
+	listNext->prev = listPrev;
+	listPrev->next = listNext;
+
+}
+
+static __inline__ void ylist_del_init(struct ylist_head *entry)
+{
+	ylist_del(entry);
+	entry->next = entry->prev = entry;
+}
+
+
+/* Test if the list is empty */
+static __inline__ int ylist_empty(struct ylist_head *entry)
+{
+	return (entry->next == entry);
+}
+
+
+/* ylist_entry takes a pointer to a list entry and offsets it to that
+ * we can find a pointer to the object it is embedded in.
+ */
+
+
+#define ylist_entry(entry, type, member) \
+	((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member)))
+
+
+/* ylist_for_each and list_for_each_safe  iterate over lists.
+ * ylist_for_each_safe uses temporary storage to make the list delete safe
+ */
+
+#define ylist_for_each(itervar, list) \
+	for (itervar = (list)->next; itervar != (list); itervar = itervar->next)
+
+#define ylist_for_each_safe(itervar, saveVar, list) \
+	for (itervar = (list)->next, saveVar = (list)->next->next; \
+		itervar != (list); itervar = saveVar, saveVar = saveVar->next)
+
+
+#if !(defined __KERNEL__)
+
+
+#ifndef WIN32
+#include <sys/stat.h>
+#endif
+
+
+#ifdef CONFIG_YAFFS_PROVIDE_DEFS
+/* File types */
+
+
+#define DT_UNKNOWN	0
+#define DT_FIFO		1
+#define DT_CHR		2
+#define DT_DIR		4
+#define DT_BLK		6
+#define DT_REG		8
+#define DT_LNK		10
+#define DT_SOCK		12
+#define DT_WHT		14
+
+
+#ifndef WIN32
+#include <sys/stat.h>
+#endif
+
+/*
+ * Attribute flags.  These should be or-ed together to figure out what
+ * has been changed!
+ */
+#define ATTR_MODE	1
+#define ATTR_UID	2
+#define ATTR_GID	4
+#define ATTR_SIZE	8
+#define ATTR_ATIME	16
+#define ATTR_MTIME	32
+#define ATTR_CTIME	64
+
+struct iattr {
+	unsigned int ia_valid;
+	unsigned ia_mode;
+	unsigned ia_uid;
+	unsigned ia_gid;
+	unsigned ia_size;
+	unsigned ia_atime;
+	unsigned ia_mtime;
+	unsigned ia_ctime;
+	unsigned int ia_attr_flags;
+};
+
+#endif
+
+#else
+
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/stat.h>
+
+#endif
+
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/Kconfig linux-2.6.27.6.yaffs/fs/yaffs2/Kconfig
--- linux-2.6.27.6/fs/yaffs2/Kconfig	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/Kconfig	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,200 @@
+#
+# YAFFS file system configurations
+#
+
+config YAFFS_FS
+	tristate "YAFFS2 file system support"
+	default n
+	depends on MTD_BLOCK
+	select YAFFS_YAFFS1
+	select YAFFS_YAFFS2
+	help
+	  YAFFS2, or Yet Another Flash Filing System, is a filing system
+	  optimised for NAND Flash chips.
+
+	  To compile the YAFFS2 file system support as a module, choose M
+	  here: the module will be called yaffs2.
+
+	  If unsure, say N.
+
+	  Further information on YAFFS2 is available at
+	  <http://www.aleph1.co.uk/yaffs/>.
+
+config YAFFS_YAFFS1
+	bool "512 byte / page devices"
+	depends on YAFFS_FS
+	default y
+	help
+	  Enable YAFFS1 support -- yaffs for 512 byte / page devices
+
+	  Not needed for 2K-page devices.
+
+	  If unsure, say Y.
+
+config YAFFS_9BYTE_TAGS
+	bool "Use older-style on-NAND data format with pageStatus byte"
+	depends on YAFFS_YAFFS1
+	default n
+	help
+
+	  Older-style on-NAND data format has a "pageStatus" byte to record
+	  chunk/page state.  This byte is zero when the page is discarded.
+	  Choose this option if you have existing on-NAND data using this
+	  format that you need to continue to support.  New data written
+	  also uses the older-style format.  Note: Use of this option
+	  generally requires that MTD's oob layout be adjusted to use the
+	  older-style format.  See notes on tags formats and MTD versions
+	  in yaffs_mtdif1.c.
+
+	  If unsure, say N.
+
+config YAFFS_DOES_ECC
+	bool "Lets Yaffs do its own ECC"
+	depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS
+	default n
+	help
+	  This enables Yaffs to use its own ECC functions instead of using
+	  the ones from the generic MTD-NAND driver.
+
+	  If unsure, say N.
+
+config YAFFS_ECC_WRONG_ORDER
+	bool "Use the same ecc byte order as Steven Hill's nand_ecc.c"
+	depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS
+	default n
+	help
+	  This makes yaffs_ecc.c use the same ecc byte order as Steven
+	  Hill's nand_ecc.c. If not set, then you get the same ecc byte
+	  order as SmartMedia.
+
+	  If unsure, say N.
+
+config YAFFS_YAFFS2
+	bool "2048 byte (or larger) / page devices"
+	depends on YAFFS_FS
+	default y
+	help
+	  Enable YAFFS2 support -- yaffs for >= 2K bytes per page devices
+
+	  If unsure, say Y.
+
+config YAFFS_AUTO_YAFFS2
+	bool "Autoselect yaffs2 format"
+	depends on YAFFS_YAFFS2
+	default y
+	help
+	  Without this, you need to explicitely use yaffs2 as the file
+	  system type. With this, you can say "yaffs" and yaffs or yaffs2
+	  will be used depending on the device page size (yaffs on
+	  512-byte page devices, yaffs2 on 2K page devices).
+
+	  If unsure, say Y.
+
+config YAFFS_DISABLE_TAGS_ECC
+	bool "Disable YAFFS from doing ECC on tags by default"
+	depends on YAFFS_FS && YAFFS_YAFFS2
+	default n
+	help
+	  This defaults Yaffs to using its own ECC calculations on tags instead of
+	  just relying on the MTD.
+	  This behavior can also be overridden with tags_ecc_on and
+	  tags_ecc_off mount options.
+
+	  If unsure, say N.
+
+config YAFFS_DISABLE_LAZY_LOAD
+	bool "Disable lazy loading"
+	depends on YAFFS_YAFFS2
+	default n
+	help
+	  "Lazy loading" defers loading file details until they are
+	  required. This saves mount time, but makes the first look-up
+	  a bit longer.
+
+	  Lazy loading will only happen if enabled by this option being 'n'
+	  and if the appropriate tags are available, else yaffs2 will
+	  automatically fall back to immediate loading and do the right
+	  thing.
+
+	  Lazy laoding will be required by checkpointing.
+
+	  Setting this to 'y' will disable lazy loading.
+
+	  If unsure, say N.
+
+
+config YAFFS_DISABLE_WIDE_TNODES
+	bool "Turn off wide tnodes"
+	depends on YAFFS_FS
+	default n
+	help
+	  Wide tnodes are only used for NAND arrays >=32MB for 512-byte
+	  page devices and >=128MB for 2k page devices. They use slightly
+	  more RAM but are faster since they eliminate chunk group
+	  searching.
+
+	  Setting this to 'y' will force tnode width to 16 bits and save
+	  memory but make large arrays slower.
+
+	  If unsure, say N.
+
+config YAFFS_ALWAYS_CHECK_CHUNK_ERASED
+	bool "Force chunk erase check"
+	depends on YAFFS_FS
+	default n
+	help
+          Normally YAFFS only checks chunks before writing until an erased
+	  chunk is found. This helps to detect any partially written
+	  chunks that might have happened due to power loss.
+
+	  Enabling this forces on the test that chunks are erased in flash
+	  before writing to them. This takes more time but is potentially
+	  a bit more secure.
+
+	  Suggest setting Y during development and ironing out driver
+	  issues etc. Suggest setting to N if you want faster writing.
+
+	  If unsure, say Y.
+
+config YAFFS_SHORT_NAMES_IN_RAM
+	bool "Cache short names in RAM"
+	depends on YAFFS_FS
+	default y
+	help
+	  If this config is set, then short names are stored with the
+	  yaffs_Object.  This costs an extra 16 bytes of RAM per object,
+	  but makes look-ups faster.
+
+	  If unsure, say Y.
+
+config YAFFS_EMPTY_LOST_AND_FOUND
+	bool "Empty lost and found on boot"
+	depends on YAFFS_FS
+	default n
+	help
+	  If this is enabled then the contents of lost and found is
+	  automatically dumped at mount.
+
+	  If unsure, say N.
+
+config YAFFS_DISABLE_BLOCK_REFRESHING
+	bool "Disable yaffs2 block refreshing"
+	depends on YAFFS_FS
+	default n
+	help
+	 If this is set, then block refreshing is disabled.
+	 Block refreshing infrequently refreshes the oldest block in
+	 a yaffs2 file system. This mechanism helps to refresh flash to
+	 mitigate against data loss. This is particularly useful for MLC.
+
+	  If unsure, say N.
+
+config YAFFS_DISABLE_BACKGROUND
+	bool "Disable yaffs2 background processing"
+	depends on YAFFS_FS
+	default n
+	help
+	 If this is set, then background processing is disabled.
+	 Background processing makes many foreground activities faster.
+
+	  If unsure, say N.
diff -uNra linux-2.6.27.6/fs/yaffs2/Makefile linux-2.6.27.6.yaffs/fs/yaffs2/Makefile
--- linux-2.6.27.6/fs/yaffs2/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/Makefile	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux YAFFS filesystem routines.
+#
+
+obj-$(CONFIG_YAFFS_FS) += yaffs.o
+
+yaffs-y := yaffs_ecc.o yaffs_fs.o yaffs_guts.o yaffs_checkptrw.o
+yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o yaffs_qsort.o
+yaffs-y += yaffs_tagscompat.o yaffs_tagsvalidity.o
+yaffs-y += yaffs_mtdif.o yaffs_mtdif1.o yaffs_mtdif2.o
diff -uNra linux-2.6.27.6/fs/yaffs2/moduleconfig.h linux-2.6.27.6.yaffs/fs/yaffs2/moduleconfig.h
--- linux-2.6.27.6/fs/yaffs2/moduleconfig.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/moduleconfig.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,81 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Martin Fouts <Martin.Fouts@palmsource.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_CONFIG_H__
+#define __YAFFS_CONFIG_H__
+
+#ifdef YAFFS_OUT_OF_TREE
+
+/* DO NOT UNSET THESE THREE. YAFFS2 will not compile if you do. */
+#define CONFIG_YAFFS_FS
+#define CONFIG_YAFFS_YAFFS1
+#define CONFIG_YAFFS_YAFFS2
+
+/* These options are independent of each other.  Select those that matter. */
+
+/* Default: Not selected */
+/* Meaning: Yaffs does its own ECC, rather than using MTD ECC */
+/* #define CONFIG_YAFFS_DOES_ECC */
+
+/* Default: Selected */
+/* Meaning: Yaffs does its own ECC on tags for packed tags rather than use mtd */
+#define CONFIG_YAFFS_DOES_TAGS_ECC
+
+/* Default: Not selected */
+/* Meaning: ECC byte order is 'wrong'.  Only meaningful if */
+/*          CONFIG_YAFFS_DOES_ECC is set */
+/* #define CONFIG_YAFFS_ECC_WRONG_ORDER */
+
+/* Default: Selected */
+/* Meaning: Disables testing whether chunks are erased before writing to them*/
+#define CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK
+
+/* Default: Not Selected */
+/* Meaning: At mount automatically empty all files from lost and found. */
+/* This is done to fix an old problem where rmdir was not checking for an */
+/* empty directory. This can also be achieved with a mount option. */
+#define CONFIG_YAFFS_EMPTY_LOST_AND_FOUND
+
+/* Default: Selected */
+/* Meaning: Cache short names, taking more RAM, but faster look-ups */
+#define CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+
+/* Default: Unselected */
+/* Meaning: Select to disable block refreshing. */
+/* Block Refreshing periodically rewrites the oldest block. */
+/* #define CONFIG_DISABLE_BLOCK_REFRESHING */
+
+/* Default: Unselected */
+/* Meaning: Select to disable background processing */
+/* #define CONFIG_DISABLE_BACKGROUND */
+
+
+/*
+Older-style on-NAND data format has a "pageStatus" byte to record
+chunk/page state.  This byte is zeroed when the page is discarded.
+Choose this option if you have existing on-NAND data in this format
+that you need to continue to support.  New data written also uses the
+older-style format.
+Note: Use of this option generally requires that MTD's oob layout be
+adjusted to use the older-style format.  See notes on tags formats and
+MTD versions in yaffs_mtdif1.c.
+*/
+/* Default: Not selected */
+/* Meaning: Use older-style on-NAND data format with pageStatus byte */
+/* #define CONFIG_YAFFS_9BYTE_TAGS */
+
+#endif /* YAFFS_OUT_OF_TREE */
+
+#endif /* __YAFFS_CONFIG_H__ */
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_checkptrw.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_checkptrw.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_checkptrw.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_checkptrw.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,405 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_checkptrw_c_version =
+	"$Id: yaffs_checkptrw.c,v 1.23 2010/02/18 01:18:04 charles Exp $";
+
+
+#include "yaffs_checkptrw.h"
+#include "yaffs_getblockinfo.h"
+
+static int yaffs_CheckpointSpaceOk(yaffs_Device *dev)
+{
+	int blocksAvailable = dev->nErasedBlocks - dev->param.nReservedBlocks;
+
+	T(YAFFS_TRACE_CHECKPOINT,
+		(TSTR("checkpt blocks available = %d" TENDSTR),
+		blocksAvailable));
+
+	return (blocksAvailable <= 0) ? 0 : 1;
+}
+
+
+static int yaffs_CheckpointErase(yaffs_Device *dev)
+{
+	int i;
+
+	if (!dev->param.eraseBlockInNAND)
+		return 0;
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checking blocks %d to %d"TENDSTR),
+		dev->internalStartBlock, dev->internalEndBlock));
+
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, i);
+		if (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT) {
+			T(YAFFS_TRACE_CHECKPOINT, (TSTR("erasing checkpt block %d"TENDSTR), i));
+
+			dev->nBlockErasures++;
+
+			if (dev->param.eraseBlockInNAND(dev, i - dev->blockOffset /* realign */)) {
+				bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
+				dev->nErasedBlocks++;
+				dev->nFreeChunks += dev->param.nChunksPerBlock;
+			} else {
+				dev->param.markNANDBlockBad(dev, i);
+				bi->blockState = YAFFS_BLOCK_STATE_DEAD;
+			}
+		}
+	}
+
+	dev->blocksInCheckpoint = 0;
+
+	return 1;
+}
+
+
+static void yaffs_CheckpointFindNextErasedBlock(yaffs_Device *dev)
+{
+	int  i;
+	int blocksAvailable = dev->nErasedBlocks - dev->param.nReservedBlocks;
+	T(YAFFS_TRACE_CHECKPOINT,
+		(TSTR("allocating checkpt block: erased %d reserved %d avail %d next %d "TENDSTR),
+		dev->nErasedBlocks, dev->param.nReservedBlocks, blocksAvailable, dev->checkpointNextBlock));
+
+	if (dev->checkpointNextBlock >= 0 &&
+			dev->checkpointNextBlock <= dev->internalEndBlock &&
+			blocksAvailable > 0) {
+
+		for (i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++) {
+			yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, i);
+			if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) {
+				dev->checkpointNextBlock = i + 1;
+				dev->checkpointCurrentBlock = i;
+				T(YAFFS_TRACE_CHECKPOINT, (TSTR("allocating checkpt block %d"TENDSTR), i));
+				return;
+			}
+		}
+	}
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("out of checkpt blocks"TENDSTR)));
+
+	dev->checkpointNextBlock = -1;
+	dev->checkpointCurrentBlock = -1;
+}
+
+static void yaffs_CheckpointFindNextCheckpointBlock(yaffs_Device *dev)
+{
+	int  i;
+	yaffs_ExtendedTags tags;
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("find next checkpt block: start:  blocks %d next %d" TENDSTR),
+		dev->blocksInCheckpoint, dev->checkpointNextBlock));
+
+	if (dev->blocksInCheckpoint < dev->checkpointMaxBlocks)
+		for (i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++) {
+			int chunk = i * dev->param.nChunksPerBlock;
+			int realignedChunk = chunk - dev->chunkOffset;
+
+			dev->param.readChunkWithTagsFromNAND(dev, realignedChunk,
+					NULL, &tags);
+			T(YAFFS_TRACE_CHECKPOINT, (TSTR("find next checkpt block: search: block %d oid %d seq %d eccr %d" TENDSTR),
+				i, tags.objectId, tags.sequenceNumber, tags.eccResult));
+
+			if (tags.sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA) {
+				/* Right kind of block */
+				dev->checkpointNextBlock = tags.objectId;
+				dev->checkpointCurrentBlock = i;
+				dev->checkpointBlockList[dev->blocksInCheckpoint] = i;
+				dev->blocksInCheckpoint++;
+				T(YAFFS_TRACE_CHECKPOINT, (TSTR("found checkpt block %d"TENDSTR), i));
+				return;
+			}
+		}
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("found no more checkpt blocks"TENDSTR)));
+
+	dev->checkpointNextBlock = -1;
+	dev->checkpointCurrentBlock = -1;
+}
+
+
+int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting)
+{
+
+
+	dev->checkpointOpenForWrite = forWriting;
+
+	/* Got the functions we need? */
+	if (!dev->param.writeChunkWithTagsToNAND ||
+		!dev->param.readChunkWithTagsFromNAND ||
+		!dev->param.eraseBlockInNAND ||
+		!dev->param.markNANDBlockBad)
+		return 0;
+
+	if (forWriting && !yaffs_CheckpointSpaceOk(dev))
+		return 0;
+
+	if (!dev->checkpointBuffer)
+		dev->checkpointBuffer = YMALLOC_DMA(dev->param.totalBytesPerChunk);
+	if (!dev->checkpointBuffer)
+		return 0;
+
+
+	dev->checkpointPageSequence = 0;
+	dev->checkpointByteCount = 0;
+	dev->checkpointSum = 0;
+	dev->checkpointXor = 0;
+	dev->checkpointCurrentBlock = -1;
+	dev->checkpointCurrentChunk = -1;
+	dev->checkpointNextBlock = dev->internalStartBlock;
+
+	/* Erase all the blocks in the checkpoint area */
+	if (forWriting) {
+		memset(dev->checkpointBuffer, 0, dev->nDataBytesPerChunk);
+		dev->checkpointByteOffset = 0;
+		return yaffs_CheckpointErase(dev);
+	} else {
+		int i;
+		/* Set to a value that will kick off a read */
+		dev->checkpointByteOffset = dev->nDataBytesPerChunk;
+		/* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully)
+		 * going to be way more than we need */
+		dev->blocksInCheckpoint = 0;
+		dev->checkpointMaxBlocks = (dev->internalEndBlock - dev->internalStartBlock)/16 + 2;
+		dev->checkpointBlockList = YMALLOC(sizeof(int) * dev->checkpointMaxBlocks);
+		if(!dev->checkpointBlockList)
+			return 0;
+
+		for (i = 0; i < dev->checkpointMaxBlocks; i++)
+			dev->checkpointBlockList[i] = -1;
+	}
+
+	return 1;
+}
+
+int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum)
+{
+	__u32 compositeSum;
+	compositeSum =  (dev->checkpointSum << 8) | (dev->checkpointXor & 0xFF);
+	*sum = compositeSum;
+	return 1;
+}
+
+static int yaffs_CheckpointFlushBuffer(yaffs_Device *dev)
+{
+	int chunk;
+	int realignedChunk;
+
+	yaffs_ExtendedTags tags;
+
+	if (dev->checkpointCurrentBlock < 0) {
+		yaffs_CheckpointFindNextErasedBlock(dev);
+		dev->checkpointCurrentChunk = 0;
+	}
+
+	if (dev->checkpointCurrentBlock < 0)
+		return 0;
+
+	tags.chunkDeleted = 0;
+	tags.objectId = dev->checkpointNextBlock; /* Hint to next place to look */
+	tags.chunkId = dev->checkpointPageSequence + 1;
+	tags.sequenceNumber =  YAFFS_SEQUENCE_CHECKPOINT_DATA;
+	tags.byteCount = dev->nDataBytesPerChunk;
+	if (dev->checkpointCurrentChunk == 0) {
+		/* First chunk we write for the block? Set block state to
+		   checkpoint */
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, dev->checkpointCurrentBlock);
+		bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
+		dev->blocksInCheckpoint++;
+	}
+
+	chunk = dev->checkpointCurrentBlock * dev->param.nChunksPerBlock + dev->checkpointCurrentChunk;
+
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR),
+		chunk, dev->checkpointCurrentBlock, dev->checkpointCurrentChunk, tags.objectId, tags.chunkId));
+
+	realignedChunk = chunk - dev->chunkOffset;
+
+	dev->nPageWrites++;
+
+	dev->param.writeChunkWithTagsToNAND(dev, realignedChunk,
+			dev->checkpointBuffer, &tags);
+	dev->checkpointByteOffset = 0;
+	dev->checkpointPageSequence++;
+	dev->checkpointCurrentChunk++;
+	if (dev->checkpointCurrentChunk >= dev->param.nChunksPerBlock) {
+		dev->checkpointCurrentChunk = 0;
+		dev->checkpointCurrentBlock = -1;
+	}
+	memset(dev->checkpointBuffer, 0, dev->nDataBytesPerChunk);
+
+	return 1;
+}
+
+
+int yaffs_CheckpointWrite(yaffs_Device *dev, const void *data, int nBytes)
+{
+	int i = 0;
+	int ok = 1;
+
+
+	__u8 * dataBytes = (__u8 *)data;
+
+
+
+	if (!dev->checkpointBuffer)
+		return 0;
+
+	if (!dev->checkpointOpenForWrite)
+		return -1;
+
+	while (i < nBytes && ok) {
+		dev->checkpointBuffer[dev->checkpointByteOffset] = *dataBytes;
+		dev->checkpointSum += *dataBytes;
+		dev->checkpointXor ^= *dataBytes;
+
+		dev->checkpointByteOffset++;
+		i++;
+		dataBytes++;
+		dev->checkpointByteCount++;
+
+
+		if (dev->checkpointByteOffset < 0 ||
+		   dev->checkpointByteOffset >= dev->nDataBytesPerChunk)
+			ok = yaffs_CheckpointFlushBuffer(dev);
+	}
+
+	return i;
+}
+
+int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes)
+{
+	int i = 0;
+	int ok = 1;
+	yaffs_ExtendedTags tags;
+
+
+	int chunk;
+	int realignedChunk;
+
+	__u8 *dataBytes = (__u8 *)data;
+
+	if (!dev->checkpointBuffer)
+		return 0;
+
+	if (dev->checkpointOpenForWrite)
+		return -1;
+
+	while (i < nBytes && ok) {
+
+
+		if (dev->checkpointByteOffset < 0 ||
+			dev->checkpointByteOffset >= dev->nDataBytesPerChunk) {
+
+			if (dev->checkpointCurrentBlock < 0) {
+				yaffs_CheckpointFindNextCheckpointBlock(dev);
+				dev->checkpointCurrentChunk = 0;
+			}
+
+			if (dev->checkpointCurrentBlock < 0)
+				ok = 0;
+			else {
+				chunk = dev->checkpointCurrentBlock *
+					dev->param.nChunksPerBlock +
+					dev->checkpointCurrentChunk;
+
+				realignedChunk = chunk - dev->chunkOffset;
+				
+				dev->nPageReads++;
+
+				/* read in the next chunk */
+				/* printf("read checkpoint page %d\n",dev->checkpointPage); */
+				dev->param.readChunkWithTagsFromNAND(dev,
+						realignedChunk,
+						dev->checkpointBuffer,
+						&tags);
+
+				if (tags.chunkId != (dev->checkpointPageSequence + 1) ||
+					tags.eccResult > YAFFS_ECC_RESULT_FIXED ||
+					tags.sequenceNumber != YAFFS_SEQUENCE_CHECKPOINT_DATA)
+					ok = 0;
+
+				dev->checkpointByteOffset = 0;
+				dev->checkpointPageSequence++;
+				dev->checkpointCurrentChunk++;
+
+				if (dev->checkpointCurrentChunk >= dev->param.nChunksPerBlock)
+					dev->checkpointCurrentBlock = -1;
+			}
+		}
+
+		if (ok) {
+			*dataBytes = dev->checkpointBuffer[dev->checkpointByteOffset];
+			dev->checkpointSum += *dataBytes;
+			dev->checkpointXor ^= *dataBytes;
+			dev->checkpointByteOffset++;
+			i++;
+			dataBytes++;
+			dev->checkpointByteCount++;
+		}
+	}
+
+	return 	i;
+}
+
+int yaffs_CheckpointClose(yaffs_Device *dev)
+{
+
+	if (dev->checkpointOpenForWrite) {
+		if (dev->checkpointByteOffset != 0)
+			yaffs_CheckpointFlushBuffer(dev);
+	} else if(dev->checkpointBlockList){
+		int i;
+		for (i = 0; i < dev->blocksInCheckpoint && dev->checkpointBlockList[i] >= 0; i++) {
+			int blk = dev->checkpointBlockList[i];
+			yaffs_BlockInfo *bi = NULL;
+			if( dev->internalStartBlock <= blk && blk <= dev->internalEndBlock)
+				bi = yaffs_GetBlockInfo(dev, blk);
+			if (bi && bi->blockState == YAFFS_BLOCK_STATE_EMPTY)
+				bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
+			else {
+				/* Todo this looks odd... */
+			}
+		}
+		YFREE(dev->checkpointBlockList);
+		dev->checkpointBlockList = NULL;
+	}
+
+	dev->nFreeChunks -= dev->blocksInCheckpoint * dev->param.nChunksPerBlock;
+	dev->nErasedBlocks -= dev->blocksInCheckpoint;
+
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint byte count %d" TENDSTR),
+			dev->checkpointByteCount));
+
+	if (dev->checkpointBuffer) {
+		/* free the buffer */
+		YFREE(dev->checkpointBuffer);
+		dev->checkpointBuffer = NULL;
+		return 1;
+	} else
+		return 0;
+}
+
+int yaffs_CheckpointInvalidateStream(yaffs_Device *dev)
+{
+	/* Erase the checkpoint data */
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint invalidate of %d blocks"TENDSTR),
+		dev->blocksInCheckpoint));
+
+	return yaffs_CheckpointErase(dev);
+}
+
+
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_checkptrw.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_checkptrw.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_checkptrw.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_checkptrw.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,35 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_CHECKPTRW_H__
+#define __YAFFS_CHECKPTRW_H__
+
+#include "yaffs_guts.h"
+
+int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting);
+
+int yaffs_CheckpointWrite(yaffs_Device *dev, const void *data, int nBytes);
+
+int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes);
+
+int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum);
+
+int yaffs_CheckpointClose(yaffs_Device *dev);
+
+int yaffs_CheckpointInvalidateStream(yaffs_Device *dev);
+
+
+#endif
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_ecc.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_ecc.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_ecc.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_ecc.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,326 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This code implements the ECC algorithm used in SmartMedia.
+ *
+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
+ * The two unused bit are set to 1.
+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
+ * blocks are used on a 512-byte NAND page.
+ *
+ */
+
+/* Table generated by gen-ecc.c
+ * Using a table means we do not have to calculate p1..p4 and p1'..p4'
+ * for each byte of data. These are instead provided in a table in bits7..2.
+ * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore
+ * this bytes influence on the line parity.
+ */
+
+const char *yaffs_ecc_c_version =
+	"$Id: yaffs_ecc.c,v 1.11 2009/03/06 17:20:50 wookey Exp $";
+
+#include "yportenv.h"
+
+#include "yaffs_ecc.h"
+
+static const unsigned char column_parity_table[] = {
+	0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
+	0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
+	0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc,
+	0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95,
+	0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0,
+	0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99,
+	0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65,
+	0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c,
+	0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc,
+	0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5,
+	0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59,
+	0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30,
+	0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55,
+	0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c,
+	0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0,
+	0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9,
+	0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0,
+	0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9,
+	0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55,
+	0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c,
+	0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59,
+	0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30,
+	0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc,
+	0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5,
+	0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65,
+	0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c,
+	0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0,
+	0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99,
+	0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc,
+	0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95,
+	0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
+	0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
+};
+
+/* Count the bits in an unsigned char or a U32 */
+
+static int yaffs_CountBits(unsigned char x)
+{
+	int r = 0;
+	while (x) {
+		if (x & 1)
+			r++;
+		x >>= 1;
+	}
+	return r;
+}
+
+static int yaffs_CountBits32(unsigned x)
+{
+	int r = 0;
+	while (x) {
+		if (x & 1)
+			r++;
+		x >>= 1;
+	}
+	return r;
+}
+
+/* Calculate the ECC for a 256-byte block of data */
+void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc)
+{
+	unsigned int i;
+
+	unsigned char col_parity = 0;
+	unsigned char line_parity = 0;
+	unsigned char line_parity_prime = 0;
+	unsigned char t;
+	unsigned char b;
+
+	for (i = 0; i < 256; i++) {
+		b = column_parity_table[*data++];
+		col_parity ^= b;
+
+		if (b & 0x01) {		/* odd number of bits in the byte */
+			line_parity ^= i;
+			line_parity_prime ^= ~i;
+		}
+	}
+
+	ecc[2] = (~col_parity) | 0x03;
+
+	t = 0;
+	if (line_parity & 0x80)
+		t |= 0x80;
+	if (line_parity_prime & 0x80)
+		t |= 0x40;
+	if (line_parity & 0x40)
+		t |= 0x20;
+	if (line_parity_prime & 0x40)
+		t |= 0x10;
+	if (line_parity & 0x20)
+		t |= 0x08;
+	if (line_parity_prime & 0x20)
+		t |= 0x04;
+	if (line_parity & 0x10)
+		t |= 0x02;
+	if (line_parity_prime & 0x10)
+		t |= 0x01;
+	ecc[1] = ~t;
+
+	t = 0;
+	if (line_parity & 0x08)
+		t |= 0x80;
+	if (line_parity_prime & 0x08)
+		t |= 0x40;
+	if (line_parity & 0x04)
+		t |= 0x20;
+	if (line_parity_prime & 0x04)
+		t |= 0x10;
+	if (line_parity & 0x02)
+		t |= 0x08;
+	if (line_parity_prime & 0x02)
+		t |= 0x04;
+	if (line_parity & 0x01)
+		t |= 0x02;
+	if (line_parity_prime & 0x01)
+		t |= 0x01;
+	ecc[0] = ~t;
+
+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
+	/* Swap the bytes into the wrong order */
+	t = ecc[0];
+	ecc[0] = ecc[1];
+	ecc[1] = t;
+#endif
+}
+
+
+/* Correct the ECC on a 256 byte block of data */
+
+int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
+		     const unsigned char *test_ecc)
+{
+	unsigned char d0, d1, d2;	/* deltas */
+
+	d0 = read_ecc[0] ^ test_ecc[0];
+	d1 = read_ecc[1] ^ test_ecc[1];
+	d2 = read_ecc[2] ^ test_ecc[2];
+
+	if ((d0 | d1 | d2) == 0)
+		return 0; /* no error */
+
+	if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 &&
+	    ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 &&
+	    ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) {
+		/* Single bit (recoverable) error in data */
+
+		unsigned byte;
+		unsigned bit;
+
+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
+		/* swap the bytes to correct for the wrong order */
+		unsigned char t;
+
+		t = d0;
+		d0 = d1;
+		d1 = t;
+#endif
+
+		bit = byte = 0;
+
+		if (d1 & 0x80)
+			byte |= 0x80;
+		if (d1 & 0x20)
+			byte |= 0x40;
+		if (d1 & 0x08)
+			byte |= 0x20;
+		if (d1 & 0x02)
+			byte |= 0x10;
+		if (d0 & 0x80)
+			byte |= 0x08;
+		if (d0 & 0x20)
+			byte |= 0x04;
+		if (d0 & 0x08)
+			byte |= 0x02;
+		if (d0 & 0x02)
+			byte |= 0x01;
+
+		if (d2 & 0x80)
+			bit |= 0x04;
+		if (d2 & 0x20)
+			bit |= 0x02;
+		if (d2 & 0x08)
+			bit |= 0x01;
+
+		data[byte] ^= (1 << bit);
+
+		return 1; /* Corrected the error */
+	}
+
+	if ((yaffs_CountBits(d0) +
+	     yaffs_CountBits(d1) +
+	     yaffs_CountBits(d2)) ==  1) {
+		/* Reccoverable error in ecc */
+
+		read_ecc[0] = test_ecc[0];
+		read_ecc[1] = test_ecc[1];
+		read_ecc[2] = test_ecc[2];
+
+		return 1; /* Corrected the error */
+	}
+
+	/* Unrecoverable error */
+
+	return -1;
+
+}
+
+
+/*
+ * ECCxxxOther does ECC calcs on arbitrary n bytes of data
+ */
+void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
+				yaffs_ECCOther *eccOther)
+{
+	unsigned int i;
+
+	unsigned char col_parity = 0;
+	unsigned line_parity = 0;
+	unsigned line_parity_prime = 0;
+	unsigned char b;
+
+	for (i = 0; i < nBytes; i++) {
+		b = column_parity_table[*data++];
+		col_parity ^= b;
+
+		if (b & 0x01)	 {
+			/* odd number of bits in the byte */
+			line_parity ^= i;
+			line_parity_prime ^= ~i;
+		}
+
+	}
+
+	eccOther->colParity = (col_parity >> 2) & 0x3f;
+	eccOther->lineParity = line_parity;
+	eccOther->lineParityPrime = line_parity_prime;
+}
+
+int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
+			yaffs_ECCOther *read_ecc,
+			const yaffs_ECCOther *test_ecc)
+{
+	unsigned char cDelta;	/* column parity delta */
+	unsigned lDelta;	/* line parity delta */
+	unsigned lDeltaPrime;	/* line parity delta */
+	unsigned bit;
+
+	cDelta = read_ecc->colParity ^ test_ecc->colParity;
+	lDelta = read_ecc->lineParity ^ test_ecc->lineParity;
+	lDeltaPrime = read_ecc->lineParityPrime ^ test_ecc->lineParityPrime;
+
+	if ((cDelta | lDelta | lDeltaPrime) == 0)
+		return 0; /* no error */
+
+	if (lDelta == ~lDeltaPrime &&
+	    (((cDelta ^ (cDelta >> 1)) & 0x15) == 0x15)) {
+		/* Single bit (recoverable) error in data */
+
+		bit = 0;
+
+		if (cDelta & 0x20)
+			bit |= 0x04;
+		if (cDelta & 0x08)
+			bit |= 0x02;
+		if (cDelta & 0x02)
+			bit |= 0x01;
+
+		if (lDelta >= nBytes)
+			return -1;
+
+		data[lDelta] ^= (1 << bit);
+
+		return 1; /* corrected */
+	}
+
+	if ((yaffs_CountBits32(lDelta) + yaffs_CountBits32(lDeltaPrime) +
+			yaffs_CountBits(cDelta)) == 1) {
+		/* Reccoverable error in ecc */
+
+		*read_ecc = *test_ecc;
+		return 1; /* corrected */
+	}
+
+	/* Unrecoverable error */
+
+	return -1;
+}
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_ecc.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_ecc.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_ecc.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_ecc.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,44 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/*
+ * This code implements the ECC algorithm used in SmartMedia.
+ *
+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
+ * The two unused bit are set to 1.
+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
+ * blocks are used on a 512-byte NAND page.
+ *
+ */
+
+#ifndef __YAFFS_ECC_H__
+#define __YAFFS_ECC_H__
+
+typedef struct {
+	unsigned char colParity;
+	unsigned lineParity;
+	unsigned lineParityPrime;
+} yaffs_ECCOther;
+
+void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc);
+int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
+		const unsigned char *test_ecc);
+
+void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
+			yaffs_ECCOther *ecc);
+int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
+			yaffs_ECCOther *read_ecc,
+			const yaffs_ECCOther *test_ecc);
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_fs.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_fs.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_fs.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_fs.c	2011-05-16 22:29:25.000000000 +0800
@@ -0,0 +1,3031 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2009 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ * Acknowledgements:
+ * Luc van OostenRyck for numerous patches.
+ * Nick Bane for numerous patches.
+ * Nick Bane for 2.5/2.6 integration.
+ * Andras Toth for mknod rdev issue.
+ * Michael Fischer for finding the problem with inode inconsistency.
+ * Some code bodily lifted from JFFS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ *
+ * This is the file system front-end to YAFFS that hooks it up to
+ * the VFS.
+ *
+ * Special notes:
+ * >> 2.4: sb->u.generic_sbp points to the yaffs_Device associated with
+ *         this superblock
+ * >> 2.6: sb->s_fs_info  points to the yaffs_Device associated with this
+ *         superblock
+ * >> inode->u.generic_ip points to the associated yaffs_Object.
+ */
+
+const char *yaffs_fs_c_version =
+    "$Id: yaffs_fs.c,v 1.102 2010/03/15 23:10:33 charles Exp $";
+extern const char *yaffs_guts_c_version;
+
+#include <linux/version.h>
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10))
+#define YAFFS_COMPILE_BACKGROUND
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+#include <linux/config.h>
+#endif
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/smp_lock.h>
+#include <linux/pagemap.h>
+#include <linux/mtd/mtd.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+
+#ifdef YAFFS_COMPILE_BACKGROUND
+#include <linux/kthread.h>
+#include <linux/delay.h>
+#endif
+
+
+#include "asm/div64.h"
+
+
+#define LOCK_TRACE 0
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+
+#include <linux/statfs.h>	/* Added NCB 15-8-2003 */
+#include <linux/statfs.h>
+#define UnlockPage(p) unlock_page(p)
+#define Page_Uptodate(page)	test_bit(PG_uptodate, &(page)->flags)
+
+/* FIXME: use sb->s_id instead ? */
+#define yaffs_devname(sb, buf)	bdevname(sb->s_bdev, buf)
+
+#else
+
+#include <linux/locks.h>
+#define	BDEVNAME_SIZE		0
+#define	yaffs_devname(sb, buf)	kdevname(sb->s_dev)
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0))
+/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */
+#define __user
+#endif
+
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
+#define YPROC_ROOT  (&proc_root)
+#else
+#define YPROC_ROOT  NULL
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+#define WRITE_SIZE_STR "writesize"
+#define WRITE_SIZE(mtd) ((mtd)->writesize)
+#else
+#define WRITE_SIZE_STR "oobblock"
+#define WRITE_SIZE(mtd) ((mtd)->oobblock)
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27))
+#define YAFFS_USE_WRITE_BEGIN_END 1
+#else
+#define YAFFS_USE_WRITE_BEGIN_END 0
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28))
+static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size)
+{
+	uint64_t result = partition_size;
+	do_div(result, block_size);
+	return (uint32_t)result;
+}
+#else
+#define YCALCBLOCKS(s, b) ((s)/(b))
+#endif
+
+#include <linux/uaccess.h>
+
+#include "yportenv.h"
+#include "yaffs_trace.h"
+#include "yaffs_guts.h"
+
+#include "yaffs_linux.h"
+
+#include <linux/mtd/mtd.h>
+#include "yaffs_mtdif.h"
+#include "yaffs_mtdif1.h"
+#include "yaffs_mtdif2.h"
+
+unsigned int yaffs_traceMask = YAFFS_TRACE_BAD_BLOCKS | YAFFS_TRACE_ALWAYS;
+unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS;
+//unsigned int yaffs_auto_checkpoint = 1; //majian change
+unsigned int yaffs_auto_checkpoint = 2;
+
+unsigned int yaffs_gc_control = 1;
+
+/* Module Parameters */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+module_param(yaffs_traceMask, uint, 0644);
+module_param(yaffs_wr_attempts, uint, 0644);
+module_param(yaffs_auto_checkpoint, uint, 0644);
+module_param(yaffs_gc_control, uint, 0644);
+#else
+MODULE_PARM(yaffs_traceMask, "i");
+MODULE_PARM(yaffs_wr_attempts, "i");
+MODULE_PARM(yaffs_auto_checkpoint, "i");
+MODULE_PARM(yaffs_gc_control, "i");
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
+/* use iget and read_inode */
+#define Y_IGET(sb, inum) iget((sb), (inum))
+static void yaffs_read_inode(struct inode *inode);
+
+#else
+/* Call local equivalent */
+#define YAFFS_USE_OWN_IGET
+#define Y_IGET(sb, inum) yaffs_iget((sb), (inum))
+
+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino);
+#endif
+
+/*#define T(x) printk x */
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
+#define yaffs_InodeToObjectLV(iptr) ((iptr)->i_private)
+#else
+#define yaffs_InodeToObjectLV(iptr) ((iptr)->u.generic_ip)
+#endif
+
+#define yaffs_InodeToObject(iptr) ((yaffs_Object *)(yaffs_InodeToObjectLV(iptr)))
+#define yaffs_DentryToObject(dptr) yaffs_InodeToObject((dptr)->d_inode)
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+#define yaffs_SuperToDevice(sb)	((yaffs_Device *)sb->s_fs_info)
+#else
+#define yaffs_SuperToDevice(sb)	((yaffs_Device *)sb->u.generic_sbp)
+#endif
+
+
+#define update_dir_time(dir) do {\
+			(dir)->i_ctime = (dir)->i_mtime = CURRENT_TIME; \
+		} while(0)
+		
+static void yaffs_put_super(struct super_block *sb);
+
+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n,
+				loff_t *pos);
+static ssize_t yaffs_hold_space(struct file *f);
+static void yaffs_release_space(struct file *f);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_file_flush(struct file *file, fl_owner_t id);
+#else
+static int yaffs_file_flush(struct file *file);
+#endif
+
+static int yaffs_sync_object(struct file *file, struct dentry *dentry,
+				int datasync);
+
+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode,
+			struct nameidata *n);
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry,
+					struct nameidata *n);
+#else
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode);
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry);
+#endif
+static int yaffs_link(struct dentry *old_dentry, struct inode *dir,
+			struct dentry *dentry);
+static int yaffs_unlink(struct inode *dir, struct dentry *dentry);
+static int yaffs_symlink(struct inode *dir, struct dentry *dentry,
+			const char *symname);
+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			dev_t dev);
+#else
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			int dev);
+#endif
+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry,
+			struct inode *new_dir, struct dentry *new_dentry);
+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_sync_fs(struct super_block *sb, int wait);
+static void yaffs_write_super(struct super_block *sb);
+#else
+static int yaffs_sync_fs(struct super_block *sb);
+static int yaffs_write_super(struct super_block *sb);
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf);
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf);
+#else
+static int yaffs_statfs(struct super_block *sb, struct statfs *buf);
+#endif
+
+#ifdef YAFFS_HAS_PUT_INODE
+static void yaffs_put_inode(struct inode *inode);
+#endif
+
+static void yaffs_delete_inode(struct inode *);
+static void yaffs_clear_inode(struct inode *);
+
+static int yaffs_readpage(struct file *file, struct page *page);
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_writepage(struct page *page, struct writeback_control *wbc);
+#else
+static int yaffs_writepage(struct page *page);
+#endif
+
+
+#if (YAFFS_USE_WRITE_BEGIN_END != 0)
+static int yaffs_write_begin(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned flags,
+				struct page **pagep, void **fsdata);
+static int yaffs_write_end(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned copied,
+				struct page *pg, void *fsdadata);
+#else
+static int yaffs_prepare_write(struct file *f, struct page *pg,
+				unsigned offset, unsigned to);
+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset,
+				unsigned to);
+
+#endif
+
+static int yaffs_readlink(struct dentry *dentry, char __user *buffer,
+				int buflen);
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd);
+#else
+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd);
+#endif
+
+static struct address_space_operations yaffs_file_address_operations = {
+	.readpage = yaffs_readpage,
+	.writepage = yaffs_writepage,
+#if (YAFFS_USE_WRITE_BEGIN_END > 0)
+	.write_begin = yaffs_write_begin,
+	.write_end = yaffs_write_end,
+#else
+	.prepare_write = yaffs_prepare_write,
+	.commit_write = yaffs_commit_write,
+#endif
+};
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22))
+static const struct file_operations yaffs_file_operations = {
+	.read = do_sync_read,
+	.write = do_sync_write,
+	.aio_read = generic_file_aio_read,
+	.aio_write = generic_file_aio_write,
+	.mmap = generic_file_mmap,
+	.flush = yaffs_file_flush,
+	.fsync = yaffs_sync_object,
+	.splice_read = generic_file_splice_read,
+	.splice_write = generic_file_splice_write,
+	.llseek = generic_file_llseek,
+};
+
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
+
+static const struct file_operations yaffs_file_operations = {
+	.read = do_sync_read,
+	.write = do_sync_write,
+	.aio_read = generic_file_aio_read,
+	.aio_write = generic_file_aio_write,
+	.mmap = generic_file_mmap,
+	.flush = yaffs_file_flush,
+	.fsync = yaffs_sync_object,
+	.sendfile = generic_file_sendfile,
+};
+
+#else
+
+static const struct file_operations yaffs_file_operations = {
+	.read = generic_file_read,
+	.write = generic_file_write,
+	.mmap = generic_file_mmap,
+	.flush = yaffs_file_flush,
+	.fsync = yaffs_sync_object,
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+	.sendfile = generic_file_sendfile,
+#endif
+};
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25))
+static void zero_user_segment(struct page *page, unsigned start, unsigned end)
+{
+	void * kaddr = kmap_atomic(page, KM_USER0);
+	memset(kaddr + start, 0, end - start);
+	kunmap_atomic(kaddr, KM_USER0);
+	flush_dcache_page(page);
+}
+#endif
+
+
+static const struct inode_operations yaffs_file_inode_operations = {
+	.setattr = yaffs_setattr,
+};
+
+static const struct inode_operations yaffs_symlink_inode_operations = {
+	.readlink = yaffs_readlink,
+	.follow_link = yaffs_follow_link,
+	.setattr = yaffs_setattr,
+};
+
+static const struct inode_operations yaffs_dir_inode_operations = {
+	.create = yaffs_create,
+	.lookup = yaffs_lookup,
+	.link = yaffs_link,
+	.unlink = yaffs_unlink,
+	.symlink = yaffs_symlink,
+	.mkdir = yaffs_mkdir,
+	.rmdir = yaffs_unlink,
+	.mknod = yaffs_mknod,
+	.rename = yaffs_rename,
+	.setattr = yaffs_setattr,
+};
+
+static const struct file_operations yaffs_dir_operations = {
+	.read = generic_read_dir,
+	.readdir = yaffs_readdir,
+	.fsync = yaffs_sync_object,
+};
+
+static const struct super_operations yaffs_super_ops = {
+	.statfs = yaffs_statfs,
+
+#ifndef YAFFS_USE_OWN_IGET
+	.read_inode = yaffs_read_inode,
+#endif
+#ifdef YAFFS_HAS_PUT_INODE
+	.put_inode = yaffs_put_inode,
+#endif
+	.put_super = yaffs_put_super,
+	.delete_inode = yaffs_delete_inode,
+	.clear_inode = yaffs_clear_inode,
+	.sync_fs = yaffs_sync_fs,
+	.write_super = yaffs_write_super,
+};
+
+static unsigned yaffs_gc_control_callback(yaffs_Device *dev)
+{
+	return yaffs_gc_control;
+}
+                	                                                                                          	
+static void yaffs_GrossLock(yaffs_Device *dev)
+{
+	T(LOCK_TRACE && YAFFS_TRACE_OS, ("yaffs locking %p\n", current));
+	down(&(yaffs_DeviceToContext(dev)->grossLock));
+	T(LOCK_TRACE && YAFFS_TRACE_OS, ("yaffs locked %p\n", current));
+}
+
+static void yaffs_GrossUnlock(yaffs_Device *dev)
+{
+	T(LOCK_TRACE && YAFFS_TRACE_OS, ("yaffs unlocking %p\n", current));
+	up(&(yaffs_DeviceToContext(dev)->grossLock));
+}
+
+
+/*-----------------------------------------------------------------*/
+/* Directory search context allows us to unlock access to yaffs during
+ * filldir without causing problems with the directory being modified.
+ * This is similar to the tried and tested mechanism used in yaffs direct.
+ *
+ * A search context iterates along a doubly linked list of siblings in the
+ * directory. If the iterating object is deleted then this would corrupt
+ * the list iteration, likely causing a crash. The search context avoids
+ * this by using the removeObjectCallback to move the search context to the
+ * next object before the object is deleted.
+ *
+ * Many readdirs (and thus seach conexts) may be alive simulateously so
+ * each yaffs_Device has a list of these.
+ *
+ * A seach context lives for the duration of a readdir.
+ *
+ * All these functions must be called while yaffs is locked.
+ */
+
+struct yaffs_SearchContext {
+	yaffs_Device *dev;
+	yaffs_Object *dirObj;
+	yaffs_Object *nextReturn;
+	struct ylist_head others;
+};
+
+/*
+ * yaffs_NewSearch() creates a new search context, initialises it and
+ * adds it to the device's search context list.
+ *
+ * Called at start of readdir.
+ */
+static struct yaffs_SearchContext * yaffs_NewSearch(yaffs_Object *dir)
+{
+	yaffs_Device *dev = dir->myDev;
+	struct yaffs_SearchContext *sc = YMALLOC(sizeof(struct yaffs_SearchContext));
+	if(sc){
+		sc->dirObj = dir;
+		sc->dev = dev;
+		if( ylist_empty(&sc->dirObj->variant.directoryVariant.children))
+			sc->nextReturn = NULL;
+		else
+			sc->nextReturn = ylist_entry(
+                                dir->variant.directoryVariant.children.next,
+				yaffs_Object,siblings);
+		YINIT_LIST_HEAD(&sc->others);
+		ylist_add(&sc->others,&(yaffs_DeviceToContext(dev)->searchContexts));
+	}
+	return sc;
+}
+
+/*
+ * yaffs_EndSearch() disposes of a search context and cleans up.
+ */
+static void yaffs_EndSearch(struct yaffs_SearchContext * sc)
+{
+	if(sc){
+		ylist_del(&sc->others);
+		YFREE(sc);
+	}
+}
+
+/*
+ * yaffs_SearchAdvance() moves a search context to the next object.
+ * Called when the search iterates or when an object removal causes
+ * the search context to be moved to the next object.
+ */
+static void yaffs_SearchAdvance(struct yaffs_SearchContext *sc)
+{
+        if(!sc)
+                return;
+
+        if( sc->nextReturn == NULL ||
+                ylist_empty(&sc->dirObj->variant.directoryVariant.children))
+                sc->nextReturn = NULL;
+        else {
+                struct ylist_head *next = sc->nextReturn->siblings.next;
+
+                if( next == &sc->dirObj->variant.directoryVariant.children)
+                        sc->nextReturn = NULL; /* end of list */
+                else
+                        sc->nextReturn = ylist_entry(next,yaffs_Object,siblings);
+        }
+}
+
+/*
+ * yaffs_RemoveObjectCallback() is called when an object is unlinked.
+ * We check open search contexts and advance any which are currently
+ * on the object being iterated.
+ */
+static void yaffs_RemoveObjectCallback(yaffs_Object *obj)
+{
+
+        struct ylist_head *i;
+        struct yaffs_SearchContext *sc;
+        struct ylist_head *search_contexts = &(yaffs_DeviceToContext(obj->myDev)->searchContexts);
+
+
+        /* Iterate through the directory search contexts.
+         * If any are currently on the object being removed, then advance
+         * the search context to the next object to prevent a hanging pointer.
+         */
+         ylist_for_each(i, search_contexts) {
+                if (i) {
+                        sc = ylist_entry(i, struct yaffs_SearchContext,others);
+                        if(sc->nextReturn == obj)
+                                yaffs_SearchAdvance(sc);
+                }
+	}
+
+}
+
+
+/*-----------------------------------------------------------------*/
+
+static int yaffs_readlink(struct dentry *dentry, char __user *buffer,
+			int buflen)
+{
+	unsigned char *alias;
+	int ret;
+
+	yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry));
+
+	yaffs_GrossUnlock(dev);
+
+	if (!alias)
+		return -ENOMEM;
+
+	ret = vfs_readlink(dentry, buffer, buflen, alias);
+	kfree(alias);
+	return ret;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd)
+#else
+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd)
+#endif
+{
+	unsigned char *alias;
+	int ret;
+	yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry));
+
+	yaffs_GrossUnlock(dev);
+
+	if (!alias) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = vfs_follow_link(nd, alias);
+	kfree(alias);
+out:
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+	return ERR_PTR(ret);
+#else
+	return ret;
+#endif
+}
+
+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev,
+				yaffs_Object *obj);
+
+/*
+ * Lookup is used to find objects in the fs
+ */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry,
+				struct nameidata *n)
+#else
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry)
+#endif
+{
+	yaffs_Object *obj;
+	struct inode *inode = NULL;	/* NCB 2.5/2.6 needs NULL here */
+
+	yaffs_Device *dev = yaffs_InodeToObject(dir)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_lookup for %d:%s\n",
+		yaffs_InodeToObject(dir)->objectId, dentry->d_name.name));
+
+	obj = yaffs_FindObjectByName(yaffs_InodeToObject(dir),
+					dentry->d_name.name);
+
+	obj = yaffs_GetEquivalentObject(obj);	/* in case it was a hardlink */
+
+	/* Can't hold gross lock when calling yaffs_get_inode() */
+	yaffs_GrossUnlock(dev);
+
+	if (obj) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_lookup found %d\n", obj->objectId));
+
+		inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj);
+
+		if (inode) {
+			T(YAFFS_TRACE_OS,
+				("yaffs_loookup dentry \n"));
+/* #if 0 asserted by NCB for 2.5/6 compatability - falls through to
+ * d_add even if NULL inode */
+#if 0
+			/*dget(dentry); // try to solve directory bug */
+			d_add(dentry, inode);
+
+			/* return dentry; */
+			return NULL;
+#endif
+		}
+
+	} else {
+		T(YAFFS_TRACE_OS, ("yaffs_lookup not found\n"));
+
+	}
+
+/* added NCB for 2.5/6 compatability - forces add even if inode is
+ * NULL which creates dentry hash */
+	d_add(dentry, inode);
+
+	return NULL;
+}
+
+
+#ifdef YAFFS_HAS_PUT_INODE
+
+/* For now put inode is just for debugging
+ * Put inode is called when the inode **structure** is put.
+ */
+static void yaffs_put_inode(struct inode *inode)
+{
+	T(YAFFS_TRACE_OS,
+		("yaffs_put_inode: ino %d, count %d\n", (int)inode->i_ino,
+		atomic_read(&inode->i_count)));
+
+}
+#endif
+
+/* clear is called to tell the fs to release any per-inode data it holds */
+static void yaffs_clear_inode(struct inode *inode)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+	obj = yaffs_InodeToObject(inode);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_clear_inode: ino %d, count %d %s\n", (int)inode->i_ino,
+		atomic_read(&inode->i_count),
+		obj ? "object exists" : "null object"));
+
+	if (obj) {
+		dev = obj->myDev;
+		yaffs_GrossLock(dev);
+
+		/* Clear the association between the inode and
+		 * the yaffs_Object.
+		 */
+		obj->myInode = NULL;
+		yaffs_InodeToObjectLV(inode) = NULL;
+
+		/* If the object freeing was deferred, then the real
+		 * free happens now.
+		 * This should fix the inode inconsistency problem.
+		 */
+
+		yaffs_HandleDeferedFree(obj);
+
+		yaffs_GrossUnlock(dev);
+	}
+
+}
+
+/* delete is called when the link count is zero and the inode
+ * is put (ie. nobody wants to know about it anymore, time to
+ * delete the file).
+ * NB Must call clear_inode()
+ */
+static void yaffs_delete_inode(struct inode *inode)
+{
+	yaffs_Object *obj = yaffs_InodeToObject(inode);
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_delete_inode: ino %d, count %d %s\n", (int)inode->i_ino,
+		atomic_read(&inode->i_count),
+		obj ? "object exists" : "null object"));
+
+	if (obj) {
+		dev = obj->myDev;
+		yaffs_GrossLock(dev);
+		yaffs_DeleteObject(obj);
+		yaffs_GrossUnlock(dev);
+	}
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+	truncate_inode_pages(&inode->i_data, 0);
+#endif
+	clear_inode(inode);
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_file_flush(struct file *file, fl_owner_t id)
+#else
+static int yaffs_file_flush(struct file *file)
+#endif
+{
+	yaffs_Object *obj = yaffs_DentryToObject(file->f_dentry);
+
+	yaffs_Device *dev = obj->myDev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_file_flush object %d (%s)\n", obj->objectId,
+		obj->dirty ? "dirty" : "clean"));
+
+	yaffs_GrossLock(dev);
+
+	yaffs_FlushFile(obj, 1, 0);
+
+	yaffs_GrossUnlock(dev);
+
+	return 0;
+}
+
+static int yaffs_readpage_nolock(struct file *f, struct page *pg)
+{
+	/* Lifted from jffs2 */
+
+	yaffs_Object *obj;
+	unsigned char *pg_buf;
+	int ret;
+
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS, ("yaffs_readpage_nolock at %08x, size %08x\n",
+			(unsigned)(pg->index << PAGE_CACHE_SHIFT),
+			(unsigned)PAGE_CACHE_SIZE));
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+	BUG_ON(!PageLocked(pg));
+#else
+	if (!PageLocked(pg))
+		PAGE_BUG(pg);
+#endif
+
+	pg_buf = kmap(pg);
+	/* FIXME: Can kmap fail? */
+
+	yaffs_GrossLock(dev);
+
+	ret = yaffs_ReadDataFromFile(obj, pg_buf,
+				pg->index << PAGE_CACHE_SHIFT,
+				PAGE_CACHE_SIZE);
+
+	yaffs_GrossUnlock(dev);
+
+	if (ret >= 0)
+		ret = 0;
+
+	if (ret) {
+		ClearPageUptodate(pg);
+		SetPageError(pg);
+	} else {
+		SetPageUptodate(pg);
+		ClearPageError(pg);
+	}
+
+	flush_dcache_page(pg);
+	kunmap(pg);
+
+	T(YAFFS_TRACE_OS, ("yaffs_readpage_nolock done\n"));
+	return ret;
+}
+
+static int yaffs_readpage_unlock(struct file *f, struct page *pg)
+{
+	int ret = yaffs_readpage_nolock(f, pg);
+	UnlockPage(pg);
+	return ret;
+}
+
+static int yaffs_readpage(struct file *f, struct page *pg)
+{
+	int ret;
+
+	T(YAFFS_TRACE_OS, ("yaffs_readpage\n"));
+	ret=yaffs_readpage_unlock(f, pg);
+	T(YAFFS_TRACE_OS, ("yaffs_readpage done\n"));
+	return ret;
+}
+
+/* writepage inspired by/stolen from smbfs */
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_writepage(struct page *page, struct writeback_control *wbc)
+#else
+static int yaffs_writepage(struct page *page)
+#endif
+{
+	struct address_space *mapping = page->mapping;
+	struct inode *inode;
+	unsigned long end_index;
+	char *buffer;
+	yaffs_Object *obj;
+	int nWritten = 0;
+	unsigned nBytes;
+	loff_t i_size;
+
+	if (!mapping)
+		BUG();
+	inode = mapping->host;
+	if (!inode)
+		BUG();
+	i_size = i_size_read(inode);
+
+	end_index = i_size >> PAGE_CACHE_SHIFT;
+
+	if(page->index < end_index)
+		nBytes = PAGE_CACHE_SIZE;
+	else {
+		nBytes = i_size & (PAGE_CACHE_SIZE -1);
+
+		if (page->index > end_index || !nBytes) {
+			T(YAFFS_TRACE_OS,
+				("yaffs_writepage at %08x, inode size = %08x!!!\n",
+				(unsigned)(page->index << PAGE_CACHE_SHIFT),
+				(unsigned)inode->i_size));
+			T(YAFFS_TRACE_OS,
+				("                -> don't care!!\n"));
+
+			zero_user_segment(page,0,PAGE_CACHE_SIZE);
+			set_page_writeback(page);
+			unlock_page(page);
+			end_page_writeback(page);
+			return 0;
+		}
+	}
+
+	if(nBytes != PAGE_CACHE_SIZE)
+		zero_user_segment(page,nBytes,PAGE_CACHE_SIZE);
+
+	get_page(page);
+
+	buffer = kmap(page);
+
+	obj = yaffs_InodeToObject(inode);
+	yaffs_GrossLock(obj->myDev);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_writepage at %08x, size %08x\n",
+		(unsigned)(page->index << PAGE_CACHE_SHIFT), nBytes));
+	T(YAFFS_TRACE_OS,
+		("writepag0: obj = %05x, ino = %05x\n",
+		(int)obj->variant.fileVariant.fileSize, (int)inode->i_size));
+
+	nWritten = yaffs_WriteDataToFile(obj, buffer,
+			page->index << PAGE_CACHE_SHIFT, nBytes, 0);
+
+	T(YAFFS_TRACE_OS,
+		("writepag1: obj = %05x, ino = %05x\n",
+		(int)obj->variant.fileVariant.fileSize, (int)inode->i_size));
+
+	yaffs_GrossUnlock(obj->myDev);
+
+	kunmap(page);
+	set_page_writeback(page);
+	unlock_page(page);
+	end_page_writeback(page);
+	put_page(page);
+
+	return (nWritten == nBytes) ? 0 : -ENOSPC;
+}
+
+
+#if (YAFFS_USE_WRITE_BEGIN_END > 0)
+static int yaffs_write_begin(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned flags,
+				struct page **pagep, void **fsdata)
+{
+	struct page *pg = NULL;
+	pgoff_t index = pos >> PAGE_CACHE_SHIFT;
+
+	int ret = 0;
+	int space_held = 0;
+
+	/* Get a page */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
+	pg = grab_cache_page_write_begin(mapping, index, flags);
+#else
+	pg = __grab_cache_page(mapping, index);
+#endif
+
+	*pagep = pg;
+	if (!pg) {
+		ret =  -ENOMEM;
+		goto out;
+	}
+	T(YAFFS_TRACE_OS, ("start yaffs_write_begin index %d(%x) uptodate %d\n",(int)index,(int)index,Page_Uptodate(pg) ? 1 : 0));
+
+	/* Get fs space */
+	space_held = yaffs_hold_space(filp);
+
+	if (!space_held) {
+		ret = -ENOSPC;
+		goto out;
+	}
+
+	/* Update page if required */
+
+	if (!Page_Uptodate(pg))
+		ret = yaffs_readpage_nolock(filp, pg);
+
+	if (ret)
+		goto out;
+
+	/* Happy path return */
+	T(YAFFS_TRACE_OS, ("end yaffs_write_begin - ok\n"));
+
+	return 0;
+
+out:
+	T(YAFFS_TRACE_OS, ("end yaffs_write_begin fail returning %d\n", ret));
+	if (space_held)
+		yaffs_release_space(filp);
+	if (pg) {
+		unlock_page(pg);
+		page_cache_release(pg);
+	}
+	return ret;
+}
+
+#else
+
+static int yaffs_prepare_write(struct file *f, struct page *pg,
+				unsigned offset, unsigned to)
+{
+	T(YAFFS_TRACE_OS, ("yaffs_prepair_write\n"));
+
+	if (!Page_Uptodate(pg))
+		return yaffs_readpage_nolock(f, pg);
+	return 0;
+}
+#endif
+
+#if (YAFFS_USE_WRITE_BEGIN_END > 0)
+static int yaffs_write_end(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned copied,
+				struct page *pg, void *fsdadata)
+{
+	int ret = 0;
+	void *addr, *kva;
+	uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE - 1);
+
+	kva = kmap(pg);
+	addr = kva + offset_into_page;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_write_end addr %x pos %x nBytes %d\n",
+		(unsigned) addr,
+		(int)pos, copied));
+
+	ret = yaffs_file_write(filp, addr, copied, &pos);
+
+	if (ret != copied) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_write_end not same size ret %d  copied %d\n",
+			ret, copied));
+		SetPageError(pg);
+	} else {
+		/* Nothing */
+	}
+
+	kunmap(pg);
+
+	yaffs_release_space(filp);
+	unlock_page(pg);
+	page_cache_release(pg);
+	return ret;
+}
+#else
+
+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset,
+				unsigned to)
+{
+	void *addr, *kva;
+
+	loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset;
+	int nBytes = to - offset;
+	int nWritten;
+
+	unsigned spos = pos;
+	unsigned saddr;
+
+	kva = kmap(pg);
+	addr = kva + offset;
+
+	saddr = (unsigned) addr;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_commit_write addr %x pos %x nBytes %d\n",
+		saddr, spos, nBytes));
+
+	nWritten = yaffs_file_write(f, addr, nBytes, &pos);
+
+	if (nWritten != nBytes) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_commit_write not same size nWritten %d  nBytes %d\n",
+			nWritten, nBytes));
+		SetPageError(pg);
+	} else {
+		/* Nothing */
+	}
+
+	kunmap(pg);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_commit_write returning %d\n",
+		nWritten == nBytes ? 0 : nWritten));
+
+	return nWritten == nBytes ? 0 : nWritten;
+}
+#endif
+
+
+static void yaffs_FillInodeFromObject(struct inode *inode, yaffs_Object *obj)
+{
+	if (inode && obj) {
+
+
+		/* Check mode against the variant type and attempt to repair if broken. */
+		__u32 mode = obj->yst_mode;
+		switch (obj->variantType) {
+		case YAFFS_OBJECT_TYPE_FILE:
+			if (!S_ISREG(mode)) {
+				obj->yst_mode &= ~S_IFMT;
+				obj->yst_mode |= S_IFREG;
+			}
+
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			if (!S_ISLNK(mode)) {
+				obj->yst_mode &= ~S_IFMT;
+				obj->yst_mode |= S_IFLNK;
+			}
+
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			if (!S_ISDIR(mode)) {
+				obj->yst_mode &= ~S_IFMT;
+				obj->yst_mode |= S_IFDIR;
+			}
+
+			break;
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+		default:
+			/* TODO? */
+			break;
+		}
+
+		inode->i_flags |= S_NOATIME;
+
+		inode->i_ino = obj->objectId;
+		inode->i_mode = obj->yst_mode;
+		inode->i_uid = obj->yst_uid;
+		inode->i_gid = obj->yst_gid;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+		inode->i_blksize = inode->i_sb->s_blocksize;
+#endif
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+
+		inode->i_rdev = old_decode_dev(obj->yst_rdev);
+		inode->i_atime.tv_sec = (time_t) (obj->yst_atime);
+		inode->i_atime.tv_nsec = 0;
+		inode->i_mtime.tv_sec = (time_t) obj->yst_mtime;
+		inode->i_mtime.tv_nsec = 0;
+		inode->i_ctime.tv_sec = (time_t) obj->yst_ctime;
+		inode->i_ctime.tv_nsec = 0;
+#else
+		inode->i_rdev = obj->yst_rdev;
+		inode->i_atime = obj->yst_atime;
+		inode->i_mtime = obj->yst_mtime;
+		inode->i_ctime = obj->yst_ctime;
+#endif
+		inode->i_size = yaffs_GetObjectFileLength(obj);
+		inode->i_blocks = (inode->i_size + 511) >> 9;
+
+		inode->i_nlink = yaffs_GetObjectLinkCount(obj);
+
+		T(YAFFS_TRACE_OS,
+			("yaffs_FillInode mode %x uid %d gid %d size %d count %d\n",
+			inode->i_mode, inode->i_uid, inode->i_gid,
+			(int)inode->i_size, atomic_read(&inode->i_count)));
+
+		switch (obj->yst_mode & S_IFMT) {
+		default:	/* fifo, device or socket */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+			init_special_inode(inode, obj->yst_mode,
+					old_decode_dev(obj->yst_rdev));
+#else
+			init_special_inode(inode, obj->yst_mode,
+					(dev_t) (obj->yst_rdev));
+#endif
+			break;
+		case S_IFREG:	/* file */
+			inode->i_op = &yaffs_file_inode_operations;
+			inode->i_fop = &yaffs_file_operations;
+			inode->i_mapping->a_ops =
+				&yaffs_file_address_operations;
+			break;
+		case S_IFDIR:	/* directory */
+			inode->i_op = &yaffs_dir_inode_operations;
+			inode->i_fop = &yaffs_dir_operations;
+			break;
+		case S_IFLNK:	/* symlink */
+			inode->i_op = &yaffs_symlink_inode_operations;
+			break;
+		}
+
+		yaffs_InodeToObjectLV(inode) = obj;
+
+		obj->myInode = inode;
+
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_FileInode invalid parameters\n"));
+	}
+
+}
+
+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev,
+				yaffs_Object *obj)
+{
+	struct inode *inode;
+
+	if (!sb) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_get_inode for NULL super_block!!\n"));
+		return NULL;
+
+	}
+
+	if (!obj) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_get_inode for NULL object!!\n"));
+		return NULL;
+
+	}
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_get_inode for object %d\n", obj->objectId));
+
+	inode = Y_IGET(sb, obj->objectId);
+	if (IS_ERR(inode))
+		return NULL;
+
+	/* NB Side effect: iget calls back to yaffs_read_inode(). */
+	/* iget also increments the inode's i_count */
+	/* NB You can't be holding grossLock or deadlock will happen! */
+
+	return inode;
+}
+
+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n,
+				loff_t *pos)
+{
+	yaffs_Object *obj;
+	int nWritten, ipos;
+	struct inode *inode;
+	yaffs_Device *dev;
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	inode = f->f_dentry->d_inode;
+
+	if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND)
+		ipos = inode->i_size;
+	else
+		ipos = *pos;
+
+	if (!obj)
+		T(YAFFS_TRACE_OS,
+			("yaffs_file_write: hey obj is null!\n"));
+	else
+		T(YAFFS_TRACE_OS,
+			("yaffs_file_write about to write writing %u(%x) bytes"
+			"to object %d at %d(%x)\n",
+			(unsigned) n, (unsigned) n, obj->objectId, ipos,ipos));
+
+	nWritten = yaffs_WriteDataToFile(obj, buf, ipos, n, 0);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_file_write: %d(%x) bytes written\n",
+		(unsigned )n,(unsigned)n));
+
+	if (nWritten > 0) {
+		ipos += nWritten;
+		*pos = ipos;
+		if (ipos > inode->i_size) {
+			inode->i_size = ipos;
+			inode->i_blocks = (ipos + 511) >> 9;
+
+			T(YAFFS_TRACE_OS,
+				("yaffs_file_write size updated to %d bytes, "
+				"%d blocks\n",
+				ipos, (int)(inode->i_blocks)));
+		}
+
+	}
+	yaffs_GrossUnlock(dev);
+	return (nWritten == 0) && (n > 0) ? -ENOSPC : nWritten;
+}
+
+/* Space holding and freeing is done to ensure we have space available for write_begin/end */
+/* For now we just assume few parallel writes and check against a small number. */
+/* Todo: need to do this with a counter to handle parallel reads better */
+
+static ssize_t yaffs_hold_space(struct file *f)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+	int nFreeChunks;
+
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	nFreeChunks = yaffs_GetNumberOfFreeChunks(dev);
+
+	yaffs_GrossUnlock(dev);
+
+	return (nFreeChunks > 20) ? 1 : 0;
+}
+
+static void yaffs_release_space(struct file *f)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+
+	yaffs_GrossUnlock(dev);
+}
+
+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+        struct yaffs_SearchContext *sc;
+	struct inode *inode = f->f_dentry->d_inode;
+	unsigned long offset, curoffs;
+	yaffs_Object *l;
+        int retVal = 0;
+
+	char name[YAFFS_MAX_NAME_LENGTH + 1];
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	offset = f->f_pos;
+
+        sc = yaffs_NewSearch(obj);
+        if(!sc){
+                retVal = -ENOMEM;
+                goto unlock_out;
+        }
+
+	T(YAFFS_TRACE_OS, ("yaffs_readdir: starting at %d\n", (int)offset));
+
+	if (offset == 0) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_readdir: entry . ino %d \n",
+			(int)inode->i_ino));
+		yaffs_GrossUnlock(dev);
+		if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) < 0)
+			goto out;
+		yaffs_GrossLock(dev);
+		offset++;
+		f->f_pos++;
+	}
+	if (offset == 1) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_readdir: entry .. ino %d \n",
+			(int)f->f_dentry->d_parent->d_inode->i_ino));
+		yaffs_GrossUnlock(dev);
+		if (filldir(dirent, "..", 2, offset,
+			f->f_dentry->d_parent->d_inode->i_ino, DT_DIR) < 0)
+			goto out;
+		yaffs_GrossLock(dev);
+		offset++;
+		f->f_pos++;
+	}
+
+	curoffs = 1;
+
+	/* If the directory has changed since the open or last call to
+	   readdir, rewind to after the 2 canned entries. */
+
+	if (f->f_version != inode->i_version) {
+		offset = 2;
+		f->f_pos = offset;
+		f->f_version = inode->i_version;
+	}
+
+	while(sc->nextReturn){
+		curoffs++;
+                l = sc->nextReturn;
+		if (curoffs >= offset) {
+                        int this_inode = yaffs_GetObjectInode(l);
+                        int this_type = yaffs_GetObjectType(l);
+
+			yaffs_GetObjectName(l, name,
+					    YAFFS_MAX_NAME_LENGTH + 1);
+			T(YAFFS_TRACE_OS,
+			  ("yaffs_readdir: %s inode %d\n", name,
+			   yaffs_GetObjectInode(l)));
+
+                        yaffs_GrossUnlock(dev);
+
+			if (filldir(dirent,
+					name,
+					strlen(name),
+					offset,
+					this_inode,
+					this_type) < 0)
+				goto out;
+
+                        yaffs_GrossLock(dev);
+
+			offset++;
+			f->f_pos++;
+		}
+                yaffs_SearchAdvance(sc);
+	}
+
+unlock_out:
+	yaffs_GrossUnlock(dev);
+out:
+        yaffs_EndSearch(sc);
+
+	return retVal;
+}
+
+/*
+ * File creation. Allocate an inode, and we're done..
+ */
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)
+#define YCRED(x) x
+#else
+#define YCRED(x) (x->cred)
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			dev_t rdev)
+#else
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			int rdev)
+#endif
+{
+	struct inode *inode;
+
+	yaffs_Object *obj = NULL;
+	yaffs_Device *dev;
+
+	yaffs_Object *parent = yaffs_InodeToObject(dir);
+
+	int error = -ENOSPC;
+	uid_t uid = YCRED(current)->fsuid;
+	gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid;
+
+	if ((dir->i_mode & S_ISGID) && S_ISDIR(mode))
+		mode |= S_ISGID;
+
+	if (parent) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod: parent object %d type %d\n",
+			parent->objectId, parent->variantType));
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod: could not get parent object\n"));
+		return -EPERM;
+	}
+
+	T(YAFFS_TRACE_OS, ("yaffs_mknod: making oject for %s, "
+			"mode %x dev %x\n",
+			dentry->d_name.name, mode, rdev));
+
+	dev = parent->myDev;
+
+	yaffs_GrossLock(dev);
+
+	switch (mode & S_IFMT) {
+	default:
+		/* Special (socket, fifo, device...) */
+		T(YAFFS_TRACE_OS, ("yaffs_mknod: making special\n"));
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+		obj = yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid,
+				gid, old_encode_dev(rdev));
+#else
+		obj = yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid,
+				gid, rdev);
+#endif
+		break;
+	case S_IFREG:		/* file          */
+		T(YAFFS_TRACE_OS, ("yaffs_mknod: making file\n"));
+		obj = yaffs_MknodFile(parent, dentry->d_name.name, mode, uid,
+				gid);
+		break;
+	case S_IFDIR:		/* directory */
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod: making directory\n"));
+		obj = yaffs_MknodDirectory(parent, dentry->d_name.name, mode,
+					uid, gid);
+		break;
+	case S_IFLNK:		/* symlink */
+		T(YAFFS_TRACE_OS, ("yaffs_mknod: making symlink\n"));
+		obj = NULL;	/* Do we ever get here? */
+		break;
+	}
+
+	/* Can not call yaffs_get_inode() with gross lock held */
+	yaffs_GrossUnlock(dev);
+
+	if (obj) {
+		inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj);
+		d_instantiate(dentry, inode);
+		update_dir_time(dir);
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod created object %d count = %d\n",
+			obj->objectId, atomic_read(&inode->i_count)));
+		error = 0;
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod failed making object\n"));
+		error = -ENOMEM;
+	}
+
+	return error;
+}
+
+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
+{
+	int retVal;
+	T(YAFFS_TRACE_OS, ("yaffs_mkdir\n"));
+	retVal = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0);
+	return retVal;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode,
+			struct nameidata *n)
+#else
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode)
+#endif
+{
+	T(YAFFS_TRACE_OS, ("yaffs_create\n"));
+	return yaffs_mknod(dir, dentry, mode | S_IFREG, 0);
+}
+
+static int yaffs_unlink(struct inode *dir, struct dentry *dentry)
+{
+	int retVal;
+
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_unlink %d:%s\n", (int)(dir->i_ino),
+		dentry->d_name.name));
+
+	dev = yaffs_InodeToObject(dir)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	retVal = yaffs_Unlink(yaffs_InodeToObject(dir), dentry->d_name.name);
+
+	if (retVal == YAFFS_OK) {
+		dentry->d_inode->i_nlink--;
+		dir->i_version++;
+		yaffs_GrossUnlock(dev);
+		mark_inode_dirty(dentry->d_inode);
+		update_dir_time(dir);
+		return 0;
+	}
+	yaffs_GrossUnlock(dev);
+	return -ENOTEMPTY;
+}
+
+/*
+ * Create a link...
+ */
+static int yaffs_link(struct dentry *old_dentry, struct inode *dir,
+			struct dentry *dentry)
+{
+	struct inode *inode = old_dentry->d_inode;
+	yaffs_Object *obj = NULL;
+	yaffs_Object *link = NULL;
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS, ("yaffs_link\n"));
+
+	obj = yaffs_InodeToObject(inode);
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	if (!S_ISDIR(inode->i_mode))		/* Don't link directories */
+		link = yaffs_Link(yaffs_InodeToObject(dir), dentry->d_name.name,
+			obj);
+
+	if (link) {
+		old_dentry->d_inode->i_nlink = yaffs_GetObjectLinkCount(obj);
+		d_instantiate(dentry, old_dentry->d_inode);
+		atomic_inc(&old_dentry->d_inode->i_count);
+		T(YAFFS_TRACE_OS,
+			("yaffs_link link count %d i_count %d\n",
+			old_dentry->d_inode->i_nlink,
+			atomic_read(&old_dentry->d_inode->i_count)));
+	}
+
+	yaffs_GrossUnlock(dev);
+
+	if (link){
+		update_dir_time(dir);
+		return 0;
+	}
+
+	return -EPERM;
+}
+
+static int yaffs_symlink(struct inode *dir, struct dentry *dentry,
+				const char *symname)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+	uid_t uid = YCRED(current)->fsuid;
+	gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid;
+
+	T(YAFFS_TRACE_OS, ("yaffs_symlink\n"));
+
+	dev = yaffs_InodeToObject(dir)->myDev;
+	yaffs_GrossLock(dev);
+	obj = yaffs_MknodSymLink(yaffs_InodeToObject(dir), dentry->d_name.name,
+				S_IFLNK | S_IRWXUGO, uid, gid, symname);
+	yaffs_GrossUnlock(dev);
+
+	if (obj) {
+		struct inode *inode;
+
+		inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj);
+		d_instantiate(dentry, inode);
+		update_dir_time(dir);
+		T(YAFFS_TRACE_OS, ("symlink created OK\n"));
+		return 0;
+	} else {
+		T(YAFFS_TRACE_OS, ("symlink not created\n"));
+	}
+
+	return -ENOMEM;
+}
+
+static int yaffs_sync_object(struct file *file, struct dentry *dentry,
+				int datasync)
+{
+
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+	obj = yaffs_DentryToObject(dentry);
+
+	dev = obj->myDev;
+
+	T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, ("yaffs_sync_object\n"));
+	yaffs_GrossLock(dev);
+	yaffs_FlushFile(obj, 1, datasync);
+	yaffs_GrossUnlock(dev);
+	return 0;
+}
+
+/*
+ * The VFS layer already does all the dentry stuff for rename.
+ *
+ * NB: POSIX says you can rename an object over an old object of the same name
+ */
+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry,
+			struct inode *new_dir, struct dentry *new_dentry)
+{
+	yaffs_Device *dev;
+	int retVal = YAFFS_FAIL;
+	yaffs_Object *target;
+
+	T(YAFFS_TRACE_OS, ("yaffs_rename\n"));
+	dev = yaffs_InodeToObject(old_dir)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	/* Check if the target is an existing directory that is not empty. */
+	target = yaffs_FindObjectByName(yaffs_InodeToObject(new_dir),
+				new_dentry->d_name.name);
+
+
+
+	if (target && target->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
+		!ylist_empty(&target->variant.directoryVariant.children)) {
+
+		T(YAFFS_TRACE_OS, ("target is non-empty dir\n"));
+
+		retVal = YAFFS_FAIL;
+	} else {
+		/* Now does unlinking internally using shadowing mechanism */
+		T(YAFFS_TRACE_OS, ("calling yaffs_RenameObject\n"));
+
+		retVal = yaffs_RenameObject(yaffs_InodeToObject(old_dir),
+				old_dentry->d_name.name,
+				yaffs_InodeToObject(new_dir),
+				new_dentry->d_name.name);
+	}
+	yaffs_GrossUnlock(dev);
+
+	if (retVal == YAFFS_OK) {
+		if (target) {
+			new_dentry->d_inode->i_nlink--;
+			mark_inode_dirty(new_dentry->d_inode);
+		}
+		
+		update_dir_time(old_dir);
+		if(old_dir != new_dir)
+			update_dir_time(new_dir);
+		return 0;
+	} else {
+		return -ENOTEMPTY;
+	}
+}
+
+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr)
+{
+	struct inode *inode = dentry->d_inode;
+	int error = 0;
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_setattr of object %d\n",
+		yaffs_InodeToObject(inode)->objectId));
+
+	/* Fail if a requested resize >= 2GB */		
+	if (attr->ia_valid & ATTR_SIZE &&
+		(attr->ia_size >> 31))
+		error = -EINVAL;
+
+	if (error == 0)
+		error = inode_change_ok(inode, attr);
+	if (error == 0) {
+		int result;
+		if (!error){
+			error = inode_setattr(inode, attr);
+			T(YAFFS_TRACE_OS,("inode_setattr called\n"));
+			if (attr->ia_valid & ATTR_SIZE)
+                        	truncate_inode_pages(&inode->i_data,attr->ia_size);
+		}
+		dev = yaffs_InodeToObject(inode)->myDev;
+		if (attr->ia_valid & ATTR_SIZE){
+			T(YAFFS_TRACE_OS,("resize to %d(%x)\n",(int)(attr->ia_size),(int)(attr->ia_size)));
+		}
+		yaffs_GrossLock(dev);
+		result = yaffs_SetAttributes(yaffs_InodeToObject(inode), attr);
+		if(result == YAFFS_OK) {
+			error = 0;
+		} else {
+			error = -EPERM;
+		}
+		yaffs_GrossUnlock(dev);
+
+	}
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_setattr done returning %d\n",error));
+
+	return error;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf)
+{
+	yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
+	struct super_block *sb = dentry->d_sb;
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+#else
+static int yaffs_statfs(struct super_block *sb, struct statfs *buf)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+#endif
+
+	T(YAFFS_TRACE_OS, ("yaffs_statfs\n"));
+
+	yaffs_GrossLock(dev);
+
+	buf->f_type = YAFFS_MAGIC;
+	buf->f_bsize = sb->s_blocksize;
+	buf->f_namelen = 255;
+
+	if (dev->nDataBytesPerChunk & (dev->nDataBytesPerChunk - 1)) {
+		/* Do this if chunk size is not a power of 2 */
+
+		uint64_t bytesInDev;
+		uint64_t bytesFree;
+
+		bytesInDev = ((uint64_t)((dev->param.endBlock - dev->param.startBlock + 1))) *
+			((uint64_t)(dev->param.nChunksPerBlock * dev->nDataBytesPerChunk));
+
+		do_div(bytesInDev, sb->s_blocksize); /* bytesInDev becomes the number of blocks */
+		buf->f_blocks = bytesInDev;
+
+		bytesFree  = ((uint64_t)(yaffs_GetNumberOfFreeChunks(dev))) *
+			((uint64_t)(dev->nDataBytesPerChunk));
+
+		do_div(bytesFree, sb->s_blocksize);
+
+		buf->f_bfree = bytesFree;
+
+	} else if (sb->s_blocksize > dev->nDataBytesPerChunk) {
+
+		buf->f_blocks =
+			(dev->param.endBlock - dev->param.startBlock + 1) *
+			dev->param.nChunksPerBlock /
+			(sb->s_blocksize / dev->nDataBytesPerChunk);
+		buf->f_bfree =
+			yaffs_GetNumberOfFreeChunks(dev) /
+			(sb->s_blocksize / dev->nDataBytesPerChunk);
+	} else {
+		buf->f_blocks =
+			(dev->param.endBlock - dev->param.startBlock + 1) *
+			dev->param.nChunksPerBlock *
+			(dev->nDataBytesPerChunk / sb->s_blocksize);
+
+		buf->f_bfree =
+			yaffs_GetNumberOfFreeChunks(dev) *
+			(dev->nDataBytesPerChunk / sb->s_blocksize);
+	}
+
+	buf->f_files = 0;
+	buf->f_ffree = 0;
+	buf->f_bavail = buf->f_bfree;
+
+	yaffs_GrossUnlock(dev);
+	return 0;
+}
+
+
+
+static void yaffs_FlushInodes(struct super_block *sb)
+{
+	struct inode *iptr;
+	yaffs_Object *obj;
+	
+	list_for_each_entry(iptr,&sb->s_inodes, i_sb_list){
+		obj = yaffs_InodeToObject(iptr);
+		if(obj){
+			T(YAFFS_TRACE_OS, ("flushing obj %d\n",obj->objectId));
+			yaffs_FlushFile(obj,1,0);
+		}
+	}
+}
+
+
+static void yaffs_FlushSuperBlock(struct super_block *sb, int do_checkpoint)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);	
+	if(!dev)
+		return;
+	
+	yaffs_FlushInodes(sb);
+	yaffs_UpdateDirtyDirectories(dev);
+	yaffs_FlushEntireDeviceCache(dev);
+	if(do_checkpoint)
+		yaffs_CheckpointSave(dev);
+}
+
+static int yaffs_do_sync_fs(struct super_block *sb, int do_checkpoint)
+{
+
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+	T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, 
+		("yaffs_do_sync_fs: %s %s\n", 
+		sb->s_dirt ? "dirty" : "clean",
+		do_checkpoint ? "with checkpoint" : "no checkpoint"));
+
+	if (sb->s_dirt) {
+		yaffs_GrossLock(dev);
+		yaffs_FlushSuperBlock(sb,do_checkpoint);
+		yaffs_GrossUnlock(dev);
+
+		sb->s_dirt = 0;
+	}
+	return 0;
+}
+
+/*
+ * yaffs background thread functions .
+ * yaffs_BackgroundThread() the thread function
+ * yaffs_BackgroundStart() launches the background thread.
+ * yaffs_BackgroundStop() cleans up the background thread.
+ *
+ * NB: 
+ * The thread should only run after the yaffs is initialised
+ * The thread should be stopped before yaffs is unmounted.
+ * The thread should not do any writing while the fs is in read only.
+ */
+
+#ifdef YAFFS_COMPILE_BACKGROUND
+static int yaffs_BackgroundThread(void *data)
+{
+	yaffs_Device *dev = (yaffs_Device *)data;
+	struct yaffs_LinuxContext *context = yaffs_DeviceToContext(dev);
+
+	T(YAFFS_TRACE_BACKGROUND,
+		("yaffs_background starting for dev %p\n",
+		(void *)dev));
+	
+	while(context->bgRunning){
+		T(YAFFS_TRACE_BACKGROUND,
+			("yaffs_background\n"));
+
+		if(kthread_should_stop())
+			break;
+		yaffs_GrossLock(dev);
+		yaffs_UpdateDirtyDirectories(dev);
+		yaffs_GrossUnlock(dev);
+		msleep(500);
+	}
+	return 0;
+}
+
+static int yaffs_BackgroundStart(yaffs_Device *dev)
+{
+	int retval = 0;
+
+	struct yaffs_LinuxContext *context = yaffs_DeviceToContext(dev);
+
+	context->bgRunning = 1;
+
+	context->bgThread = kthread_run(yaffs_BackgroundThread,(void *)dev,"yaffs_%x",(unsigned)dev);
+
+	if(IS_ERR(context->bgThread)){
+		retval = PTR_ERR(context->bgThread);
+		context->bgThread = NULL;
+		context->bgRunning = 0;
+	}
+	return retval;
+}
+
+static void yaffs_BackgroundStop(yaffs_Device *dev)
+{
+	struct yaffs_LinuxContext *ctxt = yaffs_DeviceToContext(dev);
+
+	ctxt->bgRunning = 0;
+
+	if( ctxt->bgThread){
+		kthread_stop(ctxt->bgThread);
+		ctxt->bgThread = NULL;
+	}
+}
+#else
+static int yaffs_BackgroundThread(void *data)
+{
+	return 0;
+}
+
+static int yaffs_BackgroundStart(yaffs_Device *dev)
+{
+	return 0;
+}
+
+static void yaffs_BackgroundStop(yaffs_Device *dev)
+{
+}
+#endif
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static void yaffs_write_super(struct super_block *sb)
+#else
+static int yaffs_write_super(struct super_block *sb)
+#endif
+{
+
+	T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, ("yaffs_write_super\n"));
+	yaffs_do_sync_fs(sb, yaffs_auto_checkpoint >= 2);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+	return 0;
+#endif
+}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_sync_fs(struct super_block *sb, int wait)
+#else
+static int yaffs_sync_fs(struct super_block *sb)
+#endif
+{
+	T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, ("yaffs_sync_fs\n"));
+
+	yaffs_do_sync_fs(sb,yaffs_auto_checkpoint >= 1);
+
+	return 0;
+}
+
+#ifdef YAFFS_USE_OWN_IGET
+
+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino)
+{
+	struct inode *inode;
+	yaffs_Object *obj;
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_iget for %lu\n", ino));
+
+	inode = iget_locked(sb, ino);
+	if (!inode)
+		return ERR_PTR(-ENOMEM);
+	if (!(inode->i_state & I_NEW))
+		return inode;
+
+	/* NB This is called as a side effect of other functions, but
+	 * we had to release the lock to prevent deadlocks, so
+	 * need to lock again.
+	 */
+
+	yaffs_GrossLock(dev);
+
+	obj = yaffs_FindObjectByNumber(dev, inode->i_ino);
+
+	yaffs_FillInodeFromObject(inode, obj);
+
+	yaffs_GrossUnlock(dev);
+
+	unlock_new_inode(inode);
+	return inode;
+}
+
+#else
+
+static void yaffs_read_inode(struct inode *inode)
+{
+	/* NB This is called as a side effect of other functions, but
+	 * we had to release the lock to prevent deadlocks, so
+	 * need to lock again.
+	 */
+
+	yaffs_Object *obj;
+	yaffs_Device *dev = yaffs_SuperToDevice(inode->i_sb);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_read_inode for %d\n", (int)inode->i_ino));
+
+	yaffs_GrossLock(dev);
+
+	obj = yaffs_FindObjectByNumber(dev, inode->i_ino);
+
+	yaffs_FillInodeFromObject(inode, obj);
+
+	yaffs_GrossUnlock(dev);
+}
+
+#endif
+
+static YLIST_HEAD(yaffs_context_list);
+struct semaphore yaffs_context_lock;
+
+#if 0 /* not used */
+static int yaffs_remount_fs(struct super_block *sb, int *flags, char *data)
+{
+	yaffs_Device    *dev = yaffs_SuperToDevice(sb);
+
+	if (*flags & MS_RDONLY) {
+		struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice;
+
+		T(YAFFS_TRACE_OS,
+			("yaffs_remount_fs: %s: RO\n", dev->name));
+
+		yaffs_GrossLock(dev);
+
+		yaffs_FlushSuperBlock(sb,1);
+
+		if (mtd->sync)
+			mtd->sync(mtd);
+
+		yaffs_GrossUnlock(dev);
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_remount_fs: %s: RW\n", dev->name));
+	}
+
+	return 0;
+}
+#endif
+
+static void yaffs_put_super(struct super_block *sb)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+
+	T(YAFFS_TRACE_OS, ("yaffs_put_super\n"));
+
+	yaffs_GrossLock(dev);
+
+	yaffs_FlushSuperBlock(sb,1);
+
+	if (yaffs_DeviceToContext(dev)->putSuperFunc)
+		yaffs_DeviceToContext(dev)->putSuperFunc(sb);
+
+	yaffs_BackgroundStop(dev);
+
+	yaffs_Deinitialise(dev);
+
+	yaffs_GrossUnlock(dev);
+
+	down(&yaffs_context_lock);
+	ylist_del_init(&(yaffs_DeviceToContext(dev)->contextList));
+	up(&yaffs_context_lock);
+
+	if (yaffs_DeviceToContext(dev)->spareBuffer) {
+		YFREE(yaffs_DeviceToContext(dev)->spareBuffer);
+		yaffs_DeviceToContext(dev)->spareBuffer = NULL;
+	}
+
+	kfree(dev);
+}
+
+
+static void yaffs_MTDPutSuper(struct super_block *sb)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(yaffs_SuperToDevice(sb))->mtd;
+
+	if (mtd->sync)
+		mtd->sync(mtd);
+
+	put_mtd_device(mtd);
+}
+
+
+static void yaffs_MarkSuperBlockDirty(yaffs_Device *dev)
+{
+	struct super_block *sb = yaffs_DeviceToContext(dev)->superBlock;
+
+	T(YAFFS_TRACE_OS, ("yaffs_MarkSuperBlockDirty() sb = %p\n", sb));
+	if (sb)
+		sb->s_dirt = 1;
+}
+
+typedef struct {
+	int inband_tags;
+	int skip_checkpoint_read;
+	int skip_checkpoint_write;
+	int no_cache;
+	int tags_ecc_on;
+	int tags_ecc_overridden;
+	int lazy_loading_enabled;
+	int lazy_loading_overridden;
+	int empty_lost_and_found;
+	int empty_lost_and_found_overridden;
+} yaffs_options;
+
+#define MAX_OPT_LEN 30
+static int yaffs_parse_options(yaffs_options *options, const char *options_str)
+{
+	char cur_opt[MAX_OPT_LEN + 1];
+	int p;
+	int error = 0;
+
+	/* Parse through the options which is a comma seperated list */
+
+	while (options_str && *options_str && !error) {
+		memset(cur_opt, 0, MAX_OPT_LEN + 1);
+		p = 0;
+
+		while(*options_str == ',')
+			options_str++;
+
+		while (*options_str && *options_str != ',') {
+			if (p < MAX_OPT_LEN) {
+				cur_opt[p] = *options_str;
+				p++;
+			}
+			options_str++;
+		}
+
+		if (!strcmp(cur_opt, "inband-tags"))
+			options->inband_tags = 1;
+		else if (!strcmp(cur_opt, "tags-ecc-off")){
+			options->tags_ecc_on = 0;
+			options->tags_ecc_overridden=1;
+		} else if (!strcmp(cur_opt, "tags-ecc-on")){
+			options->tags_ecc_on = 1;
+			options->tags_ecc_overridden = 1;
+		} else if (!strcmp(cur_opt, "lazy-loading-off")){
+			options->lazy_loading_enabled = 0;
+			options->lazy_loading_overridden=1;
+		} else if (!strcmp(cur_opt, "lazy-loading-on")){
+			options->lazy_loading_enabled = 1;
+			options->lazy_loading_overridden = 1;
+		} else if (!strcmp(cur_opt, "empty-lost-and-found-off")){
+			options->empty_lost_and_found = 0;
+			options->empty_lost_and_found_overridden=1;
+		} else if (!strcmp(cur_opt, "empty-lost-and-found-on")){
+			options->empty_lost_and_found = 1;
+			options->empty_lost_and_found_overridden=1;
+		} else if (!strcmp(cur_opt, "no-cache"))
+			options->no_cache = 1;
+		else if (!strcmp(cur_opt, "no-checkpoint-read"))
+			options->skip_checkpoint_read = 1;
+		else if (!strcmp(cur_opt, "no-checkpoint-write"))
+			options->skip_checkpoint_write = 1;
+		else if (!strcmp(cur_opt, "no-checkpoint")) {
+			options->skip_checkpoint_read = 1;
+			options->skip_checkpoint_write = 1;
+		} else {
+			printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n",
+					cur_opt);
+			error = 1;
+		}
+	}
+
+	return error;
+}
+
+static struct super_block *yaffs_internal_read_super(int yaffsVersion,
+						struct super_block *sb,
+						void *data, int silent)
+{
+	int nBlocks;
+	struct inode *inode = NULL;
+	struct dentry *root;
+	yaffs_Device *dev = 0;
+	char devname_buf[BDEVNAME_SIZE + 1];
+	struct mtd_info *mtd;
+	int err;
+	char *data_str = (char *)data;
+	struct yaffs_LinuxContext *context = NULL;
+	yaffs_DeviceParam *param;
+
+	yaffs_options options;
+
+	sb->s_magic = YAFFS_MAGIC;
+	sb->s_op = &yaffs_super_ops;
+	sb->s_flags |= MS_NOATIME;
+
+	if (!sb)
+		printk(KERN_INFO "yaffs: sb is NULL\n");
+	else if (!sb->s_dev)
+		printk(KERN_INFO "yaffs: sb->s_dev is NULL\n");
+	else if (!yaffs_devname(sb, devname_buf))
+		printk(KERN_INFO "yaffs: devname is NULL\n");
+	else
+		printk(KERN_INFO "yaffs: dev is %d name is \"%s\"\n",
+		       sb->s_dev,
+		       yaffs_devname(sb, devname_buf));
+
+	if (!data_str)
+		data_str = "";
+
+	printk(KERN_INFO "yaffs: passed flags \"%s\"\n", data_str);
+
+	memset(&options, 0, sizeof(options));
+
+	if (yaffs_parse_options(&options, data_str)) {
+		/* Option parsing failed */
+		return NULL;
+	}
+
+
+	sb->s_blocksize = PAGE_CACHE_SIZE;
+	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: Using yaffs%d\n", yaffsVersion));
+	T(YAFFS_TRACE_OS,
+	  ("yaffs_read_super: block size %d\n", (int)(sb->s_blocksize)));
+
+#ifdef CONFIG_YAFFS_DISABLE_WRITE_VERIFY
+	T(YAFFS_TRACE_OS,
+	  ("yaffs: Write verification disabled. All guarantees "
+	   "null and void\n"));
+#endif
+
+	T(YAFFS_TRACE_ALWAYS, ("yaffs: Attempting MTD mount on %u.%u, "
+			       "\"%s\"\n",
+			       MAJOR(sb->s_dev), MINOR(sb->s_dev),
+			       yaffs_devname(sb, devname_buf)));
+
+	/* Check it's an mtd device..... */
+	if (MAJOR(sb->s_dev) != MTD_BLOCK_MAJOR)
+		return NULL;	/* This isn't an mtd device */
+
+	/* Get the device */
+	mtd = get_mtd_device(NULL, MINOR(sb->s_dev));
+	if (!mtd) {
+		T(YAFFS_TRACE_ALWAYS,
+		  ("yaffs: MTD device #%u doesn't appear to exist\n",
+		   MINOR(sb->s_dev)));
+		return NULL;
+	}
+	/* Check it's NAND */
+	if (mtd->type != MTD_NANDFLASH) {
+		T(YAFFS_TRACE_ALWAYS,
+		  ("yaffs: MTD device is not NAND it's type %d\n", mtd->type));
+		return NULL;
+	}
+
+	T(YAFFS_TRACE_OS, (" erase %p\n", mtd->erase));
+	T(YAFFS_TRACE_OS, (" read %p\n", mtd->read));
+	T(YAFFS_TRACE_OS, (" write %p\n", mtd->write));
+	T(YAFFS_TRACE_OS, (" readoob %p\n", mtd->read_oob));
+	T(YAFFS_TRACE_OS, (" writeoob %p\n", mtd->write_oob));
+	T(YAFFS_TRACE_OS, (" block_isbad %p\n", mtd->block_isbad));
+	T(YAFFS_TRACE_OS, (" block_markbad %p\n", mtd->block_markbad));
+	T(YAFFS_TRACE_OS, (" %s %d\n", WRITE_SIZE_STR, WRITE_SIZE(mtd)));
+	T(YAFFS_TRACE_OS, (" oobsize %d\n", mtd->oobsize));
+	T(YAFFS_TRACE_OS, (" erasesize %d\n", mtd->erasesize));
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)
+	T(YAFFS_TRACE_OS, (" size %u\n", mtd->size));
+#else
+	T(YAFFS_TRACE_OS, (" size %lld\n", mtd->size));
+#endif
+
+#ifdef CONFIG_YAFFS_AUTO_YAFFS2
+
+	if (yaffsVersion == 1 && WRITE_SIZE(mtd) >= 2048) {
+		T(YAFFS_TRACE_ALWAYS, ("yaffs: auto selecting yaffs2\n"));
+		yaffsVersion = 2;
+	}
+
+	/* Added NCB 26/5/2006 for completeness */
+	if (yaffsVersion == 2 && !options.inband_tags && WRITE_SIZE(mtd) == 512) {
+		T(YAFFS_TRACE_ALWAYS, ("yaffs: auto selecting yaffs1\n"));
+		yaffsVersion = 1;
+	}
+
+#endif
+
+	if (yaffsVersion == 2) {
+		/* Check for version 2 style functions */
+		if (!mtd->erase ||
+		    !mtd->block_isbad ||
+		    !mtd->block_markbad ||
+		    !mtd->read ||
+		    !mtd->write ||
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		    !mtd->read_oob || !mtd->write_oob) {
+#else
+		    !mtd->write_ecc ||
+		    !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) {
+#endif
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not support required "
+			   "functions\n"));;
+			return NULL;
+		}
+
+		if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE ||
+		    mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) &&
+		    !options.inband_tags) {
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not have the "
+			   "right page sizes\n"));
+			return NULL;
+		}
+	} else {
+		/* Check for V1 style functions */
+		if (!mtd->erase ||
+		    !mtd->read ||
+		    !mtd->write ||
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		    !mtd->read_oob || !mtd->write_oob) {
+#else
+		    !mtd->write_ecc ||
+		    !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) {
+#endif
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not support required "
+			   "functions\n"));;
+			return NULL;
+		}
+
+		if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK ||
+		    mtd->oobsize != YAFFS_BYTES_PER_SPARE) {
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not support have the "
+			   "right page sizes\n"));
+			return NULL;
+		}
+	}
+
+	/* OK, so if we got here, we have an MTD that's NAND and looks
+	 * like it has the right capabilities
+	 * Set the yaffs_Device up for mtd
+	 */
+
+	dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL);
+	context = kmalloc(sizeof(struct yaffs_LinuxContext),GFP_KERNEL);
+	
+	if(!dev || !context ){
+		if(dev)
+			kfree(dev);
+		if(context)
+			kfree(context);
+		dev = NULL;
+		context = NULL;
+	}
+
+	if (!dev) {
+		/* Deep shit could not allocate device structure */
+		T(YAFFS_TRACE_ALWAYS,
+		  ("yaffs_read_super: Failed trying to allocate "
+		   "yaffs_Device. \n"));
+		return NULL;
+	}
+	memset(dev, 0, sizeof(yaffs_Device));
+	param = &(dev->param);
+
+	memset(context,0,sizeof(struct yaffs_LinuxContext));
+	dev->context = context;
+	YINIT_LIST_HEAD(&(context->contextList));
+	context->dev = dev;
+	context->superBlock = sb;
+
+	
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+	sb->s_fs_info = dev;
+#else
+	sb->u.generic_sbp = dev;
+#endif
+	
+	yaffs_DeviceToContext(dev)->mtd = mtd;
+	param->name = mtd->name;
+
+	/* Set up the memory size parameters.... */
+
+	nBlocks = YCALCBLOCKS(mtd->size, (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK));
+
+	param->startBlock = 0;
+	param->endBlock = nBlocks - 1;
+	param->nChunksPerBlock = YAFFS_CHUNKS_PER_BLOCK;
+	param->totalBytesPerChunk = YAFFS_BYTES_PER_CHUNK;
+	param->nReservedBlocks = 5;
+	param->nShortOpCaches = (options.no_cache) ? 0 : 10;
+	param->inbandTags = options.inband_tags;
+
+#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD
+	param->disableLazyLoad = 1;
+#endif
+	if(options.lazy_loading_overridden)
+		param->disableLazyLoad = !options.lazy_loading_enabled;
+
+#ifdef CONFIG_YAFFS_DISABLE_TAGS_ECC
+	param->noTagsECC = 1;
+#endif
+
+#ifdef CONFIG_YAFFS_DISABLE_BACKGROUND
+#else
+	param->deferDirectoryUpdate = 1;
+#endif
+
+	if(options.tags_ecc_overridden)
+		param->noTagsECC = !options.tags_ecc_on;
+
+#ifdef CONFIG_YAFFS_EMPTY_LOST_AND_FOUND
+	param->emptyLostAndFound = 1;
+#endif
+
+#ifdef CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING
+	param->refreshPeriod = 0;
+#else
+	param->refreshPeriod = 10000;
+#endif
+
+	if(options.empty_lost_and_found_overridden)
+		param->emptyLostAndFound = options.empty_lost_and_found;
+
+	/* ... and the functions. */
+	if (yaffsVersion == 2) {
+		param->writeChunkWithTagsToNAND =
+		    nandmtd2_WriteChunkWithTagsToNAND;
+		param->readChunkWithTagsFromNAND =
+		    nandmtd2_ReadChunkWithTagsFromNAND;
+		param->markNANDBlockBad = nandmtd2_MarkNANDBlockBad;
+		param->queryNANDBlock = nandmtd2_QueryNANDBlock;
+		yaffs_DeviceToContext(dev)->spareBuffer = YMALLOC(mtd->oobsize);
+		param->isYaffs2 = 1;
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		param->totalBytesPerChunk = mtd->writesize;
+		param->nChunksPerBlock = mtd->erasesize / mtd->writesize;
+#else
+		param->totalBytesPerChunk = mtd->oobblock;
+		param->nChunksPerBlock = mtd->erasesize / mtd->oobblock;
+#endif
+		nBlocks = YCALCBLOCKS(mtd->size, mtd->erasesize);
+
+		param->startBlock = 0;
+		param->endBlock = nBlocks - 1;
+	} else {
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		/* use the MTD interface in yaffs_mtdif1.c */
+		param->writeChunkWithTagsToNAND =
+			nandmtd1_WriteChunkWithTagsToNAND;
+		param->readChunkWithTagsFromNAND =
+			nandmtd1_ReadChunkWithTagsFromNAND;
+		param->markNANDBlockBad = nandmtd1_MarkNANDBlockBad;
+		param->queryNANDBlock = nandmtd1_QueryNANDBlock;
+#else
+		param->writeChunkToNAND = nandmtd_WriteChunkToNAND;
+		param->readChunkFromNAND = nandmtd_ReadChunkFromNAND;
+#endif
+		param->isYaffs2 = 0;
+	}
+	/* ... and common functions */
+	param->eraseBlockInNAND = nandmtd_EraseBlockInNAND;
+	param->initialiseNAND = nandmtd_InitialiseNAND;
+
+	yaffs_DeviceToContext(dev)->putSuperFunc = yaffs_MTDPutSuper;
+
+	param->markSuperBlockDirty = yaffs_MarkSuperBlockDirty;
+	param->gcControl = yaffs_gc_control_callback;
+
+	yaffs_DeviceToContext(dev)->superBlock= sb;
+	
+
+#ifndef CONFIG_YAFFS_DOES_ECC
+	param->useNANDECC = 1;
+#endif
+
+#ifdef CONFIG_YAFFS_DISABLE_WIDE_TNODES
+	param->wideTnodesDisabled = 1;
+#endif
+
+	param->skipCheckpointRead = options.skip_checkpoint_read;
+	param->skipCheckpointWrite = options.skip_checkpoint_write;
+
+	/* we assume this is protected by lock_kernel() in mount/umount */
+	down(&yaffs_context_lock);
+	ylist_add_tail(&(yaffs_DeviceToContext(dev)->contextList), &yaffs_context_list);
+	up(&yaffs_context_lock);
+
+        /* Directory search handling...*/
+        YINIT_LIST_HEAD(&(yaffs_DeviceToContext(dev)->searchContexts));
+        param->removeObjectCallback = yaffs_RemoveObjectCallback;
+
+	init_MUTEX(&(yaffs_DeviceToContext(dev)->grossLock));
+
+	yaffs_GrossLock(dev);
+
+	err = yaffs_GutsInitialise(dev);
+
+	T(YAFFS_TRACE_OS,
+	  ("yaffs_read_super: guts initialised %s\n",
+	   (err == YAFFS_OK) ? "OK" : "FAILED"));
+	   
+	if(err == YAFFS_OK)
+		yaffs_BackgroundStart(dev);
+		
+	if(!context->bgThread)
+		param->deferDirectoryUpdate = 0;
+
+
+	/* Release lock before yaffs_get_inode() */
+	yaffs_GrossUnlock(dev);
+
+	/* Create root inode */
+	if (err == YAFFS_OK)
+		inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0,
+					yaffs_Root(dev));
+
+	if (!inode)
+		return NULL;
+
+	inode->i_op = &yaffs_dir_inode_operations;
+	inode->i_fop = &yaffs_dir_operations;
+
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: got root inode\n"));
+
+	root = d_alloc_root(inode);
+
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: d_alloc_root done\n"));
+
+	if (!root) {
+		iput(inode);
+		return NULL;
+	}
+	sb->s_root = root;
+	sb->s_dirt = !dev->isCheckpointed;
+	T(YAFFS_TRACE_ALWAYS,
+	  ("yaffs_read_super: isCheckpointed %d\n", dev->isCheckpointed));
+
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: done\n"));
+	return sb;
+}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data,
+					 int silent)
+{
+	return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_read_super(struct file_system_type *fs,
+			    int flags, const char *dev_name,
+			    void *data, struct vfsmount *mnt)
+{
+
+	return get_sb_bdev(fs, flags, dev_name, data,
+			   yaffs_internal_read_super_mtd, mnt);
+}
+#else
+static struct super_block *yaffs_read_super(struct file_system_type *fs,
+					    int flags, const char *dev_name,
+					    void *data)
+{
+
+	return get_sb_bdev(fs, flags, dev_name, data,
+			   yaffs_internal_read_super_mtd);
+}
+#endif
+
+static struct file_system_type yaffs_fs_type = {
+	.owner = THIS_MODULE,
+	.name = "yaffs",
+	.get_sb = yaffs_read_super,
+	.kill_sb = kill_block_super,
+	.fs_flags = FS_REQUIRES_DEV,
+};
+#else
+static struct super_block *yaffs_read_super(struct super_block *sb, void *data,
+					    int silent)
+{
+	return yaffs_internal_read_super(1, sb, data, silent);
+}
+
+static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super,
+		      FS_REQUIRES_DEV);
+#endif
+
+
+#ifdef CONFIG_YAFFS_YAFFS2
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data,
+					  int silent)
+{
+	return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs2_read_super(struct file_system_type *fs,
+			int flags, const char *dev_name, void *data,
+			struct vfsmount *mnt)
+{
+	return get_sb_bdev(fs, flags, dev_name, data,
+			yaffs2_internal_read_super_mtd, mnt);
+}
+#else
+static struct super_block *yaffs2_read_super(struct file_system_type *fs,
+					     int flags, const char *dev_name,
+					     void *data)
+{
+
+	return get_sb_bdev(fs, flags, dev_name, data,
+			   yaffs2_internal_read_super_mtd);
+}
+#endif
+
+static struct file_system_type yaffs2_fs_type = {
+	.owner = THIS_MODULE,
+	.name = "yaffs2",
+	.get_sb = yaffs2_read_super,
+	.kill_sb = kill_block_super,
+	.fs_flags = FS_REQUIRES_DEV,
+};
+#else
+static struct super_block *yaffs2_read_super(struct super_block *sb,
+					     void *data, int silent)
+{
+	return yaffs_internal_read_super(2, sb, data, silent);
+}
+
+static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super,
+		      FS_REQUIRES_DEV);
+#endif
+
+#endif				/* CONFIG_YAFFS_YAFFS2 */
+
+static struct proc_dir_entry *my_proc_entry;
+static struct proc_dir_entry *debug_proc_entry;
+
+static char *yaffs_dump_dev_part0(char *buf, yaffs_Device * dev)
+{
+	buf += sprintf(buf, "startBlock......... %d\n", dev->param.startBlock);
+	buf += sprintf(buf, "endBlock........... %d\n", dev->param.endBlock);
+	buf += sprintf(buf, "totalBytesPerChunk. %d\n", dev->param.totalBytesPerChunk);
+	buf += sprintf(buf, "useNANDECC......... %d\n", dev->param.useNANDECC);
+	buf += sprintf(buf, "noTagsECC.......... %d\n", dev->param.noTagsECC);
+	buf += sprintf(buf, "isYaffs2........... %d\n", dev->param.isYaffs2);
+	buf += sprintf(buf, "inbandTags......... %d\n", dev->param.inbandTags);
+	buf += sprintf(buf, "emptyLostAndFound.. %d\n", dev->param.emptyLostAndFound);
+	buf += sprintf(buf, "disableLazyLoad.... %d\n", dev->param.disableLazyLoad);
+	buf += sprintf(buf, "refreshPeriod...... %d\n", dev->param.refreshPeriod);
+	buf += sprintf(buf, "nShortOpCaches..... %d\n", dev->param.nShortOpCaches);
+	buf += sprintf(buf, "nReservedBlocks.... %d\n", dev->param.nReservedBlocks);
+
+	buf += sprintf(buf, "\n");
+
+	return buf;
+}
+
+
+static char *yaffs_dump_dev_part1(char *buf, yaffs_Device * dev)
+{
+	buf += sprintf(buf, "nDataBytesPerChunk. %d\n", dev->nDataBytesPerChunk);
+	buf += sprintf(buf, "chunkGroupBits..... %d\n", dev->chunkGroupBits);
+	buf += sprintf(buf, "chunkGroupSize..... %d\n", dev->chunkGroupSize);
+	buf += sprintf(buf, "nErasedBlocks...... %d\n", dev->nErasedBlocks);
+	buf += sprintf(buf, "blocksInCheckpoint. %d\n", dev->blocksInCheckpoint);
+	buf += sprintf(buf, "\n");
+	buf += sprintf(buf, "nTnodesCreated..... %d\n", dev->nTnodesCreated);
+	buf += sprintf(buf, "nFreeTnodes........ %d\n", dev->nFreeTnodes);
+	buf += sprintf(buf, "nObjectsCreated.... %d\n", dev->nObjectsCreated);
+	buf += sprintf(buf, "nFreeObjects....... %d\n", dev->nFreeObjects);
+	buf += sprintf(buf, "nFreeChunks........ %d\n", dev->nFreeChunks);
+	buf += sprintf(buf, "\n");
+	buf += sprintf(buf, "nPageWrites........ %u\n", dev->nPageWrites);
+	buf += sprintf(buf, "nPageReads......... %u\n", dev->nPageReads);
+	buf += sprintf(buf, "nBlockErasures..... %u\n", dev->nBlockErasures);
+	buf += sprintf(buf, "nGCCopies.......... %u\n", dev->nGCCopies);
+	buf += sprintf(buf, "garbageCollections. %u\n", dev->garbageCollections);
+	buf += sprintf(buf, "passiveGCs......... %u\n", dev->passiveGarbageCollections);
+	buf += sprintf(buf, "nRetriedWrites..... %u\n", dev->nRetriedWrites);
+	buf += sprintf(buf, "nRetireBlocks...... %u\n", dev->nRetiredBlocks);
+	buf += sprintf(buf, "eccFixed........... %u\n", dev->eccFixed);
+	buf += sprintf(buf, "eccUnfixed......... %u\n", dev->eccUnfixed);
+	buf += sprintf(buf, "tagsEccFixed....... %u\n", dev->tagsEccFixed);
+	buf += sprintf(buf, "tagsEccUnfixed..... %u\n", dev->tagsEccUnfixed);
+	buf += sprintf(buf, "cacheHits.......... %u\n", dev->cacheHits);
+	buf += sprintf(buf, "nDeletedFiles...... %u\n", dev->nDeletedFiles);
+	buf += sprintf(buf, "nUnlinkedFiles..... %u\n", dev->nUnlinkedFiles);
+	buf += sprintf(buf, "refreshCount....... %u\n", dev->refreshCount);
+	buf +=
+	    sprintf(buf, "nBackgroudDeletions %u\n", dev->nBackgroundDeletions);
+
+	return buf;
+}
+
+static int yaffs_proc_read(char *page,
+			   char **start,
+			   off_t offset, int count, int *eof, void *data)
+{
+	struct ylist_head *item;
+	char *buf = page;
+	int step = offset;
+	int n = 0;
+
+	/* Get proc_file_read() to step 'offset' by one on each sucessive call.
+	 * We use 'offset' (*ppos) to indicate where we are in devList.
+	 * This also assumes the user has posted a read buffer large
+	 * enough to hold the complete output; but that's life in /proc.
+	 */
+
+	*(int *)start = 1;
+
+	/* Print header first */
+	if (step == 0)
+		buf += sprintf(buf, "YAFFS built:" __DATE__ " " __TIME__
+			       "\n%s\n%s\n", yaffs_fs_c_version,
+			       yaffs_guts_c_version);
+	else if (step == 1)
+		buf += sprintf(buf,"\n");
+	else {
+		step-=2;
+		
+		down(&yaffs_context_lock);
+
+		/* Locate and print the Nth entry.  Order N-squared but N is small. */
+		ylist_for_each(item, &yaffs_context_list) {
+			struct yaffs_LinuxContext *dc = ylist_entry(item, struct yaffs_LinuxContext, contextList);
+			yaffs_Device *dev = dc->dev;
+
+			if (n < (step & ~1)) {
+				n+=2;
+				continue;
+			}
+			if((step & 1)==0){
+				buf += sprintf(buf, "\nDevice %d \"%s\"\n", n, dev->param.name);
+				buf = yaffs_dump_dev_part0(buf, dev);
+			} else
+				buf = yaffs_dump_dev_part1(buf, dev);
+			
+			break;
+		}
+		up(&yaffs_context_lock);
+	}
+
+	return buf - page < count ? buf - page : count;
+}
+
+static int yaffs_debug_proc_read(char *page,
+				char **start,
+				off_t offset, int count, int *eof, void *data)
+{
+	struct ylist_head *item;
+	char *buf = page;
+	int n = 0;
+
+	down(&yaffs_context_lock);
+
+	/* Locate and print the Nth entry.  Order N-squared but N is small. */
+	ylist_for_each(item, &yaffs_context_list) {
+		struct yaffs_LinuxContext *dc = ylist_entry(item, struct yaffs_LinuxContext, contextList);
+		yaffs_Device *dev = dc->dev;
+
+		int erasedChunks;
+		int nObjects;
+		int nTnodes;
+
+		erasedChunks = dev->nErasedBlocks * dev->param.nChunksPerBlock;
+		nObjects = dev->nObjectsCreated -dev->nFreeObjects;
+		nTnodes = dev->nTnodesCreated - dev->nFreeTnodes;
+		
+		
+		buf += sprintf(buf,"%d, %d, %d, %d, %d\n", 
+				n, dev->nFreeChunks, erasedChunks,
+				nObjects, nTnodes);
+	}
+	up(&yaffs_context_lock);
+
+
+	return buf - page < count ? buf - page : count;
+}
+
+/**
+ * Set the verbosity of the warnings and error messages.
+ *
+ * Note that the names can only be a..z or _ with the current code.
+ */
+
+static struct {
+	char *mask_name;
+	unsigned mask_bitfield;
+} mask_flags[] = {
+	{"allocate", YAFFS_TRACE_ALLOCATE},
+	{"always", YAFFS_TRACE_ALWAYS},
+	{"bad_blocks", YAFFS_TRACE_BAD_BLOCKS},
+	{"buffers", YAFFS_TRACE_BUFFERS},
+	{"bug", YAFFS_TRACE_BUG},
+	{"checkpt", YAFFS_TRACE_CHECKPOINT},
+	{"deletion", YAFFS_TRACE_DELETION},
+	{"erase", YAFFS_TRACE_ERASE},
+	{"error", YAFFS_TRACE_ERROR},
+	{"gc_detail", YAFFS_TRACE_GC_DETAIL},
+	{"gc", YAFFS_TRACE_GC},
+	{"mtd", YAFFS_TRACE_MTD},
+	{"nandaccess", YAFFS_TRACE_NANDACCESS},
+	{"os", YAFFS_TRACE_OS},
+	{"scan_debug", YAFFS_TRACE_SCAN_DEBUG},
+	{"scan", YAFFS_TRACE_SCAN},
+	{"tracing", YAFFS_TRACE_TRACING},
+	{"sync", YAFFS_TRACE_SYNC},
+
+	{"background", YAFFS_TRACE_BACKGROUND},
+
+	{"verify", YAFFS_TRACE_VERIFY},
+	{"verify_nand", YAFFS_TRACE_VERIFY_NAND},
+	{"verify_full", YAFFS_TRACE_VERIFY_FULL},
+	{"verify_all", YAFFS_TRACE_VERIFY_ALL},
+
+	{"write", YAFFS_TRACE_WRITE},
+	{"all", 0xffffffff},
+	{"none", 0},
+	{NULL, 0},
+};
+
+#define MAX_MASK_NAME_LENGTH 40
+static int yaffs_proc_write_trace_options(struct file *file, const char *buf,
+					 unsigned long count, void *data)
+{
+	unsigned rg = 0, mask_bitfield;
+	char *end;
+	char *mask_name;
+	const char *x;
+	char substring[MAX_MASK_NAME_LENGTH + 1];
+	int i;
+	int done = 0;
+	int add, len = 0;
+	int pos = 0;
+
+	rg = yaffs_traceMask;
+
+	while (!done && (pos < count)) {
+		done = 1;
+		while ((pos < count) && isspace(buf[pos]))
+			pos++;
+
+		switch (buf[pos]) {
+		case '+':
+		case '-':
+		case '=':
+			add = buf[pos];
+			pos++;
+			break;
+
+		default:
+			add = ' ';
+			break;
+		}
+		mask_name = NULL;
+
+		mask_bitfield = simple_strtoul(buf + pos, &end, 0);
+
+		if (end > buf + pos) {
+			mask_name = "numeral";
+			len = end - (buf + pos);
+			pos += len;
+			done = 0;
+		} else {
+			for (x = buf + pos, i = 0;
+			    (*x == '_' || (*x >= 'a' && *x <= 'z')) &&
+			    i < MAX_MASK_NAME_LENGTH; x++, i++, pos++)
+				substring[i] = *x;
+			substring[i] = '\0';
+
+			for (i = 0; mask_flags[i].mask_name != NULL; i++) {
+				if (strcmp(substring, mask_flags[i].mask_name) == 0) {
+					mask_name = mask_flags[i].mask_name;
+					mask_bitfield = mask_flags[i].mask_bitfield;
+					done = 0;
+					break;
+				}
+			}
+		}
+
+		if (mask_name != NULL) {
+			done = 0;
+			switch (add) {
+			case '-':
+				rg &= ~mask_bitfield;
+				break;
+			case '+':
+				rg |= mask_bitfield;
+				break;
+			case '=':
+				rg = mask_bitfield;
+				break;
+			default:
+				rg |= mask_bitfield;
+				break;
+			}
+		}
+	}
+
+	yaffs_traceMask = rg | YAFFS_TRACE_ALWAYS;
+
+	printk(KERN_DEBUG "new trace = 0x%08X\n", yaffs_traceMask);
+
+	if (rg & YAFFS_TRACE_ALWAYS) {
+		for (i = 0; mask_flags[i].mask_name != NULL; i++) {
+			char flag;
+			flag = ((rg & mask_flags[i].mask_bitfield) == mask_flags[i].mask_bitfield) ? '+' : '-';
+			printk(KERN_DEBUG "%c%s\n", flag, mask_flags[i].mask_name);
+		}
+	}
+
+	return count;
+}
+
+
+static int yaffs_proc_write(struct file *file, const char *buf,
+					 unsigned long count, void *data)
+{
+        return yaffs_proc_write_trace_options(file, buf, count, data);
+}
+
+/* Stuff to handle installation of file systems */
+struct file_system_to_install {
+	struct file_system_type *fst;
+	int installed;
+};
+
+static struct file_system_to_install fs_to_install[] = {
+	{&yaffs_fs_type, 0},
+	{&yaffs2_fs_type, 0},
+	{NULL, 0}
+};
+
+static int __init init_yaffs_fs(void)
+{
+	int error = 0;
+	struct file_system_to_install *fsinst;
+
+	T(YAFFS_TRACE_ALWAYS,
+	  ("yaffs " __DATE__ " " __TIME__ " Installing. \n"));
+
+	init_MUTEX(&yaffs_context_lock);
+
+	/* Install the proc_fs entries */
+	my_proc_entry = create_proc_entry("yaffs",
+					       S_IRUGO | S_IFREG,
+					       YPROC_ROOT);
+
+	if (my_proc_entry) {
+		my_proc_entry->write_proc = yaffs_proc_write;
+		my_proc_entry->read_proc = yaffs_proc_read;
+		my_proc_entry->data = NULL;
+	} else
+		return -ENOMEM;
+
+	debug_proc_entry = create_proc_entry("yaffs_debug",
+					       S_IRUGO | S_IFREG,
+					       YPROC_ROOT);
+
+	if (debug_proc_entry) {
+		debug_proc_entry->write_proc = NULL;
+		debug_proc_entry->read_proc = yaffs_debug_proc_read;
+		debug_proc_entry->data = NULL;
+	} else
+		return -ENOMEM;
+
+	/* Now add the file system entries */
+
+	fsinst = fs_to_install;
+
+	while (fsinst->fst && !error) {
+		error = register_filesystem(fsinst->fst);
+		if (!error)
+			fsinst->installed = 1;
+		fsinst++;
+	}
+
+	/* Any errors? uninstall  */
+	if (error) {
+		fsinst = fs_to_install;
+
+		while (fsinst->fst) {
+			if (fsinst->installed) {
+				unregister_filesystem(fsinst->fst);
+				fsinst->installed = 0;
+			}
+			fsinst++;
+		}
+	}
+
+	return error;
+}
+
+static void __exit exit_yaffs_fs(void)
+{
+
+	struct file_system_to_install *fsinst;
+
+	T(YAFFS_TRACE_ALWAYS, ("yaffs " __DATE__ " " __TIME__
+			       " removing. \n"));
+
+	remove_proc_entry("yaffs", YPROC_ROOT);
+
+	fsinst = fs_to_install;
+
+	while (fsinst->fst) {
+		if (fsinst->installed) {
+			unregister_filesystem(fsinst->fst);
+			fsinst->installed = 0;
+		}
+		fsinst++;
+	}
+}
+
+module_init(init_yaffs_fs)
+module_exit(exit_yaffs_fs)
+
+MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system");
+MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2006");
+MODULE_LICENSE("GPL");
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_getblockinfo.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_getblockinfo.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_getblockinfo.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_getblockinfo.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,35 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_GETBLOCKINFO_H__
+#define __YAFFS_GETBLOCKINFO_H__
+
+#include "yaffs_guts.h"
+#include "yaffs_trace.h"
+
+/* Function to manipulate block info */
+static Y_INLINE yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blk)
+{
+	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("**>> yaffs: getBlockInfo block %d is not valid" TENDSTR),
+		   blk));
+		YBUG();
+	}
+	return &dev->blockInfo[blk - dev->internalStartBlock];
+}
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_guts.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_guts.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_guts.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_guts.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,8113 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_guts_c_version =
+    "$Id: yaffs_guts.c,v 1.120 2010/03/15 23:10:34 charles Exp $";
+
+#include "yportenv.h"
+#include "yaffs_trace.h"
+
+#include "yaffsinterface.h"
+#include "yaffs_guts.h"
+#include "yaffs_tagsvalidity.h"
+#include "yaffs_getblockinfo.h"
+
+#include "yaffs_tagscompat.h"
+#ifndef CONFIG_YAFFS_USE_OWN_SORT
+#include "yaffs_qsort.h"
+#endif
+#include "yaffs_nand.h"
+
+#include "yaffs_checkptrw.h"
+
+#include "yaffs_nand.h"
+#include "yaffs_packedtags2.h"
+
+
+#define YAFFS_PASSIVE_GC_CHUNKS 2
+#define YAFFS_SMALL_HOLE_THRESHOLD 3
+
+#include "yaffs_ecc.h"
+
+
+/* Robustification (if it ever comes about...) */
+static void yaffs_RetireBlock(yaffs_Device *dev, int blockInNAND);
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND,
+		int erasedOk);
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				const __u8 *data,
+				const yaffs_ExtendedTags *tags);
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				const yaffs_ExtendedTags *tags);
+
+/* Other local prototypes */
+static void yaffs_UpdateParent(yaffs_Object *obj);
+static int yaffs_UnlinkObject(yaffs_Object *obj);
+static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj);
+
+static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList);
+
+static int yaffs_WriteNewChunkWithTagsToNAND(yaffs_Device *dev,
+					const __u8 *buffer,
+					yaffs_ExtendedTags *tags,
+					int useReserve);
+static int yaffs_PutChunkIntoFile(yaffs_Object *in, int chunkInInode,
+				int chunkInNAND, int inScan);
+
+static yaffs_Object *yaffs_CreateNewObject(yaffs_Device *dev, int number,
+					yaffs_ObjectType type);
+static void yaffs_AddObjectToDirectory(yaffs_Object *directory,
+				yaffs_Object *obj);
+static int yaffs_UpdateObjectHeader(yaffs_Object *in, const YCHAR *name,
+				int force, int isShrink, int shadows);
+static void yaffs_RemoveObjectFromDirectory(yaffs_Object *obj);
+static int yaffs_CheckStructures(void);
+static int yaffs_DeleteWorker(yaffs_Object *in, yaffs_Tnode *tn, __u32 level,
+			int chunkOffset, int *limit);
+static int yaffs_DoGenericObjectDeletion(yaffs_Object *in);
+
+static yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device *dev, int blockNo);
+
+
+static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
+				int chunkInNAND);
+
+static int yaffs_UnlinkWorker(yaffs_Object *obj);
+
+static int yaffs_TagsMatch(const yaffs_ExtendedTags *tags, int objectId,
+			int chunkInObject);
+
+static int yaffs_AllocateChunk(yaffs_Device *dev, int useReserve,
+				yaffs_BlockInfo **blockUsedPtr);
+
+static void yaffs_VerifyFreeChunks(yaffs_Device *dev);
+
+static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in);
+
+static void yaffs_VerifyDirectory(yaffs_Object *directory);
+#ifdef YAFFS_PARANOID
+static int yaffs_CheckFileSanity(yaffs_Object *in);
+#else
+#define yaffs_CheckFileSanity(in)
+#endif
+
+static void yaffs_InvalidateWholeChunkCache(yaffs_Object *in);
+static void yaffs_InvalidateChunkCache(yaffs_Object *object, int chunkId);
+
+static void yaffs_InvalidateCheckpoint(yaffs_Device *dev);
+
+static int yaffs_FindChunkInFile(yaffs_Object *in, int chunkInInode,
+				yaffs_ExtendedTags *tags);
+
+static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn,
+		unsigned pos);
+static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device *dev,
+					yaffs_FileStructure *fStruct,
+					__u32 chunkId);
+
+static int yaffs_HandleHole(yaffs_Object *obj, loff_t newSize);
+static void yaffs_SkipRestOfBlock(yaffs_Device *dev);
+static int yaffs_VerifyChunkWritten(yaffs_Device *dev,
+					int chunkInNAND,
+					const __u8 *data,
+					yaffs_ExtendedTags *tags);
+
+/* Function to calculate chunk and offset */
+
+static void yaffs_AddrToChunk(yaffs_Device *dev, loff_t addr, int *chunkOut,
+		__u32 *offsetOut)
+{
+	int chunk;
+	__u32 offset;
+
+	chunk  = (__u32)(addr >> dev->chunkShift);
+
+	if (dev->chunkDiv == 1) {
+		/* easy power of 2 case */
+		offset = (__u32)(addr & dev->chunkMask);
+	} else {
+		/* Non power-of-2 case */
+
+		loff_t chunkBase;
+
+		chunk /= dev->chunkDiv;
+
+		chunkBase = ((loff_t)chunk) * dev->nDataBytesPerChunk;
+		offset = (__u32)(addr - chunkBase);
+	}
+
+	*chunkOut = chunk;
+	*offsetOut = offset;
+}
+
+/* Function to return the number of shifts for a power of 2 greater than or
+ * equal to the given number
+ * Note we don't try to cater for all possible numbers and this does not have to
+ * be hellishly efficient.
+ */
+
+static __u32 ShiftsGE(__u32 x)
+{
+	int extraBits;
+	int nShifts;
+
+	nShifts = extraBits = 0;
+
+	while (x > 1) {
+		if (x & 1)
+			extraBits++;
+		x >>= 1;
+		nShifts++;
+	}
+
+	if (extraBits)
+		nShifts++;
+
+	return nShifts;
+}
+
+/* Function to return the number of shifts to get a 1 in bit 0
+ */
+
+static __u32 Shifts(__u32 x)
+{
+	int nShifts;
+
+	nShifts =  0;
+
+	if (!x)
+		return 0;
+
+	while (!(x&1)) {
+		x >>= 1;
+		nShifts++;
+	}
+
+	return nShifts;
+}
+
+
+
+/*
+ * Temporary buffer manipulations.
+ */
+
+static int yaffs_InitialiseTempBuffers(yaffs_Device *dev)
+{
+	int i;
+	__u8 *buf = (__u8 *)1;
+
+	memset(dev->tempBuffer, 0, sizeof(dev->tempBuffer));
+
+	for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) {
+		dev->tempBuffer[i].line = 0;	/* not in use */
+		dev->tempBuffer[i].buffer = buf =
+		    YMALLOC_DMA(dev->param.totalBytesPerChunk);
+	}
+
+	return buf ? YAFFS_OK : YAFFS_FAIL;
+}
+
+__u8 *yaffs_GetTempBuffer(yaffs_Device *dev, int lineNo)
+{
+	int i, j;
+
+	dev->tempInUse++;
+	if (dev->tempInUse > dev->maxTemp)
+		dev->maxTemp = dev->tempInUse;
+
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
+		if (dev->tempBuffer[i].line == 0) {
+			dev->tempBuffer[i].line = lineNo;
+			if ((i + 1) > dev->maxTemp) {
+				dev->maxTemp = i + 1;
+				for (j = 0; j <= i; j++)
+					dev->tempBuffer[j].maxLine =
+					    dev->tempBuffer[j].line;
+			}
+
+			return dev->tempBuffer[i].buffer;
+		}
+	}
+
+	T(YAFFS_TRACE_BUFFERS,
+	  (TSTR("Out of temp buffers at line %d, other held by lines:"),
+	   lineNo));
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++)
+		T(YAFFS_TRACE_BUFFERS, (TSTR(" %d "), dev->tempBuffer[i].line));
+
+	T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR)));
+
+	/*
+	 * If we got here then we have to allocate an unmanaged one
+	 * This is not good.
+	 */
+
+	dev->unmanagedTempAllocations++;
+	return YMALLOC(dev->nDataBytesPerChunk);
+
+}
+
+void yaffs_ReleaseTempBuffer(yaffs_Device *dev, __u8 *buffer,
+				    int lineNo)
+{
+	int i;
+
+	dev->tempInUse--;
+
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
+		if (dev->tempBuffer[i].buffer == buffer) {
+			dev->tempBuffer[i].line = 0;
+			return;
+		}
+	}
+
+	if (buffer) {
+		/* assume it is an unmanaged one. */
+		T(YAFFS_TRACE_BUFFERS,
+		  (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR),
+		   lineNo));
+		YFREE(buffer);
+		dev->unmanagedTempDeallocations++;
+	}
+
+}
+
+/*
+ * Determine if we have a managed buffer.
+ */
+int yaffs_IsManagedTempBuffer(yaffs_Device *dev, const __u8 *buffer)
+{
+	int i;
+
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
+		if (dev->tempBuffer[i].buffer == buffer)
+			return 1;
+	}
+
+	for (i = 0; i < dev->param.nShortOpCaches; i++) {
+		if (dev->srCache[i].data == buffer)
+			return 1;
+	}
+
+	if (buffer == dev->checkpointBuffer)
+		return 1;
+
+	T(YAFFS_TRACE_ALWAYS,
+		(TSTR("yaffs: unmaged buffer detected.\n" TENDSTR)));
+	return 0;
+}
+
+
+
+/*
+ * Chunk bitmap manipulations
+ */
+
+static Y_INLINE __u8 *yaffs_BlockBits(yaffs_Device *dev, int blk)
+{
+	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
+		T(YAFFS_TRACE_ERROR,
+			(TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR),
+			blk));
+		YBUG();
+	}
+	return dev->chunkBits +
+		(dev->chunkBitmapStride * (blk - dev->internalStartBlock));
+}
+
+static Y_INLINE void yaffs_VerifyChunkBitId(yaffs_Device *dev, int blk, int chunk)
+{
+	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock ||
+			chunk < 0 || chunk >= dev->param.nChunksPerBlock) {
+		T(YAFFS_TRACE_ERROR,
+		(TSTR("**>> yaffs: Chunk Id (%d:%d) invalid"TENDSTR),
+			blk, chunk));
+		YBUG();
+	}
+}
+
+static Y_INLINE void yaffs_ClearChunkBits(yaffs_Device *dev, int blk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+
+	memset(blkBits, 0, dev->chunkBitmapStride);
+}
+
+static Y_INLINE void yaffs_ClearChunkBit(yaffs_Device *dev, int blk, int chunk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+
+	yaffs_VerifyChunkBitId(dev, blk, chunk);
+
+	blkBits[chunk / 8] &= ~(1 << (chunk & 7));
+}
+
+static Y_INLINE void yaffs_SetChunkBit(yaffs_Device *dev, int blk, int chunk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+
+	yaffs_VerifyChunkBitId(dev, blk, chunk);
+
+	blkBits[chunk / 8] |= (1 << (chunk & 7));
+}
+
+static Y_INLINE int yaffs_CheckChunkBit(yaffs_Device *dev, int blk, int chunk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	yaffs_VerifyChunkBitId(dev, blk, chunk);
+
+	return (blkBits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0;
+}
+
+static Y_INLINE int yaffs_StillSomeChunkBits(yaffs_Device *dev, int blk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	int i;
+	for (i = 0; i < dev->chunkBitmapStride; i++) {
+		if (*blkBits)
+			return 1;
+		blkBits++;
+	}
+	return 0;
+}
+
+static int yaffs_CountChunkBits(yaffs_Device *dev, int blk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	int i;
+	int n = 0;
+	for (i = 0; i < dev->chunkBitmapStride; i++) {
+		__u8 x = *blkBits;
+		while (x) {
+			if (x & 1)
+				n++;
+			x >>= 1;
+		}
+
+		blkBits++;
+	}
+	return n;
+}
+
+/*
+ * Verification code
+ */
+
+static int yaffs_SkipVerification(yaffs_Device *dev)
+{
+	dev=dev;
+	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
+}
+
+static int yaffs_SkipFullVerification(yaffs_Device *dev)
+{
+	dev=dev;
+	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_FULL));
+}
+
+static int yaffs_SkipNANDVerification(yaffs_Device *dev)
+{
+	dev=dev;
+	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_NAND));
+}
+
+static const char *blockStateName[] = {
+"Unknown",
+"Needs scanning",
+"Scanning",
+"Empty",
+"Allocating",
+"Full",
+"Dirty",
+"Checkpoint",
+"Collecting",
+"Dead"
+};
+
+static void yaffs_VerifyBlock(yaffs_Device *dev, yaffs_BlockInfo *bi, int n)
+{
+	int actuallyUsed;
+	int inUse;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	/* Report illegal runtime states */
+	if (bi->blockState >= YAFFS_NUMBER_OF_BLOCK_STATES)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has undefined state %d"TENDSTR), n, bi->blockState));
+
+	switch (bi->blockState) {
+	case YAFFS_BLOCK_STATE_UNKNOWN:
+	case YAFFS_BLOCK_STATE_SCANNING:
+	case YAFFS_BLOCK_STATE_NEEDS_SCANNING:
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has bad run-state %s"TENDSTR),
+		n, blockStateName[bi->blockState]));
+	}
+
+	/* Check pages in use and soft deletions are legal */
+
+	actuallyUsed = bi->pagesInUse - bi->softDeletions;
+
+	if (bi->pagesInUse < 0 || bi->pagesInUse > dev->param.nChunksPerBlock ||
+	   bi->softDeletions < 0 || bi->softDeletions > dev->param.nChunksPerBlock ||
+	   actuallyUsed < 0 || actuallyUsed > dev->param.nChunksPerBlock)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has illegal values pagesInUsed %d softDeletions %d"TENDSTR),
+		n, bi->pagesInUse, bi->softDeletions));
+
+
+	/* Check chunk bitmap legal */
+	inUse = yaffs_CountChunkBits(dev, n);
+	if (inUse != bi->pagesInUse)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has inconsistent values pagesInUse %d counted chunk bits %d"TENDSTR),
+			n, bi->pagesInUse, inUse));
+
+	/* Check that the sequence number is valid.
+	 * Ten million is legal, but is very unlikely
+	 */
+	if (dev->param.isYaffs2 &&
+	   (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING || bi->blockState == YAFFS_BLOCK_STATE_FULL) &&
+	   (bi->sequenceNumber < YAFFS_LOWEST_SEQUENCE_NUMBER || bi->sequenceNumber > 10000000))
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has suspect sequence number of %d"TENDSTR),
+		n, bi->sequenceNumber));
+}
+
+static void yaffs_VerifyCollectedBlock(yaffs_Device *dev, yaffs_BlockInfo *bi,
+		int n)
+{
+	yaffs_VerifyBlock(dev, bi, n);
+
+	/* After collection the block should be in the erased state */
+	/* This will need to change if we do partial gc */
+
+	if (bi->blockState != YAFFS_BLOCK_STATE_COLLECTING &&
+			bi->blockState != YAFFS_BLOCK_STATE_EMPTY) {
+		T(YAFFS_TRACE_ERROR, (TSTR("Block %d is in state %d after gc, should be erased"TENDSTR),
+			n, bi->blockState));
+	}
+}
+
+static void yaffs_VerifyBlocks(yaffs_Device *dev)
+{
+	int i;
+	int nBlocksPerState[YAFFS_NUMBER_OF_BLOCK_STATES];
+	int nIllegalBlockStates = 0;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	memset(nBlocksPerState, 0, sizeof(nBlocksPerState));
+
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, i);
+		yaffs_VerifyBlock(dev, bi, i);
+
+		if (bi->blockState < YAFFS_NUMBER_OF_BLOCK_STATES)
+			nBlocksPerState[bi->blockState]++;
+		else
+			nIllegalBlockStates++;
+	}
+
+	T(YAFFS_TRACE_VERIFY, (TSTR(""TENDSTR)));
+	T(YAFFS_TRACE_VERIFY, (TSTR("Block summary"TENDSTR)));
+
+	T(YAFFS_TRACE_VERIFY, (TSTR("%d blocks have illegal states"TENDSTR), nIllegalBlockStates));
+	if (nBlocksPerState[YAFFS_BLOCK_STATE_ALLOCATING] > 1)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Too many allocating blocks"TENDSTR)));
+
+	for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++)
+		T(YAFFS_TRACE_VERIFY,
+		  (TSTR("%s %d blocks"TENDSTR),
+		  blockStateName[i], nBlocksPerState[i]));
+
+	if (dev->blocksInCheckpoint != nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT])
+		T(YAFFS_TRACE_VERIFY,
+		 (TSTR("Checkpoint block count wrong dev %d count %d"TENDSTR),
+		 dev->blocksInCheckpoint, nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT]));
+
+	if (dev->nErasedBlocks != nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY])
+		T(YAFFS_TRACE_VERIFY,
+		 (TSTR("Erased block count wrong dev %d count %d"TENDSTR),
+		 dev->nErasedBlocks, nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY]));
+
+	if (nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING] > 1)
+		T(YAFFS_TRACE_VERIFY,
+		 (TSTR("Too many collecting blocks %d (max is 1)"TENDSTR),
+		 nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING]));
+
+	T(YAFFS_TRACE_VERIFY, (TSTR(""TENDSTR)));
+
+}
+
+/*
+ * Verify the object header. oh must be valid, but obj and tags may be NULL in which
+ * case those tests will not be performed.
+ */
+static void yaffs_VerifyObjectHeader(yaffs_Object *obj, yaffs_ObjectHeader *oh, yaffs_ExtendedTags *tags, int parentCheck)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+
+	if (!(tags && obj && oh)) {
+		T(YAFFS_TRACE_VERIFY,
+				(TSTR("Verifying object header tags %p obj %p oh %p"TENDSTR),
+				tags, obj, oh));
+		return;
+	}
+
+	if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN ||
+			oh->type > YAFFS_OBJECT_TYPE_MAX)
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header type is illegal value 0x%x"TENDSTR),
+			tags->objectId, oh->type));
+
+	if (tags->objectId != obj->objectId)
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header mismatch objectId %d"TENDSTR),
+			tags->objectId, obj->objectId));
+
+
+	/*
+	 * Check that the object's parent ids match if parentCheck requested.
+	 *
+	 * Tests do not apply to the root object.
+	 */
+
+	if (parentCheck && tags->objectId > 1 && !obj->parent)
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header mismatch parentId %d obj->parent is NULL"TENDSTR),
+			tags->objectId, oh->parentObjectId));
+
+	if (parentCheck && obj->parent &&
+			oh->parentObjectId != obj->parent->objectId &&
+			(oh->parentObjectId != YAFFS_OBJECTID_UNLINKED ||
+			obj->parent->objectId != YAFFS_OBJECTID_DELETED))
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header mismatch parentId %d parentObjectId %d"TENDSTR),
+			tags->objectId, oh->parentObjectId, obj->parent->objectId));
+
+	if (tags->objectId > 1 && oh->name[0] == 0) /* Null name */
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header name is NULL"TENDSTR),
+			obj->objectId));
+
+	if (tags->objectId > 1 && ((__u8)(oh->name[0])) == 0xff) /* Trashed name */
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header name is 0xFF"TENDSTR),
+			obj->objectId));
+}
+
+
+
+static int yaffs_VerifyTnodeWorker(yaffs_Object *obj, yaffs_Tnode *tn,
+					__u32 level, int chunkOffset)
+{
+	int i;
+	yaffs_Device *dev = obj->myDev;
+	int ok = 1;
+
+	if (tn) {
+		if (level > 0) {
+
+			for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) {
+				if (tn->internal[i]) {
+					ok = yaffs_VerifyTnodeWorker(obj,
+							tn->internal[i],
+							level - 1,
+							(chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
+				}
+			}
+		} else if (level == 0) {
+			yaffs_ExtendedTags tags;
+			__u32 objectId = obj->objectId;
+
+			chunkOffset <<=  YAFFS_TNODES_LEVEL0_BITS;
+
+			for (i = 0; i < YAFFS_NTNODES_LEVEL0; i++) {
+				__u32 theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+
+				if (theChunk > 0) {
+					/* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),tags.objectId,tags.chunkId,theChunk)); */
+					yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL, &tags);
+					if (tags.objectId != objectId || tags.chunkId != chunkOffset) {
+						T(~0, (TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
+							objectId, chunkOffset, theChunk,
+							tags.objectId, tags.chunkId));
+					}
+				}
+				chunkOffset++;
+			}
+		}
+	}
+
+	return ok;
+
+}
+
+
+static void yaffs_VerifyFile(yaffs_Object *obj)
+{
+	int requiredTallness;
+	int actualTallness;
+	__u32 lastChunk;
+	__u32 x;
+	__u32 i;
+	yaffs_Device *dev;
+	yaffs_ExtendedTags tags;
+	yaffs_Tnode *tn;
+	__u32 objectId;
+
+	if (!obj)
+		return;
+
+	if (yaffs_SkipVerification(obj->myDev))
+		return;
+
+	dev = obj->myDev;
+	objectId = obj->objectId;
+
+	/* Check file size is consistent with tnode depth */
+	lastChunk =  obj->variant.fileVariant.fileSize / dev->nDataBytesPerChunk + 1;
+	x = lastChunk >> YAFFS_TNODES_LEVEL0_BITS;
+	requiredTallness = 0;
+	while (x > 0) {
+		x >>= YAFFS_TNODES_INTERNAL_BITS;
+		requiredTallness++;
+	}
+
+	actualTallness = obj->variant.fileVariant.topLevel;
+
+	/* Check that the chunks in the tnode tree are all correct.
+	 * We do this by scanning through the tnode tree and
+	 * checking the tags for every chunk match.
+	 */
+
+	if (yaffs_SkipNANDVerification(dev))
+		return;
+
+	for (i = 1; i <= lastChunk; i++) {
+		tn = yaffs_FindLevel0Tnode(dev, &obj->variant.fileVariant, i);
+
+		if (tn) {
+			__u32 theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+			if (theChunk > 0) {
+				/* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),objectId,i,theChunk)); */
+				yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL, &tags);
+				if (tags.objectId != objectId || tags.chunkId != i) {
+					T(~0, (TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
+						objectId, i, theChunk,
+						tags.objectId, tags.chunkId));
+				}
+			}
+		}
+	}
+}
+
+
+static void yaffs_VerifyHardLink(yaffs_Object *obj)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+
+	/* Verify sane equivalent object */
+}
+
+static void yaffs_VerifySymlink(yaffs_Object *obj)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+
+	/* Verify symlink string */
+}
+
+static void yaffs_VerifySpecial(yaffs_Object *obj)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+}
+
+static void yaffs_VerifyObject(yaffs_Object *obj)
+{
+	yaffs_Device *dev;
+
+	__u32 chunkMin;
+	__u32 chunkMax;
+
+	__u32 chunkIdOk;
+	__u32 chunkInRange;
+	__u32 chunkShouldNotBeDeleted;
+	__u32 chunkValid;
+
+	if (!obj)
+		return;
+
+	if (obj->beingCreated)
+		return;
+
+	dev = obj->myDev;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	/* Check sane object header chunk */
+
+	chunkMin = dev->internalStartBlock * dev->param.nChunksPerBlock;
+	chunkMax = (dev->internalEndBlock+1) * dev->param.nChunksPerBlock - 1;
+
+	chunkInRange = (((unsigned)(obj->hdrChunk)) >= chunkMin && ((unsigned)(obj->hdrChunk)) <= chunkMax);
+	chunkIdOk = chunkInRange || (obj->hdrChunk == 0);
+	chunkValid = chunkInRange &&
+			yaffs_CheckChunkBit(dev,
+					obj->hdrChunk / dev->param.nChunksPerBlock,
+					obj->hdrChunk % dev->param.nChunksPerBlock);
+	chunkShouldNotBeDeleted = chunkInRange && !chunkValid;
+
+	if (!obj->fake &&
+			(!chunkIdOk || chunkShouldNotBeDeleted)) {
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d has chunkId %d %s %s"TENDSTR),
+			obj->objectId, obj->hdrChunk,
+			chunkIdOk ? "" : ",out of range",
+			chunkShouldNotBeDeleted ? ",marked as deleted" : ""));
+	}
+
+	if (chunkValid && !yaffs_SkipNANDVerification(dev)) {
+		yaffs_ExtendedTags tags;
+		yaffs_ObjectHeader *oh;
+		__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+		oh = (yaffs_ObjectHeader *)buffer;
+
+		yaffs_ReadChunkWithTagsFromNAND(dev, obj->hdrChunk, buffer,
+				&tags);
+
+		yaffs_VerifyObjectHeader(obj, oh, &tags, 1);
+
+		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+	}
+
+	/* Verify it has a parent */
+	if (obj && !obj->fake &&
+			(!obj->parent || obj->parent->myDev != dev)) {
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d has parent pointer %p which does not look like an object"TENDSTR),
+			obj->objectId, obj->parent));
+	}
+
+	/* Verify parent is a directory */
+	if (obj->parent && obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d's parent is not a directory (type %d)"TENDSTR),
+			obj->objectId, obj->parent->variantType));
+	}
+
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		yaffs_VerifyFile(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		yaffs_VerifySymlink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		yaffs_VerifyDirectory(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		yaffs_VerifyHardLink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		yaffs_VerifySpecial(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+	default:
+		T(YAFFS_TRACE_VERIFY,
+		(TSTR("Obj %d has illegaltype %d"TENDSTR),
+		obj->objectId, obj->variantType));
+		break;
+	}
+}
+
+static void yaffs_VerifyObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	int i;
+	struct ylist_head *lh;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	/* Iterate through the objects in each hash entry */
+
+	for (i = 0; i <  YAFFS_NOBJECT_BUCKETS; i++) {
+		ylist_for_each(lh, &dev->objectBucket[i].list) {
+			if (lh) {
+				obj = ylist_entry(lh, yaffs_Object, hashLink);
+				yaffs_VerifyObject(obj);
+			}
+		}
+	}
+}
+
+
+/*
+ *  Simple hash function. Needs to have a reasonable spread
+ */
+
+static Y_INLINE int yaffs_HashFunction(int n)
+{
+	n = abs(n);
+	return n % YAFFS_NOBJECT_BUCKETS;
+}
+
+/*
+ * Access functions to useful fake objects.
+ * Note that root might have a presence in NAND if permissions are set.
+ */
+
+yaffs_Object *yaffs_Root(yaffs_Device *dev)
+{
+	return dev->rootDir;
+}
+
+yaffs_Object *yaffs_LostNFound(yaffs_Device *dev)
+{
+	return dev->lostNFoundDir;
+}
+
+
+/*
+ *  Erased NAND checking functions
+ */
+
+int yaffs_CheckFF(__u8 *buffer, int nBytes)
+{
+	/* Horrible, slow implementation */
+	while (nBytes--) {
+		if (*buffer != 0xFF)
+			return 0;
+		buffer++;
+	}
+	return 1;
+}
+
+static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
+				int chunkInNAND)
+{
+	int retval = YAFFS_OK;
+	__u8 *data = yaffs_GetTempBuffer(dev, __LINE__);
+	yaffs_ExtendedTags tags;
+	int result;
+
+	result = yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags);
+
+	if (tags.eccResult > YAFFS_ECC_RESULT_NO_ERROR)
+		retval = YAFFS_FAIL;
+
+	if (!yaffs_CheckFF(data, dev->nDataBytesPerChunk) || tags.chunkUsed) {
+		T(YAFFS_TRACE_NANDACCESS,
+		  (TSTR("Chunk %d not erased" TENDSTR), chunkInNAND));
+		retval = YAFFS_FAIL;
+	}
+
+	yaffs_ReleaseTempBuffer(dev, data, __LINE__);
+
+	return retval;
+
+}
+
+
+static int yaffs_VerifyChunkWritten(yaffs_Device *dev,
+					int chunkInNAND,
+					const __u8 *data,
+					yaffs_ExtendedTags *tags)
+{
+	int retval = YAFFS_OK;
+	yaffs_ExtendedTags tempTags;
+	__u8 *buffer = yaffs_GetTempBuffer(dev,__LINE__);
+	int result;
+	
+	result = yaffs_ReadChunkWithTagsFromNAND(dev,chunkInNAND,buffer,&tempTags);
+	if(memcmp(buffer,data,dev->nDataBytesPerChunk) ||
+		tempTags.objectId != tags->objectId ||
+		tempTags.chunkId  != tags->chunkId ||
+		tempTags.byteCount != tags->byteCount)
+		retval = YAFFS_FAIL;
+
+	yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+
+	return retval;
+}
+
+static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
+					const __u8 *data,
+					yaffs_ExtendedTags *tags,
+					int useReserve)
+{
+	int attempts = 0;
+	int writeOk = 0;
+	int chunk;
+
+	yaffs_InvalidateCheckpoint(dev);
+
+	do {
+		yaffs_BlockInfo *bi = 0;
+		int erasedOk = 0;
+
+		chunk = yaffs_AllocateChunk(dev, useReserve, &bi);
+		if (chunk < 0) {
+			/* no space */
+			break;
+		}
+
+		/* First check this chunk is erased, if it needs
+		 * checking.  The checking policy (unless forced
+		 * always on) is as follows:
+		 *
+		 * Check the first page we try to write in a block.
+		 * If the check passes then we don't need to check any
+		 * more.	If the check fails, we check again...
+		 * If the block has been erased, we don't need to check.
+		 *
+		 * However, if the block has been prioritised for gc,
+		 * then we think there might be something odd about
+		 * this block and stop using it.
+		 *
+		 * Rationale: We should only ever see chunks that have
+		 * not been erased if there was a partially written
+		 * chunk due to power loss.  This checking policy should
+		 * catch that case with very few checks and thus save a
+		 * lot of checks that are most likely not needed.
+		 *
+		 * Mods to the above
+		 * If an erase check fails or the write fails we skip the 
+		 * rest of the block.
+		 */
+
+		/* let's give it a try */
+		attempts++;
+
+#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED
+		bi->skipErasedCheck = 0;
+#endif
+		if (!bi->skipErasedCheck) {
+			erasedOk = yaffs_CheckChunkErased(dev, chunk);
+			if (erasedOk != YAFFS_OK) {
+				T(YAFFS_TRACE_ERROR,
+				(TSTR("**>> yaffs chunk %d was not erased"
+				TENDSTR), chunk));
+
+				/* If not erased, delete this one,
+				 * skip rest of block and
+				 * try another chunk */
+				 yaffs_DeleteChunk(dev,chunk,1,__LINE__);
+				 yaffs_SkipRestOfBlock(dev);
+				continue;
+			}
+		}
+
+		writeOk = yaffs_WriteChunkWithTagsToNAND(dev, chunk,
+				data, tags);
+
+		if(!bi->skipErasedCheck)
+			writeOk = yaffs_VerifyChunkWritten(dev, chunk, data, tags);
+
+		if (writeOk != YAFFS_OK) {
+			/* Clean up aborted write, skip to next block and
+			 * try another chunk */
+			yaffs_HandleWriteChunkError(dev, chunk, erasedOk);
+			continue;
+		}
+
+		bi->skipErasedCheck = 1;
+
+		/* Copy the data into the robustification buffer */
+		yaffs_HandleWriteChunkOk(dev, chunk, data, tags);
+
+	} while (writeOk != YAFFS_OK &&
+		(yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts));
+
+	if (!writeOk)
+		chunk = -1;
+
+	if (attempts > 1) {
+		T(YAFFS_TRACE_ERROR,
+			(TSTR("**>> yaffs write required %d attempts" TENDSTR),
+			attempts));
+
+		dev->nRetriedWrites += (attempts - 1);
+	}
+
+	return chunk;
+}
+
+
+/*
+ * Oldest Dirty Sequence Number handling.
+ */
+ 
+/* yaffs_CalcOldestDirtySequence()
+ * yaffs_FindOldestDirtySequence()
+ * Calculate the oldest dirty sequence number if we don't know it.
+ */
+static int yaffs_CalcOldestDirtySequence(yaffs_Device *dev)
+{
+	int i;
+	__u32 seq;
+	yaffs_BlockInfo *b;
+
+	if(!dev->param.isYaffs2)
+		return 0;
+
+	/* Find the oldest dirty sequence number. */
+	seq = dev->sequenceNumber;
+	b = dev->blockInfo;
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		if (b->blockState == YAFFS_BLOCK_STATE_FULL &&
+		    (b->pagesInUse - b->softDeletions) < dev->param.nChunksPerBlock &&
+		    b->sequenceNumber < seq) 
+				seq = b->sequenceNumber;
+		b++;
+	}
+	return seq;
+}
+
+
+static void yaffs_FindOldestDirtySequence(yaffs_Device *dev)
+{
+	if(dev->param.isYaffs2 && !dev->oldestDirtySequence)
+		dev->oldestDirtySequence = 
+			yaffs_CalcOldestDirtySequence(dev);
+
+#if 0
+	if(!yaffs_SkipVerification(dev) &&
+		dev->oldestDirtySequence != yaffs_CalcOldestDirtySequence(dev))
+		YBUG();
+
+#endif
+}
+
+/*
+ * yaffs_ClearOldestDirtySequence()
+ * Called when a block is erased or marked bad. (ie. when its sequenceNumber
+ * becomes invalid). If the value matches the oldest then we clear 
+ * dev->oldestDirtySequence to force its recomputation.
+ */
+static void yaffs_ClearOldestDirtySequence(yaffs_Device *dev, yaffs_BlockInfo *bi)
+{
+
+	if(!dev->param.isYaffs2)
+		return;
+
+	if(!bi || bi->sequenceNumber == dev->oldestDirtySequence)
+		dev->oldestDirtySequence = 0;
+}
+
+/*
+ * yaffs_UpdateOldestDirtySequence()
+ * Update the oldest dirty sequence number whenever we dirty a block.
+ * Only do this if the oldestDirtySequence is actually being tracked.
+ */
+static void yaffs_UpdateOldestDirtySequence(yaffs_Device *dev, yaffs_BlockInfo *bi)
+{
+	if(dev->param.isYaffs2 && dev->oldestDirtySequence){
+		if(dev->oldestDirtySequence > bi->sequenceNumber)
+			dev->oldestDirtySequence = bi->sequenceNumber;
+	}
+}
+ 
+/*
+ * Block retiring for handling a broken block.
+ */
+
+static void yaffs_RetireBlock(yaffs_Device *dev, int blockInNAND)
+{
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
+
+	yaffs_InvalidateCheckpoint(dev);
+	
+	yaffs_ClearOldestDirtySequence(dev,bi);
+
+	if (yaffs_MarkBlockBad(dev, blockInNAND) != YAFFS_OK) {
+		if (yaffs_EraseBlockInNAND(dev, blockInNAND) != YAFFS_OK) {
+			T(YAFFS_TRACE_ALWAYS, (TSTR(
+				"yaffs: Failed to mark bad and erase block %d"
+				TENDSTR), blockInNAND));
+		} else {
+			yaffs_ExtendedTags tags;
+			int chunkId = blockInNAND * dev->param.nChunksPerBlock;
+
+			__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+			memset(buffer, 0xff, dev->nDataBytesPerChunk);
+			yaffs_InitialiseTags(&tags);
+			tags.sequenceNumber = YAFFS_SEQUENCE_BAD_BLOCK;
+			if (dev->param.writeChunkWithTagsToNAND(dev, chunkId -
+				dev->chunkOffset, buffer, &tags) != YAFFS_OK)
+				T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Failed to "
+					TCONT("write bad block marker to block %d")
+					TENDSTR), blockInNAND));
+
+			yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+		}
+	}
+
+	bi->blockState = YAFFS_BLOCK_STATE_DEAD;
+	bi->gcPrioritise = 0;
+	bi->needsRetiring = 0;
+
+	dev->nRetiredBlocks++;
+}
+
+/*
+ * Functions for robustisizing TODO
+ *
+ */
+
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				const __u8 *data,
+				const yaffs_ExtendedTags *tags)
+{
+	dev=dev;
+	chunkInNAND=chunkInNAND;
+	data=data;
+	tags=tags;
+}
+
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				const yaffs_ExtendedTags *tags)
+{
+	dev=dev;
+	chunkInNAND=chunkInNAND;
+	tags=tags;
+}
+
+void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi)
+{
+	if (!bi->gcPrioritise) {
+		bi->gcPrioritise = 1;
+		dev->hasPendingPrioritisedGCs = 1;
+		bi->chunkErrorStrikes++;
+
+		if (bi->chunkErrorStrikes > 3) {
+			bi->needsRetiring = 1; /* Too many stikes, so retire this */
+			T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Block struck out" TENDSTR)));
+
+		}
+	}
+}
+
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND,
+		int erasedOk)
+{
+	int blockInNAND = chunkInNAND / dev->param.nChunksPerBlock;
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
+
+	yaffs_HandleChunkError(dev, bi);
+
+	if (erasedOk) {
+		/* Was an actual write failure, so mark the block for retirement  */
+		bi->needsRetiring = 1;
+		T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+		  (TSTR("**>> Block %d needs retiring" TENDSTR), blockInNAND));
+	}
+
+	/* Delete the chunk */
+	yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+	yaffs_SkipRestOfBlock(dev);
+}
+
+
+/*---------------- Name handling functions ------------*/
+
+static __u16 yaffs_CalcNameSum(const YCHAR *name)
+{
+	__u16 sum = 0;
+	__u16 i = 1;
+
+	const YUCHAR *bname = (const YUCHAR *) name;
+	if (bname) {
+		while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH/2))) {
+
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+			sum += yaffs_toupper(*bname) * i;
+#else
+			sum += (*bname) * i;
+#endif
+			i++;
+			bname++;
+		}
+	}
+	return sum;
+}
+
+static void yaffs_SetObjectName(yaffs_Object *obj, const YCHAR *name)
+{
+#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+	memset(obj->shortName, 0, sizeof(YCHAR) * (YAFFS_SHORT_NAME_LENGTH+1));
+	if (name && yaffs_strnlen(name,YAFFS_SHORT_NAME_LENGTH+1) <= YAFFS_SHORT_NAME_LENGTH)
+		yaffs_strcpy(obj->shortName, name);
+	else
+		obj->shortName[0] = _Y('\0');
+#endif
+	obj->sum = yaffs_CalcNameSum(name);
+}
+
+/*-------------------- TNODES -------------------
+
+ * List of spare tnodes
+ * The list is hooked together using the first pointer
+ * in the tnode.
+ */
+
+/* yaffs_CreateTnodes creates a bunch more tnodes and
+ * adds them to the tnode free list.
+ * Don't use this function directly
+ */
+static Y_INLINE int yaffs_CalcTnodeSize(yaffs_Device *dev)
+{
+	int tnodeSize;
+	/* Calculate the tnode size in bytes for variable width tnode support.
+	 * Must be a multiple of 32-bits  */
+	tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
+
+	if (tnodeSize < sizeof(yaffs_Tnode))
+		tnodeSize = sizeof(yaffs_Tnode);
+	return tnodeSize;
+}
+
+static int yaffs_CreateTnodes(yaffs_Device *dev, int nTnodes)
+{
+	int i;
+	int tnodeSize = yaffs_CalcTnodeSize(dev);
+	yaffs_Tnode *newTnodes;
+	__u8 *mem;
+	yaffs_Tnode *curr;
+	yaffs_Tnode *next;
+	yaffs_TnodeList *tnl;
+
+	if (nTnodes < 1)
+		return YAFFS_OK;
+
+
+	/* make these things */
+
+	newTnodes = YMALLOC(nTnodes * tnodeSize);
+	mem = (__u8 *)newTnodes;
+
+	if (!newTnodes) {
+		T(YAFFS_TRACE_ERROR,
+			(TSTR("yaffs: Could not allocate Tnodes" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Hook them into the free list */
+#if 0
+	for (i = 0; i < nTnodes - 1; i++) {
+		newTnodes[i].internal[0] = &newTnodes[i + 1];
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+		newTnodes[i].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
+#endif
+	}
+
+	newTnodes[nTnodes - 1].internal[0] = dev->freeTnodes;
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+	newTnodes[nTnodes - 1].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
+#endif
+	dev->freeTnodes = newTnodes;
+#else
+	/* New hookup for wide tnodes */
+	for (i = 0; i < nTnodes - 1; i++) {
+		curr = (yaffs_Tnode *) &mem[i * tnodeSize];
+		next = (yaffs_Tnode *) &mem[(i+1) * tnodeSize];
+		curr->internal[0] = next;
+	}
+
+	curr = (yaffs_Tnode *) &mem[(nTnodes - 1) * tnodeSize];
+	curr->internal[0] = dev->freeTnodes;
+	dev->freeTnodes = (yaffs_Tnode *)mem;
+
+#endif
+
+
+	dev->nFreeTnodes += nTnodes;
+	dev->nTnodesCreated += nTnodes;
+
+	/* Now add this bunch of tnodes to a list for freeing up.
+	 * NB If we can't add this to the management list it isn't fatal
+	 * but it just means we can't free this bunch of tnodes later.
+	 */
+
+	tnl = YMALLOC(sizeof(yaffs_TnodeList));
+	if (!tnl) {
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("yaffs: Could not add tnodes to management list" TENDSTR)));
+		   return YAFFS_FAIL;
+	} else {
+		tnl->tnodes = newTnodes;
+		tnl->next = dev->allocatedTnodeList;
+		dev->allocatedTnodeList = tnl;
+	}
+
+	T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR)));
+
+	return YAFFS_OK;
+}
+
+/* GetTnode gets us a clean tnode. Tries to make allocate more if we run out */
+
+static yaffs_Tnode *yaffs_GetTnodeRaw(yaffs_Device *dev)
+{
+	yaffs_Tnode *tn = NULL;
+
+#ifdef CONFIG_YAFFS_VALGRIND_TEST
+	tn = YMALLOC(yaffs_CalcTnodeSize(dev));
+	if(tn)
+		dev->nTnodesCreated++;
+#else
+	/* If there are none left make more */
+	if (!dev->freeTnodes)
+		yaffs_CreateTnodes(dev, YAFFS_ALLOCATION_NTNODES);
+
+	if (dev->freeTnodes) {
+		tn = dev->freeTnodes;
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+		if (tn->internal[YAFFS_NTNODES_INTERNAL] != (void *)1) {
+			/* Hoosterman, this thing looks like it isn't in the list */
+			T(YAFFS_TRACE_ALWAYS,
+			  (TSTR("yaffs: Tnode list bug 1" TENDSTR)));
+		}
+#endif
+		dev->freeTnodes = dev->freeTnodes->internal[0];
+		dev->nFreeTnodes--;
+	}
+#endif
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+
+	return tn;
+}
+
+static yaffs_Tnode *yaffs_GetTnode(yaffs_Device *dev)
+{
+	yaffs_Tnode *tn = yaffs_GetTnodeRaw(dev);
+	int tnodeSize = yaffs_CalcTnodeSize(dev);
+
+	if (tn)
+		memset(tn, 0, tnodeSize);
+
+	return tn;
+}
+
+/* FreeTnode frees up a tnode and puts it back on the free list */
+static void yaffs_FreeTnode(yaffs_Device *dev, yaffs_Tnode *tn)
+{
+	if (tn) {
+#ifdef CONFIG_YAFFS_VALGRIND_TEST
+		YFREE(tn);
+		dev->nTnodesCreated--;
+#else
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+		if (tn->internal[YAFFS_NTNODES_INTERNAL] != 0) {
+			/* Hoosterman, this thing looks like it is already in the list */
+			T(YAFFS_TRACE_ALWAYS,
+			  (TSTR("yaffs: Tnode list bug 2" TENDSTR)));
+		}
+		tn->internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
+#endif
+		tn->internal[0] = dev->freeTnodes;
+		dev->freeTnodes = tn;
+		dev->nFreeTnodes++;
+#endif
+	}
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+}
+
+static void yaffs_DeinitialiseTnodes(yaffs_Device *dev)
+{
+	/* Free the list of allocated tnodes */
+	yaffs_TnodeList *tmp;
+
+	while (dev->allocatedTnodeList) {
+		tmp = dev->allocatedTnodeList->next;
+
+		YFREE(dev->allocatedTnodeList->tnodes);
+		YFREE(dev->allocatedTnodeList);
+		dev->allocatedTnodeList = tmp;
+
+	}
+
+	dev->freeTnodes = NULL;
+	dev->nFreeTnodes = 0;
+	dev->nTnodesCreated = 0;
+}
+
+static void yaffs_InitialiseTnodes(yaffs_Device *dev)
+{
+	dev->allocatedTnodeList = NULL;
+	dev->freeTnodes = NULL;
+	dev->nFreeTnodes = 0;
+	dev->nTnodesCreated = 0;
+}
+
+
+void yaffs_LoadLevel0Tnode(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos,
+		unsigned val)
+{
+	__u32 *map = (__u32 *)tn;
+	__u32 bitInMap;
+	__u32 bitInWord;
+	__u32 wordInMap;
+	__u32 mask;
+
+	pos &= YAFFS_TNODES_LEVEL0_MASK;
+	val >>= dev->chunkGroupBits;
+
+	bitInMap = pos * dev->tnodeWidth;
+	wordInMap = bitInMap / 32;
+	bitInWord = bitInMap & (32 - 1);
+
+	mask = dev->tnodeMask << bitInWord;
+
+	map[wordInMap] &= ~mask;
+	map[wordInMap] |= (mask & (val << bitInWord));
+
+	if (dev->tnodeWidth > (32 - bitInWord)) {
+		bitInWord = (32 - bitInWord);
+		wordInMap++;;
+		mask = dev->tnodeMask >> (/*dev->tnodeWidth -*/ bitInWord);
+		map[wordInMap] &= ~mask;
+		map[wordInMap] |= (mask & (val >> bitInWord));
+	}
+}
+
+static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn,
+		unsigned pos)
+{
+	__u32 *map = (__u32 *)tn;
+	__u32 bitInMap;
+	__u32 bitInWord;
+	__u32 wordInMap;
+	__u32 val;
+
+	pos &= YAFFS_TNODES_LEVEL0_MASK;
+
+	bitInMap = pos * dev->tnodeWidth;
+	wordInMap = bitInMap / 32;
+	bitInWord = bitInMap & (32 - 1);
+
+	val = map[wordInMap] >> bitInWord;
+
+	if	(dev->tnodeWidth > (32 - bitInWord)) {
+		bitInWord = (32 - bitInWord);
+		wordInMap++;;
+		val |= (map[wordInMap] << bitInWord);
+	}
+
+	val &= dev->tnodeMask;
+	val <<= dev->chunkGroupBits;
+
+	return val;
+}
+
+/* ------------------- End of individual tnode manipulation -----------------*/
+
+/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------
+ * The look up tree is represented by the top tnode and the number of topLevel
+ * in the tree. 0 means only the level 0 tnode is in the tree.
+ */
+
+/* FindLevel0Tnode finds the level 0 tnode, if one exists. */
+static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device *dev,
+					yaffs_FileStructure *fStruct,
+					__u32 chunkId)
+{
+	yaffs_Tnode *tn = fStruct->top;
+	__u32 i;
+	int requiredTallness;
+	int level = fStruct->topLevel;
+
+	dev=dev;
+
+	/* Check sane level and chunk Id */
+	if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL)
+		return NULL;
+
+	if (chunkId > YAFFS_MAX_CHUNK_ID)
+		return NULL;
+
+	/* First check we're tall enough (ie enough topLevel) */
+
+	i = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
+	requiredTallness = 0;
+	while (i) {
+		i >>= YAFFS_TNODES_INTERNAL_BITS;
+		requiredTallness++;
+	}
+
+	if (requiredTallness > fStruct->topLevel)
+		return NULL; /* Not tall enough, so we can't find it */
+
+	/* Traverse down to level 0 */
+	while (level > 0 && tn) {
+		tn = tn->internal[(chunkId >>
+			(YAFFS_TNODES_LEVEL0_BITS +
+				(level - 1) *
+				YAFFS_TNODES_INTERNAL_BITS)) &
+			YAFFS_TNODES_INTERNAL_MASK];
+		level--;
+	}
+
+	return tn;
+}
+
+/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree.
+ * This happens in two steps:
+ *  1. If the tree isn't tall enough, then make it taller.
+ *  2. Scan down the tree towards the level 0 tnode adding tnodes if required.
+ *
+ * Used when modifying the tree.
+ *
+ *  If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will
+ *  be plugged into the ttree.
+ */
+
+static yaffs_Tnode *yaffs_AddOrFindLevel0Tnode(yaffs_Device *dev,
+					yaffs_FileStructure *fStruct,
+					__u32 chunkId,
+					yaffs_Tnode *passedTn)
+{
+	int requiredTallness;
+	int i;
+	int l;
+	yaffs_Tnode *tn;
+
+	__u32 x;
+
+
+	/* Check sane level and page Id */
+	if (fStruct->topLevel < 0 || fStruct->topLevel > YAFFS_TNODES_MAX_LEVEL)
+		return NULL;
+
+	if (chunkId > YAFFS_MAX_CHUNK_ID)
+		return NULL;
+
+	/* First check we're tall enough (ie enough topLevel) */
+
+	x = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
+	requiredTallness = 0;
+	while (x) {
+		x >>= YAFFS_TNODES_INTERNAL_BITS;
+		requiredTallness++;
+	}
+
+
+	if (requiredTallness > fStruct->topLevel) {
+		/* Not tall enough, gotta make the tree taller */
+		for (i = fStruct->topLevel; i < requiredTallness; i++) {
+
+			tn = yaffs_GetTnode(dev);
+
+			if (tn) {
+				tn->internal[0] = fStruct->top;
+				fStruct->top = tn;
+				fStruct->topLevel++;
+			} else {
+				T(YAFFS_TRACE_ERROR,
+					(TSTR("yaffs: no more tnodes" TENDSTR)));
+				return NULL;
+			}
+		}
+	}
+
+	/* Traverse down to level 0, adding anything we need */
+
+	l = fStruct->topLevel;
+	tn = fStruct->top;
+
+	if (l > 0) {
+		while (l > 0 && tn) {
+			x = (chunkId >>
+			     (YAFFS_TNODES_LEVEL0_BITS +
+			      (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) &
+			    YAFFS_TNODES_INTERNAL_MASK;
+
+
+			if ((l > 1) && !tn->internal[x]) {
+				/* Add missing non-level-zero tnode */
+				tn->internal[x] = yaffs_GetTnode(dev);
+				if(!tn->internal[x])
+					return NULL;
+			} else if (l == 1) {
+				/* Looking from level 1 at level 0 */
+				if (passedTn) {
+					/* If we already have one, then release it.*/
+					if (tn->internal[x])
+						yaffs_FreeTnode(dev, tn->internal[x]);
+					tn->internal[x] = passedTn;
+
+				} else if (!tn->internal[x]) {
+					/* Don't have one, none passed in */
+					tn->internal[x] = yaffs_GetTnode(dev);
+					if(!tn->internal[x])
+						return NULL;
+				}
+			}
+
+			tn = tn->internal[x];
+			l--;
+		}
+	} else {
+		/* top is level 0 */
+		if (passedTn) {
+			memcpy(tn, passedTn, (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8);
+			yaffs_FreeTnode(dev, passedTn);
+		}
+	}
+
+	return tn;
+}
+
+static int yaffs_FindChunkInGroup(yaffs_Device *dev, int theChunk,
+				yaffs_ExtendedTags *tags, int objectId,
+				int chunkInInode)
+{
+	int j;
+
+	for (j = 0; theChunk && j < dev->chunkGroupSize; j++) {
+		if (yaffs_CheckChunkBit(dev, theChunk / dev->param.nChunksPerBlock,
+				theChunk % dev->param.nChunksPerBlock)) {
+			
+			if(dev->chunkGroupSize == 1)
+				return theChunk;
+			else {
+				yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL,
+								tags);
+				if (yaffs_TagsMatch(tags, objectId, chunkInInode)) {
+					/* found it; */
+					return theChunk;
+				}
+			}
+		}
+		theChunk++;
+	}
+	return -1;
+}
+
+
+/* DeleteWorker scans backwards through the tnode tree and deletes all the
+ * chunks and tnodes in the file
+ * Returns 1 if the tree was deleted.
+ * Returns 0 if it stopped early due to hitting the limit and the delete is incomplete.
+ */
+
+static int yaffs_DeleteWorker(yaffs_Object *in, yaffs_Tnode *tn, __u32 level,
+			      int chunkOffset, int *limit)
+{
+	int i;
+	int chunkInInode;
+	int theChunk;
+	yaffs_ExtendedTags tags;
+	int foundChunk;
+	yaffs_Device *dev = in->myDev;
+
+	int allDone = 1;
+
+	if (tn) {
+		if (level > 0) {
+			for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
+			     i--) {
+				if (tn->internal[i]) {
+					if (limit && (*limit) < 0) {
+						allDone = 0;
+					} else {
+						allDone =
+							yaffs_DeleteWorker(in,
+								tn->
+								internal
+								[i],
+								level -
+								1,
+								(chunkOffset
+									<<
+									YAFFS_TNODES_INTERNAL_BITS)
+								+ i,
+								limit);
+					}
+					if (allDone) {
+						yaffs_FreeTnode(dev,
+								tn->
+								internal[i]);
+						tn->internal[i] = NULL;
+					}
+				}
+			}
+			return (allDone) ? 1 : 0;
+		} else if (level == 0) {
+			int hitLimit = 0;
+
+			for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0 && !hitLimit;
+					i--) {
+				theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+				if (theChunk) {
+
+					chunkInInode = (chunkOffset <<
+						YAFFS_TNODES_LEVEL0_BITS) + i;
+
+					foundChunk =
+						yaffs_FindChunkInGroup(dev,
+								theChunk,
+								&tags,
+								in->objectId,
+								chunkInInode);
+
+					if (foundChunk > 0) {
+						yaffs_DeleteChunk(dev,
+								  foundChunk, 1,
+								  __LINE__);
+						in->nDataChunks--;
+						if (limit) {
+							*limit = *limit - 1;
+							if (*limit <= 0)
+								hitLimit = 1;
+						}
+
+					}
+
+					yaffs_LoadLevel0Tnode(dev, tn, i, 0);
+				}
+
+			}
+			return (i < 0) ? 1 : 0;
+
+		}
+
+	}
+
+	return 1;
+
+}
+
+static void yaffs_SoftDeleteChunk(yaffs_Device *dev, int chunk)
+{
+	yaffs_BlockInfo *theBlock;
+
+	T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk));
+
+	theBlock = yaffs_GetBlockInfo(dev, chunk / dev->param.nChunksPerBlock);
+	if (theBlock) {
+		theBlock->softDeletions++;
+		dev->nFreeChunks++;
+		yaffs_UpdateOldestDirtySequence(dev,theBlock);
+	}
+}
+
+/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file.
+ * All soft deleting does is increment the block's softdelete count and pulls the chunk out
+ * of the tnode.
+ * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted.
+ */
+
+static int yaffs_SoftDeleteWorker(yaffs_Object *in, yaffs_Tnode *tn,
+				  __u32 level, int chunkOffset)
+{
+	int i;
+	int theChunk;
+	int allDone = 1;
+	yaffs_Device *dev = in->myDev;
+
+	if (tn) {
+		if (level > 0) {
+
+			for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
+			     i--) {
+				if (tn->internal[i]) {
+					allDone =
+					    yaffs_SoftDeleteWorker(in,
+								   tn->
+								   internal[i],
+								   level - 1,
+								   (chunkOffset
+								    <<
+								    YAFFS_TNODES_INTERNAL_BITS)
+								   + i);
+					if (allDone) {
+						yaffs_FreeTnode(dev,
+								tn->
+								internal[i]);
+						tn->internal[i] = NULL;
+					} else {
+						/* Hoosterman... how could this happen? */
+					}
+				}
+			}
+			return (allDone) ? 1 : 0;
+		} else if (level == 0) {
+
+			for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) {
+				theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+				if (theChunk) {
+					/* Note this does not find the real chunk, only the chunk group.
+					 * We make an assumption that a chunk group is not larger than
+					 * a block.
+					 */
+					yaffs_SoftDeleteChunk(dev, theChunk);
+					yaffs_LoadLevel0Tnode(dev, tn, i, 0);
+				}
+
+			}
+			return 1;
+
+		}
+
+	}
+
+	return 1;
+
+}
+
+static void yaffs_SoftDeleteFile(yaffs_Object *obj)
+{
+	if (obj->deleted &&
+	    obj->variantType == YAFFS_OBJECT_TYPE_FILE && !obj->softDeleted) {
+		if (obj->nDataChunks <= 0) {
+			/* Empty file with no duplicate object headers, just delete it immediately */
+			yaffs_FreeTnode(obj->myDev,
+					obj->variant.fileVariant.top);
+			obj->variant.fileVariant.top = NULL;
+			T(YAFFS_TRACE_TRACING,
+			  (TSTR("yaffs: Deleting empty file %d" TENDSTR),
+			   obj->objectId));
+			yaffs_DoGenericObjectDeletion(obj);
+		} else {
+			yaffs_SoftDeleteWorker(obj,
+					       obj->variant.fileVariant.top,
+					       obj->variant.fileVariant.
+					       topLevel, 0);
+			obj->softDeleted = 1;
+		}
+	}
+}
+
+/* Pruning removes any part of the file structure tree that is beyond the
+ * bounds of the file (ie that does not point to chunks).
+ *
+ * A file should only get pruned when its size is reduced.
+ *
+ * Before pruning, the chunks must be pulled from the tree and the
+ * level 0 tnode entries must be zeroed out.
+ * Could also use this for file deletion, but that's probably better handled
+ * by a special case.
+ *
+ * This function is recursive. For levels > 0 the function is called again on
+ * any sub-tree. For level == 0 we just check if the sub-tree has data.
+ * If there is no data in a subtree then it is pruned.
+ */
+
+static yaffs_Tnode *yaffs_PruneWorker(yaffs_Device *dev, yaffs_Tnode *tn,
+				__u32 level, int del0)
+{
+	int i;
+	int hasData;
+
+	if (tn) {
+		hasData = 0;
+
+		if(level > 0){
+			for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) {
+				if (tn->internal[i]) {
+					tn->internal[i] =
+						yaffs_PruneWorker(dev, tn->internal[i],
+							level - 1,
+							(i == 0) ? del0 : 1);
+				}
+
+				if (tn->internal[i])
+					hasData++;
+			}
+		} else {
+			int tnodeSize_u32 = yaffs_CalcTnodeSize(dev)/sizeof(__u32);
+			__u32 *map = (__u32 *)tn;
+
+                        for(i = 0; !hasData && i < tnodeSize_u32; i++){
+                                if(map[i])
+                                        hasData++;
+                        }
+                }
+
+		if (hasData == 0 && del0) {
+			/* Free and return NULL */
+
+			yaffs_FreeTnode(dev, tn);
+			tn = NULL;
+		}
+
+	}
+
+	return tn;
+
+}
+
+static int yaffs_PruneFileStructure(yaffs_Device *dev,
+				yaffs_FileStructure *fStruct)
+{
+	int i;
+	int hasData;
+	int done = 0;
+	yaffs_Tnode *tn;
+
+	if (fStruct->topLevel > 0) {
+		fStruct->top =
+		    yaffs_PruneWorker(dev, fStruct->top, fStruct->topLevel, 0);
+
+		/* Now we have a tree with all the non-zero branches NULL but the height
+		 * is the same as it was.
+		 * Let's see if we can trim internal tnodes to shorten the tree.
+		 * We can do this if only the 0th element in the tnode is in use
+		 * (ie all the non-zero are NULL)
+		 */
+
+		while (fStruct->topLevel && !done) {
+			tn = fStruct->top;
+
+			hasData = 0;
+			for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) {
+				if (tn->internal[i])
+					hasData++;
+			}
+
+			if (!hasData) {
+				fStruct->top = tn->internal[0];
+				fStruct->topLevel--;
+				yaffs_FreeTnode(dev, tn);
+			} else {
+				done = 1;
+			}
+		}
+	}
+
+	return YAFFS_OK;
+}
+
+/*-------------------- End of File Structure functions.-------------------*/
+
+/* yaffs_CreateFreeObjects creates a bunch more objects and
+ * adds them to the object free list.
+ */
+static int yaffs_CreateFreeObjects(yaffs_Device *dev, int nObjects)
+{
+	int i;
+	yaffs_Object *newObjects;
+	yaffs_ObjectList *list;
+
+	if (nObjects < 1)
+		return YAFFS_OK;
+
+	/* make these things */
+	newObjects = YMALLOC(nObjects * sizeof(yaffs_Object));
+	list = YMALLOC(sizeof(yaffs_ObjectList));
+
+	if (!newObjects || !list) {
+		if (newObjects){
+			YFREE(newObjects);
+			newObjects = NULL;
+		}
+		if (list){
+			YFREE(list);
+			list = NULL;
+		}
+		T(YAFFS_TRACE_ALLOCATE,
+		  (TSTR("yaffs: Could not allocate more objects" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Hook them into the free list */
+	for (i = 0; i < nObjects - 1; i++) {
+		newObjects[i].siblings.next =
+				(struct ylist_head *)(&newObjects[i + 1]);
+	}
+
+	newObjects[nObjects - 1].siblings.next = (void *)dev->freeObjects;
+	dev->freeObjects = newObjects;
+	dev->nFreeObjects += nObjects;
+	dev->nObjectsCreated += nObjects;
+
+	/* Now add this bunch of Objects to a list for freeing up. */
+
+	list->objects = newObjects;
+	list->next = dev->allocatedObjectList;
+	dev->allocatedObjectList = list;
+
+	return YAFFS_OK;
+}
+
+
+/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */
+static yaffs_Object *yaffs_AllocateEmptyObject(yaffs_Device *dev)
+{
+	yaffs_Object *tn = NULL;
+
+#ifdef CONFIG_YAFFS_VALGRIND_TEST
+	tn = YMALLOC(sizeof(yaffs_Object));
+	if(tn)
+		dev->nObjectsCreated++;
+#else
+	/* If there are none left make more */
+	if (!dev->freeObjects)
+		yaffs_CreateFreeObjects(dev, YAFFS_ALLOCATION_NOBJECTS);
+
+	if (dev->freeObjects) {
+		tn = dev->freeObjects;
+		dev->freeObjects =
+			(yaffs_Object *) (dev->freeObjects->siblings.next);
+		dev->nFreeObjects--;
+	}
+#endif
+	if (tn) {
+		/* Now sweeten it up... */
+
+		memset(tn, 0, sizeof(yaffs_Object));
+		tn->beingCreated = 1;
+
+		tn->myDev = dev;
+		tn->hdrChunk = 0;
+		tn->variantType = YAFFS_OBJECT_TYPE_UNKNOWN;
+		YINIT_LIST_HEAD(&(tn->hardLinks));
+		YINIT_LIST_HEAD(&(tn->hashLink));
+		YINIT_LIST_HEAD(&tn->siblings);
+
+
+		/* Now make the directory sane */
+		if (dev->rootDir) {
+			tn->parent = dev->rootDir;
+			ylist_add(&(tn->siblings), &dev->rootDir->variant.directoryVariant.children);
+		}
+
+		/* Add it to the lost and found directory.
+		 * NB Can't put root or lostNFound in lostNFound so
+		 * check if lostNFound exists first
+		 */
+		if (dev->lostNFoundDir)
+			yaffs_AddObjectToDirectory(dev->lostNFoundDir, tn);
+
+		tn->beingCreated = 0;
+	}
+
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+
+	return tn;
+}
+
+static yaffs_Object *yaffs_CreateFakeDirectory(yaffs_Device *dev, int number,
+					       __u32 mode)
+{
+
+	yaffs_Object *obj =
+	    yaffs_CreateNewObject(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY);
+	if (obj) {
+		obj->fake = 1;		/* it is fake so it might have no NAND presence... */
+		obj->renameAllowed = 0;	/* ... and we're not allowed to rename it... */
+		obj->unlinkAllowed = 0;	/* ... or unlink it */
+		obj->deleted = 0;
+		obj->unlinked = 0;
+		obj->yst_mode = mode;
+		obj->myDev = dev;
+		obj->hdrChunk = 0;	/* Not a valid chunk. */
+	}
+
+	return obj;
+
+}
+
+static void yaffs_UnhashObject(yaffs_Object *tn)
+{
+	int bucket;
+	yaffs_Device *dev = tn->myDev;
+
+	/* If it is still linked into the bucket list, free from the list */
+	if (!ylist_empty(&tn->hashLink)) {
+		ylist_del_init(&tn->hashLink);
+		bucket = yaffs_HashFunction(tn->objectId);
+		dev->objectBucket[bucket].count--;
+	}
+}
+
+/*  FreeObject frees up a Object and puts it back on the free list */
+static void yaffs_FreeObject(yaffs_Object *tn)
+{
+	yaffs_Device *dev = tn->myDev;
+
+	T(YAFFS_TRACE_OS, (TSTR("FreeObject %p inode %p"TENDSTR), tn, tn->myInode));
+
+	if (!tn)
+		YBUG();
+	if (tn->parent)
+		YBUG();
+	if (!ylist_empty(&tn->siblings))
+		YBUG();
+
+
+	if (tn->myInode) {
+		/* We're still hooked up to a cached inode.
+		 * Don't delete now, but mark for later deletion
+		 */
+		tn->deferedFree = 1;
+		return;
+	}
+
+	yaffs_UnhashObject(tn);
+
+#ifdef CONFIG_YAFFS_VALGRIND_TEST
+	YFREE(tn);
+	dev->nObjectsCreated--;
+	tn = NULL;
+#else
+	/* Link into the free list. */
+	tn->siblings.next = (struct ylist_head *)(dev->freeObjects);
+	dev->freeObjects = tn;
+	dev->nFreeObjects++;
+#endif
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+}
+
+
+void yaffs_HandleDeferedFree(yaffs_Object *obj)
+{
+	if (obj->deferedFree)
+		yaffs_FreeObject(obj);
+}
+
+
+static void yaffs_DeinitialiseObjects(yaffs_Device *dev)
+{
+	/* Free the list of allocated Objects */
+
+	yaffs_ObjectList *tmp;
+
+	while (dev->allocatedObjectList) {
+		tmp = dev->allocatedObjectList->next;
+		YFREE(dev->allocatedObjectList->objects);
+		YFREE(dev->allocatedObjectList);
+
+		dev->allocatedObjectList = tmp;
+	}
+
+	dev->freeObjects = NULL;
+	dev->nFreeObjects = 0;
+	dev->nObjectsCreated = 0;
+}
+
+static void yaffs_InitialiseObjects(yaffs_Device *dev)
+{
+	int i;
+
+	dev->allocatedObjectList = NULL;
+	dev->freeObjects = NULL;
+	dev->nFreeObjects = 0;
+
+	for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
+		YINIT_LIST_HEAD(&dev->objectBucket[i].list);
+		dev->objectBucket[i].count = 0;
+	}
+}
+
+static int yaffs_FindNiceObjectBucket(yaffs_Device *dev)
+{
+	int i;
+	int l = 999;
+	int lowest = 999999;
+
+
+	/* Search for the shortest list or one that
+	 * isn't too long.
+	 */
+
+	for (i = 0; i < 10 && lowest > 4; i++) {
+		dev->bucketFinder++;
+		dev->bucketFinder %= YAFFS_NOBJECT_BUCKETS;
+		if (dev->objectBucket[dev->bucketFinder].count < lowest) {
+			lowest = dev->objectBucket[dev->bucketFinder].count;
+			l = dev->bucketFinder;
+		}
+
+	}
+
+	return l;
+}
+
+static int yaffs_CreateNewObjectNumber(yaffs_Device *dev)
+{
+	int bucket = yaffs_FindNiceObjectBucket(dev);
+
+	/* Now find an object value that has not already been taken
+	 * by scanning the list.
+	 */
+
+	int found = 0;
+	struct ylist_head *i;
+
+	__u32 n = (__u32) bucket;
+
+	/* yaffs_CheckObjectHashSanity();  */
+
+	while (!found) {
+		found = 1;
+		n += YAFFS_NOBJECT_BUCKETS;
+		if (1 || dev->objectBucket[bucket].count > 0) {
+			ylist_for_each(i, &dev->objectBucket[bucket].list) {
+				/* If there is already one in the list */
+				if (i && ylist_entry(i, yaffs_Object,
+						hashLink)->objectId == n) {
+					found = 0;
+				}
+			}
+		}
+	}
+
+	return n;
+}
+
+static void yaffs_HashObject(yaffs_Object *in)
+{
+	int bucket = yaffs_HashFunction(in->objectId);
+	yaffs_Device *dev = in->myDev;
+
+	ylist_add(&in->hashLink, &dev->objectBucket[bucket].list);
+	dev->objectBucket[bucket].count++;
+}
+
+yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device *dev, __u32 number)
+{
+	int bucket = yaffs_HashFunction(number);
+	struct ylist_head *i;
+	yaffs_Object *in;
+
+	ylist_for_each(i, &dev->objectBucket[bucket].list) {
+		/* Look if it is in the list */
+		if (i) {
+			in = ylist_entry(i, yaffs_Object, hashLink);
+			if (in->objectId == number) {
+
+				/* Don't tell the VFS about this one if it is defered free */
+				if (in->deferedFree)
+					return NULL;
+
+				return in;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+yaffs_Object *yaffs_CreateNewObject(yaffs_Device *dev, int number,
+				    yaffs_ObjectType type)
+{
+	yaffs_Object *theObject=NULL;
+	yaffs_Tnode *tn = NULL;
+
+	if (number < 0)
+		number = yaffs_CreateNewObjectNumber(dev);
+
+	if (type == YAFFS_OBJECT_TYPE_FILE) {
+		tn = yaffs_GetTnode(dev);
+		if (!tn)
+			return NULL;
+	}
+
+	theObject = yaffs_AllocateEmptyObject(dev);
+	if (!theObject){
+		if(tn)
+			yaffs_FreeTnode(dev,tn);
+		return NULL;
+	}
+
+
+	if (theObject) {
+		theObject->fake = 0;
+		theObject->renameAllowed = 1;
+		theObject->unlinkAllowed = 1;
+		theObject->objectId = number;
+		yaffs_HashObject(theObject);
+		theObject->variantType = type;
+#ifdef CONFIG_YAFFS_WINCE
+		yfsd_WinFileTimeNow(theObject->win_atime);
+		theObject->win_ctime[0] = theObject->win_mtime[0] =
+		    theObject->win_atime[0];
+		theObject->win_ctime[1] = theObject->win_mtime[1] =
+		    theObject->win_atime[1];
+
+#else
+
+		theObject->yst_atime = theObject->yst_mtime =
+		    theObject->yst_ctime = Y_CURRENT_TIME;
+#endif
+		switch (type) {
+		case YAFFS_OBJECT_TYPE_FILE:
+			theObject->variant.fileVariant.fileSize = 0;
+			theObject->variant.fileVariant.scannedFileSize = 0;
+			theObject->variant.fileVariant.shrinkSize = 0xFFFFFFFF;	/* max __u32 */
+			theObject->variant.fileVariant.topLevel = 0;
+			theObject->variant.fileVariant.top = tn;
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			YINIT_LIST_HEAD(&theObject->variant.directoryVariant.
+					children);
+			YINIT_LIST_HEAD(&theObject->variant.directoryVariant.
+					dirty);
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+			/* No action required */
+			break;
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+			/* todo this should not happen */
+			break;
+		}
+	}
+
+	return theObject;
+}
+
+static yaffs_Object *yaffs_FindOrCreateObjectByNumber(yaffs_Device *dev,
+						      int number,
+						      yaffs_ObjectType type)
+{
+	yaffs_Object *theObject = NULL;
+
+	if (number > 0)
+		theObject = yaffs_FindObjectByNumber(dev, number);
+
+	if (!theObject)
+		theObject = yaffs_CreateNewObject(dev, number, type);
+
+	return theObject;
+
+}
+
+
+static YCHAR *yaffs_CloneString(const YCHAR *str)
+{
+	YCHAR *newStr = NULL;
+	int len;
+
+	if (!str)
+		str = _Y("");
+
+	len = yaffs_strnlen(str,YAFFS_MAX_ALIAS_LENGTH);
+	newStr = YMALLOC((len + 1) * sizeof(YCHAR));
+	if (newStr){
+		yaffs_strncpy(newStr, str,len);
+		newStr[len] = 0;
+	}
+	return newStr;
+
+}
+
+/*
+ * Mknod (create) a new object.
+ * equivalentObject only has meaning for a hard link;
+ * aliasString only has meaning for a symlink.
+ * rdev only has meaning for devices (a subset of special objects)
+ */
+
+static yaffs_Object *yaffs_MknodObject(yaffs_ObjectType type,
+				       yaffs_Object *parent,
+				       const YCHAR *name,
+				       __u32 mode,
+				       __u32 uid,
+				       __u32 gid,
+				       yaffs_Object *equivalentObject,
+				       const YCHAR *aliasString, __u32 rdev)
+{
+	yaffs_Object *in;
+	YCHAR *str = NULL;
+
+	yaffs_Device *dev = parent->myDev;
+
+	/* Check if the entry exists. If it does then fail the call since we don't want a dup.*/
+	if (yaffs_FindObjectByName(parent, name))
+		return NULL;
+
+	if (type == YAFFS_OBJECT_TYPE_SYMLINK) {
+		str = yaffs_CloneString(aliasString);
+		if (!str)
+			return NULL;
+	}
+
+	in = yaffs_CreateNewObject(dev, -1, type);
+
+	if (!in){
+		if(str)
+			YFREE(str);
+		return NULL;
+	}
+
+
+
+
+
+	if (in) {
+		in->hdrChunk = 0;
+		in->valid = 1;
+		in->variantType = type;
+
+		in->yst_mode = mode;
+
+#ifdef CONFIG_YAFFS_WINCE
+		yfsd_WinFileTimeNow(in->win_atime);
+		in->win_ctime[0] = in->win_mtime[0] = in->win_atime[0];
+		in->win_ctime[1] = in->win_mtime[1] = in->win_atime[1];
+
+#else
+		in->yst_atime = in->yst_mtime = in->yst_ctime = Y_CURRENT_TIME;
+
+		in->yst_rdev = rdev;
+		in->yst_uid = uid;
+		in->yst_gid = gid;
+#endif
+		in->nDataChunks = 0;
+
+		yaffs_SetObjectName(in, name);
+		in->dirty = 1;
+
+		yaffs_AddObjectToDirectory(parent, in);
+
+		in->myDev = parent->myDev;
+
+		switch (type) {
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			in->variant.symLinkVariant.alias = str;
+			break;
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+			in->variant.hardLinkVariant.equivalentObject =
+				equivalentObject;
+			in->variant.hardLinkVariant.equivalentObjectId =
+				equivalentObject->objectId;
+			ylist_add(&in->hardLinks, &equivalentObject->hardLinks);
+			break;
+		case YAFFS_OBJECT_TYPE_FILE:
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+			/* do nothing */
+			break;
+		}
+
+		if (yaffs_UpdateObjectHeader(in, name, 0, 0, 0) < 0) {
+			/* Could not create the object header, fail the creation */
+			yaffs_DeleteObject(in);
+			in = NULL;
+		}
+
+		yaffs_UpdateParent(parent);
+	}
+
+	return in;
+}
+
+yaffs_Object *yaffs_MknodFile(yaffs_Object *parent, const YCHAR *name,
+			__u32 mode, __u32 uid, __u32 gid)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_FILE, parent, name, mode,
+				uid, gid, NULL, NULL, 0);
+}
+
+yaffs_Object *yaffs_MknodDirectory(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name,
+				 mode, uid, gid, NULL, NULL, 0);
+}
+
+yaffs_Object *yaffs_MknodSpecial(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid, __u32 rdev)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode,
+				 uid, gid, NULL, NULL, rdev);
+}
+
+yaffs_Object *yaffs_MknodSymLink(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid,
+				const YCHAR *alias)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode,
+				uid, gid, NULL, alias, 0);
+}
+
+/* yaffs_Link returns the object id of the equivalent object.*/
+yaffs_Object *yaffs_Link(yaffs_Object *parent, const YCHAR *name,
+			yaffs_Object *equivalentObject)
+{
+	/* Get the real object in case we were fed a hard link as an equivalent object */
+	equivalentObject = yaffs_GetEquivalentObject(equivalentObject);
+
+	if (yaffs_MknodObject
+	    (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0,
+	     equivalentObject, NULL, 0)) {
+		return equivalentObject;
+	} else {
+		return NULL;
+	}
+
+}
+
+static int yaffs_ChangeObjectName(yaffs_Object *obj, yaffs_Object *newDir,
+				const YCHAR *newName, int force, int shadows)
+{
+	int unlinkOp;
+	int deleteOp;
+
+	yaffs_Object *existingTarget;
+
+	if (newDir == NULL)
+		newDir = obj->parent;	/* use the old directory */
+
+	if (newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_ChangeObjectName: newDir is not a directory"
+		    TENDSTR)));
+		YBUG();
+	}
+
+	/* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */
+	if (obj->myDev->param.isYaffs2)
+		unlinkOp = (newDir == obj->myDev->unlinkedDir);
+	else
+		unlinkOp = (newDir == obj->myDev->unlinkedDir
+			    && obj->variantType == YAFFS_OBJECT_TYPE_FILE);
+
+	deleteOp = (newDir == obj->myDev->deletedDir);
+
+	existingTarget = yaffs_FindObjectByName(newDir, newName);
+
+	/* If the object is a file going into the unlinked directory,
+	 *   then it is OK to just stuff it in since duplicate names are allowed.
+	 *   else only proceed if the new name does not exist and if we're putting
+	 *   it into a directory.
+	 */
+	if ((unlinkOp ||
+	     deleteOp ||
+	     force ||
+	     (shadows > 0) ||
+	     !existingTarget) &&
+	    newDir->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_SetObjectName(obj, newName);
+		obj->dirty = 1;
+
+		yaffs_AddObjectToDirectory(newDir, obj);
+
+		if (unlinkOp)
+			obj->unlinked = 1;
+
+		/* If it is a deletion then we mark it as a shrink for gc purposes. */
+		if (yaffs_UpdateObjectHeader(obj, newName, 0, deleteOp, shadows) >= 0)
+			return YAFFS_OK;
+	}
+
+	return YAFFS_FAIL;
+}
+
+int yaffs_RenameObject(yaffs_Object *oldDir, const YCHAR *oldName,
+		yaffs_Object *newDir, const YCHAR *newName)
+{
+	yaffs_Object *obj = NULL;
+	yaffs_Object *existingTarget = NULL;
+	int force = 0;
+	int result;
+	yaffs_Device *dev;
+
+
+	if (!oldDir || oldDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+		YBUG();
+	if (!newDir || newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+		YBUG();
+
+	dev = oldDir->myDev;
+
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+	/* Special case for case insemsitive systems (eg. WinCE).
+	 * While look-up is case insensitive, the name isn't.
+	 * Therefore we might want to change x.txt to X.txt
+	*/
+	if (oldDir == newDir && yaffs_strcmp(oldName, newName) == 0)
+		force = 1;
+#endif
+
+	if(yaffs_strnlen(newName,YAFFS_MAX_NAME_LENGTH+1) > YAFFS_MAX_NAME_LENGTH)
+		/* ENAMETOOLONG */
+		return YAFFS_FAIL;
+
+	obj = yaffs_FindObjectByName(oldDir, oldName);
+
+	if (obj && obj->renameAllowed) {
+
+		/* Now do the handling for an existing target, if there is one */
+
+		existingTarget = yaffs_FindObjectByName(newDir, newName);
+		if (existingTarget &&
+			existingTarget->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
+			!ylist_empty(&existingTarget->variant.directoryVariant.children)) {
+			/* There is a target that is a non-empty directory, so we fail */
+			return YAFFS_FAIL;	/* EEXIST or ENOTEMPTY */
+		} else if (existingTarget && existingTarget != obj) {
+			/* Nuke the target first, using shadowing,
+			 * but only if it isn't the same object.
+			 *
+			 * Note we must disable gc otherwise it can mess up the shadowing.
+			 *
+			 */
+			dev->isDoingGC=1;
+			yaffs_ChangeObjectName(obj, newDir, newName, force,
+						existingTarget->objectId);
+			existingTarget->isShadowed = 1;
+			yaffs_UnlinkObject(existingTarget);
+			dev->isDoingGC=0;
+		}
+
+		result = yaffs_ChangeObjectName(obj, newDir, newName, 1, 0);
+
+		yaffs_UpdateParent(oldDir);
+		if(newDir != oldDir)
+			yaffs_UpdateParent(newDir);
+		
+		return result;
+	}
+	return YAFFS_FAIL;
+}
+
+/*------------------------- Block Management and Page Allocation ----------------*/
+
+static int yaffs_InitialiseBlocks(yaffs_Device *dev)
+{
+	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
+
+	dev->blockInfo = NULL;
+	dev->chunkBits = NULL;
+
+	dev->allocationBlock = -1;	/* force it to get a new one */
+
+	/* If the first allocation strategy fails, thry the alternate one */
+	dev->blockInfo = YMALLOC(nBlocks * sizeof(yaffs_BlockInfo));
+	if (!dev->blockInfo) {
+		dev->blockInfo = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockInfo));
+		dev->blockInfoAlt = 1;
+	} else
+		dev->blockInfoAlt = 0;
+
+	if (dev->blockInfo) {
+		/* Set up dynamic blockinfo stuff. */
+		dev->chunkBitmapStride = (dev->param.nChunksPerBlock + 7) / 8; /* round up bytes */
+		dev->chunkBits = YMALLOC(dev->chunkBitmapStride * nBlocks);
+		if (!dev->chunkBits) {
+			dev->chunkBits = YMALLOC_ALT(dev->chunkBitmapStride * nBlocks);
+			dev->chunkBitsAlt = 1;
+		} else
+			dev->chunkBitsAlt = 0;
+	}
+
+	if (dev->blockInfo && dev->chunkBits) {
+		memset(dev->blockInfo, 0, nBlocks * sizeof(yaffs_BlockInfo));
+		memset(dev->chunkBits, 0, dev->chunkBitmapStride * nBlocks);
+		return YAFFS_OK;
+	}
+
+	return YAFFS_FAIL;
+}
+
+static void yaffs_DeinitialiseBlocks(yaffs_Device *dev)
+{
+	if (dev->blockInfoAlt && dev->blockInfo)
+		YFREE_ALT(dev->blockInfo);
+	else if (dev->blockInfo)
+		YFREE(dev->blockInfo);
+
+	dev->blockInfoAlt = 0;
+
+	dev->blockInfo = NULL;
+
+	if (dev->chunkBitsAlt && dev->chunkBits)
+		YFREE_ALT(dev->chunkBits);
+	else if (dev->chunkBits)
+		YFREE(dev->chunkBits);
+	dev->chunkBitsAlt = 0;
+	dev->chunkBits = NULL;
+}
+
+static int yaffs_BlockNotDisqualifiedFromGC(yaffs_Device *dev,
+					yaffs_BlockInfo *bi)
+{
+
+	if (!dev->param.isYaffs2)
+		return 1;	/* disqualification only applies to yaffs2. */
+
+	if (!bi->hasShrinkHeader)
+		return 1;	/* can gc */
+
+	yaffs_FindOldestDirtySequence(dev);
+
+	/* Can't do gc of this block if there are any blocks older than this one that have
+	 * discarded pages.
+	 */
+	return (bi->sequenceNumber <= dev->oldestDirtySequence);
+}
+
+/*
+ * yaffs_FindRefreshBlock()
+ * periodically finds the oldest full block by sequence number for refreshing.
+ * Only for yaffs2.
+ */
+static __u32 yaffs_FindRefreshBlock(yaffs_Device *dev)
+{
+	__u32 b ;
+
+	__u32 oldest = 0;
+	__u32 oldestSequence = 0;
+
+	yaffs_BlockInfo *bi;
+
+	/*
+	 * If refresh period < 10 then refreshing is disabled.
+	 */
+	if(dev->param.refreshPeriod < 10 ||
+		!dev->param.isYaffs2)
+	        return oldest;
+
+        /*
+         * Fix broken values.
+         */
+        if(dev->refreshSkip > dev->param.refreshPeriod)
+                dev->refreshSkip = dev->param.refreshPeriod;
+
+	if(dev->refreshSkip > 0){
+	        dev->refreshSkip--;
+	        return oldest;
+	}
+
+	/*
+	 * Refresh skip is now zero.
+	 * We'll do a refresh this time around....
+	 * Update the refresh skip and find the oldest block.
+	 */
+	dev->refreshSkip = dev->param.refreshPeriod;
+	dev->refreshCount++;
+	bi = dev->blockInfo;
+	for (b = dev->internalStartBlock; b <=dev->internalEndBlock; b++){
+
+		if (bi->blockState == YAFFS_BLOCK_STATE_FULL){
+
+			if(oldest < 1 ||
+                                bi->sequenceNumber < oldestSequence){
+                                oldest = b;
+                                oldestSequence = bi->sequenceNumber;
+                        }
+		}
+		bi++;
+	}
+
+	if (oldest > 0) {
+		T(YAFFS_TRACE_GC,
+		  (TSTR("GC refresh count %d selected block %d with sequenceNumber %d" TENDSTR),
+		   dev->refreshCount, oldest, oldestSequence));
+	}
+
+	return oldest;
+}
+
+/*
+ * FindDiretiestBlock is used to select the dirtiest block (or close enough)
+ * for garbage collection.
+ */
+
+static int yaffs_FindBlockForGarbageCollection(yaffs_Device *dev,
+					int aggressive)
+{
+	int b = dev->currentDirtyChecker;
+
+	int i;
+	int iterations;
+	int dirtiest = -1;
+	int pagesInUse = 0;
+	int prioritised = 0;
+	yaffs_BlockInfo *bi;
+	int pendingPrioritisedExist = 0;
+
+	/* First let's see if we need to grab a prioritised block */
+	if (dev->hasPendingPrioritisedGCs) {
+		bi = dev->blockInfo;
+		for (i = dev->internalStartBlock; i < dev->internalEndBlock && !prioritised; i++) {
+
+			if (bi->gcPrioritise) {
+				pendingPrioritisedExist = 1;
+				if (bi->blockState == YAFFS_BLOCK_STATE_FULL &&
+				   yaffs_BlockNotDisqualifiedFromGC(dev, bi)) {
+					pagesInUse = (bi->pagesInUse - bi->softDeletions);
+					dirtiest = i;
+					prioritised = 1;
+					aggressive = 1; /* Fool the non-aggressive skip logiv below */
+				}
+			}
+			bi++;
+		}
+
+		if (!pendingPrioritisedExist) /* None found, so we can clear this */
+			dev->hasPendingPrioritisedGCs = 0;
+	}
+
+	/* If we're doing aggressive GC then we are happy to take a less-dirty block, and
+	 * search harder.
+	 * else (we're doing a leasurely gc), then we only bother to do this if the
+	 * block has only a few pages in use.
+	 */
+
+	dev->nonAggressiveSkip--;
+
+	if (!aggressive && (dev->nonAggressiveSkip > 0))
+		return -1;
+
+	if (!prioritised)
+		pagesInUse =
+			(aggressive) ? dev->param.nChunksPerBlock : YAFFS_PASSIVE_GC_CHUNKS + 1;
+
+	if (aggressive)
+		iterations =
+		    dev->internalEndBlock - dev->internalStartBlock + 1;
+	else {
+		iterations =
+		    dev->internalEndBlock - dev->internalStartBlock + 1;
+		iterations = iterations / 16;
+		if (iterations > 200)
+			iterations = 200;
+	}
+
+	for (i = 0; i <= iterations && pagesInUse > 0 && !prioritised; i++) {
+		b++;
+		if (b < dev->internalStartBlock || b > dev->internalEndBlock)
+			b = dev->internalStartBlock;
+
+		if (b < dev->internalStartBlock || b > dev->internalEndBlock) {
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR("**>> Block %d is not valid" TENDSTR), b));
+			YBUG();
+		}
+
+		bi = yaffs_GetBlockInfo(dev, b);
+
+		if (bi->blockState == YAFFS_BLOCK_STATE_FULL &&
+			(bi->pagesInUse - bi->softDeletions) < pagesInUse &&
+				yaffs_BlockNotDisqualifiedFromGC(dev, bi)) {
+			dirtiest = b;
+			pagesInUse = (bi->pagesInUse - bi->softDeletions);
+		}
+	}
+
+	dev->currentDirtyChecker = b;
+
+	if (dirtiest > 0) {
+		T(YAFFS_TRACE_GC,
+		  (TSTR("GC Selected block %d with %d free, prioritised:%d" TENDSTR), dirtiest,
+		   dev->param.nChunksPerBlock - pagesInUse, prioritised));
+	}
+
+	if (dirtiest > 0)
+		dev->nonAggressiveSkip = 4;
+
+	return dirtiest;
+}
+
+static void yaffs_BlockBecameDirty(yaffs_Device *dev, int blockNo)
+{
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockNo);
+
+	int erasedOk = 0;
+
+	/* If the block is still healthy erase it and mark as clean.
+	 * If the block has had a data failure, then retire it.
+	 */
+
+	T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE,
+		(TSTR("yaffs_BlockBecameDirty block %d state %d %s"TENDSTR),
+		blockNo, bi->blockState, (bi->needsRetiring) ? "needs retiring" : ""));
+
+	yaffs_ClearOldestDirtySequence(dev,bi);
+
+	bi->blockState = YAFFS_BLOCK_STATE_DIRTY;
+
+	if (!bi->needsRetiring) {
+		yaffs_InvalidateCheckpoint(dev);
+		erasedOk = yaffs_EraseBlockInNAND(dev, blockNo);
+		if (!erasedOk) {
+			dev->nErasureFailures++;
+			T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+			  (TSTR("**>> Erasure failed %d" TENDSTR), blockNo));
+		}
+	}
+
+	if (erasedOk &&
+	    ((yaffs_traceMask & YAFFS_TRACE_ERASE) || !yaffs_SkipVerification(dev))) {
+		int i;
+		for (i = 0; i < dev->param.nChunksPerBlock; i++) {
+			if (!yaffs_CheckChunkErased
+			    (dev, blockNo * dev->param.nChunksPerBlock + i)) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   (">>Block %d erasure supposedly OK, but chunk %d not erased"
+				    TENDSTR), blockNo, i));
+			}
+		}
+	}
+
+	if (erasedOk) {
+		/* Clean it up... */
+		bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
+		bi->sequenceNumber = 0;
+		dev->nErasedBlocks++;
+		bi->pagesInUse = 0;
+		bi->softDeletions = 0;
+		bi->hasShrinkHeader = 0;
+		bi->skipErasedCheck = 1;  /* This is clean, so no need to check */
+		bi->gcPrioritise = 0;
+		yaffs_ClearChunkBits(dev, blockNo);
+
+		T(YAFFS_TRACE_ERASE,
+		  (TSTR("Erased block %d" TENDSTR), blockNo));
+	} else {
+		dev->nFreeChunks -= dev->param.nChunksPerBlock;	/* We lost a block of free space */
+
+		yaffs_RetireBlock(dev, blockNo);
+		T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+		  (TSTR("**>> Block %d retired" TENDSTR), blockNo));
+	}
+}
+
+static int yaffs_FindBlockForAllocation(yaffs_Device *dev)
+{
+	int i;
+
+	yaffs_BlockInfo *bi;
+
+	if (dev->nErasedBlocks < 1) {
+		/* Hoosterman we've got a problem.
+		 * Can't get space to gc
+		 */
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR("yaffs tragedy: no more erased blocks" TENDSTR)));
+
+		return -1;
+	}
+
+	/* Find an empty block. */
+
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		dev->allocationBlockFinder++;
+		if (dev->allocationBlockFinder < dev->internalStartBlock
+		    || dev->allocationBlockFinder > dev->internalEndBlock) {
+			dev->allocationBlockFinder = dev->internalStartBlock;
+		}
+
+		bi = yaffs_GetBlockInfo(dev, dev->allocationBlockFinder);
+
+		if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) {
+			bi->blockState = YAFFS_BLOCK_STATE_ALLOCATING;
+			dev->sequenceNumber++;
+			bi->sequenceNumber = dev->sequenceNumber;
+			dev->nErasedBlocks--;
+			T(YAFFS_TRACE_ALLOCATE,
+			  (TSTR("Allocated block %d, seq  %d, %d left" TENDSTR),
+			   dev->allocationBlockFinder, dev->sequenceNumber,
+			   dev->nErasedBlocks));
+			return dev->allocationBlockFinder;
+		}
+	}
+
+	T(YAFFS_TRACE_ALWAYS,
+	  (TSTR
+	   ("yaffs tragedy: no more erased blocks, but there should have been %d"
+	    TENDSTR), dev->nErasedBlocks));
+
+	return -1;
+}
+
+
+
+static int yaffs_CalcCheckpointBlocksRequired(yaffs_Device *dev)
+{
+	if (!dev->nCheckpointBlocksRequired &&
+	   dev->param.isYaffs2) {
+		/* Not a valid value so recalculate */
+		int nBytes = 0;
+		int nBlocks;
+		int devBlocks = (dev->param.endBlock - dev->param.startBlock + 1);
+		int tnodeSize = yaffs_CalcTnodeSize(dev);
+
+		nBytes += sizeof(yaffs_CheckpointValidity);
+		nBytes += sizeof(yaffs_CheckpointDevice);
+		nBytes += devBlocks * sizeof(yaffs_BlockInfo);
+		nBytes += devBlocks * dev->chunkBitmapStride;
+		nBytes += (sizeof(yaffs_CheckpointObject) + sizeof(__u32)) * (dev->nObjectsCreated - dev->nFreeObjects);
+		nBytes += (tnodeSize + sizeof(__u32)) * (dev->nTnodesCreated - dev->nFreeTnodes);
+		nBytes += sizeof(yaffs_CheckpointValidity);
+		nBytes += sizeof(__u32); /* checksum*/
+
+		/* Round up and add 2 blocks to allow for some bad blocks, so add 3 */
+
+		nBlocks = (nBytes/(dev->nDataBytesPerChunk * dev->param.nChunksPerBlock)) + 3;
+
+		dev->nCheckpointBlocksRequired = nBlocks;
+	}
+
+	return dev->nCheckpointBlocksRequired;
+}
+
+/*
+ * Check if there's space to allocate...
+ * Thinks.... do we need top make this ths same as yaffs_GetFreeChunks()?
+ */
+static int yaffs_CheckSpaceForAllocation(yaffs_Device *dev, int nChunks)
+{
+	int reservedChunks;
+	int reservedBlocks = dev->param.nReservedBlocks;
+	int checkpointBlocks;
+
+	if (dev->param.isYaffs2) {
+		checkpointBlocks =  yaffs_CalcCheckpointBlocksRequired(dev) -
+				    dev->blocksInCheckpoint;
+		if (checkpointBlocks < 0)
+			checkpointBlocks = 0;
+	} else {
+		checkpointBlocks = 0;
+	}
+
+	reservedChunks = ((reservedBlocks + checkpointBlocks) * dev->param.nChunksPerBlock);
+
+	return (dev->nFreeChunks > (reservedChunks + nChunks));
+}
+
+static int yaffs_AllocateChunk(yaffs_Device *dev, int useReserve,
+		yaffs_BlockInfo **blockUsedPtr)
+{
+	int retVal;
+	yaffs_BlockInfo *bi;
+
+	if (dev->allocationBlock < 0) {
+		/* Get next block to allocate off */
+		dev->allocationBlock = yaffs_FindBlockForAllocation(dev);
+		dev->allocationPage = 0;
+	}
+
+	if (!useReserve && !yaffs_CheckSpaceForAllocation(dev, 1)) {
+		/* Not enough space to allocate unless we're allowed to use the reserve. */
+		return -1;
+	}
+
+	if (dev->nErasedBlocks < dev->param.nReservedBlocks
+			&& dev->allocationPage == 0) {
+		T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR)));
+	}
+
+	/* Next page please.... */
+	if (dev->allocationBlock >= 0) {
+		bi = yaffs_GetBlockInfo(dev, dev->allocationBlock);
+
+		retVal = (dev->allocationBlock * dev->param.nChunksPerBlock) +
+			dev->allocationPage;
+		bi->pagesInUse++;
+		yaffs_SetChunkBit(dev, dev->allocationBlock,
+				dev->allocationPage);
+
+		dev->allocationPage++;
+
+		dev->nFreeChunks--;
+
+		/* If the block is full set the state to full */
+		if (dev->allocationPage >= dev->param.nChunksPerBlock) {
+			bi->blockState = YAFFS_BLOCK_STATE_FULL;
+			dev->allocationBlock = -1;
+		}
+
+		if (blockUsedPtr)
+			*blockUsedPtr = bi;
+
+		return retVal;
+	}
+
+	T(YAFFS_TRACE_ERROR,
+			(TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR)));
+
+	return -1;
+}
+
+static int yaffs_GetErasedChunks(yaffs_Device *dev)
+{
+	int n;
+
+	n = dev->nErasedBlocks * dev->param.nChunksPerBlock;
+
+	if (dev->allocationBlock > 0)
+		n += (dev->param.nChunksPerBlock - dev->allocationPage);
+
+	return n;
+
+}
+
+/*
+ * yaffs_SkipRestOfBlock() skips over the rest of the allocation block
+ * if we don't want to write to it.
+ */
+static void yaffs_SkipRestOfBlock(yaffs_Device *dev)
+{
+	if(dev->allocationBlock > 0){
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, dev->allocationBlock);
+		if(bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING){
+			bi->blockState = YAFFS_BLOCK_STATE_FULL;
+			dev->allocationBlock = -1;
+		}
+	}
+}
+
+
+static int yaffs_GarbageCollectBlock(yaffs_Device *dev, int block,
+		int wholeBlock)
+{
+	int oldChunk;
+	int newChunk;
+	int markNAND;
+	int retVal = YAFFS_OK;
+	int cleanups = 0;
+	int i;
+	int isCheckpointBlock;
+	int matchingChunk;
+	int maxCopies;
+
+	int chunksBefore = yaffs_GetErasedChunks(dev);
+	int chunksAfter;
+
+	yaffs_ExtendedTags tags;
+
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, block);
+
+	yaffs_Object *object;
+
+	isCheckpointBlock = (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT);
+
+
+	T(YAFFS_TRACE_TRACING,
+			(TSTR("Collecting block %d, in use %d, shrink %d, wholeBlock %d" TENDSTR),
+			 block,
+			 bi->pagesInUse,
+			 bi->hasShrinkHeader,
+			 wholeBlock));
+
+	/*yaffs_VerifyFreeChunks(dev); */
+
+	if(bi->blockState == YAFFS_BLOCK_STATE_FULL)
+		bi->blockState = YAFFS_BLOCK_STATE_COLLECTING;
+	
+	bi->hasShrinkHeader = 0;	/* clear the flag so that the block can erase */
+
+	/* Take off the number of soft deleted entries because
+	 * they're going to get really deleted during GC.
+	 */
+	if(dev->gcChunk == 0) /* first time through for this block */
+		dev->nFreeChunks -= bi->softDeletions;
+
+	dev->isDoingGC = 1;
+
+	if (isCheckpointBlock ||
+			!yaffs_StillSomeChunkBits(dev, block)) {
+		T(YAFFS_TRACE_TRACING,
+				(TSTR
+				 ("Collecting block %d that has no chunks in use" TENDSTR),
+				 block));
+		yaffs_BlockBecameDirty(dev, block);
+	} else {
+
+		__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+		yaffs_VerifyBlock(dev, bi, block);
+
+		maxCopies = (wholeBlock) ? dev->param.nChunksPerBlock : 10;
+		oldChunk = block * dev->param.nChunksPerBlock + dev->gcChunk;
+
+		for (/* init already done */;
+		     retVal == YAFFS_OK &&
+		     dev->gcChunk < dev->param.nChunksPerBlock &&
+		     (bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) &&
+		     maxCopies > 0;
+		     dev->gcChunk++, oldChunk++) {
+			if (yaffs_CheckChunkBit(dev, block, dev->gcChunk)) {
+
+				/* This page is in use and might need to be copied off */
+
+				maxCopies--;
+
+				markNAND = 1;
+
+				yaffs_InitialiseTags(&tags);
+
+				yaffs_ReadChunkWithTagsFromNAND(dev, oldChunk,
+								buffer, &tags);
+
+				object =
+				    yaffs_FindObjectByNumber(dev,
+							     tags.objectId);
+
+				T(YAFFS_TRACE_GC_DETAIL,
+				  (TSTR
+				   ("Collecting chunk in block %d, %d %d %d " TENDSTR),
+				   dev->gcChunk, tags.objectId, tags.chunkId,
+				   tags.byteCount));
+
+				if (object && !yaffs_SkipVerification(dev)) {
+					if (tags.chunkId == 0)
+						matchingChunk = object->hdrChunk;
+					else if (object->softDeleted)
+						matchingChunk = oldChunk; /* Defeat the test */
+					else
+						matchingChunk = yaffs_FindChunkInFile(object, tags.chunkId, NULL);
+
+					if (oldChunk != matchingChunk)
+						T(YAFFS_TRACE_ERROR,
+						  (TSTR("gc: page in gc mismatch: %d %d %d %d"TENDSTR),
+						  oldChunk, matchingChunk, tags.objectId, tags.chunkId));
+
+				}
+
+				if (!object) {
+					T(YAFFS_TRACE_ERROR,
+					  (TSTR
+					   ("page %d in gc has no object: %d %d %d "
+					    TENDSTR), oldChunk,
+					    tags.objectId, tags.chunkId, tags.byteCount));
+				}
+
+				if (object &&
+				    object->deleted &&
+				    object->softDeleted &&
+				    tags.chunkId != 0) {
+					/* Data chunk in a soft deleted file, throw it away
+					 * It's a soft deleted data chunk,
+					 * No need to copy this, just forget about it and
+					 * fix up the object.
+					 */
+
+					object->nDataChunks--;
+
+					if (object->nDataChunks <= 0) {
+						/* remeber to clean up the object */
+						dev->gcCleanupList[cleanups] =
+						    tags.objectId;
+						cleanups++;
+					}
+					markNAND = 0;
+				} else if (0) {
+					/* Todo object && object->deleted && object->nDataChunks == 0 */
+					/* Deleted object header with no data chunks.
+					 * Can be discarded and the file deleted.
+					 */
+					object->hdrChunk = 0;
+					yaffs_FreeTnode(object->myDev,
+							object->variant.
+							fileVariant.top);
+					object->variant.fileVariant.top = NULL;
+					yaffs_DoGenericObjectDeletion(object);
+
+				} else if (object) {
+					/* It's either a data chunk in a live file or
+					 * an ObjectHeader, so we're interested in it.
+					 * NB Need to keep the ObjectHeaders of deleted files
+					 * until the whole file has been deleted off
+					 */
+					tags.serialNumber++;
+
+					dev->nGCCopies++;
+
+					if (tags.chunkId == 0) {
+						/* It is an object Id,
+						 * We need to nuke the shrinkheader flags first
+						 * Also need to clean up shadowing.
+						 * We no longer want the shrinkHeader flag since its work is done
+						 * and if it is left in place it will mess up scanning.
+						 */
+
+						yaffs_ObjectHeader *oh;
+						oh = (yaffs_ObjectHeader *)buffer;
+
+						oh->isShrink = 0;
+						tags.extraIsShrinkHeader = 0;
+
+						oh->shadowsObject = 0;
+						oh->inbandShadowsObject = 0;
+						tags.extraShadows = 0;
+
+						/* Update file size */
+						if(object->variantType == YAFFS_OBJECT_TYPE_FILE){
+							oh->fileSize = object->variant.fileVariant.fileSize;
+							tags.extraFileLength = oh->fileSize;
+						}
+
+						yaffs_VerifyObjectHeader(object, oh, &tags, 1);
+						newChunk =
+						    yaffs_WriteNewChunkWithTagsToNAND(dev,(__u8 *) oh, &tags, 1);
+					} else
+						newChunk =
+						    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &tags, 1);
+
+					if (newChunk < 0) {
+						retVal = YAFFS_FAIL;
+					} else {
+
+						/* Ok, now fix up the Tnodes etc. */
+
+						if (tags.chunkId == 0) {
+							/* It's a header */
+							object->hdrChunk =  newChunk;
+							object->serial =   tags.serialNumber;
+						} else {
+							/* It's a data chunk */
+							int ok;
+							ok = yaffs_PutChunkIntoFile
+							    (object,
+							     tags.chunkId,
+							     newChunk, 0);
+						}
+					}
+				}
+
+				if (retVal == YAFFS_OK)
+					yaffs_DeleteChunk(dev, oldChunk, markNAND, __LINE__);
+
+			}
+		}
+
+		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+
+
+		/* Do any required cleanups */
+		for (i = 0; i < cleanups; i++) {
+			/* Time to delete the file too */
+			object =
+			    yaffs_FindObjectByNumber(dev,
+						     dev->gcCleanupList[i]);
+			if (object) {
+				yaffs_FreeTnode(dev,
+						object->variant.fileVariant.
+						top);
+				object->variant.fileVariant.top = NULL;
+				T(YAFFS_TRACE_GC,
+				  (TSTR
+				   ("yaffs: About to finally delete object %d"
+				    TENDSTR), object->objectId));
+				yaffs_DoGenericObjectDeletion(object);
+				object->myDev->nDeletedFiles--;
+			}
+
+		}
+
+	}
+
+	yaffs_VerifyCollectedBlock(dev, bi, block);
+
+
+
+	/* If the gc completed then clear the current gcBlock so that we find another. */
+	if (bi->blockState != YAFFS_BLOCK_STATE_COLLECTING) {
+		chunksAfter = yaffs_GetErasedChunks(dev);
+		if (chunksBefore >= chunksAfter) {
+			T(YAFFS_TRACE_GC,
+			  (TSTR
+			   ("gc did not increase free chunks before %d after %d"
+			    TENDSTR), chunksBefore, chunksAfter));
+		}
+		dev->gcBlock = -1;
+		dev->gcChunk = 0;
+	}
+
+	dev->isDoingGC = 0;
+
+	return retVal;
+}
+
+/* New garbage collector
+ * If we're very low on erased blocks then we do aggressive garbage collection
+ * otherwise we do "leasurely" garbage collection.
+ * Aggressive gc looks further (whole array) and will accept less dirty blocks.
+ * Passive gc only inspects smaller areas and will only accept more dirty blocks.
+ *
+ * The idea is to help clear out space in a more spread-out manner.
+ * Dunno if it really does anything useful.
+ */
+static int yaffs_CheckGarbageCollection(yaffs_Device *dev)
+{
+	int block;
+	int aggressive;
+	int gcOk = YAFFS_OK;
+	int maxTries = 0;
+
+	int checkpointBlockAdjust;
+
+	if(dev->param.gcControl &&
+		(dev->param.gcControl(dev) & 1) == 0)
+		return YAFFS_OK;
+
+	if (dev->isDoingGC) {
+		/* Bail out so we don't get recursive gc */
+		return YAFFS_OK;
+	}
+
+	/* This loop should pass the first time.
+	 * We'll only see looping here if the erase of the collected block fails.
+	 */
+
+	do {
+		maxTries++;
+
+		checkpointBlockAdjust = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint;
+		if (checkpointBlockAdjust < 0)
+			checkpointBlockAdjust = 0;
+
+		/* If we need a block soon then do aggressive gc.*/
+		if (dev->nErasedBlocks < (dev->param.nReservedBlocks + checkpointBlockAdjust + 2))
+			aggressive = 1;
+		else
+			aggressive = 0;
+
+                /* If we don't already have a block being gc'd then see if we should start another */
+
+		if (dev->gcBlock < 1 && !aggressive) {
+			dev->gcBlock = yaffs_FindRefreshBlock(dev);
+			dev->gcChunk = 0;
+		}
+		if (dev->gcBlock < 1) {
+			dev->gcBlock = yaffs_FindBlockForGarbageCollection(dev, aggressive);
+			dev->gcChunk = 0;
+		}
+
+		block = dev->gcBlock;
+
+		if (block > 0) {
+			dev->garbageCollections++;
+			if (!aggressive)
+				dev->passiveGarbageCollections++;
+
+			T(YAFFS_TRACE_GC,
+			  (TSTR
+			   ("yaffs: GC erasedBlocks %d aggressive %d" TENDSTR),
+			   dev->nErasedBlocks, aggressive));
+
+			gcOk = yaffs_GarbageCollectBlock(dev, block, aggressive);
+		}
+
+		if (dev->nErasedBlocks < (dev->param.nReservedBlocks) && block > 0) {
+			T(YAFFS_TRACE_GC,
+			  (TSTR
+			   ("yaffs: GC !!!no reclaim!!! erasedBlocks %d after try %d block %d"
+			    TENDSTR), dev->nErasedBlocks, maxTries, block));
+		}
+	} while ((dev->nErasedBlocks < dev->param.nReservedBlocks) &&
+		 (block > 0) &&
+		 (maxTries < 2));
+
+	return aggressive ? gcOk : YAFFS_OK;
+}
+
+/*-------------------------  TAGS --------------------------------*/
+
+static int yaffs_TagsMatch(const yaffs_ExtendedTags *tags, int objectId,
+			   int chunkInObject)
+{
+	return (tags->chunkId == chunkInObject &&
+		tags->objectId == objectId && !tags->chunkDeleted) ? 1 : 0;
+
+}
+
+
+/*-------------------- Data file manipulation -----------------*/
+
+static int yaffs_FindChunkInFile(yaffs_Object *in, int chunkInInode,
+				 yaffs_ExtendedTags *tags)
+{
+	/*Get the Tnode, then get the level 0 offset chunk offset */
+	yaffs_Tnode *tn;
+	int theChunk = -1;
+	yaffs_ExtendedTags localTags;
+	int retVal = -1;
+
+	yaffs_Device *dev = in->myDev;
+
+	if (!tags) {
+		/* Passed a NULL, so use our own tags space */
+		tags = &localTags;
+	}
+
+	tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
+
+	if (tn) {
+		theChunk = yaffs_GetChunkGroupBase(dev, tn, chunkInInode);
+
+		retVal =
+		    yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
+					   chunkInInode);
+	}
+	return retVal;
+}
+
+static int yaffs_FindAndDeleteChunkInFile(yaffs_Object *in, int chunkInInode,
+					  yaffs_ExtendedTags *tags)
+{
+	/* Get the Tnode, then get the level 0 offset chunk offset */
+	yaffs_Tnode *tn;
+	int theChunk = -1;
+	yaffs_ExtendedTags localTags;
+
+	yaffs_Device *dev = in->myDev;
+	int retVal = -1;
+
+	if (!tags) {
+		/* Passed a NULL, so use our own tags space */
+		tags = &localTags;
+	}
+
+	tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
+
+	if (tn) {
+
+		theChunk = yaffs_GetChunkGroupBase(dev, tn, chunkInInode);
+
+		retVal =
+		    yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
+					   chunkInInode);
+
+		/* Delete the entry in the filestructure (if found) */
+		if (retVal != -1)
+			yaffs_LoadLevel0Tnode(dev, tn, chunkInInode, 0);
+	}
+
+	return retVal;
+}
+
+#ifdef YAFFS_PARANOID
+
+static int yaffs_CheckFileSanity(yaffs_Object *in)
+{
+	int chunk;
+	int nChunks;
+	int fSize;
+	int failed = 0;
+	int objId;
+	yaffs_Tnode *tn;
+	yaffs_Tags localTags;
+	yaffs_Tags *tags = &localTags;
+	int theChunk;
+	int chunkDeleted;
+
+	if (in->variantType != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
+
+	objId = in->objectId;
+	fSize = in->variant.fileVariant.fileSize;
+	nChunks =
+	    (fSize + in->myDev->nDataBytesPerChunk - 1) / in->myDev->nDataBytesPerChunk;
+
+	for (chunk = 1; chunk <= nChunks; chunk++) {
+		tn = yaffs_FindLevel0Tnode(in->myDev, &in->variant.fileVariant,
+					   chunk);
+
+		if (tn) {
+
+			theChunk = yaffs_GetChunkGroupBase(dev, tn, chunk);
+
+			if (yaffs_CheckChunkBits
+			    (dev, theChunk / dev->param.nChunksPerBlock,
+			     theChunk % dev->param.nChunksPerBlock)) {
+
+				yaffs_ReadChunkTagsFromNAND(in->myDev, theChunk,
+							    tags,
+							    &chunkDeleted);
+				if (yaffs_TagsMatch
+				    (tags, in->objectId, chunk, chunkDeleted)) {
+					/* found it; */
+
+				}
+			} else {
+
+				failed = 1;
+			}
+
+		} else {
+			/* T(("No level 0 found for %d\n", chunk)); */
+		}
+	}
+
+	return failed ? YAFFS_FAIL : YAFFS_OK;
+}
+
+#endif
+
+static int yaffs_PutChunkIntoFile(yaffs_Object *in, int chunkInInode,
+				  int chunkInNAND, int inScan)
+{
+	/* NB inScan is zero unless scanning.
+	 * For forward scanning, inScan is > 0;
+	 * for backward scanning inScan is < 0
+	 *
+	 * chunkInNAND = 0 is a dummy insert to make sure the tnodes are there.
+	 */
+
+	yaffs_Tnode *tn;
+	yaffs_Device *dev = in->myDev;
+	int existingChunk;
+	yaffs_ExtendedTags existingTags;
+	yaffs_ExtendedTags newTags;
+	unsigned existingSerial, newSerial;
+
+	if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
+		/* Just ignore an attempt at putting a chunk into a non-file during scanning
+		 * If it is not during Scanning then something went wrong!
+		 */
+		if (!inScan) {
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR
+			   ("yaffs tragedy:attempt to put data chunk into a non-file"
+			    TENDSTR)));
+			YBUG();
+		}
+
+		yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+		return YAFFS_OK;
+	}
+
+	tn = yaffs_AddOrFindLevel0Tnode(dev,
+					&in->variant.fileVariant,
+					chunkInInode,
+					NULL);
+	if (!tn)
+		return YAFFS_FAIL;
+	
+	if(!chunkInNAND)
+		/* Dummy insert, bail now */
+		return YAFFS_OK;
+
+	existingChunk = yaffs_GetChunkGroupBase(dev, tn, chunkInInode);
+
+	if (inScan != 0) {
+		/* If we're scanning then we need to test for duplicates
+		 * NB This does not need to be efficient since it should only ever
+		 * happen when the power fails during a write, then only one
+		 * chunk should ever be affected.
+		 *
+		 * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO
+		 * Update: For backward scanning we don't need to re-read tags so this is quite cheap.
+		 */
+
+		if (existingChunk > 0) {
+			/* NB Right now existing chunk will not be real chunkId if the device >= 32MB
+			 *    thus we have to do a FindChunkInFile to get the real chunk id.
+			 *
+			 * We have a duplicate now we need to decide which one to use:
+			 *
+			 * Backwards scanning YAFFS2: The old one is what we use, dump the new one.
+			 * Forward scanning YAFFS2: The new one is what we use, dump the old one.
+			 * YAFFS1: Get both sets of tags and compare serial numbers.
+			 */
+
+			if (inScan > 0) {
+				/* Only do this for forward scanning */
+				yaffs_ReadChunkWithTagsFromNAND(dev,
+								chunkInNAND,
+								NULL, &newTags);
+
+				/* Do a proper find */
+				existingChunk =
+				    yaffs_FindChunkInFile(in, chunkInInode,
+							  &existingTags);
+			}
+
+			if (existingChunk <= 0) {
+				/*Hoosterman - how did this happen? */
+
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("yaffs tragedy: existing chunk < 0 in scan"
+				    TENDSTR)));
+
+			}
+
+			/* NB The deleted flags should be false, otherwise the chunks will
+			 * not be loaded during a scan
+			 */
+
+			if (inScan > 0) {
+				newSerial = newTags.serialNumber;
+				existingSerial = existingTags.serialNumber;
+			}
+
+			if ((inScan > 0) &&
+			    (in->myDev->param.isYaffs2 ||
+			     existingChunk <= 0 ||
+			     ((existingSerial + 1) & 3) == newSerial)) {
+				/* Forward scanning.
+				 * Use new
+				 * Delete the old one and drop through to update the tnode
+				 */
+				yaffs_DeleteChunk(dev, existingChunk, 1,
+						  __LINE__);
+			} else {
+				/* Backward scanning or we want to use the existing one
+				 * Use existing.
+				 * Delete the new one and return early so that the tnode isn't changed
+				 */
+				yaffs_DeleteChunk(dev, chunkInNAND, 1,
+						  __LINE__);
+				return YAFFS_OK;
+			}
+		}
+
+	}
+
+	if (existingChunk == 0)
+		in->nDataChunks++;
+
+	yaffs_LoadLevel0Tnode(dev, tn, chunkInInode, chunkInNAND);
+
+	return YAFFS_OK;
+}
+
+static int yaffs_ReadChunkDataFromObject(yaffs_Object *in, int chunkInInode,
+					__u8 *buffer)
+{
+	int chunkInNAND = yaffs_FindChunkInFile(in, chunkInInode, NULL);
+
+	if (chunkInNAND >= 0)
+		return yaffs_ReadChunkWithTagsFromNAND(in->myDev, chunkInNAND,
+						buffer, NULL);
+	else {
+		T(YAFFS_TRACE_NANDACCESS,
+		  (TSTR("Chunk %d not found zero instead" TENDSTR),
+		   chunkInNAND));
+		/* get sane (zero) data if you read a hole */
+		memset(buffer, 0, in->myDev->nDataBytesPerChunk);
+		return 0;
+	}
+
+}
+
+void yaffs_DeleteChunk(yaffs_Device *dev, int chunkId, int markNAND, int lyn)
+{
+	int block;
+	int page;
+	yaffs_ExtendedTags tags;
+	yaffs_BlockInfo *bi;
+
+	if (chunkId <= 0)
+		return;
+
+	dev->nDeletions++;
+	block = chunkId / dev->param.nChunksPerBlock;
+	page = chunkId % dev->param.nChunksPerBlock;
+
+
+	if (!yaffs_CheckChunkBit(dev, block, page))
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Deleting invalid chunk %d"TENDSTR),
+			 chunkId));
+
+	bi = yaffs_GetBlockInfo(dev, block);
+	
+	yaffs_UpdateOldestDirtySequence(dev,bi);
+
+	T(YAFFS_TRACE_DELETION,
+	  (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunkId));
+
+	if (markNAND &&
+	    bi->blockState != YAFFS_BLOCK_STATE_COLLECTING && !dev->param.isYaffs2) {
+
+		yaffs_InitialiseTags(&tags);
+
+		tags.chunkDeleted = 1;
+
+		yaffs_WriteChunkWithTagsToNAND(dev, chunkId, NULL, &tags);
+		yaffs_HandleUpdateChunk(dev, chunkId, &tags);
+	} else {
+		dev->nUnmarkedDeletions++;
+	}
+
+	/* Pull out of the management area.
+	 * If the whole block became dirty, this will kick off an erasure.
+	 */
+	if (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING ||
+	    bi->blockState == YAFFS_BLOCK_STATE_FULL ||
+	    bi->blockState == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
+	    bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) {
+		dev->nFreeChunks++;
+
+		yaffs_ClearChunkBit(dev, block, page);
+
+		bi->pagesInUse--;
+
+		if (bi->pagesInUse == 0 &&
+		    !bi->hasShrinkHeader &&
+		    bi->blockState != YAFFS_BLOCK_STATE_ALLOCATING &&
+		    bi->blockState != YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+			yaffs_BlockBecameDirty(dev, block);
+		}
+
+	}
+
+}
+
+static int yaffs_WriteChunkDataToObject(yaffs_Object *in, int chunkInInode,
+					const __u8 *buffer, int nBytes,
+					int useReserve)
+{
+	/* Find old chunk Need to do this to get serial number
+	 * Write new one and patch into tree.
+	 * Invalidate old tags.
+	 */
+
+	int prevChunkId;
+	yaffs_ExtendedTags prevTags;
+
+	int newChunkId;
+	yaffs_ExtendedTags newTags;
+
+	yaffs_Device *dev = in->myDev;
+
+	yaffs_CheckGarbageCollection(dev);
+
+	/* Get the previous chunk at this location in the file if it exists.
+	 * If it does not exist then put a zero into the tree. This creates
+	 * the tnode now, rather than later when it is harder to clean up.
+	 */
+	prevChunkId = yaffs_FindChunkInFile(in, chunkInInode, &prevTags);
+	if(prevChunkId < 1 &&
+		!yaffs_PutChunkIntoFile(in, chunkInInode, 0, 0))
+		return 0;
+
+	/* Set up new tags */
+	yaffs_InitialiseTags(&newTags);
+
+	newTags.chunkId = chunkInInode;
+	newTags.objectId = in->objectId;
+	newTags.serialNumber =
+	    (prevChunkId > 0) ? prevTags.serialNumber + 1 : 1;
+	newTags.byteCount = nBytes;
+
+	if (nBytes < 1 || nBytes > dev->param.totalBytesPerChunk) {
+		T(YAFFS_TRACE_ERROR,
+		(TSTR("Writing %d bytes to chunk!!!!!!!!!" TENDSTR), nBytes));
+		YBUG();
+	}
+	
+		
+	newChunkId =
+	    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
+					      useReserve);
+
+	if (newChunkId > 0) {
+		yaffs_PutChunkIntoFile(in, chunkInInode, newChunkId, 0);
+
+		if (prevChunkId > 0)
+			yaffs_DeleteChunk(dev, prevChunkId, 1, __LINE__);
+
+		yaffs_CheckFileSanity(in);
+	}
+	return newChunkId;
+
+}
+
+/* UpdateObjectHeader updates the header on NAND for an object.
+ * If name is not NULL, then that new name is used.
+ */
+int yaffs_UpdateObjectHeader(yaffs_Object *in, const YCHAR *name, int force,
+			     int isShrink, int shadows)
+{
+
+	yaffs_BlockInfo *bi;
+
+	yaffs_Device *dev = in->myDev;
+
+	int prevChunkId;
+	int retVal = 0;
+	int result = 0;
+
+	int newChunkId;
+	yaffs_ExtendedTags newTags;
+	yaffs_ExtendedTags oldTags;
+	YCHAR *alias = NULL;
+
+	__u8 *buffer = NULL;
+	YCHAR oldName[YAFFS_MAX_NAME_LENGTH + 1];
+
+	yaffs_ObjectHeader *oh = NULL;
+
+	yaffs_strcpy(oldName, _Y("silly old name"));
+
+
+	if (!in->fake ||
+		in == dev->rootDir || /* The rootDir should also be saved */
+		force) {
+
+		yaffs_CheckGarbageCollection(dev);
+		yaffs_CheckObjectDetailsLoaded(in);
+
+		buffer = yaffs_GetTempBuffer(in->myDev, __LINE__);
+		oh = (yaffs_ObjectHeader *) buffer;
+
+		prevChunkId = in->hdrChunk;
+
+		if (prevChunkId > 0) {
+			result = yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId,
+							buffer, &oldTags);
+
+			yaffs_VerifyObjectHeader(in, oh, &oldTags, 0);
+
+			memcpy(oldName, oh->name, sizeof(oh->name));
+		}
+
+		memset(buffer, 0xFF, dev->nDataBytesPerChunk);
+
+		oh->type = in->variantType;
+		oh->yst_mode = in->yst_mode;
+		oh->shadowsObject = oh->inbandShadowsObject = shadows;
+
+#ifdef CONFIG_YAFFS_WINCE
+		oh->win_atime[0] = in->win_atime[0];
+		oh->win_ctime[0] = in->win_ctime[0];
+		oh->win_mtime[0] = in->win_mtime[0];
+		oh->win_atime[1] = in->win_atime[1];
+		oh->win_ctime[1] = in->win_ctime[1];
+		oh->win_mtime[1] = in->win_mtime[1];
+#else
+		oh->yst_uid = in->yst_uid;
+		oh->yst_gid = in->yst_gid;
+		oh->yst_atime = in->yst_atime;
+		oh->yst_mtime = in->yst_mtime;
+		oh->yst_ctime = in->yst_ctime;
+		oh->yst_rdev = in->yst_rdev;
+#endif
+		if (in->parent)
+			oh->parentObjectId = in->parent->objectId;
+		else
+			oh->parentObjectId = 0;
+
+		if (name && *name) {
+			memset(oh->name, 0, sizeof(oh->name));
+			yaffs_strncpy(oh->name, name, YAFFS_MAX_NAME_LENGTH);
+		} else if (prevChunkId > 0)
+			memcpy(oh->name, oldName, sizeof(oh->name));
+		else
+			memset(oh->name, 0, sizeof(oh->name));
+
+		oh->isShrink = isShrink;
+
+		switch (in->variantType) {
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+			/* Should not happen */
+			break;
+		case YAFFS_OBJECT_TYPE_FILE:
+			oh->fileSize =
+			    (oh->parentObjectId == YAFFS_OBJECTID_DELETED
+			     || oh->parentObjectId ==
+			     YAFFS_OBJECTID_UNLINKED) ? 0 : in->variant.
+			    fileVariant.fileSize;
+			break;
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+			oh->equivalentObjectId =
+			    in->variant.hardLinkVariant.equivalentObjectId;
+			break;
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+			/* Do nothing */
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			/* Do nothing */
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			alias = in->variant.symLinkVariant.alias;
+			if(!alias)
+				alias = _Y("no alias");
+			yaffs_strncpy(oh->alias,
+					alias,
+				      YAFFS_MAX_ALIAS_LENGTH);
+			oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0;
+			break;
+		}
+
+		/* Tags */
+		yaffs_InitialiseTags(&newTags);
+		in->serial++;
+		newTags.chunkId = 0;
+		newTags.objectId = in->objectId;
+		newTags.serialNumber = in->serial;
+
+		/* Add extra info for file header */
+
+		newTags.extraHeaderInfoAvailable = 1;
+		newTags.extraParentObjectId = oh->parentObjectId;
+		newTags.extraFileLength = oh->fileSize;
+		newTags.extraIsShrinkHeader = oh->isShrink;
+		newTags.extraEquivalentObjectId = oh->equivalentObjectId;
+		newTags.extraShadows = (oh->shadowsObject > 0) ? 1 : 0;
+		newTags.extraObjectType = in->variantType;
+
+		yaffs_VerifyObjectHeader(in, oh, &newTags, 1);
+
+		/* Create new chunk in NAND */
+		newChunkId =
+		    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
+						      (prevChunkId > 0) ? 1 : 0);
+
+		if (newChunkId >= 0) {
+
+			in->hdrChunk = newChunkId;
+
+			if (prevChunkId > 0) {
+				yaffs_DeleteChunk(dev, prevChunkId, 1,
+						  __LINE__);
+			}
+
+			if (!yaffs_ObjectHasCachedWriteData(in))
+				in->dirty = 0;
+
+			/* If this was a shrink, then mark the block that the chunk lives on */
+			if (isShrink) {
+				bi = yaffs_GetBlockInfo(in->myDev,
+					newChunkId / in->myDev->param.nChunksPerBlock);
+				bi->hasShrinkHeader = 1;
+			}
+
+		}
+
+		retVal = newChunkId;
+
+	}
+
+	if (buffer)
+		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+
+	return retVal;
+}
+
+/*------------------------ Short Operations Cache ----------------------------------------
+ *   In many situations where there is no high level buffering (eg WinCE) a lot of
+ *   reads might be short sequential reads, and a lot of writes may be short
+ *   sequential writes. eg. scanning/writing a jpeg file.
+ *   In these cases, a short read/write cache can provide a huge perfomance benefit
+ *   with dumb-as-a-rock code.
+ *   In Linux, the page cache provides read buffering aand the short op cache provides write
+ *   buffering.
+ *
+ *   There are a limited number (~10) of cache chunks per device so that we don't
+ *   need a very intelligent search.
+ */
+
+static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj)
+{
+	yaffs_Device *dev = obj->myDev;
+	int i;
+	yaffs_ChunkCache *cache;
+	int nCaches = obj->myDev->param.nShortOpCaches;
+
+	for (i = 0; i < nCaches; i++) {
+		cache = &dev->srCache[i];
+		if (cache->object == obj &&
+		    cache->dirty)
+			return 1;
+	}
+
+	return 0;
+}
+
+
+static void yaffs_FlushFilesChunkCache(yaffs_Object *obj)
+{
+	yaffs_Device *dev = obj->myDev;
+	int lowest = -99;	/* Stop compiler whining. */
+	int i;
+	yaffs_ChunkCache *cache;
+	int chunkWritten = 0;
+	int nCaches = obj->myDev->param.nShortOpCaches;
+
+	if (nCaches > 0) {
+		do {
+			cache = NULL;
+
+			/* Find the dirty cache for this object with the lowest chunk id. */
+			for (i = 0; i < nCaches; i++) {
+				if (dev->srCache[i].object == obj &&
+				    dev->srCache[i].dirty) {
+					if (!cache
+					    || dev->srCache[i].chunkId <
+					    lowest) {
+						cache = &dev->srCache[i];
+						lowest = cache->chunkId;
+					}
+				}
+			}
+
+			if (cache && !cache->locked) {
+				/* Write it out and free it up */
+
+				chunkWritten =
+				    yaffs_WriteChunkDataToObject(cache->object,
+								 cache->chunkId,
+								 cache->data,
+								 cache->nBytes,
+								 1);
+				cache->dirty = 0;
+				cache->object = NULL;
+			}
+
+		} while (cache && chunkWritten > 0);
+
+		if (cache) {
+			/* Hoosterman, disk full while writing cache out. */
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR("yaffs tragedy: no space during cache write" TENDSTR)));
+
+		}
+	}
+
+}
+
+/*yaffs_FlushEntireDeviceCache(dev)
+ *
+ *
+ */
+
+void yaffs_FlushEntireDeviceCache(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	int nCaches = dev->param.nShortOpCaches;
+	int i;
+
+	/* Find a dirty object in the cache and flush it...
+	 * until there are no further dirty objects.
+	 */
+	do {
+		obj = NULL;
+		for (i = 0; i < nCaches && !obj; i++) {
+			if (dev->srCache[i].object &&
+			    dev->srCache[i].dirty)
+				obj = dev->srCache[i].object;
+
+		}
+		if (obj)
+			yaffs_FlushFilesChunkCache(obj);
+
+	} while (obj);
+
+}
+
+
+/* Grab us a cache chunk for use.
+ * First look for an empty one.
+ * Then look for the least recently used non-dirty one.
+ * Then look for the least recently used dirty one...., flush and look again.
+ */
+static yaffs_ChunkCache *yaffs_GrabChunkCacheWorker(yaffs_Device *dev)
+{
+	int i;
+
+	if (dev->param.nShortOpCaches > 0) {
+		for (i = 0; i < dev->param.nShortOpCaches; i++) {
+			if (!dev->srCache[i].object)
+				return &dev->srCache[i];
+		}
+	}
+
+	return NULL;
+}
+
+static yaffs_ChunkCache *yaffs_GrabChunkCache(yaffs_Device *dev)
+{
+	yaffs_ChunkCache *cache;
+	yaffs_Object *theObj;
+	int usage;
+	int i;
+	int pushout;
+
+	if (dev->param.nShortOpCaches > 0) {
+		/* Try find a non-dirty one... */
+
+		cache = yaffs_GrabChunkCacheWorker(dev);
+
+		if (!cache) {
+			/* They were all dirty, find the last recently used object and flush
+			 * its cache, then  find again.
+			 * NB what's here is not very accurate, we actually flush the object
+			 * the last recently used page.
+			 */
+
+			/* With locking we can't assume we can use entry zero */
+
+			theObj = NULL;
+			usage = -1;
+			cache = NULL;
+			pushout = -1;
+
+			for (i = 0; i < dev->param.nShortOpCaches; i++) {
+				if (dev->srCache[i].object &&
+				    !dev->srCache[i].locked &&
+				    (dev->srCache[i].lastUse < usage || !cache)) {
+					usage = dev->srCache[i].lastUse;
+					theObj = dev->srCache[i].object;
+					cache = &dev->srCache[i];
+					pushout = i;
+				}
+			}
+
+			if (!cache || cache->dirty) {
+				/* Flush and try again */
+				yaffs_FlushFilesChunkCache(theObj);
+				cache = yaffs_GrabChunkCacheWorker(dev);
+			}
+
+		}
+		return cache;
+	} else
+		return NULL;
+
+}
+
+/* Find a cached chunk */
+static yaffs_ChunkCache *yaffs_FindChunkCache(const yaffs_Object *obj,
+					      int chunkId)
+{
+	yaffs_Device *dev = obj->myDev;
+	int i;
+	if (dev->param.nShortOpCaches > 0) {
+		for (i = 0; i < dev->param.nShortOpCaches; i++) {
+			if (dev->srCache[i].object == obj &&
+			    dev->srCache[i].chunkId == chunkId) {
+				dev->cacheHits++;
+
+				return &dev->srCache[i];
+			}
+		}
+	}
+	return NULL;
+}
+
+/* Mark the chunk for the least recently used algorithym */
+static void yaffs_UseChunkCache(yaffs_Device *dev, yaffs_ChunkCache *cache,
+				int isAWrite)
+{
+
+	if (dev->param.nShortOpCaches > 0) {
+		if (dev->srLastUse < 0 || dev->srLastUse > 100000000) {
+			/* Reset the cache usages */
+			int i;
+			for (i = 1; i < dev->param.nShortOpCaches; i++)
+				dev->srCache[i].lastUse = 0;
+
+			dev->srLastUse = 0;
+		}
+
+		dev->srLastUse++;
+
+		cache->lastUse = dev->srLastUse;
+
+		if (isAWrite)
+			cache->dirty = 1;
+	}
+}
+
+/* Invalidate a single cache page.
+ * Do this when a whole page gets written,
+ * ie the short cache for this page is no longer valid.
+ */
+static void yaffs_InvalidateChunkCache(yaffs_Object *object, int chunkId)
+{
+	if (object->myDev->param.nShortOpCaches > 0) {
+		yaffs_ChunkCache *cache = yaffs_FindChunkCache(object, chunkId);
+
+		if (cache)
+			cache->object = NULL;
+	}
+}
+
+/* Invalidate all the cache pages associated with this object
+ * Do this whenever ther file is deleted or resized.
+ */
+static void yaffs_InvalidateWholeChunkCache(yaffs_Object *in)
+{
+	int i;
+	yaffs_Device *dev = in->myDev;
+
+	if (dev->param.nShortOpCaches > 0) {
+		/* Invalidate it. */
+		for (i = 0; i < dev->param.nShortOpCaches; i++) {
+			if (dev->srCache[i].object == in)
+				dev->srCache[i].object = NULL;
+		}
+	}
+}
+
+/*--------------------- Checkpointing --------------------*/
+
+
+static int yaffs_WriteCheckpointValidityMarker(yaffs_Device *dev, int head)
+{
+	yaffs_CheckpointValidity cp;
+
+	memset(&cp, 0, sizeof(cp));
+
+	cp.structType = sizeof(cp);
+	cp.magic = YAFFS_MAGIC;
+	cp.version = YAFFS_CHECKPOINT_VERSION;
+	cp.head = (head) ? 1 : 0;
+
+	return (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp)) ?
+		1 : 0;
+}
+
+static int yaffs_ReadCheckpointValidityMarker(yaffs_Device *dev, int head)
+{
+	yaffs_CheckpointValidity cp;
+	int ok;
+
+	ok = (yaffs_CheckpointRead(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	if (ok)
+		ok = (cp.structType == sizeof(cp)) &&
+		     (cp.magic == YAFFS_MAGIC) &&
+		     (cp.version == YAFFS_CHECKPOINT_VERSION) &&
+		     (cp.head == ((head) ? 1 : 0));
+	return ok ? 1 : 0;
+}
+
+static void yaffs_DeviceToCheckpointDevice(yaffs_CheckpointDevice *cp,
+					   yaffs_Device *dev)
+{
+	cp->nErasedBlocks = dev->nErasedBlocks;
+	cp->allocationBlock = dev->allocationBlock;
+	cp->allocationPage = dev->allocationPage;
+	cp->nFreeChunks = dev->nFreeChunks;
+
+	cp->nDeletedFiles = dev->nDeletedFiles;
+	cp->nUnlinkedFiles = dev->nUnlinkedFiles;
+	cp->nBackgroundDeletions = dev->nBackgroundDeletions;
+	cp->sequenceNumber = dev->sequenceNumber;
+
+}
+
+static void yaffs_CheckpointDeviceToDevice(yaffs_Device *dev,
+					   yaffs_CheckpointDevice *cp)
+{
+	dev->nErasedBlocks = cp->nErasedBlocks;
+	dev->allocationBlock = cp->allocationBlock;
+	dev->allocationPage = cp->allocationPage;
+	dev->nFreeChunks = cp->nFreeChunks;
+
+	dev->nDeletedFiles = cp->nDeletedFiles;
+	dev->nUnlinkedFiles = cp->nUnlinkedFiles;
+	dev->nBackgroundDeletions = cp->nBackgroundDeletions;
+	dev->sequenceNumber = cp->sequenceNumber;
+}
+
+
+static int yaffs_WriteCheckpointDevice(yaffs_Device *dev)
+{
+	yaffs_CheckpointDevice cp;
+	__u32 nBytes;
+	__u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
+
+	int ok;
+
+	/* Write device runtime values*/
+	yaffs_DeviceToCheckpointDevice(&cp, dev);
+	cp.structType = sizeof(cp);
+
+	ok = (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	/* Write block info */
+	if (ok) {
+		nBytes = nBlocks * sizeof(yaffs_BlockInfo);
+		ok = (yaffs_CheckpointWrite(dev, dev->blockInfo, nBytes) == nBytes);
+	}
+
+	/* Write chunk bits */
+	if (ok) {
+		nBytes = nBlocks * dev->chunkBitmapStride;
+		ok = (yaffs_CheckpointWrite(dev, dev->chunkBits, nBytes) == nBytes);
+	}
+	return	 ok ? 1 : 0;
+
+}
+
+static int yaffs_ReadCheckpointDevice(yaffs_Device *dev)
+{
+	yaffs_CheckpointDevice cp;
+	__u32 nBytes;
+	__u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
+
+	int ok;
+
+	ok = (yaffs_CheckpointRead(dev, &cp, sizeof(cp)) == sizeof(cp));
+	if (!ok)
+		return 0;
+
+	if (cp.structType != sizeof(cp))
+		return 0;
+
+
+	yaffs_CheckpointDeviceToDevice(dev, &cp);
+
+	nBytes = nBlocks * sizeof(yaffs_BlockInfo);
+
+	ok = (yaffs_CheckpointRead(dev, dev->blockInfo, nBytes) == nBytes);
+
+	if (!ok)
+		return 0;
+	nBytes = nBlocks * dev->chunkBitmapStride;
+
+	ok = (yaffs_CheckpointRead(dev, dev->chunkBits, nBytes) == nBytes);
+
+	return ok ? 1 : 0;
+}
+
+static void yaffs_ObjectToCheckpointObject(yaffs_CheckpointObject *cp,
+					   yaffs_Object *obj)
+{
+
+	cp->objectId = obj->objectId;
+	cp->parentId = (obj->parent) ? obj->parent->objectId : 0;
+	cp->hdrChunk = obj->hdrChunk;
+	cp->variantType = obj->variantType;
+	cp->deleted = obj->deleted;
+	cp->softDeleted = obj->softDeleted;
+	cp->unlinked = obj->unlinked;
+	cp->fake = obj->fake;
+	cp->renameAllowed = obj->renameAllowed;
+	cp->unlinkAllowed = obj->unlinkAllowed;
+	cp->serial = obj->serial;
+	cp->nDataChunks = obj->nDataChunks;
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+		cp->fileSizeOrEquivalentObjectId = obj->variant.fileVariant.fileSize;
+	else if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
+		cp->fileSizeOrEquivalentObjectId = obj->variant.hardLinkVariant.equivalentObjectId;
+}
+
+static int yaffs_CheckpointObjectToObject(yaffs_Object *obj, yaffs_CheckpointObject *cp)
+{
+
+	yaffs_Object *parent;
+
+	if (obj->variantType != cp->variantType) {
+		T(YAFFS_TRACE_ERROR, (TSTR("Checkpoint read object %d type %d "
+			TCONT("chunk %d does not match existing object type %d")
+			TENDSTR), cp->objectId, cp->variantType, cp->hdrChunk,
+			obj->variantType));
+		return 0;
+	}
+
+	obj->objectId = cp->objectId;
+
+	if (cp->parentId)
+		parent = yaffs_FindOrCreateObjectByNumber(
+					obj->myDev,
+					cp->parentId,
+					YAFFS_OBJECT_TYPE_DIRECTORY);
+	else
+		parent = NULL;
+
+	if (parent) {
+		if (parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+			T(YAFFS_TRACE_ALWAYS, (TSTR("Checkpoint read object %d parent %d type %d"
+				TCONT(" chunk %d Parent type, %d, not directory")
+				TENDSTR),
+				cp->objectId, cp->parentId, cp->variantType,
+				cp->hdrChunk, parent->variantType));
+			return 0;
+		}
+		yaffs_AddObjectToDirectory(parent, obj);
+	}
+
+	obj->hdrChunk = cp->hdrChunk;
+	obj->variantType = cp->variantType;
+	obj->deleted = cp->deleted;
+	obj->softDeleted = cp->softDeleted;
+	obj->unlinked = cp->unlinked;
+	obj->fake = cp->fake;
+	obj->renameAllowed = cp->renameAllowed;
+	obj->unlinkAllowed = cp->unlinkAllowed;
+	obj->serial = cp->serial;
+	obj->nDataChunks = cp->nDataChunks;
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+		obj->variant.fileVariant.fileSize = cp->fileSizeOrEquivalentObjectId;
+	else if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
+		obj->variant.hardLinkVariant.equivalentObjectId = cp->fileSizeOrEquivalentObjectId;
+
+	if (obj->hdrChunk > 0)
+		obj->lazyLoaded = 1;
+	return 1;
+}
+
+
+
+static int yaffs_CheckpointTnodeWorker(yaffs_Object *in, yaffs_Tnode *tn,
+					__u32 level, int chunkOffset)
+{
+	int i;
+	yaffs_Device *dev = in->myDev;
+	int ok = 1;
+	int tnodeSize = yaffs_CalcTnodeSize(dev);
+
+	if (tn) {
+		if (level > 0) {
+
+			for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) {
+				if (tn->internal[i]) {
+					ok = yaffs_CheckpointTnodeWorker(in,
+							tn->internal[i],
+							level - 1,
+							(chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
+				}
+			}
+		} else if (level == 0) {
+			__u32 baseOffset = chunkOffset <<  YAFFS_TNODES_LEVEL0_BITS;
+			ok = (yaffs_CheckpointWrite(dev, &baseOffset, sizeof(baseOffset)) == sizeof(baseOffset));
+			if (ok)
+				ok = (yaffs_CheckpointWrite(dev, tn, tnodeSize) == tnodeSize);
+		}
+	}
+
+	return ok;
+
+}
+
+static int yaffs_WriteCheckpointTnodes(yaffs_Object *obj)
+{
+	__u32 endMarker = ~0;
+	int ok = 1;
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
+		ok = yaffs_CheckpointTnodeWorker(obj,
+					    obj->variant.fileVariant.top,
+					    obj->variant.fileVariant.topLevel,
+					    0);
+		if (ok)
+			ok = (yaffs_CheckpointWrite(obj->myDev, &endMarker, sizeof(endMarker)) ==
+				sizeof(endMarker));
+	}
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs_ReadCheckpointTnodes(yaffs_Object *obj)
+{
+	__u32 baseChunk;
+	int ok = 1;
+	yaffs_Device *dev = obj->myDev;
+	yaffs_FileStructure *fileStructPtr = &obj->variant.fileVariant;
+	yaffs_Tnode *tn;
+	int nread = 0;
+	int tnodeSize = yaffs_CalcTnodeSize(dev);
+
+	ok = (yaffs_CheckpointRead(dev, &baseChunk, sizeof(baseChunk)) == sizeof(baseChunk));
+
+	while (ok && (~baseChunk)) {
+		nread++;
+		/* Read level 0 tnode */
+
+
+		tn = yaffs_GetTnodeRaw(dev);
+		if (tn)
+			ok = (yaffs_CheckpointRead(dev, tn, tnodeSize) == tnodeSize);
+		else
+			ok = 0;
+
+		if (tn && ok)
+			ok = yaffs_AddOrFindLevel0Tnode(dev,
+							fileStructPtr,
+							baseChunk,
+							tn) ? 1 : 0;
+
+		if (ok)
+			ok = (yaffs_CheckpointRead(dev, &baseChunk, sizeof(baseChunk)) == sizeof(baseChunk));
+
+	}
+
+	T(YAFFS_TRACE_CHECKPOINT, (
+		TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR),
+		nread, baseChunk, ok));
+
+	return ok ? 1 : 0;
+}
+
+
+static int yaffs_WriteCheckpointObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	yaffs_CheckpointObject cp;
+	int i;
+	int ok = 1;
+	struct ylist_head *lh;
+
+
+	/* Iterate through the objects in each hash entry,
+	 * dumping them to the checkpointing stream.
+	 */
+
+	for (i = 0; ok &&  i <  YAFFS_NOBJECT_BUCKETS; i++) {
+		ylist_for_each(lh, &dev->objectBucket[i].list) {
+			if (lh) {
+				obj = ylist_entry(lh, yaffs_Object, hashLink);
+				if (!obj->deferedFree) {
+					yaffs_ObjectToCheckpointObject(&cp, obj);
+					cp.structType = sizeof(cp);
+
+					T(YAFFS_TRACE_CHECKPOINT, (
+						TSTR("Checkpoint write object %d parent %d type %d chunk %d obj addr %p" TENDSTR),
+						cp.objectId, cp.parentId, cp.variantType, cp.hdrChunk, obj));
+
+					ok = (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+					if (ok && obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+						ok = yaffs_WriteCheckpointTnodes(obj);
+				}
+			}
+		}
+	}
+
+	/* Dump end of list */
+	memset(&cp, 0xFF, sizeof(yaffs_CheckpointObject));
+	cp.structType = sizeof(cp);
+
+	if (ok)
+		ok = (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs_ReadCheckpointObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	yaffs_CheckpointObject cp;
+	int ok = 1;
+	int done = 0;
+	yaffs_Object *hardList = NULL;
+
+	while (ok && !done) {
+		ok = (yaffs_CheckpointRead(dev, &cp, sizeof(cp)) == sizeof(cp));
+		if (cp.structType != sizeof(cp)) {
+			T(YAFFS_TRACE_CHECKPOINT, (TSTR("struct size %d instead of %d ok %d"TENDSTR),
+				cp.structType, (int)sizeof(cp), ok));
+			ok = 0;
+		}
+
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("Checkpoint read object %d parent %d type %d chunk %d " TENDSTR),
+			cp.objectId, cp.parentId, cp.variantType, cp.hdrChunk));
+
+		if (ok && cp.objectId == ~0)
+			done = 1;
+		else if (ok) {
+			obj = yaffs_FindOrCreateObjectByNumber(dev, cp.objectId, cp.variantType);
+			if (obj) {
+				ok = yaffs_CheckpointObjectToObject(obj, &cp);
+				if (!ok)
+					break;
+				if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
+					ok = yaffs_ReadCheckpointTnodes(obj);
+				} else if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
+					obj->hardLinks.next =
+						(struct ylist_head *) hardList;
+					hardList = obj;
+				}
+			} else
+				ok = 0;
+		}
+	}
+
+	if (ok)
+		yaffs_HardlinkFixup(dev, hardList);
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs_WriteCheckpointSum(yaffs_Device *dev)
+{
+	__u32 checkpointSum;
+	int ok;
+
+	yaffs_GetCheckpointSum(dev, &checkpointSum);
+
+	ok = (yaffs_CheckpointWrite(dev, &checkpointSum, sizeof(checkpointSum)) == sizeof(checkpointSum));
+
+	if (!ok)
+		return 0;
+
+	return 1;
+}
+
+static int yaffs_ReadCheckpointSum(yaffs_Device *dev)
+{
+	__u32 checkpointSum0;
+	__u32 checkpointSum1;
+	int ok;
+
+	yaffs_GetCheckpointSum(dev, &checkpointSum0);
+
+	ok = (yaffs_CheckpointRead(dev, &checkpointSum1, sizeof(checkpointSum1)) == sizeof(checkpointSum1));
+
+	if (!ok)
+		return 0;
+
+	if (checkpointSum0 != checkpointSum1)
+		return 0;
+
+	return 1;
+}
+
+
+static int yaffs_WriteCheckpointData(yaffs_Device *dev)
+{
+	int ok = 1;
+
+	if (dev->param.skipCheckpointWrite || !dev->param.isYaffs2) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("skipping checkpoint write" TENDSTR)));
+		ok = 0;
+	}
+
+	if (ok)
+		ok = yaffs_CheckpointOpen(dev, 1);
+
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint validity" TENDSTR)));
+		ok = yaffs_WriteCheckpointValidityMarker(dev, 1);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint device" TENDSTR)));
+		ok = yaffs_WriteCheckpointDevice(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint objects" TENDSTR)));
+		ok = yaffs_WriteCheckpointObjects(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint validity" TENDSTR)));
+		ok = yaffs_WriteCheckpointValidityMarker(dev, 0);
+	}
+
+	if (ok)
+		ok = yaffs_WriteCheckpointSum(dev);
+
+	if (!yaffs_CheckpointClose(dev))
+		ok = 0;
+
+	if (ok)
+		dev->isCheckpointed = 1;
+	else
+		dev->isCheckpointed = 0;
+
+	return dev->isCheckpointed;
+}
+
+static int yaffs_ReadCheckpointData(yaffs_Device *dev)
+{
+	int ok = 1;
+
+	if (dev->param.skipCheckpointRead || !dev->param.isYaffs2) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("skipping checkpoint read" TENDSTR)));
+		ok = 0;
+	}
+
+	if (ok)
+		ok = yaffs_CheckpointOpen(dev, 0); /* open for read */
+
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint validity" TENDSTR)));
+		ok = yaffs_ReadCheckpointValidityMarker(dev, 1);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint device" TENDSTR)));
+		ok = yaffs_ReadCheckpointDevice(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint objects" TENDSTR)));
+		ok = yaffs_ReadCheckpointObjects(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint validity" TENDSTR)));
+		ok = yaffs_ReadCheckpointValidityMarker(dev, 0);
+	}
+
+	if (ok) {
+		ok = yaffs_ReadCheckpointSum(dev);
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint checksum %d" TENDSTR), ok));
+	}
+
+	if (!yaffs_CheckpointClose(dev))
+		ok = 0;
+
+	if (ok)
+		dev->isCheckpointed = 1;
+	else
+		dev->isCheckpointed = 0;
+
+	return ok ? 1 : 0;
+
+}
+
+static void yaffs_InvalidateCheckpoint(yaffs_Device *dev)
+{
+	if (dev->isCheckpointed ||
+			dev->blocksInCheckpoint > 0) {
+		dev->isCheckpointed = 0;
+		yaffs_CheckpointInvalidateStream(dev);
+	}
+	if (dev->param.markSuperBlockDirty)
+		dev->param.markSuperBlockDirty(dev);
+}
+
+
+int yaffs_CheckpointSave(yaffs_Device *dev)
+{
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("save entry: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	yaffs_VerifyObjects(dev);
+	yaffs_VerifyBlocks(dev);
+	yaffs_VerifyFreeChunks(dev);
+
+	if (!dev->isCheckpointed) {
+		yaffs_InvalidateCheckpoint(dev);
+		yaffs_WriteCheckpointData(dev);
+	}
+
+	T(YAFFS_TRACE_ALWAYS, (TSTR("save exit: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	return dev->isCheckpointed;
+}
+
+int yaffs_CheckpointRestore(yaffs_Device *dev)
+{
+	int retval;
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("restore entry: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	retval = yaffs_ReadCheckpointData(dev);
+
+	if (dev->isCheckpointed) {
+		yaffs_VerifyObjects(dev);
+		yaffs_VerifyBlocks(dev);
+		yaffs_VerifyFreeChunks(dev);
+	}
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("restore exit: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	return retval;
+}
+
+/*--------------------- File read/write ------------------------
+ * Read and write have very similar structures.
+ * In general the read/write has three parts to it
+ * An incomplete chunk to start with (if the read/write is not chunk-aligned)
+ * Some complete chunks
+ * An incomplete chunk to end off with
+ *
+ * Curve-balls: the first chunk might also be the last chunk.
+ */
+
+int yaffs_ReadDataFromFile(yaffs_Object *in, __u8 *buffer, loff_t offset,
+			int nBytes)
+{
+
+	int chunk;
+	__u32 start;
+	int nToCopy;
+	int n = nBytes;
+	int nDone = 0;
+	yaffs_ChunkCache *cache;
+
+	yaffs_Device *dev;
+
+	dev = in->myDev;
+
+	while (n > 0) {
+		/* chunk = offset / dev->nDataBytesPerChunk + 1; */
+		/* start = offset % dev->nDataBytesPerChunk; */
+		yaffs_AddrToChunk(dev, offset, &chunk, &start);
+		chunk++;
+
+		/* OK now check for the curveball where the start and end are in
+		 * the same chunk.
+		 */
+		if ((start + n) < dev->nDataBytesPerChunk)
+			nToCopy = n;
+		else
+			nToCopy = dev->nDataBytesPerChunk - start;
+
+		cache = yaffs_FindChunkCache(in, chunk);
+
+		/* If the chunk is already in the cache or it is less than a whole chunk
+		 * or we're using inband tags then use the cache (if there is caching)
+		 * else bypass the cache.
+		 */
+		if (cache || nToCopy != dev->nDataBytesPerChunk || dev->param.inbandTags) {
+			if (dev->param.nShortOpCaches > 0) {
+
+				/* If we can't find the data in the cache, then load it up. */
+
+				if (!cache) {
+					cache = yaffs_GrabChunkCache(in->myDev);
+					cache->object = in;
+					cache->chunkId = chunk;
+					cache->dirty = 0;
+					cache->locked = 0;
+					yaffs_ReadChunkDataFromObject(in, chunk,
+								      cache->
+								      data);
+					cache->nBytes = 0;
+				}
+
+				yaffs_UseChunkCache(dev, cache, 0);
+
+				cache->locked = 1;
+
+
+				memcpy(buffer, &cache->data[start], nToCopy);
+
+				cache->locked = 0;
+			} else {
+				/* Read into the local buffer then copy..*/
+
+				__u8 *localBuffer =
+				    yaffs_GetTempBuffer(dev, __LINE__);
+				yaffs_ReadChunkDataFromObject(in, chunk,
+							      localBuffer);
+
+				memcpy(buffer, &localBuffer[start], nToCopy);
+
+
+				yaffs_ReleaseTempBuffer(dev, localBuffer,
+							__LINE__);
+			}
+
+		} else {
+
+			/* A full chunk. Read directly into the supplied buffer. */
+			yaffs_ReadChunkDataFromObject(in, chunk, buffer);
+
+		}
+
+		n -= nToCopy;
+		offset += nToCopy;
+		buffer += nToCopy;
+		nDone += nToCopy;
+
+	}
+
+	return nDone;
+}
+
+int yaffs_DoWriteDataToFile(yaffs_Object *in, const __u8 *buffer, loff_t offset,
+			int nBytes, int writeThrough)
+{
+
+	int chunk;
+	__u32 start;
+	int nToCopy;
+	int n = nBytes;
+	int nDone = 0;
+	int nToWriteBack;
+	int startOfWrite = offset;
+	int chunkWritten = 0;
+	__u32 nBytesRead;
+	__u32 chunkStart;
+
+	yaffs_Device *dev;
+
+	dev = in->myDev;
+
+	while (n > 0 && chunkWritten >= 0) {
+		/* chunk = offset / dev->nDataBytesPerChunk + 1; */
+		/* start = offset % dev->nDataBytesPerChunk; */
+		yaffs_AddrToChunk(dev, offset, &chunk, &start);
+
+		if (chunk * dev->nDataBytesPerChunk + start != offset ||
+				start >= dev->nDataBytesPerChunk) {
+			T(YAFFS_TRACE_ERROR, (
+			   TSTR("AddrToChunk of offset %d gives chunk %d start %d"
+			   TENDSTR),
+			   (int)offset, chunk, start));
+		}
+		chunk++;
+
+		/* OK now check for the curveball where the start and end are in
+		 * the same chunk.
+		 */
+
+		if ((start + n) < dev->nDataBytesPerChunk) {
+			nToCopy = n;
+
+			/* Now folks, to calculate how many bytes to write back....
+			 * If we're overwriting and not writing to then end of file then
+			 * we need to write back as much as was there before.
+			 */
+
+			chunkStart = ((chunk - 1) * dev->nDataBytesPerChunk);
+
+			if (chunkStart > in->variant.fileVariant.fileSize)
+				nBytesRead = 0; /* Past end of file */
+			else
+				nBytesRead = in->variant.fileVariant.fileSize - chunkStart;
+
+			if (nBytesRead > dev->nDataBytesPerChunk)
+				nBytesRead = dev->nDataBytesPerChunk;
+
+			nToWriteBack =
+			    (nBytesRead >
+			     (start + n)) ? nBytesRead : (start + n);
+
+			if (nToWriteBack < 0 || nToWriteBack > dev->nDataBytesPerChunk)
+				YBUG();
+
+		} else {
+			nToCopy = dev->nDataBytesPerChunk - start;
+			nToWriteBack = dev->nDataBytesPerChunk;
+		}
+
+		if (nToCopy != dev->nDataBytesPerChunk || dev->param.inbandTags) {
+			/* An incomplete start or end chunk (or maybe both start and end chunk),
+			 * or we're using inband tags, so we want to use the cache buffers.
+			 */
+			if (dev->param.nShortOpCaches > 0) {
+				yaffs_ChunkCache *cache;
+				/* If we can't find the data in the cache, then load the cache */
+				cache = yaffs_FindChunkCache(in, chunk);
+
+				if (!cache
+				    && yaffs_CheckSpaceForAllocation(dev, 1)) {
+					cache = yaffs_GrabChunkCache(dev);
+					cache->object = in;
+					cache->chunkId = chunk;
+					cache->dirty = 0;
+					cache->locked = 0;
+					yaffs_ReadChunkDataFromObject(in, chunk,
+								      cache->data);
+				} else if (cache &&
+					!cache->dirty &&
+					!yaffs_CheckSpaceForAllocation(dev, 1)) {
+					/* Drop the cache if it was a read cache item and
+					 * no space check has been made for it.
+					 */
+					 cache = NULL;
+				}
+
+				if (cache) {
+					yaffs_UseChunkCache(dev, cache, 1);
+					cache->locked = 1;
+
+
+					memcpy(&cache->data[start], buffer,
+					       nToCopy);
+
+
+					cache->locked = 0;
+					cache->nBytes = nToWriteBack;
+
+					if (writeThrough) {
+						chunkWritten =
+						    yaffs_WriteChunkDataToObject
+						    (cache->object,
+						     cache->chunkId,
+						     cache->data, cache->nBytes,
+						     1);
+						cache->dirty = 0;
+					}
+
+				} else {
+					chunkWritten = -1;	/* fail the write */
+				}
+			} else {
+				/* An incomplete start or end chunk (or maybe both start and end chunk)
+				 * Read into the local buffer then copy, then copy over and write back.
+				 */
+
+				__u8 *localBuffer =
+				    yaffs_GetTempBuffer(dev, __LINE__);
+
+				yaffs_ReadChunkDataFromObject(in, chunk,
+							      localBuffer);
+
+
+
+				memcpy(&localBuffer[start], buffer, nToCopy);
+
+				chunkWritten =
+				    yaffs_WriteChunkDataToObject(in, chunk,
+								 localBuffer,
+								 nToWriteBack,
+								 0);
+
+				yaffs_ReleaseTempBuffer(dev, localBuffer,
+							__LINE__);
+
+			}
+
+		} else {
+			/* A full chunk. Write directly from the supplied buffer. */
+
+
+
+			chunkWritten =
+			    yaffs_WriteChunkDataToObject(in, chunk, buffer,
+							 dev->nDataBytesPerChunk,
+							 0);
+
+			/* Since we've overwritten the cached data, we better invalidate it. */
+			yaffs_InvalidateChunkCache(in, chunk);
+		}
+
+		if (chunkWritten >= 0) {
+			n -= nToCopy;
+			offset += nToCopy;
+			buffer += nToCopy;
+			nDone += nToCopy;
+		}
+
+	}
+
+	/* Update file object */
+
+	if ((startOfWrite + nDone) > in->variant.fileVariant.fileSize)
+		in->variant.fileVariant.fileSize = (startOfWrite + nDone);
+
+	in->dirty = 1;
+
+	return nDone;
+}
+
+int yaffs_WriteDataToFile(yaffs_Object *in, const __u8 *buffer, loff_t offset,
+			int nBytes, int writeThrough)
+{
+	yaffs_HandleHole(in,offset);
+	return yaffs_DoWriteDataToFile(in,buffer,offset,nBytes,writeThrough);
+}
+
+
+
+/* ---------------------- File resizing stuff ------------------ */
+
+static void yaffs_PruneResizedChunks(yaffs_Object *in, int newSize)
+{
+
+	yaffs_Device *dev = in->myDev;
+	int oldFileSize = in->variant.fileVariant.fileSize;
+
+	int lastDel = 1 + (oldFileSize - 1) / dev->nDataBytesPerChunk;
+
+	int startDel = 1 + (newSize + dev->nDataBytesPerChunk - 1) /
+	    dev->nDataBytesPerChunk;
+	int i;
+	int chunkId;
+
+	/* Delete backwards so that we don't end up with holes if
+	 * power is lost part-way through the operation.
+	 */
+	for (i = lastDel; i >= startDel; i--) {
+		/* NB this could be optimised somewhat,
+		 * eg. could retrieve the tags and write them without
+		 * using yaffs_DeleteChunk
+		 */
+
+		chunkId = yaffs_FindAndDeleteChunkInFile(in, i, NULL);
+		if (chunkId > 0) {
+			if (chunkId <
+			    (dev->internalStartBlock * dev->param.nChunksPerBlock)
+			    || chunkId >=
+			    ((dev->internalEndBlock +
+			      1) * dev->param.nChunksPerBlock)) {
+				T(YAFFS_TRACE_ALWAYS,
+				  (TSTR("Found daft chunkId %d for %d" TENDSTR),
+				   chunkId, i));
+			} else {
+				in->nDataChunks--;
+				yaffs_DeleteChunk(dev, chunkId, 1, __LINE__);
+			}
+		}
+	}
+
+}
+
+
+static void yaffs_ResizeDown( yaffs_Object *obj, loff_t newSize)
+{
+	int newFullChunks;
+	__u32 newSizeOfPartialChunk;
+	yaffs_Device *dev = obj->myDev;
+
+	yaffs_AddrToChunk(dev, newSize, &newFullChunks, &newSizeOfPartialChunk);
+
+	yaffs_PruneResizedChunks(obj, newSize);
+
+	if (newSizeOfPartialChunk != 0) {
+		int lastChunk = 1 + newFullChunks;
+		__u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+		/* Got to read and rewrite the last chunk with its new size and zero pad */
+		yaffs_ReadChunkDataFromObject(obj, lastChunk, localBuffer);
+		memset(localBuffer + newSizeOfPartialChunk, 0,
+			dev->nDataBytesPerChunk - newSizeOfPartialChunk);
+
+		yaffs_WriteChunkDataToObject(obj, lastChunk, localBuffer,
+					     newSizeOfPartialChunk, 1);
+
+		yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
+	}
+
+	obj->variant.fileVariant.fileSize = newSize;
+
+	yaffs_PruneFileStructure(dev, &obj->variant.fileVariant);
+}
+
+
+static int yaffs_HandleHole(yaffs_Object *obj, loff_t newSize)
+{
+	/* if newsSize > oldFileSize.
+	 * We're going to be writing a hole.
+	 * If the hole is small then write zeros otherwise write a start of hole marker.
+	 */
+		
+
+	loff_t oldFileSize;
+	int increase;
+	int smallHole   ;
+	int result = YAFFS_OK;
+	yaffs_Device *dev = NULL;
+
+	__u8 *localBuffer = NULL;
+	
+	int smallIncreaseOk = 0;
+	
+	if(!obj)
+		return YAFFS_FAIL;
+
+	if(obj->variantType != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
+	
+	dev = obj->myDev;
+	
+	/* Bail out if not yaffs2 mode */
+	if(!dev->param.isYaffs2)
+		return YAFFS_OK;
+
+	oldFileSize = obj->variant.fileVariant.fileSize;
+
+	if (newSize <= oldFileSize)
+		return YAFFS_OK;
+
+	increase = newSize - oldFileSize;
+
+	if(increase < YAFFS_SMALL_HOLE_THRESHOLD * dev->nDataBytesPerChunk &&
+		yaffs_CheckSpaceForAllocation(dev, YAFFS_SMALL_HOLE_THRESHOLD + 1))
+		smallHole = 1;
+	else
+		smallHole = 0;
+
+	if(smallHole)
+		localBuffer= yaffs_GetTempBuffer(dev, __LINE__);
+	
+	if(localBuffer){
+		/* fill hole with zero bytes */
+		int pos = oldFileSize;
+		int thisWrite;
+		int written;
+		memset(localBuffer,0,dev->nDataBytesPerChunk);
+		smallIncreaseOk = 1;
+
+		while(increase > 0 && smallIncreaseOk){
+			thisWrite = increase;
+			if(thisWrite > dev->nDataBytesPerChunk)
+				thisWrite = dev->nDataBytesPerChunk;
+			written = yaffs_DoWriteDataToFile(obj,localBuffer,pos,thisWrite,0);
+			if(written == thisWrite){
+				pos += thisWrite;
+				increase -= thisWrite;
+			} else
+				smallIncreaseOk = 0;
+		}
+
+		yaffs_ReleaseTempBuffer(dev,localBuffer,__LINE__);
+
+		/* If we were out of space then reverse any chunks we've added */		
+		if(!smallIncreaseOk)
+			yaffs_ResizeDown(obj, oldFileSize);
+	}
+	
+	if (!smallIncreaseOk &&
+		obj->parent &&
+		obj->parent->objectId != YAFFS_OBJECTID_UNLINKED &&
+		obj->parent->objectId != YAFFS_OBJECTID_DELETED){
+		/* Write a hole start header with the old file size */
+		yaffs_UpdateObjectHeader(obj, NULL, 0,1,0);
+	}
+
+	return result;
+
+}
+
+int yaffs_ResizeFile(yaffs_Object *in, loff_t newSize)
+{
+	yaffs_Device *dev = in->myDev;
+	int oldFileSize = in->variant.fileVariant.fileSize;
+
+	yaffs_FlushFilesChunkCache(in);
+	yaffs_InvalidateWholeChunkCache(in);
+
+	yaffs_CheckGarbageCollection(dev);
+
+	if (in->variantType != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
+
+	if (newSize == oldFileSize)
+		return YAFFS_OK;
+		
+	if(newSize > oldFileSize){
+		yaffs_HandleHole(in,newSize);
+		in->variant.fileVariant.fileSize = newSize;
+	} else {
+		/* newSize < oldFileSize */ 
+		yaffs_ResizeDown(in, newSize);
+	} 
+
+	/* Write a new object header to reflect the resize.
+	 * show we've shrunk the file, if need be
+	 * Do this only if the file is not in the deleted directories
+	 * and is not shadowed.
+	 */
+	if (in->parent &&
+	    !in->isShadowed &&
+	    in->parent->objectId != YAFFS_OBJECTID_UNLINKED &&
+	    in->parent->objectId != YAFFS_OBJECTID_DELETED)
+		yaffs_UpdateObjectHeader(in, NULL, 0,0,0);
+
+
+	return YAFFS_OK;
+}
+
+loff_t yaffs_GetFileSize(yaffs_Object *obj)
+{
+	YCHAR *alias = NULL;
+	obj = yaffs_GetEquivalentObject(obj);
+
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		return obj->variant.fileVariant.fileSize;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		alias = obj->variant.symLinkVariant.alias;
+		if(!alias)
+			return 0;
+		return yaffs_strnlen(alias,YAFFS_MAX_ALIAS_LENGTH);
+	default:
+		return 0;
+	}
+}
+
+
+
+int yaffs_FlushFile(yaffs_Object *in, int updateTime, int dataSync)
+{
+	int retVal;
+	if (in->dirty) {
+		yaffs_FlushFilesChunkCache(in);
+		if(dataSync) /* Only sync data */
+			retVal=YAFFS_OK;
+		else {
+			if (updateTime) {
+#ifdef CONFIG_YAFFS_WINCE
+				yfsd_WinFileTimeNow(in->win_mtime);
+#else
+
+				in->yst_mtime = Y_CURRENT_TIME;
+
+#endif
+			}
+
+			retVal = (yaffs_UpdateObjectHeader(in, NULL, 0, 0, 0) >=
+				0) ? YAFFS_OK : YAFFS_FAIL;
+		}
+	} else {
+		retVal = YAFFS_OK;
+	}
+
+	return retVal;
+
+}
+
+static int yaffs_DoGenericObjectDeletion(yaffs_Object *in)
+{
+
+	/* First off, invalidate the file's data in the cache, without flushing. */
+	yaffs_InvalidateWholeChunkCache(in);
+
+	if (in->myDev->param.isYaffs2 && (in->parent != in->myDev->deletedDir)) {
+		/* Move to the unlinked directory so we have a record that it was deleted. */
+		yaffs_ChangeObjectName(in, in->myDev->deletedDir, _Y("deleted"), 0, 0);
+
+	}
+
+	yaffs_RemoveObjectFromDirectory(in);
+	yaffs_DeleteChunk(in->myDev, in->hdrChunk, 1, __LINE__);
+	in->hdrChunk = 0;
+
+	yaffs_FreeObject(in);
+	return YAFFS_OK;
+
+}
+
+/* yaffs_DeleteFile deletes the whole file data
+ * and the inode associated with the file.
+ * It does not delete the links associated with the file.
+ */
+static int yaffs_UnlinkFileIfNeeded(yaffs_Object *in)
+{
+
+	int retVal;
+	int immediateDeletion = 0;
+
+	if (!in->myInode)
+		immediateDeletion = 1;
+
+	if (immediateDeletion) {
+		retVal =
+		    yaffs_ChangeObjectName(in, in->myDev->deletedDir,
+					   _Y("deleted"), 0, 0);
+		T(YAFFS_TRACE_TRACING,
+		  (TSTR("yaffs: immediate deletion of file %d" TENDSTR),
+		   in->objectId));
+		in->deleted = 1;
+		in->myDev->nDeletedFiles++;
+		if (1 || in->myDev->param.isYaffs2)
+			yaffs_ResizeFile(in, 0);
+		yaffs_SoftDeleteFile(in);
+	} else {
+		retVal =
+		    yaffs_ChangeObjectName(in, in->myDev->unlinkedDir,
+					   _Y("unlinked"), 0, 0);
+	}
+
+
+	return retVal;
+}
+
+int yaffs_DeleteFile(yaffs_Object *in)
+{
+	int retVal = YAFFS_OK;
+	int deleted = in->deleted;
+
+	yaffs_ResizeFile(in, 0);
+
+	if (in->nDataChunks > 0) {
+		/* Use soft deletion if there is data in the file.
+		 * That won't be the case if it has been resized to zero.
+		 */
+		if (!in->unlinked)
+			retVal = yaffs_UnlinkFileIfNeeded(in);
+
+		if (retVal == YAFFS_OK && in->unlinked && !in->deleted) {
+			in->deleted = 1;
+			deleted = 1;
+			in->myDev->nDeletedFiles++;
+			yaffs_SoftDeleteFile(in);
+		}
+		return deleted ? YAFFS_OK : YAFFS_FAIL;
+	} else {
+		/* The file has no data chunks so we toss it immediately */
+		yaffs_FreeTnode(in->myDev, in->variant.fileVariant.top);
+		in->variant.fileVariant.top = NULL;
+		yaffs_DoGenericObjectDeletion(in);
+
+		return YAFFS_OK;
+	}
+}
+
+static int yaffs_IsNonEmptyDirectory(yaffs_Object *obj)
+{
+	return (obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) &&
+		!(ylist_empty(&obj->variant.directoryVariant.children));
+}
+
+static int yaffs_DeleteDirectory(yaffs_Object *obj)
+{
+	/* First check that the directory is empty. */
+	if (yaffs_IsNonEmptyDirectory(obj))
+		return YAFFS_FAIL;
+
+	return yaffs_DoGenericObjectDeletion(obj);
+}
+
+static int yaffs_DeleteSymLink(yaffs_Object *in)
+{
+	if(in->variant.symLinkVariant.alias)
+		YFREE(in->variant.symLinkVariant.alias);
+	in->variant.symLinkVariant.alias=NULL;
+
+	return yaffs_DoGenericObjectDeletion(in);
+}
+
+static int yaffs_DeleteHardLink(yaffs_Object *in)
+{
+	/* remove this hardlink from the list assocaited with the equivalent
+	 * object
+	 */
+	ylist_del_init(&in->hardLinks);
+	return yaffs_DoGenericObjectDeletion(in);
+}
+
+int yaffs_DeleteObject(yaffs_Object *obj)
+{
+int retVal = -1;
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		retVal = yaffs_DeleteFile(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		if(!ylist_empty(&obj->variant.directoryVariant.dirty)){
+			T(YAFFS_TRACE_BACKGROUND, (TSTR("Remove object %d from dirty directories" TENDSTR),obj->objectId));
+			ylist_del_init(&obj->variant.directoryVariant.dirty);
+		}
+		return yaffs_DeleteDirectory(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		retVal = yaffs_DeleteSymLink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		retVal = yaffs_DeleteHardLink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		retVal = yaffs_DoGenericObjectDeletion(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+		retVal = 0;
+		break;		/* should not happen. */
+	}
+
+	return retVal;
+}
+
+static int yaffs_UnlinkWorker(yaffs_Object *obj)
+{
+
+	int immediateDeletion = 0;
+
+	if (!obj->myInode)
+		immediateDeletion = 1;
+
+	if(obj)
+		yaffs_UpdateParent(obj->parent);
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
+		return yaffs_DeleteHardLink(obj);
+	} else if (!ylist_empty(&obj->hardLinks)) {
+		/* Curve ball: We're unlinking an object that has a hardlink.
+		 *
+		 * This problem arises because we are not strictly following
+		 * The Linux link/inode model.
+		 *
+		 * We can't really delete the object.
+		 * Instead, we do the following:
+		 * - Select a hardlink.
+		 * - Unhook it from the hard links
+		 * - Move it from its parent directory (so that the rename can work)
+		 * - Rename the object to the hardlink's name.
+		 * - Delete the hardlink
+		 */
+
+		yaffs_Object *hl;
+		yaffs_Object *parent;
+		int retVal;
+		YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
+
+		hl = ylist_entry(obj->hardLinks.next, yaffs_Object, hardLinks);
+
+		yaffs_GetObjectName(hl, name, YAFFS_MAX_NAME_LENGTH + 1);
+		parent = hl->parent;
+
+		ylist_del_init(&hl->hardLinks);
+
+ 		yaffs_AddObjectToDirectory(obj->myDev->unlinkedDir, hl);
+
+		retVal = yaffs_ChangeObjectName(obj,parent, name, 0, 0);
+
+		if (retVal == YAFFS_OK)
+			retVal = yaffs_DoGenericObjectDeletion(hl);
+
+		return retVal;
+
+	} else if (immediateDeletion) {
+		switch (obj->variantType) {
+		case YAFFS_OBJECT_TYPE_FILE:
+			return yaffs_DeleteFile(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			ylist_del_init(&obj->variant.directoryVariant.dirty);
+			return yaffs_DeleteDirectory(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			return yaffs_DeleteSymLink(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+			return yaffs_DoGenericObjectDeletion(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+		default:
+			return YAFFS_FAIL;
+		}
+	} else if(yaffs_IsNonEmptyDirectory(obj))
+		return YAFFS_FAIL;
+	else
+		return yaffs_ChangeObjectName(obj, obj->myDev->unlinkedDir,
+					   _Y("unlinked"), 0, 0);
+}
+
+
+static int yaffs_UnlinkObject(yaffs_Object *obj)
+{
+
+	if (obj && obj->unlinkAllowed)
+		return yaffs_UnlinkWorker(obj);
+
+	return YAFFS_FAIL;
+
+}
+int yaffs_Unlink(yaffs_Object *dir, const YCHAR *name)
+{
+	yaffs_Object *obj;
+
+	obj = yaffs_FindObjectByName(dir, name);
+	return yaffs_UnlinkObject(obj);
+}
+
+/*----------------------- Initialisation Scanning ---------------------- */
+
+static void yaffs_HandleShadowedObject(yaffs_Device *dev, int objId,
+				int backwardScanning)
+{
+	yaffs_Object *obj;
+
+	if (!backwardScanning) {
+		/* Handle YAFFS1 forward scanning case
+		 * For YAFFS1 we always do the deletion
+		 */
+
+	} else {
+		/* Handle YAFFS2 case (backward scanning)
+		 * If the shadowed object exists then ignore.
+		 */
+		obj = yaffs_FindObjectByNumber(dev, objId);
+		if(obj)
+			return;
+	}
+
+	/* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc.
+	 * We put it in unlinked dir to be cleaned up after the scanning
+	 */
+	obj =
+	    yaffs_FindOrCreateObjectByNumber(dev, objId,
+					     YAFFS_OBJECT_TYPE_FILE);
+	if (!obj)
+		return;
+	obj->isShadowed = 1;
+	yaffs_AddObjectToDirectory(dev->unlinkedDir, obj);
+	obj->variant.fileVariant.shrinkSize = 0;
+	obj->valid = 1;		/* So that we don't read any other info for this file */
+
+}
+
+typedef struct {
+	int seq;
+	int block;
+} yaffs_BlockIndex;
+
+
+static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList)
+{
+	yaffs_Object *hl;
+	yaffs_Object *in;
+
+	while (hardList) {
+		hl = hardList;
+		hardList = (yaffs_Object *) (hardList->hardLinks.next);
+
+		in = yaffs_FindObjectByNumber(dev,
+					      hl->variant.hardLinkVariant.
+					      equivalentObjectId);
+
+		if (in) {
+			/* Add the hardlink pointers */
+			hl->variant.hardLinkVariant.equivalentObject = in;
+			ylist_add(&hl->hardLinks, &in->hardLinks);
+		} else {
+			/* Todo Need to report/handle this better.
+			 * Got a problem... hardlink to a non-existant object
+			 */
+			hl->variant.hardLinkVariant.equivalentObject = NULL;
+			YINIT_LIST_HEAD(&hl->hardLinks);
+
+		}
+	}
+}
+
+
+
+
+
+static int ybicmp(const void *a, const void *b)
+{
+	register int aseq = ((yaffs_BlockIndex *)a)->seq;
+	register int bseq = ((yaffs_BlockIndex *)b)->seq;
+	register int ablock = ((yaffs_BlockIndex *)a)->block;
+	register int bblock = ((yaffs_BlockIndex *)b)->block;
+	if (aseq == bseq)
+		return ablock - bblock;
+	else
+		return aseq - bseq;
+}
+
+
+struct yaffs_ShadowFixerStruct {
+	int objectId;
+	int shadowedId;
+	struct yaffs_ShadowFixerStruct *next;
+};
+
+
+static void yaffs_StripDeletedObjects(yaffs_Device *dev)
+{
+	/*
+	*  Sort out state of unlinked and deleted objects after scanning.
+	*/
+	struct ylist_head *i;
+	struct ylist_head *n;
+	yaffs_Object *l;
+
+	/* Soft delete all the unlinked files */
+	ylist_for_each_safe(i, n,
+		&dev->unlinkedDir->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+			yaffs_DeleteObject(l);
+		}
+	}
+
+	ylist_for_each_safe(i, n,
+		&dev->deletedDir->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+			yaffs_DeleteObject(l);
+		}
+	}
+
+}
+
+/*
+ * This code iterates through all the objects making sure that they are rooted.
+ * Any unrooted objects are re-rooted in lost+found.
+ * An object needs to be in one of:
+ * - Directly under deleted, unlinked
+ * - Directly or indirectly under root.
+ *
+ * Note:
+ *  This code assumes that we don't ever change the current relationships between
+ *  directories:
+ *   rootDir->parent == unlinkedDir->parent == deletedDir->parent == NULL
+ *   lostNfound->parent == rootDir
+ *
+ * This fixes the problem where directories might have inadvertently been deleted
+ * leaving the object "hanging" without being rooted in the directory tree.
+ */
+ 
+static int yaffs_HasNULLParent(yaffs_Device *dev, yaffs_Object *obj)
+{
+	return (obj == dev->deletedDir ||
+		obj == dev->unlinkedDir||
+		obj == dev->rootDir);
+}
+
+static void yaffs_FixHangingObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	yaffs_Object *parent;
+	int i;
+	struct ylist_head *lh;
+	struct ylist_head *n;
+	int depthLimit;
+	int hanging;
+
+
+	/* Iterate through the objects in each hash entry,
+	 * looking at each object.
+	 * Make sure it is rooted.
+	 */
+
+	for (i = 0; i <  YAFFS_NOBJECT_BUCKETS; i++) {
+		ylist_for_each_safe(lh, n, &dev->objectBucket[i].list) {
+			if (lh) {
+				obj = ylist_entry(lh, yaffs_Object, hashLink);
+				parent= obj->parent;
+				
+				if(yaffs_HasNULLParent(dev,obj)){
+					/* These directories are not hanging */
+					hanging = 0;
+				}
+				else if(!parent || parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+					hanging = 1;
+				else if(yaffs_HasNULLParent(dev,parent))
+					hanging = 0;
+				else {
+					/*
+					 * Need to follow the parent chain to see if it is hanging.
+					 */
+					hanging = 0;
+					depthLimit=100;
+
+					while(parent != dev->rootDir &&
+						parent->parent &&
+						parent->parent->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
+						depthLimit > 0){
+						parent = parent->parent;
+						depthLimit--;
+					}
+					if(parent != dev->rootDir)
+						hanging = 1;
+				}
+				if(hanging){
+					T(YAFFS_TRACE_SCAN,
+					  (TSTR("Hanging object %d moved to lost and found" TENDSTR),
+					  	obj->objectId));
+					yaffs_AddObjectToDirectory(dev->lostNFoundDir,obj);
+				}
+			}
+		}
+	}
+}
+
+
+/*
+ * Delete directory contents for cleaning up lost and found.
+ */
+static void yaffs_DeleteDirectoryContents(yaffs_Object *dir)
+{
+	yaffs_Object *obj;
+	struct ylist_head *lh;
+	struct ylist_head *n;
+
+	if(dir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+		YBUG();
+	
+	ylist_for_each_safe(lh, n, &dir->variant.directoryVariant.children) {
+		if (lh) {
+			obj = ylist_entry(lh, yaffs_Object, siblings);
+			if(obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY)
+				yaffs_DeleteDirectoryContents(obj);
+
+			T(YAFFS_TRACE_SCAN,
+				(TSTR("Deleting lost_found object %d" TENDSTR),
+				obj->objectId));
+
+			/* Need to use UnlinkObject since Delete would not handle
+			 * hardlinked objects correctly.
+			 */
+			yaffs_UnlinkObject(obj); 
+		}
+	}
+			
+}
+
+static void yaffs_EmptyLostAndFound(yaffs_Device *dev)
+{
+	yaffs_DeleteDirectoryContents(dev->lostNFoundDir);
+}
+
+static int yaffs_Scan(yaffs_Device *dev)
+{
+	yaffs_ExtendedTags tags;
+	int blk;
+	int blockIterator;
+	int startIterator;
+	int endIterator;
+	int result;
+
+	int chunk;
+	int c;
+	int deleted;
+	yaffs_BlockState state;
+	yaffs_Object *hardList = NULL;
+	yaffs_BlockInfo *bi;
+	__u32 sequenceNumber;
+	yaffs_ObjectHeader *oh;
+	yaffs_Object *in;
+	yaffs_Object *parent;
+
+	int alloc_failed = 0;
+
+	struct yaffs_ShadowFixerStruct *shadowFixerList = NULL;
+
+
+	__u8 *chunkData;
+
+
+
+	T(YAFFS_TRACE_SCAN,
+	  (TSTR("yaffs_Scan starts  intstartblk %d intendblk %d..." TENDSTR),
+	   dev->internalStartBlock, dev->internalEndBlock));
+
+	chunkData = yaffs_GetTempBuffer(dev, __LINE__);
+
+	dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+	/* Scan all the blocks to determine their state */
+	bi = dev->blockInfo;
+	for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
+		yaffs_ClearChunkBits(dev, blk);
+		bi->pagesInUse = 0;
+		bi->softDeletions = 0;
+
+		yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
+
+		bi->blockState = state;
+		bi->sequenceNumber = sequenceNumber;
+
+		if (bi->sequenceNumber == YAFFS_SEQUENCE_BAD_BLOCK)
+			bi->blockState = state = YAFFS_BLOCK_STATE_DEAD;
+
+		T(YAFFS_TRACE_SCAN_DEBUG,
+		  (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
+		   state, sequenceNumber));
+
+		if (state == YAFFS_BLOCK_STATE_DEAD) {
+			T(YAFFS_TRACE_BAD_BLOCKS,
+			  (TSTR("block %d is bad" TENDSTR), blk));
+		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
+			T(YAFFS_TRACE_SCAN_DEBUG,
+			  (TSTR("Block empty " TENDSTR)));
+			dev->nErasedBlocks++;
+			dev->nFreeChunks += dev->param.nChunksPerBlock;
+		}
+		bi++;
+	}
+
+	startIterator = dev->internalStartBlock;
+	endIterator = dev->internalEndBlock;
+
+	/* For each block.... */
+	for (blockIterator = startIterator; !alloc_failed && blockIterator <= endIterator;
+	     blockIterator++) {
+
+		YYIELD();
+
+		YYIELD();
+
+		blk = blockIterator;
+
+		bi = yaffs_GetBlockInfo(dev, blk);
+		state = bi->blockState;
+
+		deleted = 0;
+
+		/* For each chunk in each block that needs scanning....*/
+		for (c = 0; !alloc_failed && c < dev->param.nChunksPerBlock &&
+		     state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) {
+			/* Read the tags and decide what to do */
+			chunk = blk * dev->param.nChunksPerBlock + c;
+
+			result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
+							&tags);
+
+			/* Let's have a good look at this chunk... */
+
+			if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED || tags.chunkDeleted) {
+				/* YAFFS1 only...
+				 * A deleted chunk
+				 */
+				deleted++;
+				dev->nFreeChunks++;
+				/*T((" %d %d deleted\n",blk,c)); */
+			} else if (!tags.chunkUsed) {
+				/* An unassigned chunk in the block
+				 * This means that either the block is empty or
+				 * this is the one being allocated from
+				 */
+
+				if (c == 0) {
+					/* We're looking at the first chunk in the block so the block is unused */
+					state = YAFFS_BLOCK_STATE_EMPTY;
+					dev->nErasedBlocks++;
+				} else {
+					/* this is the block being allocated from */
+					T(YAFFS_TRACE_SCAN,
+					  (TSTR
+					   (" Allocating from %d %d" TENDSTR),
+					   blk, c));
+					state = YAFFS_BLOCK_STATE_ALLOCATING;
+					dev->allocationBlock = blk;
+					dev->allocationPage = c;
+					dev->allocationBlockFinder = blk;
+					/* Set block finder here to encourage the allocator to go forth from here. */
+
+				}
+
+				dev->nFreeChunks += (dev->param.nChunksPerBlock - c);
+			} else if (tags.chunkId > 0) {
+				/* chunkId > 0 so it is a data chunk... */
+				unsigned int endpos;
+
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				in = yaffs_FindOrCreateObjectByNumber(dev,
+								      tags.
+								      objectId,
+								      YAFFS_OBJECT_TYPE_FILE);
+				/* PutChunkIntoFile checks for a clash (two data chunks with
+				 * the same chunkId).
+				 */
+
+				if (!in)
+					alloc_failed = 1;
+
+				if (in) {
+					if (!yaffs_PutChunkIntoFile(in, tags.chunkId, chunk, 1))
+						alloc_failed = 1;
+				}
+
+				endpos =
+				    (tags.chunkId - 1) * dev->nDataBytesPerChunk +
+				    tags.byteCount;
+				if (in &&
+				    in->variantType == YAFFS_OBJECT_TYPE_FILE
+				    && in->variant.fileVariant.scannedFileSize <
+				    endpos) {
+					in->variant.fileVariant.
+					    scannedFileSize = endpos;
+					if (!dev->param.useHeaderFileSize) {
+						in->variant.fileVariant.
+						    fileSize =
+						    in->variant.fileVariant.
+						    scannedFileSize;
+					}
+
+				}
+				/* T((" %d %d data %d %d\n",blk,c,tags.objectId,tags.chunkId));   */
+			} else {
+				/* chunkId == 0, so it is an ObjectHeader.
+				 * Thus, we read in the object header and make the object
+				 */
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk,
+								chunkData,
+								NULL);
+
+				oh = (yaffs_ObjectHeader *) chunkData;
+
+				in = yaffs_FindObjectByNumber(dev,
+							      tags.objectId);
+				if (in && in->variantType != oh->type) {
+					/* This should not happen, but somehow
+					 * Wev'e ended up with an objectId that has been reused but not yet
+					 * deleted, and worse still it has changed type. Delete the old object.
+					 */
+
+					yaffs_DeleteObject(in);
+
+					in = 0;
+				}
+
+				in = yaffs_FindOrCreateObjectByNumber(dev,
+								      tags.
+								      objectId,
+								      oh->type);
+
+				if (!in)
+					alloc_failed = 1;
+
+				if (in && oh->shadowsObject > 0) {
+
+					struct yaffs_ShadowFixerStruct *fixer;
+					fixer = YMALLOC(sizeof(struct yaffs_ShadowFixerStruct));
+					if (fixer) {
+						fixer->next = shadowFixerList;
+						shadowFixerList = fixer;
+						fixer->objectId = tags.objectId;
+						fixer->shadowedId = oh->shadowsObject;
+					}
+
+				}
+
+				if (in && in->valid) {
+					/* We have already filled this one. We have a duplicate and need to resolve it. */
+
+					unsigned existingSerial = in->serial;
+					unsigned newSerial = tags.serialNumber;
+
+					if (((existingSerial + 1) & 3) == newSerial) {
+						/* Use new one - destroy the exisiting one */
+						yaffs_DeleteChunk(dev,
+								  in->hdrChunk,
+								  1, __LINE__);
+						in->valid = 0;
+					} else {
+						/* Use existing - destroy this one. */
+						yaffs_DeleteChunk(dev, chunk, 1,
+								  __LINE__);
+					}
+				}
+
+				if (in && !in->valid &&
+				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
+				     tags.objectId == YAFFS_OBJECTID_LOSTNFOUND)) {
+					/* We only load some info, don't fiddle with directory structure */
+					in->valid = 1;
+					in->variantType = oh->type;
+
+					in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+					in->win_atime[0] = oh->win_atime[0];
+					in->win_ctime[0] = oh->win_ctime[0];
+					in->win_mtime[0] = oh->win_mtime[0];
+					in->win_atime[1] = oh->win_atime[1];
+					in->win_ctime[1] = oh->win_ctime[1];
+					in->win_mtime[1] = oh->win_mtime[1];
+#else
+					in->yst_uid = oh->yst_uid;
+					in->yst_gid = oh->yst_gid;
+					in->yst_atime = oh->yst_atime;
+					in->yst_mtime = oh->yst_mtime;
+					in->yst_ctime = oh->yst_ctime;
+					in->yst_rdev = oh->yst_rdev;
+#endif
+					in->hdrChunk = chunk;
+					in->serial = tags.serialNumber;
+
+				} else if (in && !in->valid) {
+					/* we need to load this info */
+
+					in->valid = 1;
+					in->variantType = oh->type;
+
+					in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+					in->win_atime[0] = oh->win_atime[0];
+					in->win_ctime[0] = oh->win_ctime[0];
+					in->win_mtime[0] = oh->win_mtime[0];
+					in->win_atime[1] = oh->win_atime[1];
+					in->win_ctime[1] = oh->win_ctime[1];
+					in->win_mtime[1] = oh->win_mtime[1];
+#else
+					in->yst_uid = oh->yst_uid;
+					in->yst_gid = oh->yst_gid;
+					in->yst_atime = oh->yst_atime;
+					in->yst_mtime = oh->yst_mtime;
+					in->yst_ctime = oh->yst_ctime;
+					in->yst_rdev = oh->yst_rdev;
+#endif
+					in->hdrChunk = chunk;
+					in->serial = tags.serialNumber;
+
+					yaffs_SetObjectName(in, oh->name);
+					in->dirty = 0;
+
+					/* directory stuff...
+					 * hook up to parent
+					 */
+
+					parent =
+					    yaffs_FindOrCreateObjectByNumber
+					    (dev, oh->parentObjectId,
+					     YAFFS_OBJECT_TYPE_DIRECTORY);
+					if (!parent)
+						alloc_failed = 1;
+					if (parent && parent->variantType ==
+					    YAFFS_OBJECT_TYPE_UNKNOWN) {
+						/* Set up as a directory */
+						parent->variantType =
+							YAFFS_OBJECT_TYPE_DIRECTORY;
+						YINIT_LIST_HEAD(&parent->variant.
+								directoryVariant.
+								children);
+					} else if (!parent || parent->variantType !=
+						   YAFFS_OBJECT_TYPE_DIRECTORY) {
+						/* Hoosterman, another problem....
+						 * We're trying to use a non-directory as a directory
+						 */
+
+						T(YAFFS_TRACE_ERROR,
+						  (TSTR
+						   ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
+						    TENDSTR)));
+						parent = dev->lostNFoundDir;
+					}
+
+					yaffs_AddObjectToDirectory(parent, in);
+
+					if (0 && (parent == dev->deletedDir ||
+						  parent == dev->unlinkedDir)) {
+						in->deleted = 1;	/* If it is unlinked at start up then it wants deleting */
+						dev->nDeletedFiles++;
+					}
+					/* Note re hardlinks.
+					 * Since we might scan a hardlink before its equivalent object is scanned
+					 * we put them all in a list.
+					 * After scanning is complete, we should have all the objects, so we run through this
+					 * list and fix up all the chains.
+					 */
+
+					switch (in->variantType) {
+					case YAFFS_OBJECT_TYPE_UNKNOWN:
+						/* Todo got a problem */
+						break;
+					case YAFFS_OBJECT_TYPE_FILE:
+						if (dev->param.useHeaderFileSize)
+
+							in->variant.fileVariant.
+							    fileSize =
+							    oh->fileSize;
+
+						break;
+					case YAFFS_OBJECT_TYPE_HARDLINK:
+						in->variant.hardLinkVariant.
+							equivalentObjectId =
+							oh->equivalentObjectId;
+						in->hardLinks.next =
+							(struct ylist_head *)
+							hardList;
+						hardList = in;
+						break;
+					case YAFFS_OBJECT_TYPE_DIRECTORY:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SPECIAL:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SYMLINK:
+						in->variant.symLinkVariant.alias =
+						    yaffs_CloneString(oh->alias);
+						if (!in->variant.symLinkVariant.alias)
+							alloc_failed = 1;
+						break;
+					}
+
+				}
+			}
+		}
+
+		if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+			/* If we got this far while scanning, then the block is fully allocated.*/
+			state = YAFFS_BLOCK_STATE_FULL;
+		}
+
+		if (state == YAFFS_BLOCK_STATE_ALLOCATING) {
+			/* If the block was partially allocated then treat it as fully allocated.*/
+			state = YAFFS_BLOCK_STATE_FULL;
+			dev->allocationBlock = -1;
+		}
+
+		bi->blockState = state;
+
+		/* Now let's see if it was dirty */
+		if (bi->pagesInUse == 0 &&
+		    !bi->hasShrinkHeader &&
+		    bi->blockState == YAFFS_BLOCK_STATE_FULL) {
+			yaffs_BlockBecameDirty(dev, blk);
+		}
+
+	}
+
+
+	/* Ok, we've done all the scanning.
+	 * Fix up the hard link chains.
+	 * We should now have scanned all the objects, now it's time to add these
+	 * hardlinks.
+	 */
+
+	yaffs_HardlinkFixup(dev, hardList);
+
+	/* Fix up any shadowed objects */
+	{
+		struct yaffs_ShadowFixerStruct *fixer;
+		yaffs_Object *obj;
+
+		while (shadowFixerList) {
+			fixer = shadowFixerList;
+			shadowFixerList = fixer->next;
+			/* Complete the rename transaction by deleting the shadowed object
+			 * then setting the object header to unshadowed.
+			 */
+			obj = yaffs_FindObjectByNumber(dev, fixer->shadowedId);
+			if (obj)
+				yaffs_DeleteObject(obj);
+
+			obj = yaffs_FindObjectByNumber(dev, fixer->objectId);
+
+			if (obj)
+				yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0);
+
+			YFREE(fixer);
+		}
+	}
+
+	yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
+
+	if (alloc_failed)
+		return YAFFS_FAIL;
+
+	T(YAFFS_TRACE_SCAN, (TSTR("yaffs_Scan ends" TENDSTR)));
+
+
+	return YAFFS_OK;
+}
+
+static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in)
+{
+	__u8 *chunkData;
+	yaffs_ObjectHeader *oh;
+	yaffs_Device *dev;
+	yaffs_ExtendedTags tags;
+	int result;
+	int alloc_failed = 0;
+
+	if (!in)
+		return;
+
+	dev = in->myDev;
+
+#if 0
+	T(YAFFS_TRACE_SCAN, (TSTR("details for object %d %s loaded" TENDSTR),
+		in->objectId,
+		in->lazyLoaded ? "not yet" : "already"));
+#endif
+
+	if (in->lazyLoaded && in->hdrChunk > 0) {
+		in->lazyLoaded = 0;
+		chunkData = yaffs_GetTempBuffer(dev, __LINE__);
+
+		result = yaffs_ReadChunkWithTagsFromNAND(dev, in->hdrChunk, chunkData, &tags);
+		oh = (yaffs_ObjectHeader *) chunkData;
+
+		in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+		in->win_atime[0] = oh->win_atime[0];
+		in->win_ctime[0] = oh->win_ctime[0];
+		in->win_mtime[0] = oh->win_mtime[0];
+		in->win_atime[1] = oh->win_atime[1];
+		in->win_ctime[1] = oh->win_ctime[1];
+		in->win_mtime[1] = oh->win_mtime[1];
+#else
+		in->yst_uid = oh->yst_uid;
+		in->yst_gid = oh->yst_gid;
+		in->yst_atime = oh->yst_atime;
+		in->yst_mtime = oh->yst_mtime;
+		in->yst_ctime = oh->yst_ctime;
+		in->yst_rdev = oh->yst_rdev;
+
+#endif
+		yaffs_SetObjectName(in, oh->name);
+
+		if (in->variantType == YAFFS_OBJECT_TYPE_SYMLINK) {
+			in->variant.symLinkVariant.alias =
+						    yaffs_CloneString(oh->alias);
+			if (!in->variant.symLinkVariant.alias)
+				alloc_failed = 1; /* Not returned to caller */
+		}
+
+		yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
+	}
+}
+
+static int yaffs_ScanBackwards(yaffs_Device *dev)
+{
+	yaffs_ExtendedTags tags;
+	int blk;
+	int blockIterator;
+	int startIterator;
+	int endIterator;
+	int nBlocksToScan = 0;
+
+	int chunk;
+	int result;
+	int c;
+	int deleted;
+	yaffs_BlockState state;
+	yaffs_Object *hardList = NULL;
+	yaffs_BlockInfo *bi;
+	__u32 sequenceNumber;
+	yaffs_ObjectHeader *oh;
+	yaffs_Object *in;
+	yaffs_Object *parent;
+	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
+	int itsUnlinked;
+	__u8 *chunkData;
+
+	int fileSize;
+	int isShrink;
+	int foundChunksInBlock;
+	int equivalentObjectId;
+	int alloc_failed = 0;
+
+
+	yaffs_BlockIndex *blockIndex = NULL;
+	int altBlockIndex = 0;
+
+	if (!dev->param.isYaffs2) {
+		T(YAFFS_TRACE_SCAN,
+		  (TSTR("yaffs_ScanBackwards is only for YAFFS2!" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	T(YAFFS_TRACE_SCAN,
+	  (TSTR
+	   ("yaffs_ScanBackwards starts  intstartblk %d intendblk %d..."
+	    TENDSTR), dev->internalStartBlock, dev->internalEndBlock));
+
+
+	dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+	blockIndex = YMALLOC(nBlocks * sizeof(yaffs_BlockIndex));
+
+	if (!blockIndex) {
+		blockIndex = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockIndex));
+		altBlockIndex = 1;
+	}
+
+	if (!blockIndex) {
+		T(YAFFS_TRACE_SCAN,
+		  (TSTR("yaffs_Scan() could not allocate block index!" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	dev->blocksInCheckpoint = 0;
+
+	chunkData = yaffs_GetTempBuffer(dev, __LINE__);
+
+	/* Scan all the blocks to determine their state */
+	bi = dev->blockInfo;
+	for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
+		yaffs_ClearChunkBits(dev, blk);
+		bi->pagesInUse = 0;
+		bi->softDeletions = 0;
+
+		yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
+
+		bi->blockState = state;
+		bi->sequenceNumber = sequenceNumber;
+
+		if (bi->sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA)
+			bi->blockState = state = YAFFS_BLOCK_STATE_CHECKPOINT;
+		if (bi->sequenceNumber == YAFFS_SEQUENCE_BAD_BLOCK)
+			bi->blockState = state = YAFFS_BLOCK_STATE_DEAD;
+
+		T(YAFFS_TRACE_SCAN_DEBUG,
+		  (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
+		   state, sequenceNumber));
+
+
+		if (state == YAFFS_BLOCK_STATE_CHECKPOINT) {
+			dev->blocksInCheckpoint++;
+
+		} else if (state == YAFFS_BLOCK_STATE_DEAD) {
+			T(YAFFS_TRACE_BAD_BLOCKS,
+			  (TSTR("block %d is bad" TENDSTR), blk));
+		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
+			T(YAFFS_TRACE_SCAN_DEBUG,
+			  (TSTR("Block empty " TENDSTR)));
+			dev->nErasedBlocks++;
+			dev->nFreeChunks += dev->param.nChunksPerBlock;
+		} else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+
+			/* Determine the highest sequence number */
+			if (sequenceNumber >= YAFFS_LOWEST_SEQUENCE_NUMBER &&
+			    sequenceNumber < YAFFS_HIGHEST_SEQUENCE_NUMBER) {
+
+				blockIndex[nBlocksToScan].seq = sequenceNumber;
+				blockIndex[nBlocksToScan].block = blk;
+
+				nBlocksToScan++;
+
+				if (sequenceNumber >= dev->sequenceNumber)
+					dev->sequenceNumber = sequenceNumber;
+			} else {
+				/* TODO: Nasty sequence number! */
+				T(YAFFS_TRACE_SCAN,
+				  (TSTR
+				   ("Block scanning block %d has bad sequence number %d"
+				    TENDSTR), blk, sequenceNumber));
+
+			}
+		}
+		bi++;
+	}
+
+	T(YAFFS_TRACE_SCAN,
+	(TSTR("%d blocks to be sorted..." TENDSTR), nBlocksToScan));
+
+
+
+	YYIELD();
+
+	/* Sort the blocks */
+#ifndef CONFIG_YAFFS_USE_OWN_SORT
+	{
+		/* Use qsort now. */
+		yaffs_qsort(blockIndex, nBlocksToScan, sizeof(yaffs_BlockIndex), ybicmp);
+	}
+#else
+	{
+		/* Dungy old bubble sort... */
+
+		yaffs_BlockIndex temp;
+		int i;
+		int j;
+
+		for (i = 0; i < nBlocksToScan; i++)
+			for (j = i + 1; j < nBlocksToScan; j++)
+				if (blockIndex[i].seq > blockIndex[j].seq) {
+					temp = blockIndex[j];
+					blockIndex[j] = blockIndex[i];
+					blockIndex[i] = temp;
+				}
+	}
+#endif
+
+	YYIELD();
+
+	T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR)));
+
+	/* Now scan the blocks looking at the data. */
+	startIterator = 0;
+	endIterator = nBlocksToScan - 1;
+	T(YAFFS_TRACE_SCAN_DEBUG,
+	  (TSTR("%d blocks to be scanned" TENDSTR), nBlocksToScan));
+
+	/* For each block.... backwards */
+	for (blockIterator = endIterator; !alloc_failed && blockIterator >= startIterator;
+			blockIterator--) {
+		/* Cooperative multitasking! This loop can run for so
+		   long that watchdog timers expire. */
+		YYIELD();
+
+		/* get the block to scan in the correct order */
+		blk = blockIndex[blockIterator].block;
+
+		bi = yaffs_GetBlockInfo(dev, blk);
+
+
+		state = bi->blockState;
+
+		deleted = 0;
+
+		/* For each chunk in each block that needs scanning.... */
+		foundChunksInBlock = 0;
+		for (c = dev->param.nChunksPerBlock - 1;
+		     !alloc_failed && c >= 0 &&
+		     (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
+		      state == YAFFS_BLOCK_STATE_ALLOCATING); c--) {
+			/* Scan backwards...
+			 * Read the tags and decide what to do
+			 */
+
+			chunk = blk * dev->param.nChunksPerBlock + c;
+
+			result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
+							&tags);
+
+			/* Let's have a good look at this chunk... */
+
+			if (!tags.chunkUsed) {
+				/* An unassigned chunk in the block.
+				 * If there are used chunks after this one, then
+				 * it is a chunk that was skipped due to failing the erased
+				 * check. Just skip it so that it can be deleted.
+				 * But, more typically, We get here when this is an unallocated
+				 * chunk and his means that either the block is empty or
+				 * this is the one being allocated from
+				 */
+
+				if (foundChunksInBlock) {
+					/* This is a chunk that was skipped due to failing the erased check */
+				} else if (c == 0) {
+					/* We're looking at the first chunk in the block so the block is unused */
+					state = YAFFS_BLOCK_STATE_EMPTY;
+					dev->nErasedBlocks++;
+				} else {
+					if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
+					    state == YAFFS_BLOCK_STATE_ALLOCATING) {
+						if (dev->sequenceNumber == bi->sequenceNumber) {
+							/* this is the block being allocated from */
+
+							T(YAFFS_TRACE_SCAN,
+							  (TSTR
+							   (" Allocating from %d %d"
+							    TENDSTR), blk, c));
+
+							state = YAFFS_BLOCK_STATE_ALLOCATING;
+							dev->allocationBlock = blk;
+							dev->allocationPage = c;
+							dev->allocationBlockFinder = blk;
+						} else {
+							/* This is a partially written block that is not
+							 * the current allocation block.
+							 */
+
+							 T(YAFFS_TRACE_ALWAYS,
+							 (TSTR("Partially written block %d detected" TENDSTR),
+							 blk));
+						}
+					}
+				}
+
+				dev->nFreeChunks++;
+
+			} else if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED) {
+				T(YAFFS_TRACE_SCAN,
+				  (TSTR(" Unfixed ECC in chunk(%d:%d), chunk ignored"TENDSTR),
+				  blk, c));
+
+				  dev->nFreeChunks++;
+
+			} else if (tags.chunkId > 0) {
+				/* chunkId > 0 so it is a data chunk... */
+				unsigned int endpos;
+				__u32 chunkBase =
+				    (tags.chunkId - 1) * dev->nDataBytesPerChunk;
+
+				foundChunksInBlock = 1;
+
+
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				in = yaffs_FindOrCreateObjectByNumber(dev,
+								      tags.
+								      objectId,
+								      YAFFS_OBJECT_TYPE_FILE);
+				if (!in) {
+					/* Out of memory */
+					alloc_failed = 1;
+				}
+
+				if (in &&
+				    in->variantType == YAFFS_OBJECT_TYPE_FILE
+				    && chunkBase < in->variant.fileVariant.shrinkSize) {
+					/* This has not been invalidated by a resize */
+					if (!yaffs_PutChunkIntoFile(in, tags.chunkId, chunk, -1)) {
+						alloc_failed = 1;
+					}
+
+					/* File size is calculated by looking at the data chunks if we have not
+					 * seen an object header yet. Stop this practice once we find an object header.
+					 */
+					endpos = chunkBase + tags.byteCount;
+
+					if (!in->valid &&	/* have not got an object header yet */
+					    in->variant.fileVariant.scannedFileSize < endpos) {
+						in->variant.fileVariant.scannedFileSize = endpos;
+						in->variant.fileVariant.fileSize = endpos;
+					}
+
+				} else if (in) {
+					/* This chunk has been invalidated by a resize, or a past file deletion
+					 * so delete the chunk*/
+					yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
+
+				}
+			} else {
+				/* chunkId == 0, so it is an ObjectHeader.
+				 * Thus, we read in the object header and make the object
+				 */
+				foundChunksInBlock = 1;
+
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				oh = NULL;
+				in = NULL;
+
+				if (tags.extraHeaderInfoAvailable) {
+					in = yaffs_FindOrCreateObjectByNumber(dev,
+						tags.objectId,
+						tags.extraObjectType);
+					if (!in)
+						alloc_failed = 1;
+				}
+
+				if (!in ||
+				    (!in->valid && dev->param.disableLazyLoad) ||
+				    tags.extraShadows ||
+				    (!in->valid &&
+				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
+				     tags.objectId == YAFFS_OBJECTID_LOSTNFOUND))) {
+
+					/* If we don't have  valid info then we need to read the chunk
+					 * TODO In future we can probably defer reading the chunk and
+					 * living with invalid data until needed.
+					 */
+
+					result = yaffs_ReadChunkWithTagsFromNAND(dev,
+									chunk,
+									chunkData,
+									NULL);
+
+					oh = (yaffs_ObjectHeader *) chunkData;
+
+					if (dev->param.inbandTags) {
+						/* Fix up the header if they got corrupted by inband tags */
+						oh->shadowsObject = oh->inbandShadowsObject;
+						oh->isShrink = oh->inbandIsShrink;
+					}
+
+					if (!in) {
+						in = yaffs_FindOrCreateObjectByNumber(dev, tags.objectId, oh->type);
+						if (!in)
+							alloc_failed = 1;
+					}
+
+				}
+
+				if (!in) {
+					/* TODO Hoosterman we have a problem! */
+					T(YAFFS_TRACE_ERROR,
+					  (TSTR
+					   ("yaffs tragedy: Could not make object for object  %d at chunk %d during scan"
+					    TENDSTR), tags.objectId, chunk));
+					continue;
+				}
+
+				if (in->valid) {
+					/* We have already filled this one.
+					 * We have a duplicate that will be discarded, but
+					 * we first have to suck out resize info if it is a file.
+					 */
+
+					if ((in->variantType == YAFFS_OBJECT_TYPE_FILE) &&
+					     ((oh &&
+					       oh->type == YAFFS_OBJECT_TYPE_FILE) ||
+					      (tags.extraHeaderInfoAvailable  &&
+					       tags.extraObjectType == YAFFS_OBJECT_TYPE_FILE))) {
+						__u32 thisSize =
+						    (oh) ? oh->fileSize : tags.
+						    extraFileLength;
+						__u32 parentObjectId =
+						    (oh) ? oh->
+						    parentObjectId : tags.
+						    extraParentObjectId;
+
+
+						isShrink =
+						    (oh) ? oh->isShrink : tags.
+						    extraIsShrinkHeader;
+
+						/* If it is deleted (unlinked at start also means deleted)
+						 * we treat the file size as being zeroed at this point.
+						 */
+						if (parentObjectId ==
+						    YAFFS_OBJECTID_DELETED
+						    || parentObjectId ==
+						    YAFFS_OBJECTID_UNLINKED) {
+							thisSize = 0;
+							isShrink = 1;
+						}
+
+						if (isShrink && in->variant.fileVariant.shrinkSize > thisSize)
+							in->variant.fileVariant.shrinkSize = thisSize;
+
+						if (isShrink)
+							bi->hasShrinkHeader = 1;
+
+					}
+					/* Use existing - destroy this one. */
+					yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
+
+				}
+
+				if (!in->valid && in->variantType !=
+				    (oh ? oh->type : tags.extraObjectType))
+					T(YAFFS_TRACE_ERROR, (
+						TSTR("yaffs tragedy: Bad object type, "
+					    TCONT("%d != %d, for object %d at chunk ")
+					    TCONT("%d during scan")
+						TENDSTR), oh ?
+					    oh->type : tags.extraObjectType,
+					    in->variantType, tags.objectId,
+					    chunk));
+
+				if (!in->valid &&
+				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
+				     tags.objectId ==
+				     YAFFS_OBJECTID_LOSTNFOUND)) {
+					/* We only load some info, don't fiddle with directory structure */
+					in->valid = 1;
+
+					if (oh) {
+						in->variantType = oh->type;
+
+						in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+						in->win_atime[0] = oh->win_atime[0];
+						in->win_ctime[0] = oh->win_ctime[0];
+						in->win_mtime[0] = oh->win_mtime[0];
+						in->win_atime[1] = oh->win_atime[1];
+						in->win_ctime[1] = oh->win_ctime[1];
+						in->win_mtime[1] = oh->win_mtime[1];
+#else
+						in->yst_uid = oh->yst_uid;
+						in->yst_gid = oh->yst_gid;
+						in->yst_atime = oh->yst_atime;
+						in->yst_mtime = oh->yst_mtime;
+						in->yst_ctime = oh->yst_ctime;
+						in->yst_rdev = oh->yst_rdev;
+
+#endif
+					} else {
+						in->variantType = tags.extraObjectType;
+						in->lazyLoaded = 1;
+					}
+
+					in->hdrChunk = chunk;
+
+				} else if (!in->valid) {
+					/* we need to load this info */
+
+					in->valid = 1;
+					in->hdrChunk = chunk;
+
+					if (oh) {
+						in->variantType = oh->type;
+
+						in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+						in->win_atime[0] = oh->win_atime[0];
+						in->win_ctime[0] = oh->win_ctime[0];
+						in->win_mtime[0] = oh->win_mtime[0];
+						in->win_atime[1] = oh->win_atime[1];
+						in->win_ctime[1] = oh->win_ctime[1];
+						in->win_mtime[1] = oh->win_mtime[1];
+#else
+						in->yst_uid = oh->yst_uid;
+						in->yst_gid = oh->yst_gid;
+						in->yst_atime = oh->yst_atime;
+						in->yst_mtime = oh->yst_mtime;
+						in->yst_ctime = oh->yst_ctime;
+						in->yst_rdev = oh->yst_rdev;
+#endif
+
+						if (oh->shadowsObject > 0)
+							yaffs_HandleShadowedObject(dev,
+									   oh->
+									   shadowsObject,
+									   1);
+							
+
+
+						yaffs_SetObjectName(in, oh->name);
+						parent =
+						    yaffs_FindOrCreateObjectByNumber
+							(dev, oh->parentObjectId,
+							 YAFFS_OBJECT_TYPE_DIRECTORY);
+
+						 fileSize = oh->fileSize;
+						 isShrink = oh->isShrink;
+						 equivalentObjectId = oh->equivalentObjectId;
+
+					} else {
+						in->variantType = tags.extraObjectType;
+						parent =
+						    yaffs_FindOrCreateObjectByNumber
+							(dev, tags.extraParentObjectId,
+							 YAFFS_OBJECT_TYPE_DIRECTORY);
+						 fileSize = tags.extraFileLength;
+						 isShrink = tags.extraIsShrinkHeader;
+						 equivalentObjectId = tags.extraEquivalentObjectId;
+						in->lazyLoaded = 1;
+
+					}
+					in->dirty = 0;
+
+					if (!parent)
+						alloc_failed = 1;
+
+					/* directory stuff...
+					 * hook up to parent
+					 */
+
+					if (parent && parent->variantType ==
+					    YAFFS_OBJECT_TYPE_UNKNOWN) {
+						/* Set up as a directory */
+						parent->variantType =
+							YAFFS_OBJECT_TYPE_DIRECTORY;
+						YINIT_LIST_HEAD(&parent->variant.
+							directoryVariant.
+							children);
+					} else if (!parent || parent->variantType !=
+						   YAFFS_OBJECT_TYPE_DIRECTORY) {
+						/* Hoosterman, another problem....
+						 * We're trying to use a non-directory as a directory
+						 */
+
+						T(YAFFS_TRACE_ERROR,
+						  (TSTR
+						   ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
+						    TENDSTR)));
+						parent = dev->lostNFoundDir;
+					}
+
+					yaffs_AddObjectToDirectory(parent, in);
+
+					itsUnlinked = (parent == dev->deletedDir) ||
+						      (parent == dev->unlinkedDir);
+
+					if (isShrink) {
+						/* Mark the block as having a shrinkHeader */
+						bi->hasShrinkHeader = 1;
+					}
+
+					/* Note re hardlinks.
+					 * Since we might scan a hardlink before its equivalent object is scanned
+					 * we put them all in a list.
+					 * After scanning is complete, we should have all the objects, so we run
+					 * through this list and fix up all the chains.
+					 */
+
+					switch (in->variantType) {
+					case YAFFS_OBJECT_TYPE_UNKNOWN:
+						/* Todo got a problem */
+						break;
+					case YAFFS_OBJECT_TYPE_FILE:
+
+						if (in->variant.fileVariant.
+						    scannedFileSize < fileSize) {
+							/* This covers the case where the file size is greater
+							 * than where the data is
+							 * This will happen if the file is resized to be larger
+							 * than its current data extents.
+							 */
+							in->variant.fileVariant.fileSize = fileSize;
+							in->variant.fileVariant.scannedFileSize = fileSize;
+						}
+
+						if (in->variant.fileVariant.shrinkSize > fileSize)
+							in->variant.fileVariant.shrinkSize = fileSize;
+				
+
+						break;
+					case YAFFS_OBJECT_TYPE_HARDLINK:
+						if (!itsUnlinked) {
+							in->variant.hardLinkVariant.equivalentObjectId =
+								equivalentObjectId;
+							in->hardLinks.next =
+								(struct ylist_head *) hardList;
+							hardList = in;
+						}
+						break;
+					case YAFFS_OBJECT_TYPE_DIRECTORY:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SPECIAL:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SYMLINK:
+						if (oh) {
+							in->variant.symLinkVariant.alias =
+								yaffs_CloneString(oh->alias);
+							if (!in->variant.symLinkVariant.alias)
+								alloc_failed = 1;
+						}
+						break;
+					}
+
+				}
+
+			}
+
+		} /* End of scanning for each chunk */
+
+		if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+			/* If we got this far while scanning, then the block is fully allocated. */
+			state = YAFFS_BLOCK_STATE_FULL;
+		}
+
+
+		bi->blockState = state;
+
+		/* Now let's see if it was dirty */
+		if (bi->pagesInUse == 0 &&
+		    !bi->hasShrinkHeader &&
+		    bi->blockState == YAFFS_BLOCK_STATE_FULL) {
+			yaffs_BlockBecameDirty(dev, blk);
+		}
+
+	}
+	
+	yaffs_SkipRestOfBlock(dev);
+
+	if (altBlockIndex)
+		YFREE_ALT(blockIndex);
+	else
+		YFREE(blockIndex);
+
+	/* Ok, we've done all the scanning.
+	 * Fix up the hard link chains.
+	 * We should now have scanned all the objects, now it's time to add these
+	 * hardlinks.
+	 */
+	yaffs_HardlinkFixup(dev, hardList);
+
+
+	yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
+
+	if (alloc_failed)
+		return YAFFS_FAIL;
+
+	T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards ends" TENDSTR)));
+
+	return YAFFS_OK;
+}
+
+/*------------------------------  Directory Functions ----------------------------- */
+
+static void yaffs_VerifyObjectInDirectory(yaffs_Object *obj)
+{
+	struct ylist_head *lh;
+	yaffs_Object *listObj;
+
+	int count = 0;
+
+	if (!obj) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("No object to verify" TENDSTR)));
+		YBUG();
+		return;
+	}
+
+	if (yaffs_SkipVerification(obj->myDev))
+		return;
+
+	if (!obj->parent) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Object does not have parent" TENDSTR)));
+		YBUG();
+		return;
+	}
+
+	if (obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Parent is not directory" TENDSTR)));
+		YBUG();
+	}
+
+	/* Iterate through the objects in each hash entry */
+
+	ylist_for_each(lh, &obj->parent->variant.directoryVariant.children) {
+		if (lh) {
+			listObj = ylist_entry(lh, yaffs_Object, siblings);
+			yaffs_VerifyObject(listObj);
+			if (obj == listObj)
+				count++;
+		}
+	 }
+
+	if (count != 1) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory %d times" TENDSTR), count));
+		YBUG();
+	}
+}
+
+static void yaffs_VerifyDirectory(yaffs_Object *directory)
+{
+	struct ylist_head *lh;
+	yaffs_Object *listObj;
+
+	if (!directory) {
+		YBUG();
+		return;
+	}
+
+	if (yaffs_SkipFullVerification(directory->myDev))
+		return;
+
+	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Directory has wrong type: %d" TENDSTR), directory->variantType));
+		YBUG();
+	}
+
+	/* Iterate through the objects in each hash entry */
+
+	ylist_for_each(lh, &directory->variant.directoryVariant.children) {
+		if (lh) {
+			listObj = ylist_entry(lh, yaffs_Object, siblings);
+			if (listObj->parent != directory) {
+				T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory list has wrong parent %p" TENDSTR), listObj->parent));
+				YBUG();
+			}
+			yaffs_VerifyObjectInDirectory(listObj);
+		}
+	}
+}
+
+/*
+ *yaffs_UpdateParent() handles fixing a directories mtime and ctime when a new
+ * link (ie. name) is created or deleted in the directory.
+ *
+ * ie.
+ *   create dir/a : update dir's mtime/ctime
+ *   rm dir/a:   update dir's mtime/ctime
+ *   modify dir/a: don't update dir's mtimme/ctime
+ *
+ * This can be handled immediately or defered. Defering helps reduce the number
+ * of updates when many files in a directory are changed within a brief period.
+ *
+ * If the directory updating is defered then yaffs_UpdateDirtyDirecories must be
+ * called periodically.
+ */
+ 
+static void yaffs_UpdateParent(yaffs_Object *obj)
+{
+	yaffs_Device *dev;
+	if(!obj)
+		return;
+
+	dev = obj->myDev;
+	obj->dirty = 1;
+	obj->yst_mtime = obj->yst_ctime = Y_CURRENT_TIME;
+	if(dev->param.deferDirectoryUpdate){
+		struct ylist_head *link = &obj->variant.directoryVariant.dirty; 
+	
+		if(ylist_empty(link)){
+			ylist_add(link,&dev->dirtyDirectories);
+			T(YAFFS_TRACE_BACKGROUND, (TSTR("Added object %d to dirty directories" TENDSTR),obj->objectId));
+		}
+
+	} else
+		yaffs_UpdateObjectHeader(obj,NULL,0,0,0);
+}
+
+void yaffs_UpdateDirtyDirectories(yaffs_Device *dev)
+{
+	struct ylist_head *link;
+	yaffs_Object *obj;
+	yaffs_DirectoryStructure *dS;
+	yaffs_ObjectVariant *oV;
+
+	T(YAFFS_TRACE_BACKGROUND, (TSTR("Update dirty directories" TENDSTR)));
+
+	while(!ylist_empty(&dev->dirtyDirectories)){
+		link = dev->dirtyDirectories.next;
+		ylist_del_init(link);
+		
+		dS=ylist_entry(link,yaffs_DirectoryStructure,dirty);
+		oV = ylist_entry(dS,yaffs_ObjectVariant,directoryVariant);
+		obj = ylist_entry(oV,yaffs_Object,variant);
+
+		T(YAFFS_TRACE_BACKGROUND, (TSTR("Update directory %d" TENDSTR), obj->objectId));
+
+		if(obj->dirty)
+			yaffs_UpdateObjectHeader(obj,NULL,0,0,0);
+	}
+}
+
+static void yaffs_RemoveObjectFromDirectory(yaffs_Object *obj)
+{
+	yaffs_Device *dev = obj->myDev;
+	yaffs_Object *parent;
+
+	yaffs_VerifyObjectInDirectory(obj);
+	parent = obj->parent;
+
+	yaffs_VerifyDirectory(parent);
+
+	if (dev && dev->param.removeObjectCallback)
+		dev->param.removeObjectCallback(obj);
+
+
+	ylist_del_init(&obj->siblings);
+	obj->parent = NULL;
+	
+	yaffs_VerifyDirectory(parent);
+}
+
+static void yaffs_AddObjectToDirectory(yaffs_Object *directory,
+					yaffs_Object *obj)
+{
+	if (!directory) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: Trying to add an object to a null pointer directory"
+		    TENDSTR)));
+		YBUG();
+		return;
+	}
+	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: Trying to add an object to a non-directory"
+		    TENDSTR)));
+		YBUG();
+	}
+
+	if (obj->siblings.prev == NULL) {
+		/* Not initialised */
+		YBUG();
+	}
+
+
+	yaffs_VerifyDirectory(directory);
+
+	yaffs_RemoveObjectFromDirectory(obj);
+
+
+	/* Now add it */
+	ylist_add(&obj->siblings, &directory->variant.directoryVariant.children);
+	obj->parent = directory;
+
+	if (directory == obj->myDev->unlinkedDir
+			|| directory == obj->myDev->deletedDir) {
+		obj->unlinked = 1;
+		obj->myDev->nUnlinkedFiles++;
+		obj->renameAllowed = 0;
+	}
+
+	yaffs_VerifyDirectory(directory);
+	yaffs_VerifyObjectInDirectory(obj);
+}
+
+yaffs_Object *yaffs_FindObjectByName(yaffs_Object *directory,
+				     const YCHAR *name)
+{
+	int sum;
+
+	struct ylist_head *i;
+	YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1];
+
+	yaffs_Object *l;
+
+	if (!name)
+		return NULL;
+
+	if (!directory) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: null pointer directory"
+		    TENDSTR)));
+		YBUG();
+		return NULL;
+	}
+	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
+		YBUG();
+	}
+
+	sum = yaffs_CalcNameSum(name);
+
+	ylist_for_each(i, &directory->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+
+			if (l->parent != directory)
+				YBUG();
+
+			yaffs_CheckObjectDetailsLoaded(l);
+
+			/* Special case for lost-n-found */
+			if (l->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
+				if (yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME) == 0)
+					return l;
+			} else if (yaffs_SumCompare(l->sum, sum) || l->hdrChunk <= 0) {
+				/* LostnFound chunk called Objxxx
+				 * Do a real check
+				 */
+				yaffs_GetObjectName(l, buffer,
+						    YAFFS_MAX_NAME_LENGTH + 1);
+				if (yaffs_strncmp(name, buffer, YAFFS_MAX_NAME_LENGTH) == 0)
+					return l;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+
+#if 0
+int yaffs_ApplyToDirectoryChildren(yaffs_Object *theDir,
+					int (*fn) (yaffs_Object *))
+{
+	struct ylist_head *i;
+	yaffs_Object *l;
+
+	if (!theDir) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: null pointer directory"
+		    TENDSTR)));
+		YBUG();
+		return YAFFS_FAIL;
+	}
+	if (theDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
+		YBUG();
+		return YAFFS_FAIL;
+	}
+
+	ylist_for_each(i, &theDir->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+			if (l && !fn(l))
+				return YAFFS_FAIL;
+		}
+	}
+
+	return YAFFS_OK;
+
+}
+#endif
+
+/* GetEquivalentObject dereferences any hard links to get to the
+ * actual object.
+ */
+
+yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object *obj)
+{
+	if (obj && obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
+		/* We want the object id of the equivalent object, not this one */
+		obj = obj->variant.hardLinkVariant.equivalentObject;
+		yaffs_CheckObjectDetailsLoaded(obj);
+	}
+	return obj;
+}
+
+int yaffs_GetObjectName(yaffs_Object *obj, YCHAR *name, int buffSize)
+{
+	memset(name, 0, buffSize * sizeof(YCHAR));
+
+	yaffs_CheckObjectDetailsLoaded(obj);
+
+	if (obj->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
+		yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffSize - 1);
+	} else if (obj->hdrChunk <= 0) {
+		YCHAR locName[20];
+		YCHAR numString[20];
+		YCHAR *x = &numString[19];
+		unsigned v = obj->objectId;
+		numString[19] = 0;
+		while (v > 0) {
+			x--;
+			*x = '0' + (v % 10);
+			v /= 10;
+		}
+		/* make up a name */
+		yaffs_strcpy(locName, YAFFS_LOSTNFOUND_PREFIX);
+		yaffs_strcat(locName, x);
+		yaffs_strncpy(name, locName, buffSize - 1);
+
+	}
+#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+	else if (obj->shortName[0])
+		yaffs_strncpy(name, obj->shortName,YAFFS_SHORT_NAME_LENGTH+1);
+#endif
+	else {
+		int result;
+		__u8 *buffer = yaffs_GetTempBuffer(obj->myDev, __LINE__);
+
+		yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *) buffer;
+
+		memset(buffer, 0, obj->myDev->nDataBytesPerChunk);
+
+		if (obj->hdrChunk > 0) {
+			result = yaffs_ReadChunkWithTagsFromNAND(obj->myDev,
+							obj->hdrChunk, buffer,
+							NULL);
+		}
+		yaffs_strncpy(name, oh->name, buffSize - 1);
+		name[buffSize-1]=0;
+
+		yaffs_ReleaseTempBuffer(obj->myDev, buffer, __LINE__);
+	}
+
+	return yaffs_strnlen(name,buffSize-1);
+}
+
+int yaffs_GetObjectFileLength(yaffs_Object *obj)
+{
+	/* Dereference any hard linking */
+	obj = yaffs_GetEquivalentObject(obj);
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+		return obj->variant.fileVariant.fileSize;
+	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK){
+		if(!obj->variant.symLinkVariant.alias)
+			return 0;
+		return yaffs_strnlen(obj->variant.symLinkVariant.alias,YAFFS_MAX_ALIAS_LENGTH);
+	} else {
+		/* Only a directory should drop through to here */
+		return obj->myDev->nDataBytesPerChunk;
+	}
+}
+
+int yaffs_GetObjectLinkCount(yaffs_Object *obj)
+{
+	int count = 0;
+	struct ylist_head *i;
+
+	if (!obj->unlinked)
+		count++;		/* the object itself */
+
+	ylist_for_each(i, &obj->hardLinks)
+		count++;		/* add the hard links; */
+
+	return count;
+}
+
+int yaffs_GetObjectInode(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+
+	return obj->objectId;
+}
+
+unsigned yaffs_GetObjectType(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		return DT_REG;
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		return DT_DIR;
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		return DT_LNK;
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		return DT_REG;
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		if (S_ISFIFO(obj->yst_mode))
+			return DT_FIFO;
+		if (S_ISCHR(obj->yst_mode))
+			return DT_CHR;
+		if (S_ISBLK(obj->yst_mode))
+			return DT_BLK;
+		if (S_ISSOCK(obj->yst_mode))
+			return DT_SOCK;
+	default:
+		return DT_REG;
+		break;
+	}
+}
+
+YCHAR *yaffs_GetSymlinkAlias(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
+		return yaffs_CloneString(obj->variant.symLinkVariant.alias);
+	else
+		return yaffs_CloneString(_Y(""));
+}
+
+#ifndef CONFIG_YAFFS_WINCE
+
+int yaffs_SetAttributes(yaffs_Object *obj, struct iattr *attr)
+{
+	unsigned int valid = attr->ia_valid;
+
+	if (valid & ATTR_MODE)
+		obj->yst_mode = attr->ia_mode;
+	if (valid & ATTR_UID)
+		obj->yst_uid = attr->ia_uid;
+	if (valid & ATTR_GID)
+		obj->yst_gid = attr->ia_gid;
+
+	if (valid & ATTR_ATIME)
+		obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime);
+	if (valid & ATTR_CTIME)
+		obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime);
+	if (valid & ATTR_MTIME)
+		obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime);
+
+	if (valid & ATTR_SIZE)
+		yaffs_ResizeFile(obj, attr->ia_size);
+
+	yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0);
+
+	return YAFFS_OK;
+
+}
+int yaffs_GetAttributes(yaffs_Object *obj, struct iattr *attr)
+{
+	unsigned int valid = 0;
+
+	attr->ia_mode = obj->yst_mode;
+	valid |= ATTR_MODE;
+	attr->ia_uid = obj->yst_uid;
+	valid |= ATTR_UID;
+	attr->ia_gid = obj->yst_gid;
+	valid |= ATTR_GID;
+
+	Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime;
+	valid |= ATTR_ATIME;
+	Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime;
+	valid |= ATTR_CTIME;
+	Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime;
+	valid |= ATTR_MTIME;
+
+	attr->ia_size = yaffs_GetFileSize(obj);
+	valid |= ATTR_SIZE;
+
+	attr->ia_valid = valid;
+
+	return YAFFS_OK;
+}
+
+#endif
+
+#if 0
+int yaffs_DumpObject(yaffs_Object *obj)
+{
+	YCHAR name[257];
+
+	yaffs_GetObjectName(obj, name, YAFFS_MAX_NAME_LENGTH + 1);
+
+	T(YAFFS_TRACE_ALWAYS,
+	  (TSTR
+	   ("Object %d, inode %d \"%s\"\n dirty %d valid %d serial %d sum %d"
+	    " chunk %d type %d size %d\n"
+	    TENDSTR), obj->objectId, yaffs_GetObjectInode(obj), name,
+	   obj->dirty, obj->valid, obj->serial, obj->sum, obj->hdrChunk,
+	   yaffs_GetObjectType(obj), yaffs_GetObjectFileLength(obj)));
+
+	return YAFFS_OK;
+}
+#endif
+
+/*---------------------------- Initialisation code -------------------------------------- */
+
+static int yaffs_CheckDevFunctions(const yaffs_Device *dev)
+{
+
+	/* Common functions, gotta have */
+	if (!dev->param.eraseBlockInNAND || !dev->param.initialiseNAND)
+		return 0;
+
+#ifdef CONFIG_YAFFS_YAFFS2
+
+	/* Can use the "with tags" style interface for yaffs1 or yaffs2 */
+	if (dev->param.writeChunkWithTagsToNAND &&
+	    dev->param.readChunkWithTagsFromNAND &&
+	    !dev->param.writeChunkToNAND &&
+	    !dev->param.readChunkFromNAND &&
+	    dev->param.markNANDBlockBad &&
+	    dev->param.queryNANDBlock)
+		return 1;
+#endif
+
+	/* Can use the "spare" style interface for yaffs1 */
+	if (!dev->param.isYaffs2 &&
+	    !dev->param.writeChunkWithTagsToNAND &&
+	    !dev->param.readChunkWithTagsFromNAND &&
+	    dev->param.writeChunkToNAND &&
+	    dev->param.readChunkFromNAND &&
+	    !dev->param.markNANDBlockBad &&
+	    !dev->param.queryNANDBlock)
+		return 1;
+
+	return 0;	/* bad */
+}
+
+
+static int yaffs_CreateInitialDirectories(yaffs_Device *dev)
+{
+	/* Initialise the unlinked, deleted, root and lost and found directories */
+
+	dev->lostNFoundDir = dev->rootDir =  NULL;
+	dev->unlinkedDir = dev->deletedDir = NULL;
+
+	dev->unlinkedDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR);
+
+	dev->deletedDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_DELETED, S_IFDIR);
+
+	dev->rootDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_ROOT,
+				      YAFFS_ROOT_MODE | S_IFDIR);
+	dev->lostNFoundDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_LOSTNFOUND,
+				      YAFFS_LOSTNFOUND_MODE | S_IFDIR);
+
+	if (dev->lostNFoundDir && dev->rootDir && dev->unlinkedDir && dev->deletedDir) {
+		yaffs_AddObjectToDirectory(dev->rootDir, dev->lostNFoundDir);
+		return YAFFS_OK;
+	}
+
+	return YAFFS_FAIL;
+}
+
+int yaffs_GutsInitialise(yaffs_Device *dev)
+{
+	int init_failed = 0;
+	unsigned x;
+	int bits;
+
+	T(YAFFS_TRACE_TRACING, (TSTR("yaffs: yaffs_GutsInitialise()" TENDSTR)));
+
+	/* Check stuff that must be set */
+
+	if (!dev) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	dev->internalStartBlock = dev->param.startBlock;
+	dev->internalEndBlock = dev->param.endBlock;
+	dev->blockOffset = 0;
+	dev->chunkOffset = 0;
+	dev->nFreeChunks = 0;
+
+	dev->gcBlock = -1;
+
+	if (dev->param.startBlock == 0) {
+		dev->internalStartBlock = dev->param.startBlock + 1;
+		dev->internalEndBlock = dev->param.endBlock + 1;
+		dev->blockOffset = 1;
+		dev->chunkOffset = dev->param.nChunksPerBlock;
+	}
+
+	/* Check geometry parameters. */
+
+	if ((!dev->param.inbandTags && dev->param.isYaffs2 && dev->param.totalBytesPerChunk < 1024) ||
+	    (!dev->param.isYaffs2 && dev->param.totalBytesPerChunk < 512) ||
+	    (dev->param.inbandTags && !dev->param.isYaffs2) ||
+	     dev->param.nChunksPerBlock < 2 ||
+	     dev->param.nReservedBlocks < 2 ||
+	     dev->internalStartBlock <= 0 ||
+	     dev->internalEndBlock <= 0 ||
+	     dev->internalEndBlock <= (dev->internalStartBlock + dev->param.nReservedBlocks + 2)) {	/* otherwise it is too small */
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s, inbandTags %d "
+		    TENDSTR), dev->param.totalBytesPerChunk, dev->param.isYaffs2 ? "2" : "", dev->param.inbandTags));
+		return YAFFS_FAIL;
+	}
+
+	if (yaffs_InitialiseNAND(dev) != YAFFS_OK) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs: InitialiseNAND failed" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Sort out space for inband tags, if required */
+	if (dev->param.inbandTags)
+		dev->nDataBytesPerChunk = dev->param.totalBytesPerChunk - sizeof(yaffs_PackedTags2TagsPart);
+	else
+		dev->nDataBytesPerChunk = dev->param.totalBytesPerChunk;
+
+	/* Got the right mix of functions? */
+	if (!yaffs_CheckDevFunctions(dev)) {
+		/* Function missing */
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("yaffs: device function(s) missing or wrong\n" TENDSTR)));
+
+		return YAFFS_FAIL;
+	}
+
+	/* This is really a compilation check. */
+	if (!yaffs_CheckStructures()) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs_CheckStructures failed\n" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	if (dev->isMounted) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs: device already mounted\n" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Finished with most checks. One or two more checks happen later on too. */
+
+	dev->isMounted = 1;
+
+	/* OK now calculate a few things for the device */
+
+	/*
+	 *  Calculate all the chunk size manipulation numbers:
+	 */
+	x = dev->nDataBytesPerChunk;
+	/* We always use dev->chunkShift and dev->chunkDiv */
+	dev->chunkShift = Shifts(x);
+	x >>= dev->chunkShift;
+	dev->chunkDiv = x;
+	/* We only use chunk mask if chunkDiv is 1 */
+	dev->chunkMask = (1<<dev->chunkShift) - 1;
+
+	/*
+	 * Calculate chunkGroupBits.
+	 * We need to find the next power of 2 > than internalEndBlock
+	 */
+
+	x = dev->param.nChunksPerBlock * (dev->internalEndBlock + 1);
+
+	bits = ShiftsGE(x);
+
+	/* Set up tnode width if wide tnodes are enabled. */
+	if (!dev->param.wideTnodesDisabled) {
+		/* bits must be even so that we end up with 32-bit words */
+		if (bits & 1)
+			bits++;
+		if (bits < 16)
+			dev->tnodeWidth = 16;
+		else
+			dev->tnodeWidth = bits;
+	} else
+		dev->tnodeWidth = 16;
+
+	dev->tnodeMask = (1<<dev->tnodeWidth)-1;
+
+	/* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled),
+	 * so if the bitwidth of the
+	 * chunk range we're using is greater than 16 we need
+	 * to figure out chunk shift and chunkGroupSize
+	 */
+
+	if (bits <= dev->tnodeWidth)
+		dev->chunkGroupBits = 0;
+	else
+		dev->chunkGroupBits = bits - dev->tnodeWidth;
+
+
+	dev->chunkGroupSize = 1 << dev->chunkGroupBits;
+
+	if (dev->param.nChunksPerBlock < dev->chunkGroupSize) {
+		/* We have a problem because the soft delete won't work if
+		 * the chunk group size > chunks per block.
+		 * This can be remedied by using larger "virtual blocks".
+		 */
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs: chunk group too large\n" TENDSTR)));
+
+		return YAFFS_FAIL;
+	}
+
+	/* OK, we've finished verifying the device, lets continue with initialisation */
+
+	/* More device initialisation */
+	dev->garbageCollections = 0;
+	dev->passiveGarbageCollections = 0;
+	dev->currentDirtyChecker = 0;
+	dev->bufferedBlock = -1;
+	dev->doingBufferedBlockRewrite = 0;
+	dev->nDeletedFiles = 0;
+	dev->nBackgroundDeletions = 0;
+	dev->nUnlinkedFiles = 0;
+	dev->eccFixed = 0;
+	dev->eccUnfixed = 0;
+	dev->tagsEccFixed = 0;
+	dev->tagsEccUnfixed = 0;
+	dev->nErasureFailures = 0;
+	dev->nErasedBlocks = 0;
+	dev->isDoingGC = 0;
+	dev->hasPendingPrioritisedGCs = 1; /* Assume the worst for now, will get fixed on first GC */
+	YINIT_LIST_HEAD(&dev->dirtyDirectories);
+	dev->oldestDirtySequence = 0;
+
+	/* Initialise temporary buffers and caches. */
+	if (!yaffs_InitialiseTempBuffers(dev))
+		init_failed = 1;
+
+	dev->srCache = NULL;
+	dev->gcCleanupList = NULL;
+
+
+	if (!init_failed &&
+	    dev->param.nShortOpCaches > 0) {
+		int i;
+		void *buf;
+		int srCacheBytes = dev->param.nShortOpCaches * sizeof(yaffs_ChunkCache);
+
+		if (dev->param.nShortOpCaches > YAFFS_MAX_SHORT_OP_CACHES)
+			dev->param.nShortOpCaches = YAFFS_MAX_SHORT_OP_CACHES;
+
+		dev->srCache =  YMALLOC(srCacheBytes);
+
+		buf = (__u8 *) dev->srCache;
+
+		if (dev->srCache)
+			memset(dev->srCache, 0, srCacheBytes);
+
+		for (i = 0; i < dev->param.nShortOpCaches && buf; i++) {
+			dev->srCache[i].object = NULL;
+			dev->srCache[i].lastUse = 0;
+			dev->srCache[i].dirty = 0;
+			dev->srCache[i].data = buf = YMALLOC_DMA(dev->param.totalBytesPerChunk);
+		}
+		if (!buf)
+			init_failed = 1;
+
+		dev->srLastUse = 0;
+	}
+
+	dev->cacheHits = 0;
+
+	if (!init_failed) {
+		dev->gcCleanupList = YMALLOC(dev->param.nChunksPerBlock * sizeof(__u32));
+		if (!dev->gcCleanupList)
+			init_failed = 1;
+	}
+
+	if (dev->param.isYaffs2)
+		dev->param.useHeaderFileSize = 1;
+
+	if (!init_failed && !yaffs_InitialiseBlocks(dev))
+		init_failed = 1;
+
+	yaffs_InitialiseTnodes(dev);
+	yaffs_InitialiseObjects(dev);
+
+	if (!init_failed && !yaffs_CreateInitialDirectories(dev))
+		init_failed = 1;
+
+
+	if (!init_failed) {
+		/* Now scan the flash. */
+		if (dev->param.isYaffs2) {
+			if (yaffs_CheckpointRestore(dev)) {
+				yaffs_CheckObjectDetailsLoaded(dev->rootDir);
+				T(YAFFS_TRACE_ALWAYS,
+				  (TSTR("yaffs: restored from checkpoint" TENDSTR)));
+			} else {
+
+				/* Clean up the mess caused by an aborted checkpoint load
+				 * and scan backwards.
+				 */
+				yaffs_DeinitialiseBlocks(dev);
+				yaffs_DeinitialiseTnodes(dev);
+				yaffs_DeinitialiseObjects(dev);
+
+
+				dev->nErasedBlocks = 0;
+				dev->nFreeChunks = 0;
+				dev->allocationBlock = -1;
+				dev->allocationPage = -1;
+				dev->nDeletedFiles = 0;
+				dev->nUnlinkedFiles = 0;
+				dev->nBackgroundDeletions = 0;
+
+				if (!init_failed && !yaffs_InitialiseBlocks(dev))
+					init_failed = 1;
+
+				yaffs_InitialiseTnodes(dev);
+				yaffs_InitialiseObjects(dev);
+
+				if (!init_failed && !yaffs_CreateInitialDirectories(dev))
+					init_failed = 1;
+
+				if (!init_failed && !yaffs_ScanBackwards(dev))
+					init_failed = 1;
+			}
+		} else if (!yaffs_Scan(dev))
+				init_failed = 1;
+
+		yaffs_StripDeletedObjects(dev);
+		yaffs_FixHangingObjects(dev);
+		if(dev->param.emptyLostAndFound)
+			yaffs_EmptyLostAndFound(dev);
+	}
+
+	if (init_failed) {
+		/* Clean up the mess */
+		T(YAFFS_TRACE_TRACING,
+		  (TSTR("yaffs: yaffs_GutsInitialise() aborted.\n" TENDSTR)));
+
+		yaffs_Deinitialise(dev);
+		return YAFFS_FAIL;
+	}
+
+	/* Zero out stats */
+	dev->nPageReads = 0;
+	dev->nPageWrites = 0;
+	dev->nBlockErasures = 0;
+	dev->nGCCopies = 0;
+	dev->nRetriedWrites = 0;
+
+	dev->nRetiredBlocks = 0;
+
+	yaffs_VerifyFreeChunks(dev);
+	yaffs_VerifyBlocks(dev);
+
+	/* Clean up any aborted checkpoint data */
+	if(!dev->isCheckpointed && dev->blocksInCheckpoint > 0)
+		yaffs_InvalidateCheckpoint(dev);
+
+	T(YAFFS_TRACE_TRACING,
+	  (TSTR("yaffs: yaffs_GutsInitialise() done.\n" TENDSTR)));
+	return YAFFS_OK;
+
+}
+
+void yaffs_Deinitialise(yaffs_Device *dev)
+{
+	if (dev->isMounted) {
+		int i;
+
+		yaffs_DeinitialiseBlocks(dev);
+		yaffs_DeinitialiseTnodes(dev);
+		yaffs_DeinitialiseObjects(dev);
+		if (dev->param.nShortOpCaches > 0 &&
+		    dev->srCache) {
+
+			for (i = 0; i < dev->param.nShortOpCaches; i++) {
+				if (dev->srCache[i].data)
+					YFREE(dev->srCache[i].data);
+				dev->srCache[i].data = NULL;
+			}
+
+			YFREE(dev->srCache);
+			dev->srCache = NULL;
+		}
+
+		YFREE(dev->gcCleanupList);
+
+		for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++)
+			YFREE(dev->tempBuffer[i].buffer);
+
+		dev->isMounted = 0;
+
+		if (dev->param.deinitialiseNAND)
+			dev->param.deinitialiseNAND(dev);
+	}
+}
+
+static int yaffs_CountFreeChunks(yaffs_Device *dev)
+{
+	int nFree=0;
+	int b;
+
+	yaffs_BlockInfo *blk;
+
+	blk = dev->blockInfo;
+	for (b = dev->internalStartBlock; b <= dev->internalEndBlock; b++) {
+		switch (blk->blockState) {
+		case YAFFS_BLOCK_STATE_EMPTY:
+		case YAFFS_BLOCK_STATE_ALLOCATING:
+		case YAFFS_BLOCK_STATE_COLLECTING:
+		case YAFFS_BLOCK_STATE_FULL:
+			nFree +=
+			    (dev->param.nChunksPerBlock - blk->pagesInUse +
+			     blk->softDeletions);
+			break;
+		default:
+			break;
+		}
+		blk++;
+	}
+
+	return nFree;
+}
+
+int yaffs_GetNumberOfFreeChunks(yaffs_Device *dev)
+{
+	/* This is what we report to the outside world */
+
+	int nFree;
+	int nDirtyCacheChunks;
+	int blocksForCheckpoint;
+	int i;
+
+#if 1
+	nFree = dev->nFreeChunks;
+#else
+	nFree = yaffs_CountFreeChunks(dev);
+#endif
+
+	nFree += dev->nDeletedFiles;
+
+	/* Now count the number of dirty chunks in the cache and subtract those */
+
+	for (nDirtyCacheChunks = 0, i = 0; i < dev->param.nShortOpCaches; i++) {
+		if (dev->srCache[i].dirty)
+			nDirtyCacheChunks++;
+	}
+
+	nFree -= nDirtyCacheChunks;
+
+	nFree -= ((dev->param.nReservedBlocks + 1) * dev->param.nChunksPerBlock);
+
+	/* Now we figure out how much to reserve for the checkpoint and report that... */
+	blocksForCheckpoint = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint;
+	if (blocksForCheckpoint < 0)
+		blocksForCheckpoint = 0;
+
+	nFree -= (blocksForCheckpoint * dev->param.nChunksPerBlock);
+
+	if (nFree < 0)
+		nFree = 0;
+
+	return nFree;
+
+}
+
+static int yaffs_freeVerificationFailures;
+
+static void yaffs_VerifyFreeChunks(yaffs_Device *dev)
+{
+	int counted;
+	int difference;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	counted = yaffs_CountFreeChunks(dev);
+
+	difference = dev->nFreeChunks - counted;
+
+	if (difference) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("Freechunks verification failure %d %d %d" TENDSTR),
+		   dev->nFreeChunks, counted, difference));
+		yaffs_freeVerificationFailures++;
+	}
+}
+
+/*---------------------------------------- YAFFS test code ----------------------*/
+
+#define yaffs_CheckStruct(structure, syze, name) \
+	do { \
+		if (sizeof(structure) != syze) { \
+			T(YAFFS_TRACE_ALWAYS, (TSTR("%s should be %d but is %d\n" TENDSTR),\
+				name, syze, (int) sizeof(structure))); \
+			return YAFFS_FAIL; \
+		} \
+	} while (0)
+
+static int yaffs_CheckStructures(void)
+{
+/*      yaffs_CheckStruct(yaffs_Tags,8,"yaffs_Tags"); */
+/*      yaffs_CheckStruct(yaffs_TagsUnion,8,"yaffs_TagsUnion"); */
+/*      yaffs_CheckStruct(yaffs_Spare,16,"yaffs_Spare"); */
+#ifndef CONFIG_YAFFS_TNODE_LIST_DEBUG
+/*	yaffs_CheckStruct(yaffs_Tnode, 2 * YAFFS_NTNODES_LEVEL0, "yaffs_Tnode"); */
+#endif
+#ifndef CONFIG_YAFFS_WINCE
+	yaffs_CheckStruct(yaffs_ObjectHeader, 512, "yaffs_ObjectHeader");
+#endif
+	return YAFFS_OK;
+}
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_guts.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_guts.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_guts.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_guts.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,913 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_GUTS_H__
+#define __YAFFS_GUTS_H__
+
+#include "devextras.h"
+#include "yportenv.h"
+
+#define YAFFS_OK	1
+#define YAFFS_FAIL  0
+
+/* Give us a  Y=0x59,
+ * Give us an A=0x41,
+ * Give us an FF=0xFF
+ * Give us an S=0x53
+ * And what have we got...
+ */
+#define YAFFS_MAGIC			0x5941FF53
+
+#define YAFFS_NTNODES_LEVEL0	  	16
+#define YAFFS_TNODES_LEVEL0_BITS	4
+#define YAFFS_TNODES_LEVEL0_MASK	0xf
+
+#define YAFFS_NTNODES_INTERNAL 		(YAFFS_NTNODES_LEVEL0 / 2)
+#define YAFFS_TNODES_INTERNAL_BITS 	(YAFFS_TNODES_LEVEL0_BITS - 1)
+#define YAFFS_TNODES_INTERNAL_MASK	0x7
+#define YAFFS_TNODES_MAX_LEVEL		6
+
+#ifndef CONFIG_YAFFS_NO_YAFFS1
+#define YAFFS_BYTES_PER_SPARE		16
+#define YAFFS_BYTES_PER_CHUNK		512
+#define YAFFS_CHUNK_SIZE_SHIFT		9
+#define YAFFS_CHUNKS_PER_BLOCK		32
+#define YAFFS_BYTES_PER_BLOCK		(YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK)
+#endif
+
+#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 	1024
+#define YAFFS_MIN_YAFFS2_SPARE_SIZE	32
+
+#define YAFFS_MAX_CHUNK_ID		0x000FFFFF
+
+#define YAFFS_UNUSED_OBJECT_ID		0x0003FFFF
+
+#define YAFFS_ALLOCATION_NOBJECTS	100
+#define YAFFS_ALLOCATION_NTNODES	100
+#define YAFFS_ALLOCATION_NLINKS		100
+
+#define YAFFS_NOBJECT_BUCKETS		256
+
+
+#define YAFFS_OBJECT_SPACE		0x40000
+
+#define YAFFS_CHECKPOINT_VERSION 	4
+
+#ifdef CONFIG_YAFFS_UNICODE
+#define YAFFS_MAX_NAME_LENGTH		127
+#define YAFFS_MAX_ALIAS_LENGTH		79
+#else
+#define YAFFS_MAX_NAME_LENGTH		255
+#define YAFFS_MAX_ALIAS_LENGTH		159
+#endif
+
+#define YAFFS_SHORT_NAME_LENGTH		15
+
+/* Some special object ids for pseudo objects */
+#define YAFFS_OBJECTID_ROOT		1
+#define YAFFS_OBJECTID_LOSTNFOUND	2
+#define YAFFS_OBJECTID_UNLINKED		3
+#define YAFFS_OBJECTID_DELETED		4
+
+/* Pseudo object ids for checkpointing */
+#define YAFFS_OBJECTID_SB_HEADER	0x10
+#define YAFFS_OBJECTID_CHECKPOINT_DATA	0x20
+#define YAFFS_SEQUENCE_CHECKPOINT_DATA  0x21
+
+
+#define YAFFS_MAX_SHORT_OP_CACHES	20
+
+#define YAFFS_N_TEMP_BUFFERS		6
+
+/* We limit the number attempts at sucessfully saving a chunk of data.
+ * Small-page devices have 32 pages per block; large-page devices have 64.
+ * Default to something in the order of 5 to 10 blocks worth of chunks.
+ */
+#define YAFFS_WR_ATTEMPTS		(5*64)
+
+/* Sequence numbers are used in YAFFS2 to determine block allocation order.
+ * The range is limited slightly to help distinguish bad numbers from good.
+ * This also allows us to perhaps in the future use special numbers for
+ * special purposes.
+ * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years,
+ * and is a larger number than the lifetime of a 2GB device.
+ */
+#define YAFFS_LOWEST_SEQUENCE_NUMBER	0x00001000
+#define YAFFS_HIGHEST_SEQUENCE_NUMBER	0xEFFFFF00
+
+/* Special sequence number for bad block that failed to be marked bad */
+#define YAFFS_SEQUENCE_BAD_BLOCK	0xFFFF0000
+
+/* ChunkCache is used for short read/write operations.*/
+typedef struct {
+	struct yaffs_ObjectStruct *object;
+	int chunkId;
+	int lastUse;
+	int dirty;
+	int nBytes;		/* Only valid if the cache is dirty */
+	int locked;		/* Can't push out or flush while locked. */
+	__u8 *data;
+} yaffs_ChunkCache;
+
+
+
+/* Tags structures in RAM
+ * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise
+ * the structure size will get blown out.
+ */
+
+#ifndef CONFIG_YAFFS_NO_YAFFS1
+typedef struct {
+	unsigned chunkId:20;
+	unsigned serialNumber:2;
+	unsigned byteCountLSB:10;
+	unsigned objectId:18;
+	unsigned ecc:12;
+	unsigned byteCountMSB:2;
+} yaffs_Tags;
+
+typedef union {
+	yaffs_Tags asTags;
+	__u8 asBytes[8];
+} yaffs_TagsUnion;
+
+#endif
+
+/* Stuff used for extended tags in YAFFS2 */
+
+typedef enum {
+	YAFFS_ECC_RESULT_UNKNOWN,
+	YAFFS_ECC_RESULT_NO_ERROR,
+	YAFFS_ECC_RESULT_FIXED,
+	YAFFS_ECC_RESULT_UNFIXED
+} yaffs_ECCResult;
+
+typedef enum {
+	YAFFS_OBJECT_TYPE_UNKNOWN,
+	YAFFS_OBJECT_TYPE_FILE,
+	YAFFS_OBJECT_TYPE_SYMLINK,
+	YAFFS_OBJECT_TYPE_DIRECTORY,
+	YAFFS_OBJECT_TYPE_HARDLINK,
+	YAFFS_OBJECT_TYPE_SPECIAL
+} yaffs_ObjectType;
+
+#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL
+
+typedef struct {
+
+	unsigned validMarker0;
+	unsigned chunkUsed;	/*  Status of the chunk: used or unused */
+	unsigned objectId;	/* If 0 then this is not part of an object (unused) */
+	unsigned chunkId;	/* If 0 then this is a header, else a data chunk */
+	unsigned byteCount;	/* Only valid for data chunks */
+
+	/* The following stuff only has meaning when we read */
+	yaffs_ECCResult eccResult;
+	unsigned blockBad;
+
+	/* YAFFS 1 stuff */
+	unsigned chunkDeleted;	/* The chunk is marked deleted */
+	unsigned serialNumber;	/* Yaffs1 2-bit serial number */
+
+	/* YAFFS2 stuff */
+	unsigned sequenceNumber;	/* The sequence number of this block */
+
+	/* Extra info if this is an object header (YAFFS2 only) */
+
+	unsigned extraHeaderInfoAvailable;	/* There is extra info available if this is not zero */
+	unsigned extraParentObjectId;	/* The parent object */
+	unsigned extraIsShrinkHeader;	/* Is it a shrink header? */
+	unsigned extraShadows;		/* Does this shadow another object? */
+
+	yaffs_ObjectType extraObjectType;	/* What object type? */
+
+	unsigned extraFileLength;		/* Length if it is a file */
+	unsigned extraEquivalentObjectId;	/* Equivalent object Id if it is a hard link */
+
+	unsigned validMarker1;
+
+} yaffs_ExtendedTags;
+
+/* Spare structure for YAFFS1 */
+typedef struct {
+	__u8 tagByte0;
+	__u8 tagByte1;
+	__u8 tagByte2;
+	__u8 tagByte3;
+	__u8 pageStatus;	/* set to 0 to delete the chunk */
+	__u8 blockStatus;
+	__u8 tagByte4;
+	__u8 tagByte5;
+	__u8 ecc1[3];
+	__u8 tagByte6;
+	__u8 tagByte7;
+	__u8 ecc2[3];
+} yaffs_Spare;
+
+/*Special structure for passing through to mtd */
+struct yaffs_NANDSpare {
+	yaffs_Spare spare;
+	int eccres1;
+	int eccres2;
+};
+
+/* Block data in RAM */
+
+typedef enum {
+	YAFFS_BLOCK_STATE_UNKNOWN = 0,
+
+	YAFFS_BLOCK_STATE_SCANNING,
+        /* Being scanned */
+
+	YAFFS_BLOCK_STATE_NEEDS_SCANNING,
+	/* The block might have something on it (ie it is allocating or full, perhaps empty)
+	 * but it needs to be scanned to determine its true state.
+	 * This state is only valid during yaffs_Scan.
+	 * NB We tolerate empty because the pre-scanner might be incapable of deciding
+	 * However, if this state is returned on a YAFFS2 device, then we expect a sequence number
+	 */
+
+	YAFFS_BLOCK_STATE_EMPTY,
+	/* This block is empty */
+
+	YAFFS_BLOCK_STATE_ALLOCATING,
+	/* This block is partially allocated.
+	 * At least one page holds valid data.
+	 * This is the one currently being used for page
+	 * allocation. Should never be more than one of these.
+         * If a block is only partially allocated at mount it is treated as full.
+	 */
+
+	YAFFS_BLOCK_STATE_FULL,
+	/* All the pages in this block have been allocated.
+         * If a block was only partially allocated when mounted we treat
+         * it as fully allocated.
+	 */
+
+	YAFFS_BLOCK_STATE_DIRTY,
+	/* The block was full and now all chunks have been deleted.
+	 * Erase me, reuse me.
+	 */
+
+	YAFFS_BLOCK_STATE_CHECKPOINT,
+	/* This block is assigned to holding checkpoint data. */
+
+	YAFFS_BLOCK_STATE_COLLECTING,
+	/* This block is being garbage collected */
+
+	YAFFS_BLOCK_STATE_DEAD
+	/* This block has failed and is not in use */
+} yaffs_BlockState;
+
+#define	YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1)
+
+
+typedef struct {
+
+	int softDeletions:10;	/* number of soft deleted pages */
+	int pagesInUse:10;	/* number of pages in use */
+	unsigned blockState:4;	/* One of the above block states. NB use unsigned because enum is sometimes an int */
+	__u32 needsRetiring:1;	/* Data has failed on this block, need to get valid data off */
+				/* and retire the block. */
+	__u32 skipErasedCheck:1; /* If this is set we can skip the erased check on this block */
+	__u32 gcPrioritise:1; 	/* An ECC check or blank check has failed on this block.
+				   It should be prioritised for GC */
+	__u32 chunkErrorStrikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */
+
+#ifdef CONFIG_YAFFS_YAFFS2
+	__u32 hasShrinkHeader:1; /* This block has at least one shrink object header */
+	__u32 sequenceNumber;	 /* block sequence number for yaffs2 */
+#endif
+
+} yaffs_BlockInfo;
+
+/* -------------------------- Object structure -------------------------------*/
+/* This is the object structure as stored on NAND */
+
+typedef struct {
+	yaffs_ObjectType type;
+
+	/* Apply to everything  */
+	int parentObjectId;
+	__u16 sum__NoLongerUsed;        /* checksum of name. No longer used */
+	YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
+
+	/* The following apply to directories, files, symlinks - not hard links */
+	__u32 yst_mode;         /* protection */
+
+#ifdef CONFIG_YAFFS_WINCE
+	__u32 notForWinCE[5];
+#else
+	__u32 yst_uid;
+	__u32 yst_gid;
+	__u32 yst_atime;
+	__u32 yst_mtime;
+	__u32 yst_ctime;
+#endif
+
+	/* File size  applies to files only */
+	int fileSize;
+
+	/* Equivalent object id applies to hard links only. */
+	int equivalentObjectId;
+
+	/* Alias is for symlinks only. */
+	YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1];
+
+	__u32 yst_rdev;		/* device stuff for block and char devices (major/min) */
+
+#ifdef CONFIG_YAFFS_WINCE
+	__u32 win_ctime[2];
+	__u32 win_atime[2];
+	__u32 win_mtime[2];
+#else
+	__u32 roomToGrow[6];
+
+#endif
+	__u32 inbandShadowsObject;
+	__u32 inbandIsShrink;
+
+	__u32 reservedSpace[2];
+	int shadowsObject;	/* This object header shadows the specified object if > 0 */
+
+	/* isShrink applies to object headers written when we shrink the file (ie resize) */
+	__u32 isShrink;
+
+} yaffs_ObjectHeader;
+
+/*--------------------------- Tnode -------------------------- */
+
+union yaffs_Tnode_union {
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+	union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL + 1];
+#else
+	union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL];
+#endif
+/*	__u16 level0[YAFFS_NTNODES_LEVEL0]; */
+
+};
+
+typedef union yaffs_Tnode_union yaffs_Tnode;
+
+struct yaffs_TnodeList_struct {
+	struct yaffs_TnodeList_struct *next;
+	yaffs_Tnode *tnodes;
+};
+
+typedef struct yaffs_TnodeList_struct yaffs_TnodeList;
+
+/*------------------------  Object -----------------------------*/
+/* An object can be one of:
+ * - a directory (no data, has children links
+ * - a regular file (data.... not prunes :->).
+ * - a symlink [symbolic link] (the alias).
+ * - a hard link
+ */
+
+typedef struct {
+	__u32 fileSize;
+	__u32 scannedFileSize;
+	__u32 shrinkSize;
+	int topLevel;
+	yaffs_Tnode *top;
+} yaffs_FileStructure;
+
+typedef struct {
+	struct ylist_head children;     /* list of child links */
+	struct ylist_head dirty;	/* Entry for list of dirty directories */
+} yaffs_DirectoryStructure;
+
+typedef struct {
+	YCHAR *alias;
+} yaffs_SymLinkStructure;
+
+typedef struct {
+	struct yaffs_ObjectStruct *equivalentObject;
+	__u32 equivalentObjectId;
+} yaffs_HardLinkStructure;
+
+typedef union {
+	yaffs_FileStructure fileVariant;
+	yaffs_DirectoryStructure directoryVariant;
+	yaffs_SymLinkStructure symLinkVariant;
+	yaffs_HardLinkStructure hardLinkVariant;
+} yaffs_ObjectVariant;
+
+
+
+struct yaffs_ObjectStruct {
+	__u8 deleted:1;		/* This should only apply to unlinked files. */
+	__u8 softDeleted:1;	/* it has also been soft deleted */
+	__u8 unlinked:1;	/* An unlinked file. The file should be in the unlinked directory.*/
+	__u8 fake:1;		/* A fake object has no presence on NAND. */
+	__u8 renameAllowed:1;	/* Some objects are not allowed to be renamed. */
+	__u8 unlinkAllowed:1;
+	__u8 dirty:1;		/* the object needs to be written to flash */
+	__u8 valid:1;		/* When the file system is being loaded up, this
+				 * object might be created before the data
+				 * is available (ie. file data records appear before the header).
+				 */
+	__u8 lazyLoaded:1;	/* This object has been lazy loaded and is missing some detail */
+
+	__u8 deferedFree:1;	/* For Linux kernel. Object is removed from NAND, but is
+				 * still in the inode cache. Free of object is defered.
+				 * until the inode is released.
+				 */
+	__u8 beingCreated:1;	/* This object is still being created so skip some checks. */
+	__u8 isShadowed:1;	/* This object is shadowed on the way to being renamed. */
+
+	__u8 serial;		/* serial number of chunk in NAND. Cached here */
+	__u16 sum;		/* sum of the name to speed searching */
+
+	struct yaffs_DeviceStruct *myDev;       /* The device I'm on */
+
+	struct ylist_head hashLink;     /* list of objects in this hash bucket */
+
+	struct ylist_head hardLinks;    /* all the equivalent hard linked objects */
+
+	/* directory structure stuff */
+	/* also used for linking up the free list */
+	struct yaffs_ObjectStruct *parent;
+	struct ylist_head siblings;
+
+	/* Where's my object header in NAND? */
+	int hdrChunk;
+
+	int nDataChunks;	/* Number of data chunks attached to the file. */
+
+	__u32 objectId;		/* the object id value */
+
+	__u32 yst_mode;
+
+#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+	YCHAR shortName[YAFFS_SHORT_NAME_LENGTH + 1];
+#endif
+
+#ifdef CONFIG_YAFFS_WINCE
+	__u32 win_ctime[2];
+	__u32 win_mtime[2];
+	__u32 win_atime[2];
+#else
+	__u32 yst_uid;
+	__u32 yst_gid;
+	__u32 yst_atime;
+	__u32 yst_mtime;
+	__u32 yst_ctime;
+#endif
+
+	__u32 yst_rdev;
+
+	void *myInode;
+
+	yaffs_ObjectType variantType;
+
+	yaffs_ObjectVariant variant;
+
+};
+
+typedef struct yaffs_ObjectStruct yaffs_Object;
+
+struct yaffs_ObjectList_struct {
+	yaffs_Object *objects;
+	struct yaffs_ObjectList_struct *next;
+};
+
+typedef struct yaffs_ObjectList_struct yaffs_ObjectList;
+
+typedef struct {
+	struct ylist_head list;
+	int count;
+} yaffs_ObjectBucket;
+
+
+/* yaffs_CheckpointObject holds the definition of an object as dumped
+ * by checkpointing.
+ */
+
+typedef struct {
+	int structType;
+	__u32 objectId;
+	__u32 parentId;
+	int hdrChunk;
+	yaffs_ObjectType variantType:3;
+	__u8 deleted:1;
+	__u8 softDeleted:1;
+	__u8 unlinked:1;
+	__u8 fake:1;
+	__u8 renameAllowed:1;
+	__u8 unlinkAllowed:1;
+	__u8 serial;
+
+	int nDataChunks;
+	__u32 fileSizeOrEquivalentObjectId;
+} yaffs_CheckpointObject;
+
+/*--------------------- Temporary buffers ----------------
+ *
+ * These are chunk-sized working buffers. Each device has a few
+ */
+
+typedef struct {
+	__u8 *buffer;
+	int line;	/* track from whence this buffer was allocated */
+	int maxLine;
+} yaffs_TempBuffer;
+
+/*----------------- Device ---------------------------------*/
+
+
+struct yaffs_DeviceParamStruct {
+	const char *name;
+
+	/*
+         * Entry parameters set up way early. Yaffs sets up the rest.
+         * The structure should be zeroed out before use so that unused
+         * and defualt values are zero.
+         */
+
+	int inbandTags;          /* Use unband tags */
+	__u32 totalBytesPerChunk; /* Should be >= 512, does not need to be a power of 2 */
+	int nChunksPerBlock;	/* does not need to be a power of 2 */
+	int spareBytesPerChunk;	/* spare area size */
+	int startBlock;		/* Start block we're allowed to use */
+	int endBlock;		/* End block we're allowed to use */
+	int nReservedBlocks;	/* We want this tuneable so that we can reduce */
+				/* reserved blocks on NOR and RAM. */
+
+
+	int nShortOpCaches;	/* If <= 0, then short op caching is disabled, else
+				 * the number of short op caches (don't use too many).
+                                 * 10 to 20 is a good bet.
+				 */
+	int useNANDECC;		/* Flag to decide whether or not to use NANDECC on data (yaffs1) */
+	int noTagsECC;		/* Flag to decide whether or not to do ECC on packed tags (yaffs2) */ 
+
+	int isYaffs2;           /* Use yaffs2 mode on this device */
+
+	int emptyLostAndFound;  /* Auto-empty lost+found directory on mount */
+
+	int refreshPeriod;	/* How often we should check to do a block refresh */
+
+	/* Checkpoint control. Can be set before or after initialisation */
+	__u8 skipCheckpointRead;
+	__u8 skipCheckpointWrite;
+
+	/* NAND access functions (Must be set before calling YAFFS)*/
+
+	int (*writeChunkToNAND) (struct yaffs_DeviceStruct *dev,
+					int chunkInNAND, const __u8 *data,
+					const yaffs_Spare *spare);
+	int (*readChunkFromNAND) (struct yaffs_DeviceStruct *dev,
+					int chunkInNAND, __u8 *data,
+					yaffs_Spare *spare);
+	int (*eraseBlockInNAND) (struct yaffs_DeviceStruct *dev,
+					int blockInNAND);
+	int (*initialiseNAND) (struct yaffs_DeviceStruct *dev);
+	int (*deinitialiseNAND) (struct yaffs_DeviceStruct *dev);
+
+#ifdef CONFIG_YAFFS_YAFFS2
+	int (*writeChunkWithTagsToNAND) (struct yaffs_DeviceStruct *dev,
+					 int chunkInNAND, const __u8 *data,
+					 const yaffs_ExtendedTags *tags);
+	int (*readChunkWithTagsFromNAND) (struct yaffs_DeviceStruct *dev,
+					  int chunkInNAND, __u8 *data,
+					  yaffs_ExtendedTags *tags);
+	int (*markNANDBlockBad) (struct yaffs_DeviceStruct *dev, int blockNo);
+	int (*queryNANDBlock) (struct yaffs_DeviceStruct *dev, int blockNo,
+			       yaffs_BlockState *state, __u32 *sequenceNumber);
+#endif
+
+	/* The removeObjectCallback function must be supplied by OS flavours that
+	 * need it.
+         * yaffs direct uses it to implement the faster readdir.
+         * Linux uses it to protect the directory during unlocking.
+	 */
+	void (*removeObjectCallback)(struct yaffs_ObjectStruct *obj);
+
+	/* Callback to mark the superblock dirty */
+	void (*markSuperBlockDirty)(struct yaffs_DeviceStruct *dev);
+	
+	/*  Callback to control garbage collection. */
+	unsigned (*gcControl)(struct yaffs_DeviceStruct *dev);
+
+        /* Debug control flags. Don't use unless you know what you're doing */
+	int useHeaderFileSize;	/* Flag to determine if we should use file sizes from the header */
+	int disableLazyLoad;	/* Disable lazy loading on this device */
+	int wideTnodesDisabled; /* Set to disable wide tnodes */
+	
+	int deferDirectoryUpdate; /* Set to defer directory updates */
+	
+};
+
+typedef struct yaffs_DeviceParamStruct yaffs_DeviceParam;
+
+struct yaffs_DeviceStruct {
+	struct yaffs_DeviceParamStruct param;
+
+        /* Context storage. Holds extra OS specific data for this device */
+
+	void *context;
+
+	/* Runtime parameters. Set up by YAFFS. */
+	int nDataBytesPerChunk;	
+
+        /* Non-wide tnode stuff */
+	__u16 chunkGroupBits;	/* Number of bits that need to be resolved if
+                                 * the tnodes are not wide enough.
+                                 */
+	__u16 chunkGroupSize;	/* == 2^^chunkGroupBits */
+
+	/* Stuff to support wide tnodes */
+	__u32 tnodeWidth;
+	__u32 tnodeMask;
+
+	/* Stuff for figuring out file offset to chunk conversions */
+	__u32 chunkShift; /* Shift value */
+	__u32 chunkDiv;   /* Divisor after shifting: 1 for power-of-2 sizes */
+	__u32 chunkMask;  /* Mask to use for power-of-2 case */
+
+
+
+	int isMounted;
+	int readOnly;
+	int isCheckpointed;
+
+
+	/* Stuff to support block offsetting to support start block zero */
+	int internalStartBlock;
+	int internalEndBlock;
+	int blockOffset;
+	int chunkOffset;
+
+
+	/* Runtime checkpointing stuff */
+	int checkpointPageSequence;   /* running sequence number of checkpoint pages */
+	int checkpointByteCount;
+	int checkpointByteOffset;
+	__u8 *checkpointBuffer;
+	int checkpointOpenForWrite;
+	int blocksInCheckpoint;
+	int checkpointCurrentChunk;
+	int checkpointCurrentBlock;
+	int checkpointNextBlock;
+	int *checkpointBlockList;
+	int checkpointMaxBlocks;
+	__u32 checkpointSum;
+	__u32 checkpointXor;
+
+	int nCheckpointBlocksRequired; /* Number of blocks needed to store current checkpoint set */
+
+	/* Block Info */
+	yaffs_BlockInfo *blockInfo;
+	__u8 *chunkBits;	/* bitmap of chunks in use */
+	unsigned blockInfoAlt:1;	/* was allocated using alternative strategy */
+	unsigned chunkBitsAlt:1;	/* was allocated using alternative strategy */
+	int chunkBitmapStride;	/* Number of bytes of chunkBits per block.
+				 * Must be consistent with nChunksPerBlock.
+				 */
+
+	int nErasedBlocks;
+	int allocationBlock;	/* Current block being allocated off */
+	__u32 allocationPage;
+	int allocationBlockFinder;	/* Used to search for next allocation block */
+
+	int nTnodesCreated;
+	yaffs_Tnode *freeTnodes;
+	int nFreeTnodes;
+	yaffs_TnodeList *allocatedTnodeList;
+
+	int isDoingGC;
+	int gcBlock;
+	int gcChunk;
+
+	int nObjectsCreated;
+	yaffs_Object *freeObjects;
+	int nFreeObjects;
+
+	int nHardLinks;
+
+	yaffs_ObjectList *allocatedObjectList;
+
+	yaffs_ObjectBucket objectBucket[YAFFS_NOBJECT_BUCKETS];
+	__u32 bucketFinder;
+
+	int nFreeChunks;
+
+	int currentDirtyChecker;	/* Used to find current dirtiest block */
+
+	__u32 *gcCleanupList;	/* objects to delete at the end of a GC. */
+	int nonAggressiveSkip;	/* GC state/mode */
+
+	int hasPendingPrioritisedGCs; /* We think this device might have pending prioritised gcs */
+
+	/* Special directories */
+	yaffs_Object *rootDir;
+	yaffs_Object *lostNFoundDir;
+
+	/* Buffer areas for storing data to recover from write failures TODO
+	 *      __u8            bufferedData[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK];
+	 *      yaffs_Spare bufferedSpare[YAFFS_CHUNKS_PER_BLOCK];
+	 */
+
+	int bufferedBlock;	/* Which block is buffered here? */
+	int doingBufferedBlockRewrite;
+
+	yaffs_ChunkCache *srCache;
+	int srLastUse;
+
+	/* Stuff for background deletion and unlinked files.*/
+	yaffs_Object *unlinkedDir;	/* Directory where unlinked and deleted files live. */
+	yaffs_Object *deletedDir;	/* Directory where deleted objects are sent to disappear. */
+	yaffs_Object *unlinkedDeletion;	/* Current file being background deleted.*/
+	int nDeletedFiles;		/* Count of files awaiting deletion;*/
+	int nUnlinkedFiles;		/* Count of unlinked files. */
+	int nBackgroundDeletions;	/* Count of background deletions. */
+
+	/* Temporary buffer management */
+	yaffs_TempBuffer tempBuffer[YAFFS_N_TEMP_BUFFERS];
+	int maxTemp;
+	int tempInUse;
+	int unmanagedTempAllocations;
+	int unmanagedTempDeallocations;
+
+	/* yaffs2 runtime stuff */
+	unsigned sequenceNumber;	/* Sequence number of currently allocating block */
+	unsigned oldestDirtySequence;
+
+	/* Block refreshing */
+	int refreshSkip;	/* A skip down counter. Refresh happens when this gets to zero. */
+
+	/* Dirty directory handling */
+	struct ylist_head dirtyDirectories; /* List of dirty directories */
+
+
+	/* Statistcs */
+	__u32 nPageWrites;
+	__u32 nPageReads;
+	__u32 nBlockErasures;
+	__u32 nErasureFailures;
+	__u32 nGCCopies;
+	__u32 garbageCollections;
+	__u32 passiveGarbageCollections;
+	__u32 nRetriedWrites;
+	__u32 nRetiredBlocks;
+	__u32 eccFixed;
+	__u32 eccUnfixed;
+	__u32 tagsEccFixed;
+	__u32 tagsEccUnfixed;
+	__u32 nDeletions;
+	__u32 nUnmarkedDeletions;
+	__u32 refreshCount;
+	__u32 cacheHits;
+
+};
+
+typedef struct yaffs_DeviceStruct yaffs_Device;
+
+/* The static layout of block usage etc is stored in the super block header */
+typedef struct {
+	int StructType;
+	int version;
+	int checkpointStartBlock;
+	int checkpointEndBlock;
+	int startBlock;
+	int endBlock;
+	int rfu[100];
+} yaffs_SuperBlockHeader;
+
+/* The CheckpointDevice structure holds the device information that changes at runtime and
+ * must be preserved over unmount/mount cycles.
+ */
+typedef struct {
+	int structType;
+	int nErasedBlocks;
+	int allocationBlock;	/* Current block being allocated off */
+	__u32 allocationPage;
+	int nFreeChunks;
+
+	int nDeletedFiles;		/* Count of files awaiting deletion;*/
+	int nUnlinkedFiles;		/* Count of unlinked files. */
+	int nBackgroundDeletions;	/* Count of background deletions. */
+
+	/* yaffs2 runtime stuff */
+	unsigned sequenceNumber;	/* Sequence number of currently allocating block */
+
+} yaffs_CheckpointDevice;
+
+
+typedef struct {
+	int structType;
+	__u32 magic;
+	__u32 version;
+	__u32 head;
+} yaffs_CheckpointValidity;
+
+
+/*----------------------- YAFFS Functions -----------------------*/
+
+int yaffs_GutsInitialise(yaffs_Device *dev);
+void yaffs_Deinitialise(yaffs_Device *dev);
+
+int yaffs_GetNumberOfFreeChunks(yaffs_Device *dev);
+
+int yaffs_RenameObject(yaffs_Object *oldDir, const YCHAR *oldName,
+		       yaffs_Object *newDir, const YCHAR *newName);
+
+int yaffs_Unlink(yaffs_Object *dir, const YCHAR *name);
+int yaffs_DeleteObject(yaffs_Object *obj);
+
+int yaffs_GetObjectName(yaffs_Object *obj, YCHAR *name, int buffSize);
+int yaffs_GetObjectFileLength(yaffs_Object *obj);
+int yaffs_GetObjectInode(yaffs_Object *obj);
+unsigned yaffs_GetObjectType(yaffs_Object *obj);
+int yaffs_GetObjectLinkCount(yaffs_Object *obj);
+
+int yaffs_SetAttributes(yaffs_Object *obj, struct iattr *attr);
+int yaffs_GetAttributes(yaffs_Object *obj, struct iattr *attr);
+
+/* File operations */
+int yaffs_ReadDataFromFile(yaffs_Object *obj, __u8 *buffer, loff_t offset,
+				int nBytes);
+int yaffs_WriteDataToFile(yaffs_Object *obj, const __u8 *buffer, loff_t offset,
+				int nBytes, int writeThrough);
+int yaffs_ResizeFile(yaffs_Object *obj, loff_t newSize);
+
+yaffs_Object *yaffs_MknodFile(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid);
+
+int yaffs_FlushFile(yaffs_Object *obj, int updateTime, int dataSync);
+
+/* Flushing and checkpointing */
+void yaffs_FlushEntireDeviceCache(yaffs_Device *dev);
+
+int yaffs_CheckpointSave(yaffs_Device *dev);
+int yaffs_CheckpointRestore(yaffs_Device *dev);
+
+/* Directory operations */
+yaffs_Object *yaffs_MknodDirectory(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid);
+yaffs_Object *yaffs_FindObjectByName(yaffs_Object *theDir, const YCHAR *name);
+int yaffs_ApplyToDirectoryChildren(yaffs_Object *theDir,
+				   int (*fn) (yaffs_Object *));
+
+yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device *dev, __u32 number);
+
+/* Link operations */
+yaffs_Object *yaffs_Link(yaffs_Object *parent, const YCHAR *name,
+			 yaffs_Object *equivalentObject);
+
+yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object *obj);
+
+/* Symlink operations */
+yaffs_Object *yaffs_MknodSymLink(yaffs_Object *parent, const YCHAR *name,
+				 __u32 mode, __u32 uid, __u32 gid,
+				 const YCHAR *alias);
+YCHAR *yaffs_GetSymlinkAlias(yaffs_Object *obj);
+
+/* Special inodes (fifos, sockets and devices) */
+yaffs_Object *yaffs_MknodSpecial(yaffs_Object *parent, const YCHAR *name,
+				 __u32 mode, __u32 uid, __u32 gid, __u32 rdev);
+
+/* Special directories */
+yaffs_Object *yaffs_Root(yaffs_Device *dev);
+yaffs_Object *yaffs_LostNFound(yaffs_Device *dev);
+
+#ifdef CONFIG_YAFFS_WINCE
+/* CONFIG_YAFFS_WINCE special stuff */
+void yfsd_WinFileTimeNow(__u32 target[2]);
+#endif
+
+void yaffs_HandleDeferedFree(yaffs_Object *obj);
+
+
+void yaffs_UpdateDirtyDirectories(yaffs_Device *dev);
+
+
+/* Debug dump  */
+int yaffs_DumpObject(yaffs_Object *obj);
+
+void yaffs_GutsTest(yaffs_Device *dev);
+
+/* A few useful functions */
+void yaffs_InitialiseTags(yaffs_ExtendedTags *tags);
+void yaffs_DeleteChunk(yaffs_Device *dev, int chunkId, int markNAND, int lyn);
+int yaffs_CheckFF(__u8 *buffer, int nBytes);
+void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi);
+
+__u8 *yaffs_GetTempBuffer(yaffs_Device *dev, int lineNo);
+void yaffs_ReleaseTempBuffer(yaffs_Device *dev, __u8 *buffer, int lineNo);
+
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffsinterface.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffsinterface.h
--- linux-2.6.27.6/fs/yaffs2/yaffsinterface.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffsinterface.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,21 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFSINTERFACE_H__
+#define __YAFFSINTERFACE_H__
+
+int yaffs_Initialise(unsigned nBlocks);
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_linux.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_linux.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_linux.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_linux.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,40 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_LINUX_H__
+#define __YAFFS_LINUX_H__
+
+#include "devextras.h"
+#include "yportenv.h"
+
+struct yaffs_LinuxContext {
+	struct ylist_head	contextList; /* List of these we have mounted */
+	struct yaffs_DeviceStruct *dev;
+	struct super_block * superBlock;
+	struct task_struct *bgThread; /* Background thread for this device */
+	int bgRunning;
+        struct semaphore grossLock;     /* Gross locking semaphore */
+	__u8 *spareBuffer;      /* For mtdif2 use. Don't know the size of the buffer
+				 * at compile time so we have to allocate it.
+				 */
+	struct mtd_info *mtd;
+	struct ylist_head searchContexts;
+	void (*putSuperFunc)(struct super_block *sb);
+};
+
+#define yaffs_DeviceToContext(dev) ((struct yaffs_LinuxContext *)((dev)->context))
+
+#endif
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_mtdif1.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif1.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_mtdif1.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif1.c	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,363 @@
+/*
+ * YAFFS: Yet another FFS. A NAND-flash specific file system.
+ * yaffs_mtdif1.c  NAND mtd interface functions for small-page NAND.
+ *
+ * Copyright (C) 2002 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This module provides the interface between yaffs_nand.c and the
+ * MTD API.  This version is used when the MTD interface supports the
+ * 'mtd_oob_ops' style calls to read_oob and write_oob, circa 2.6.17,
+ * and we have small-page NAND device.
+ *
+ * These functions are invoked via function pointers in yaffs_nand.c.
+ * This replaces functionality provided by functions in yaffs_mtdif.c
+ * and the yaffs_TagsCompatability functions in yaffs_tagscompat.c that are
+ * called in yaffs_mtdif.c when the function pointers are NULL.
+ * We assume the MTD layer is performing ECC (useNANDECC is true).
+ */
+
+#include "yportenv.h"
+#include "yaffs_trace.h"
+#include "yaffs_guts.h"
+#include "yaffs_packedtags1.h"
+#include "yaffs_tagscompat.h"	/* for yaffs_CalcTagsECC */
+#include "yaffs_linux.h"
+
+#include "linux/kernel.h"
+#include "linux/version.h"
+#include "linux/types.h"
+#include "linux/mtd/mtd.h"
+
+/* Don't compile this module if we don't have MTD's mtd_oob_ops interface */
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+
+const char *yaffs_mtdif1_c_version = "$Id: yaffs_mtdif1.c,v 1.13 2010/02/18 01:18:04 charles Exp $";
+
+#ifndef CONFIG_YAFFS_9BYTE_TAGS
+# define YTAG1_SIZE 8
+#else
+# define YTAG1_SIZE 9
+#endif
+
+#if 0
+/* Use the following nand_ecclayout with MTD when using
+ * CONFIG_YAFFS_9BYTE_TAGS and the older on-NAND tags layout.
+ * If you have existing Yaffs images and the byte order differs from this,
+ * adjust 'oobfree' to match your existing Yaffs data.
+ *
+ * This nand_ecclayout scatters/gathers to/from the old-yaffs layout with the
+ * pageStatus byte (at NAND spare offset 4) scattered/gathered from/to
+ * the 9th byte.
+ *
+ * Old-style on-NAND format: T0,T1,T2,T3,P,B,T4,T5,E0,E1,E2,T6,T7,E3,E4,E5
+ * We have/need PackedTags1 plus pageStatus: T0,T1,T2,T3,T4,T5,T6,T7,P
+ * where Tn are the tag bytes, En are MTD's ECC bytes, P is the pageStatus
+ * byte and B is the small-page bad-block indicator byte.
+ */
+static struct nand_ecclayout nand_oob_16 = {
+	.eccbytes = 6,
+	.eccpos = { 8, 9, 10, 13, 14, 15 },
+	.oobavail = 9,
+	.oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
+};
+#endif
+
+/* Write a chunk (page) of data to NAND.
+ *
+ * Caller always provides ExtendedTags data which are converted to a more
+ * compact (packed) form for storage in NAND.  A mini-ECC runs over the
+ * contents of the tags meta-data; used to valid the tags when read.
+ *
+ *  - Pack ExtendedTags to PackedTags1 form
+ *  - Compute mini-ECC for PackedTags1
+ *  - Write data and packed tags to NAND.
+ *
+ * Note: Due to the use of the PackedTags1 meta-data which does not include
+ * a full sequence number (as found in the larger PackedTags2 form) it is
+ * necessary for Yaffs to re-write a chunk/page (just once) to mark it as
+ * discarded and dirty.  This is not ideal: newer NAND parts are supposed
+ * to be written just once.  When Yaffs performs this operation, this
+ * function is called with a NULL data pointer -- calling MTD write_oob
+ * without data is valid usage (2.6.17).
+ *
+ * Any underlying MTD error results in YAFFS_FAIL.
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device *dev,
+	int chunkInNAND, const __u8 *data, const yaffs_ExtendedTags *etags)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	int chunkBytes = dev->nDataBytesPerChunk;
+	loff_t addr = ((loff_t)chunkInNAND) * chunkBytes;
+	struct mtd_oob_ops ops;
+	yaffs_PackedTags1 pt1;
+	int retval;
+
+	/* we assume that PackedTags1 and yaffs_Tags are compatible */
+	compile_time_assertion(sizeof(yaffs_PackedTags1) == 12);
+	compile_time_assertion(sizeof(yaffs_Tags) == 8);
+
+	yaffs_PackTags1(&pt1, etags);
+	yaffs_CalcTagsECC((yaffs_Tags *)&pt1);
+
+	/* When deleting a chunk, the upper layer provides only skeletal
+	 * etags, one with chunkDeleted set.  However, we need to update the
+	 * tags, not erase them completely.  So we use the NAND write property
+	 * that only zeroed-bits stick and set tag bytes to all-ones and
+	 * zero just the (not) deleted bit.
+	 */
+#ifndef CONFIG_YAFFS_9BYTE_TAGS
+	if (etags->chunkDeleted) {
+		memset(&pt1, 0xff, 8);
+		/* clear delete status bit to indicate deleted */
+		pt1.deleted = 0;
+	}
+#else
+	((__u8 *)&pt1)[8] = 0xff;
+	if (etags->chunkDeleted) {
+		memset(&pt1, 0xff, 8);
+		/* zero pageStatus byte to indicate deleted */
+		((__u8 *)&pt1)[8] = 0;
+	}
+#endif
+
+	memset(&ops, 0, sizeof(ops));
+	ops.mode = MTD_OOB_AUTO;
+	ops.len = (data) ? chunkBytes : 0;
+	ops.ooblen = YTAG1_SIZE;
+	ops.datbuf = (__u8 *)data;
+	ops.oobbuf = (__u8 *)&pt1;
+
+	retval = mtd->write_oob(mtd, addr, &ops);
+	if (retval) {
+		yaffs_trace(YAFFS_TRACE_MTD,
+			"write_oob failed, chunk %d, mtd error %d\n",
+			chunkInNAND, retval);
+	}
+	return retval ? YAFFS_FAIL : YAFFS_OK;
+}
+
+/* Return with empty ExtendedTags but add eccResult.
+ */
+static int rettags(yaffs_ExtendedTags *etags, int eccResult, int retval)
+{
+	if (etags) {
+		memset(etags, 0, sizeof(*etags));
+		etags->eccResult = eccResult;
+	}
+	return retval;
+}
+
+/* Read a chunk (page) from NAND.
+ *
+ * Caller expects ExtendedTags data to be usable even on error; that is,
+ * all members except eccResult and blockBad are zeroed.
+ *
+ *  - Check ECC results for data (if applicable)
+ *  - Check for blank/erased block (return empty ExtendedTags if blank)
+ *  - Check the PackedTags1 mini-ECC (correct if necessary/possible)
+ *  - Convert PackedTags1 to ExtendedTags
+ *  - Update eccResult and blockBad members to refect state.
+ *
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device *dev,
+	int chunkInNAND, __u8 *data, yaffs_ExtendedTags *etags)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	int chunkBytes = dev->nDataBytesPerChunk;
+	loff_t addr = ((loff_t)chunkInNAND) * chunkBytes;
+	int eccres = YAFFS_ECC_RESULT_NO_ERROR;
+	struct mtd_oob_ops ops;
+	yaffs_PackedTags1 pt1;
+	int retval;
+	int deleted;
+
+	memset(&ops, 0, sizeof(ops));
+	ops.mode = MTD_OOB_AUTO;
+	ops.len = (data) ? chunkBytes : 0;
+	ops.ooblen = YTAG1_SIZE;
+	ops.datbuf = data;
+	ops.oobbuf = (__u8 *)&pt1;
+
+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 20))
+	/* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug;
+	 * help it out with ops.len = ops.ooblen when ops.datbuf == NULL.
+	 */
+	ops.len = (ops.datbuf) ? ops.len : ops.ooblen;
+#endif
+	/* Read page and oob using MTD.
+	 * Check status and determine ECC result.
+	 */
+	retval = mtd->read_oob(mtd, addr, &ops);
+	if (retval) {
+		yaffs_trace(YAFFS_TRACE_MTD,
+			"read_oob failed, chunk %d, mtd error %d\n",
+			chunkInNAND, retval);
+	}
+
+	switch (retval) {
+	case 0:
+		/* no error */
+		break;
+
+	case -EUCLEAN:
+		/* MTD's ECC fixed the data */
+		eccres = YAFFS_ECC_RESULT_FIXED;
+		dev->eccFixed++;
+		break;
+
+	case -EBADMSG:
+		/* MTD's ECC could not fix the data */
+		dev->eccUnfixed++;
+		/* fall into... */
+	default:
+		rettags(etags, YAFFS_ECC_RESULT_UNFIXED, 0);
+		etags->blockBad = (mtd->block_isbad)(mtd, addr);
+		return YAFFS_FAIL;
+	}
+
+	/* Check for a blank/erased chunk.
+	 */
+	if (yaffs_CheckFF((__u8 *)&pt1, 8)) {
+		/* when blank, upper layers want eccResult to be <= NO_ERROR */
+		return rettags(etags, YAFFS_ECC_RESULT_NO_ERROR, YAFFS_OK);
+	}
+
+#ifndef CONFIG_YAFFS_9BYTE_TAGS
+	/* Read deleted status (bit) then return it to it's non-deleted
+	 * state before performing tags mini-ECC check. pt1.deleted is
+	 * inverted.
+	 */
+	deleted = !pt1.deleted;
+	pt1.deleted = 1;
+#else
+	deleted = (yaffs_CountBits(((__u8 *)&pt1)[8]) < 7);
+#endif
+
+	/* Check the packed tags mini-ECC and correct if necessary/possible.
+	 */
+	retval = yaffs_CheckECCOnTags((yaffs_Tags *)&pt1);
+	switch (retval) {
+	case 0:
+		/* no tags error, use MTD result */
+		break;
+	case 1:
+		/* recovered tags-ECC error */
+		dev->tagsEccFixed++;
+		if (eccres == YAFFS_ECC_RESULT_NO_ERROR)
+			eccres = YAFFS_ECC_RESULT_FIXED;
+		break;
+	default:
+		/* unrecovered tags-ECC error */
+		dev->tagsEccUnfixed++;
+		return rettags(etags, YAFFS_ECC_RESULT_UNFIXED, YAFFS_FAIL);
+	}
+
+	/* Unpack the tags to extended form and set ECC result.
+	 * [set shouldBeFF just to keep yaffs_UnpackTags1 happy]
+	 */
+	pt1.shouldBeFF = 0xFFFFFFFF;
+	yaffs_UnpackTags1(etags, &pt1);
+	etags->eccResult = eccres;
+
+	/* Set deleted state */
+	etags->chunkDeleted = deleted;
+	return YAFFS_OK;
+}
+
+/* Mark a block bad.
+ *
+ * This is a persistant state.
+ * Use of this function should be rare.
+ *
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	int blocksize = dev->param.nChunksPerBlock * dev->nDataBytesPerChunk;
+	int retval;
+
+	yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, "marking block %d bad\n", blockNo);
+
+	retval = mtd->block_markbad(mtd, (loff_t)blocksize * blockNo);
+	return (retval) ? YAFFS_FAIL : YAFFS_OK;
+}
+
+/* Check any MTD prerequists.
+ *
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+static int nandmtd1_TestPrerequists(struct mtd_info *mtd)
+{
+	/* 2.6.18 has mtd->ecclayout->oobavail */
+	/* 2.6.21 has mtd->ecclayout->oobavail and mtd->oobavail */
+	int oobavail = mtd->ecclayout->oobavail;
+
+	if (oobavail < YTAG1_SIZE) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"mtd device has only %d bytes for tags, need %d\n",
+			oobavail, YTAG1_SIZE);
+		return YAFFS_FAIL;
+	}
+	return YAFFS_OK;
+}
+
+/* Query for the current state of a specific block.
+ *
+ * Examine the tags of the first chunk of the block and return the state:
+ *  - YAFFS_BLOCK_STATE_DEAD, the block is marked bad
+ *  - YAFFS_BLOCK_STATE_NEEDS_SCANNING, the block is in use
+ *  - YAFFS_BLOCK_STATE_EMPTY, the block is clean
+ *
+ * Always returns YAFFS_OK.
+ */
+int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+	yaffs_BlockState *pState, __u32 *pSequenceNumber)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	int chunkNo = blockNo * dev->param.nChunksPerBlock;
+	loff_t addr = (loff_t)chunkNo * dev->nDataBytesPerChunk;
+	yaffs_ExtendedTags etags;
+	int state = YAFFS_BLOCK_STATE_DEAD;
+	int seqnum = 0;
+	int retval;
+
+	/* We don't yet have a good place to test for MTD config prerequists.
+	 * Do it here as we are called during the initial scan.
+	 */
+	if (nandmtd1_TestPrerequists(mtd) != YAFFS_OK)
+		return YAFFS_FAIL;
+
+	retval = nandmtd1_ReadChunkWithTagsFromNAND(dev, chunkNo, NULL, &etags);
+	etags.blockBad = (mtd->block_isbad)(mtd, addr);
+	if (etags.blockBad) {
+		yaffs_trace(YAFFS_TRACE_BAD_BLOCKS,
+			"block %d is marked bad\n", blockNo);
+		state = YAFFS_BLOCK_STATE_DEAD;
+	} else if (etags.eccResult != YAFFS_ECC_RESULT_NO_ERROR) {
+		/* bad tags, need to look more closely */
+		state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+	} else if (etags.chunkUsed) {
+		state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+		seqnum = etags.sequenceNumber;
+	} else {
+		state = YAFFS_BLOCK_STATE_EMPTY;
+	}
+
+	*pState = state;
+	*pSequenceNumber = seqnum;
+
+	/* query always succeeds */
+	return YAFFS_OK;
+}
+
+#endif /*MTD_VERSION*/
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_mtdif1.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif1.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_mtdif1.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif1.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,28 @@
+/*
+ * YAFFS: Yet another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_MTDIF1_H__
+#define __YAFFS_MTDIF1_H__
+
+int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device *dev, int chunkInNAND,
+	const __u8 *data, const yaffs_ExtendedTags *tags);
+
+int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+	__u8 *data, yaffs_ExtendedTags *tags);
+
+int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
+
+int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+	yaffs_BlockState *state, __u32 *sequenceNumber);
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_mtdif2.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif2.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_mtdif2.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif2.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,254 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* mtd interface for YAFFS2 */
+
+const char *yaffs_mtdif2_c_version =
+	"$Id: yaffs_mtdif2.c,v 1.27 2010/02/18 01:18:04 charles Exp $";
+
+#include "yportenv.h"
+#include "yaffs_trace.h"
+
+#include "yaffs_mtdif2.h"
+
+#include "linux/mtd/mtd.h"
+#include "linux/types.h"
+#include "linux/time.h"
+
+#include "yaffs_packedtags2.h"
+
+#include "yaffs_linux.h"
+
+/* NB For use with inband tags....
+ * We assume that the data buffer is of size totalBytersPerChunk so that we can also
+ * use it to load the tags.
+ */
+int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device *dev, int chunkInNAND,
+				      const __u8 *data,
+				      const yaffs_ExtendedTags *tags)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	struct mtd_oob_ops ops;
+#else
+	size_t dummy;
+#endif
+	int retval = 0;
+
+	loff_t addr;
+
+	yaffs_PackedTags2 pt;
+
+	int packed_tags_size = dev->param.noTagsECC ? sizeof(pt.t) : sizeof(pt);
+	void * packed_tags_ptr = dev->param.noTagsECC ? (void *) &pt.t : (void *)&pt;
+
+	T(YAFFS_TRACE_MTD,
+	  (TSTR
+	   ("nandmtd2_WriteChunkWithTagsToNAND chunk %d data %p tags %p"
+	    TENDSTR), chunkInNAND, data, tags));
+
+
+	addr  = ((loff_t) chunkInNAND) * dev->param.totalBytesPerChunk;
+
+	/* For yaffs2 writing there must be both data and tags.
+	 * If we're using inband tags, then the tags are stuffed into
+	 * the end of the data buffer.
+	 */
+	if (!data || !tags)
+		BUG();
+	else if (dev->param.inbandTags) {
+		yaffs_PackedTags2TagsPart *pt2tp;
+		pt2tp = (yaffs_PackedTags2TagsPart *)(data + dev->nDataBytesPerChunk);
+		yaffs_PackTags2TagsPart(pt2tp, tags);
+	} else
+		yaffs_PackTags2(&pt, tags, !dev->param.noTagsECC);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+	ops.mode = MTD_OOB_AUTO;
+	ops.ooblen = (dev->param.inbandTags) ? 0 : packed_tags_size;
+	ops.len = dev->param.totalBytesPerChunk;
+	ops.ooboffs = 0;
+	ops.datbuf = (__u8 *)data;
+	ops.oobbuf = (dev->param.inbandTags) ? NULL : packed_tags_ptr;
+	retval = mtd->write_oob(mtd, addr, &ops);
+
+#else
+	if (!dev->param.inbandTags) {
+		retval =
+		    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
+				   &dummy, data, (__u8 *) packed_tags_ptr, NULL);
+	} else {
+		retval =
+		    mtd->write(mtd, addr, dev->param.totalBytesPerChunk, &dummy,
+			       data);
+	}
+#endif
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+				       __u8 *data, yaffs_ExtendedTags *tags)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	struct mtd_oob_ops ops;
+#endif
+	size_t dummy;
+	int retval = 0;
+	int localData = 0;
+
+	loff_t addr = ((loff_t) chunkInNAND) * dev->param.totalBytesPerChunk;
+
+	yaffs_PackedTags2 pt;
+
+	int packed_tags_size = dev->param.noTagsECC ? sizeof(pt.t) : sizeof(pt);
+	void * packed_tags_ptr = dev->param.noTagsECC ? (void *) &pt.t: (void *)&pt;
+
+	T(YAFFS_TRACE_MTD,
+	  (TSTR
+	   ("nandmtd2_ReadChunkWithTagsFromNAND chunk %d data %p tags %p"
+	    TENDSTR), chunkInNAND, data, tags));
+
+	if (dev->param.inbandTags) {
+
+		if (!data) {
+			localData = 1;
+			data = yaffs_GetTempBuffer(dev, __LINE__);
+		}
+
+
+	}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+	if (dev->param.inbandTags || (data && !tags))
+		retval = mtd->read(mtd, addr, dev->param.totalBytesPerChunk,
+				&dummy, data);
+	else if (tags) {
+		ops.mode = MTD_OOB_AUTO;
+		ops.ooblen = packed_tags_size;
+		ops.len = data ? dev->nDataBytesPerChunk : packed_tags_size;
+		ops.ooboffs = 0;
+		ops.datbuf = data;
+		ops.oobbuf = yaffs_DeviceToContext(dev)->spareBuffer;
+		retval = mtd->read_oob(mtd, addr, &ops);
+	}
+#else
+	if (!dev->param.inbandTags && data && tags) {
+
+		retval = mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
+					  &dummy, data, dev->spareBuffer,
+					  NULL);
+	} else {
+		if (data)
+			retval =
+			    mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
+				      data);
+		if (!dev->param.inbandTags && tags)
+			retval =
+			    mtd->read_oob(mtd, addr, mtd->oobsize, &dummy,
+					  dev->spareBuffer);
+	}
+#endif
+
+
+	if (dev->param.inbandTags) {
+		if (tags) {
+			yaffs_PackedTags2TagsPart *pt2tp;
+			pt2tp = (yaffs_PackedTags2TagsPart *)&data[dev->nDataBytesPerChunk];
+			yaffs_UnpackTags2TagsPart(tags, pt2tp);
+		}
+	} else {
+		if (tags) {
+			memcpy(packed_tags_ptr, yaffs_DeviceToContext(dev)->spareBuffer, packed_tags_size);
+			yaffs_UnpackTags2(tags, &pt, !dev->param.noTagsECC);
+		}
+	}
+
+	if (localData)
+		yaffs_ReleaseTempBuffer(dev, data, __LINE__);
+
+	if (tags && retval == -EBADMSG && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR)
+		tags->eccResult = YAFFS_ECC_RESULT_UNFIXED;
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	int retval;
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("nandmtd2_MarkNANDBlockBad %d" TENDSTR), blockNo));
+
+	retval =
+	    mtd->block_markbad(mtd,
+			       blockNo * dev->param.nChunksPerBlock *
+			       dev->param.totalBytesPerChunk);
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+
+}
+
+int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+			    yaffs_BlockState *state, __u32 *sequenceNumber)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	int retval;
+
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("nandmtd2_QueryNANDBlock %d" TENDSTR), blockNo));
+	retval =
+	    mtd->block_isbad(mtd,
+			     blockNo * dev->param.nChunksPerBlock *
+			     dev->param.totalBytesPerChunk);
+
+	if (retval) {
+		T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR)));
+
+		*state = YAFFS_BLOCK_STATE_DEAD;
+		*sequenceNumber = 0;
+	} else {
+		yaffs_ExtendedTags t;
+		nandmtd2_ReadChunkWithTagsFromNAND(dev,
+						   blockNo *
+						   dev->param.nChunksPerBlock, NULL,
+						   &t);
+
+		if (t.chunkUsed) {
+			*sequenceNumber = t.sequenceNumber;
+			*state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+		} else {
+			*sequenceNumber = 0;
+			*state = YAFFS_BLOCK_STATE_EMPTY;
+		}
+	}
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("block is bad seq %d state %d" TENDSTR), *sequenceNumber,
+	   *state));
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_mtdif2.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif2.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_mtdif2.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif2.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,29 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_MTDIF2_H__
+#define __YAFFS_MTDIF2_H__
+
+#include "yaffs_guts.h"
+int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device *dev, int chunkInNAND,
+				const __u8 *data,
+				const yaffs_ExtendedTags *tags);
+int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+				__u8 *data, yaffs_ExtendedTags *tags);
+int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
+int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+			yaffs_BlockState *state, __u32 *sequenceNumber);
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_mtdif.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_mtdif.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,59 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_mtdif_c_version =
+	"$Id: yaffs_mtdif.c,v 1.25 2010/02/19 01:06:31 charles Exp $";
+
+#include "yportenv.h"
+
+
+#include "yaffs_mtdif.h"
+
+#include "linux/mtd/mtd.h"
+#include "linux/types.h"
+#include "linux/time.h"
+#include "linux/mtd/nand.h"
+
+#include "yaffs_linux.h"
+
+int nandmtd_EraseBlockInNAND(yaffs_Device *dev, int blockNumber)
+{
+	struct mtd_info *mtd = yaffs_DeviceToContext(dev)->mtd;
+	__u32 addr =
+	    ((loff_t) blockNumber) * dev->param.totalBytesPerChunk
+		* dev->param.nChunksPerBlock;
+	struct erase_info ei;
+	
+	int retval = 0;
+
+	ei.mtd = mtd;
+	ei.addr = addr;
+	ei.len = dev->param.totalBytesPerChunk * dev->param.nChunksPerBlock;
+	ei.time = 1000;
+	ei.retries = 2;
+	ei.callback = NULL;
+	ei.priv = (u_long) dev;
+
+	retval = mtd->erase(mtd, &ei);
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd_InitialiseNAND(yaffs_Device *dev)
+{
+	return YAFFS_OK;
+}
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_mtdif.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_mtdif.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_mtdif.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,27 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_MTDIF_H__
+#define __YAFFS_MTDIF_H__
+
+#include "yaffs_guts.h"
+
+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 18))
+extern struct nand_oobinfo yaffs_oobinfo;
+extern struct nand_oobinfo yaffs_noeccinfo;
+#endif
+int nandmtd_EraseBlockInNAND(yaffs_Device *dev, int blockNumber);
+int nandmtd_InitialiseNAND(yaffs_Device *dev);
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_nand.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_nand.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_nand.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_nand.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,142 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_nand_c_version =
+	"$Id: yaffs_nand.c,v 1.13 2010/02/19 01:05:48 charles Exp $";
+
+#include "yaffs_nand.h"
+#include "yaffs_tagscompat.h"
+#include "yaffs_tagsvalidity.h"
+
+#include "yaffs_getblockinfo.h"
+
+int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+					   __u8 *buffer,
+					   yaffs_ExtendedTags *tags)
+{
+	int result;
+	yaffs_ExtendedTags localTags;
+
+	int realignedChunkInNAND = chunkInNAND - dev->chunkOffset;
+
+	dev->nPageReads++;
+
+	/* If there are no tags provided, use local tags to get prioritised gc working */
+	if (!tags)
+		tags = &localTags;
+
+	if (dev->param.readChunkWithTagsFromNAND)
+		result = dev->param.readChunkWithTagsFromNAND(dev, realignedChunkInNAND, buffer,
+						      tags);
+	else
+		result = yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(dev,
+									realignedChunkInNAND,
+									buffer,
+									tags);
+	if (tags &&
+	   tags->eccResult > YAFFS_ECC_RESULT_NO_ERROR) {
+
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, chunkInNAND/dev->param.nChunksPerBlock);
+		yaffs_HandleChunkError(dev, bi);
+	}
+
+	return result;
+}
+
+int yaffs_WriteChunkWithTagsToNAND(yaffs_Device *dev,
+						   int chunkInNAND,
+						   const __u8 *buffer,
+						   yaffs_ExtendedTags *tags)
+{
+
+	dev->nPageWrites++;
+
+	chunkInNAND -= dev->chunkOffset;
+
+
+	if (tags) {
+		tags->sequenceNumber = dev->sequenceNumber;
+		tags->chunkUsed = 1;
+		if (!yaffs_ValidateTags(tags)) {
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR("Writing uninitialised tags" TENDSTR)));
+			YBUG();
+		}
+		T(YAFFS_TRACE_WRITE,
+		  (TSTR("Writing chunk %d tags %d %d" TENDSTR), chunkInNAND,
+		   tags->objectId, tags->chunkId));
+	} else {
+		T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR)));
+		YBUG();
+	}
+
+	if (dev->param.writeChunkWithTagsToNAND)
+		return dev->param.writeChunkWithTagsToNAND(dev, chunkInNAND, buffer,
+						     tags);
+	else
+		return yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(dev,
+								       chunkInNAND,
+								       buffer,
+								       tags);
+}
+
+int yaffs_MarkBlockBad(yaffs_Device *dev, int blockNo)
+{
+	blockNo -= dev->blockOffset;
+
+
+	if (dev->param.markNANDBlockBad)
+		return dev->param.markNANDBlockBad(dev, blockNo);
+	else
+		return yaffs_TagsCompatabilityMarkNANDBlockBad(dev, blockNo);
+}
+
+int yaffs_QueryInitialBlockState(yaffs_Device *dev,
+						 int blockNo,
+						 yaffs_BlockState *state,
+						 __u32 *sequenceNumber)
+{
+	blockNo -= dev->blockOffset;
+
+	if (dev->param.queryNANDBlock)
+		return dev->param.queryNANDBlock(dev, blockNo, state, sequenceNumber);
+	else
+		return yaffs_TagsCompatabilityQueryNANDBlock(dev, blockNo,
+							     state,
+							     sequenceNumber);
+}
+
+
+int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
+				  int blockInNAND)
+{
+	int result;
+
+	blockInNAND -= dev->blockOffset;
+
+	dev->nBlockErasures++;
+
+	result = dev->param.eraseBlockInNAND(dev, blockInNAND);
+
+	return result;
+}
+
+int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev)
+{
+	if(dev->param.initialiseNAND)
+		return dev->param.initialiseNAND(dev);
+	return YAFFS_OK;
+}
+
+
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_nandemul2k.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_nandemul2k.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_nandemul2k.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_nandemul2k.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,39 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/* Interface to emulated NAND functions (2k page size) */
+
+#ifndef __YAFFS_NANDEMUL2K_H__
+#define __YAFFS_NANDEMUL2K_H__
+
+#include "yaffs_guts.h"
+
+int nandemul2k_WriteChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
+					int chunkInNAND, const __u8 *data,
+					const yaffs_ExtendedTags *tags);
+int nandemul2k_ReadChunkWithTagsFromNAND(struct yaffs_DeviceStruct *dev,
+					 int chunkInNAND, __u8 *data,
+					 yaffs_ExtendedTags *tags);
+int nandemul2k_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
+int nandemul2k_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+			      yaffs_BlockState *state, __u32 *sequenceNumber);
+int nandemul2k_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
+				int blockInNAND);
+int nandemul2k_InitialiseNAND(struct yaffs_DeviceStruct *dev);
+int nandemul2k_GetBytesPerChunk(void);
+int nandemul2k_GetChunksPerBlock(void);
+int nandemul2k_GetNumberOfBlocks(void);
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_nand.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_nand.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_nand.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_nand.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,44 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_NAND_H__
+#define __YAFFS_NAND_H__
+#include "yaffs_guts.h"
+
+
+
+int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+					__u8 *buffer,
+					yaffs_ExtendedTags *tags);
+
+int yaffs_WriteChunkWithTagsToNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						const __u8 *buffer,
+						yaffs_ExtendedTags *tags);
+
+int yaffs_MarkBlockBad(yaffs_Device *dev, int blockNo);
+
+int yaffs_QueryInitialBlockState(yaffs_Device *dev,
+						int blockNo,
+						yaffs_BlockState *state,
+						unsigned *sequenceNumber);
+
+int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
+				  int blockInNAND);
+
+int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev);
+
+#endif
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_packedtags1.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags1.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_packedtags1.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags1.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,50 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_packedtags1.h"
+#include "yportenv.h"
+
+void yaffs_PackTags1(yaffs_PackedTags1 *pt, const yaffs_ExtendedTags *t)
+{
+	pt->chunkId = t->chunkId;
+	pt->serialNumber = t->serialNumber;
+	pt->byteCount = t->byteCount;
+	pt->objectId = t->objectId;
+	pt->ecc = 0;
+	pt->deleted = (t->chunkDeleted) ? 0 : 1;
+	pt->unusedStuff = 0;
+	pt->shouldBeFF = 0xFFFFFFFF;
+
+}
+
+void yaffs_UnpackTags1(yaffs_ExtendedTags *t, const yaffs_PackedTags1 *pt)
+{
+	static const __u8 allFF[] =
+	    { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff };
+
+	if (memcmp(allFF, pt, sizeof(yaffs_PackedTags1))) {
+		t->blockBad = 0;
+		if (pt->shouldBeFF != 0xFFFFFFFF)
+			t->blockBad = 1;
+		t->chunkUsed = 1;
+		t->objectId = pt->objectId;
+		t->chunkId = pt->chunkId;
+		t->byteCount = pt->byteCount;
+		t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+		t->chunkDeleted = (pt->deleted) ? 0 : 1;
+		t->serialNumber = pt->serialNumber;
+	} else {
+		memset(t, 0, sizeof(yaffs_ExtendedTags));
+	}
+}
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_packedtags1.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags1.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_packedtags1.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags1.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,37 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */
+
+#ifndef __YAFFS_PACKEDTAGS1_H__
+#define __YAFFS_PACKEDTAGS1_H__
+
+#include "yaffs_guts.h"
+
+typedef struct {
+	unsigned chunkId:20;
+	unsigned serialNumber:2;
+	unsigned byteCount:10;
+	unsigned objectId:18;
+	unsigned ecc:12;
+	unsigned deleted:1;
+	unsigned unusedStuff:1;
+	unsigned shouldBeFF;
+
+} yaffs_PackedTags1;
+
+void yaffs_PackTags1(yaffs_PackedTags1 *pt, const yaffs_ExtendedTags *t);
+void yaffs_UnpackTags1(yaffs_ExtendedTags *t, const yaffs_PackedTags1 *pt);
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_packedtags2.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags2.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_packedtags2.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags2.c	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,198 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_packedtags2.h"
+#include "yportenv.h"
+#include "yaffs_trace.h"
+#include "yaffs_tagsvalidity.h"
+
+/* This code packs a set of extended tags into a binary structure for
+ * NAND storage
+ */
+
+/* Some of the information is "extra" struff which can be packed in to
+ * speed scanning
+ * This is defined by having the EXTRA_HEADER_INFO_FLAG set.
+ */
+
+/* Extra flags applied to chunkId */
+
+#define EXTRA_HEADER_INFO_FLAG	0x80000000
+#define EXTRA_SHRINK_FLAG	0x40000000
+#define EXTRA_SHADOWS_FLAG	0x20000000
+#define EXTRA_SPARE_FLAGS	0x10000000
+
+#define ALL_EXTRA_FLAGS		0xF0000000
+
+/* Also, the top 4 bits of the object Id are set to the object type. */
+#define EXTRA_OBJECT_TYPE_SHIFT (28)
+#define EXTRA_OBJECT_TYPE_MASK  ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT)
+
+
+static void yaffs_DumpPackedTags2TagsPart(const yaffs_PackedTags2TagsPart *ptt)
+{
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR),
+	   ptt->objectId, ptt->chunkId, ptt->byteCount,
+	   ptt->sequenceNumber));
+}
+static void yaffs_DumpPackedTags2(const yaffs_PackedTags2 *pt)
+{
+	yaffs_DumpPackedTags2TagsPart(&pt->t);
+}
+
+static void yaffs_DumpTags2(const yaffs_ExtendedTags *t)
+{
+	T(YAFFS_TRACE_MTD,
+	  (TSTR
+	   ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d"
+	    TENDSTR), t->eccResult, t->blockBad, t->chunkUsed, t->objectId,
+	   t->chunkId, t->byteCount, t->chunkDeleted, t->serialNumber,
+	   t->sequenceNumber));
+
+}
+
+void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart *ptt,
+		const yaffs_ExtendedTags *t)
+{
+	ptt->chunkId = t->chunkId;
+	ptt->sequenceNumber = t->sequenceNumber;
+	ptt->byteCount = t->byteCount;
+	ptt->objectId = t->objectId;
+
+	if (t->chunkId == 0 && t->extraHeaderInfoAvailable) {
+		/* Store the extra header info instead */
+		/* We save the parent object in the chunkId */
+		ptt->chunkId = EXTRA_HEADER_INFO_FLAG
+			| t->extraParentObjectId;
+		if (t->extraIsShrinkHeader)
+			ptt->chunkId |= EXTRA_SHRINK_FLAG;
+		if (t->extraShadows)
+			ptt->chunkId |= EXTRA_SHADOWS_FLAG;
+
+		ptt->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
+		ptt->objectId |=
+		    (t->extraObjectType << EXTRA_OBJECT_TYPE_SHIFT);
+
+		if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK)
+			ptt->byteCount = t->extraEquivalentObjectId;
+		else if (t->extraObjectType == YAFFS_OBJECT_TYPE_FILE)
+			ptt->byteCount = t->extraFileLength;
+		else
+			ptt->byteCount = 0;
+	}
+
+	yaffs_DumpPackedTags2TagsPart(ptt);
+	yaffs_DumpTags2(t);
+}
+
+
+void yaffs_PackTags2(yaffs_PackedTags2 *pt, const yaffs_ExtendedTags *t, int tagsECC)
+{
+	yaffs_PackTags2TagsPart(&pt->t, t);
+
+	if(tagsECC)
+		yaffs_ECCCalculateOther((unsigned char *)&pt->t,
+					sizeof(yaffs_PackedTags2TagsPart),
+					&pt->ecc);
+}
+
+
+void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags *t,
+		yaffs_PackedTags2TagsPart *ptt)
+{
+
+	memset(t, 0, sizeof(yaffs_ExtendedTags));
+
+	yaffs_InitialiseTags(t);
+
+	if (ptt->sequenceNumber != 0xFFFFFFFF) {
+		t->blockBad = 0;
+		t->chunkUsed = 1;
+		t->objectId = ptt->objectId;
+		t->chunkId = ptt->chunkId;
+		t->byteCount = ptt->byteCount;
+		t->chunkDeleted = 0;
+		t->serialNumber = 0;
+		t->sequenceNumber = ptt->sequenceNumber;
+
+		/* Do extra header info stuff */
+
+		if (ptt->chunkId & EXTRA_HEADER_INFO_FLAG) {
+			t->chunkId = 0;
+			t->byteCount = 0;
+
+			t->extraHeaderInfoAvailable = 1;
+			t->extraParentObjectId =
+			    ptt->chunkId & (~(ALL_EXTRA_FLAGS));
+			t->extraIsShrinkHeader =
+			    (ptt->chunkId & EXTRA_SHRINK_FLAG) ? 1 : 0;
+			t->extraShadows =
+			    (ptt->chunkId & EXTRA_SHADOWS_FLAG) ? 1 : 0;
+			t->extraObjectType =
+			    ptt->objectId >> EXTRA_OBJECT_TYPE_SHIFT;
+			t->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
+
+			if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK)
+				t->extraEquivalentObjectId = ptt->byteCount;
+			else
+				t->extraFileLength = ptt->byteCount;
+		}
+	}
+
+	yaffs_DumpPackedTags2TagsPart(ptt);
+	yaffs_DumpTags2(t);
+
+}
+
+
+void yaffs_UnpackTags2(yaffs_ExtendedTags *t, yaffs_PackedTags2 *pt, int tagsECC)
+{
+
+	yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+
+	if (pt->t.sequenceNumber != 0xFFFFFFFF &&
+	    tagsECC){
+		/* Chunk is in use and we need to do ECC */
+		
+		yaffs_ECCOther ecc;
+		int result;
+		yaffs_ECCCalculateOther((unsigned char *)&pt->t,
+					sizeof(yaffs_PackedTags2TagsPart),
+					&ecc);
+		result = yaffs_ECCCorrectOther((unsigned char *)&pt->t,
+						sizeof(yaffs_PackedTags2TagsPart),
+						&pt->ecc, &ecc);
+		switch (result) {
+			case 0:
+				eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+				break;
+			case 1:
+				eccResult = YAFFS_ECC_RESULT_FIXED;
+				break;
+			case -1:
+				eccResult = YAFFS_ECC_RESULT_UNFIXED;
+				break;
+			default:
+				eccResult = YAFFS_ECC_RESULT_UNKNOWN;
+		}
+	}
+
+	yaffs_UnpackTags2TagsPart(t, &pt->t);
+
+	t->eccResult = eccResult;
+
+	yaffs_DumpPackedTags2(pt);
+	yaffs_DumpTags2(t);
+}
+
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_packedtags2.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags2.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_packedtags2.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_packedtags2.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,43 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/* This is used to pack YAFFS2 tags, not YAFFS1tags. */
+
+#ifndef __YAFFS_PACKEDTAGS2_H__
+#define __YAFFS_PACKEDTAGS2_H__
+
+#include "yaffs_guts.h"
+#include "yaffs_ecc.h"
+
+typedef struct {
+	unsigned sequenceNumber;
+	unsigned objectId;
+	unsigned chunkId;
+	unsigned byteCount;
+} yaffs_PackedTags2TagsPart;
+
+typedef struct {
+	yaffs_PackedTags2TagsPart t;
+	yaffs_ECCOther ecc;
+} yaffs_PackedTags2;
+
+/* Full packed tags with ECC, used for oob tags */
+void yaffs_PackTags2(yaffs_PackedTags2 *pt, const yaffs_ExtendedTags *t, int tagsECC);
+void yaffs_UnpackTags2(yaffs_ExtendedTags *t, yaffs_PackedTags2 *pt, int tagsECC);
+
+/* Only the tags part (no ECC for use with inband tags */
+void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart *pt, const yaffs_ExtendedTags *t);
+void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags *t, yaffs_PackedTags2TagsPart *pt);
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_qsort.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_qsort.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_qsort.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_qsort.c	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "yportenv.h"
+/* #include <linux/string.h> */
+
+/*
+ * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function".
+ */
+#define swapcode(TYPE, parmi, parmj, n) do { 		\
+	long i = (n) / sizeof (TYPE); 			\
+	register TYPE *pi = (TYPE *) (parmi); 		\
+	register TYPE *pj = (TYPE *) (parmj); 		\
+	do { 						\
+		register TYPE	t = *pi;		\
+		*pi++ = *pj;				\
+		*pj++ = t;				\
+	} while (--i > 0);				\
+} while (0)
+
+#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \
+	es % sizeof(long) ? 2 : es == sizeof(long) ? 0 : 1;
+
+static __inline void
+swapfunc(char *a, char *b, int n, int swaptype)
+{
+	if (swaptype <= 1)
+		swapcode(long, a, b, n);
+	else
+		swapcode(char, a, b, n);
+}
+
+#define yswap(a, b) do {					\
+	if (swaptype == 0) {				\
+		long t = *(long *)(a);			\
+		*(long *)(a) = *(long *)(b);		\
+		*(long *)(b) = t;			\
+	} else						\
+		swapfunc(a, b, es, swaptype);		\
+} while (0)
+
+#define vecswap(a, b, n) 	if ((n) > 0) swapfunc(a, b, n, swaptype)
+
+static __inline char *
+med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *))
+{
+	return cmp(a, b) < 0 ?
+		(cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a))
+		: (cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c));
+}
+
+#ifndef min
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+void
+yaffs_qsort(void *aa, size_t n, size_t es,
+	int (*cmp)(const void *, const void *))
+{
+	char *pa, *pb, *pc, *pd, *pl, *pm, *pn;
+	int d, r, swaptype, swap_cnt;
+	register char *a = aa;
+
+loop:	SWAPINIT(a, es);
+	swap_cnt = 0;
+	if (n < 7) {
+		for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es)
+			for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
+			     pl -= es)
+				yswap(pl, pl - es);
+		return;
+	}
+	pm = (char *)a + (n / 2) * es;
+	if (n > 7) {
+		pl = (char *)a;
+		pn = (char *)a + (n - 1) * es;
+		if (n > 40) {
+			d = (n / 8) * es;
+			pl = med3(pl, pl + d, pl + 2 * d, cmp);
+			pm = med3(pm - d, pm, pm + d, cmp);
+			pn = med3(pn - 2 * d, pn - d, pn, cmp);
+		}
+		pm = med3(pl, pm, pn, cmp);
+	}
+	yswap(a, pm);
+	pa = pb = (char *)a + es;
+
+	pc = pd = (char *)a + (n - 1) * es;
+	for (;;) {
+		while (pb <= pc && (r = cmp(pb, a)) <= 0) {
+			if (r == 0) {
+				swap_cnt = 1;
+				yswap(pa, pb);
+				pa += es;
+			}
+			pb += es;
+		}
+		while (pb <= pc && (r = cmp(pc, a)) >= 0) {
+			if (r == 0) {
+				swap_cnt = 1;
+				yswap(pc, pd);
+				pd -= es;
+			}
+			pc -= es;
+		}
+		if (pb > pc)
+			break;
+		yswap(pb, pc);
+		swap_cnt = 1;
+		pb += es;
+		pc -= es;
+	}
+	if (swap_cnt == 0) {  /* Switch to insertion sort */
+		for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es)
+			for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
+			     pl -= es)
+				yswap(pl, pl - es);
+		return;
+	}
+
+	pn = (char *)a + n * es;
+	r = min(pa - (char *)a, pb - pa);
+	vecswap(a, pb - r, r);
+	r = min((long)(pd - pc), (long)(pn - pd - es));
+	vecswap(pb, pn - r, r);
+	r = pb - pa;
+	if (r > es)
+		yaffs_qsort(a, r / es, es, cmp);
+	r = pd - pc;
+	if (r > es) {
+		/* Iterate rather than recurse to save stack space */
+		a = pn - r;
+		n = r / es;
+		goto loop;
+	}
+/*		yaffs_qsort(pn - r, r / es, es, cmp);*/
+}
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_qsort.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_qsort.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_qsort.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_qsort.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,23 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YAFFS_QSORT_H__
+#define __YAFFS_QSORT_H__
+
+extern void yaffs_qsort(void *const base, size_t total_elems, size_t size,
+			int (*cmp)(const void *, const void *));
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_tagscompat.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagscompat.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_tagscompat.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagscompat.c	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,539 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_guts.h"
+#include "yaffs_tagscompat.h"
+#include "yaffs_ecc.h"
+#include "yaffs_getblockinfo.h"
+#include "yaffs_trace.h"
+
+static void yaffs_HandleReadDataError(yaffs_Device *dev, int chunkInNAND);
+#ifdef NOTYET
+static void yaffs_CheckWrittenBlock(yaffs_Device *dev, int chunkInNAND);
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				     const __u8 *data,
+				     const yaffs_Spare *spare);
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				    const yaffs_Spare *spare);
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND);
+#endif
+
+static const char yaffs_countBitsTable[256] = {
+	0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8
+};
+
+int yaffs_CountBits(__u8 x)
+{
+	int retVal;
+	retVal = yaffs_countBitsTable[x];
+	return retVal;
+}
+
+/********** Tags ECC calculations  *********/
+
+void yaffs_CalcECC(const __u8 *data, yaffs_Spare *spare)
+{
+	yaffs_ECCCalculate(data, spare->ecc1);
+	yaffs_ECCCalculate(&data[256], spare->ecc2);
+}
+
+void yaffs_CalcTagsECC(yaffs_Tags *tags)
+{
+	/* Calculate an ecc */
+
+	unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
+	unsigned i, j;
+	unsigned ecc = 0;
+	unsigned bit = 0;
+
+	tags->ecc = 0;
+
+	for (i = 0; i < 8; i++) {
+		for (j = 1; j & 0xff; j <<= 1) {
+			bit++;
+			if (b[i] & j)
+				ecc ^= bit;
+		}
+	}
+
+	tags->ecc = ecc;
+
+}
+
+int yaffs_CheckECCOnTags(yaffs_Tags *tags)
+{
+	unsigned ecc = tags->ecc;
+
+	yaffs_CalcTagsECC(tags);
+
+	ecc ^= tags->ecc;
+
+	if (ecc && ecc <= 64) {
+		/* TODO: Handle the failure better. Retire? */
+		unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
+
+		ecc--;
+
+		b[ecc / 8] ^= (1 << (ecc & 7));
+
+		/* Now recvalc the ecc */
+		yaffs_CalcTagsECC(tags);
+
+		return 1;	/* recovered error */
+	} else if (ecc) {
+		/* Wierd ecc failure value */
+		/* TODO Need to do somethiong here */
+		return -1;	/* unrecovered error */
+	}
+
+	return 0;
+}
+
+/********** Tags **********/
+
+static void yaffs_LoadTagsIntoSpare(yaffs_Spare *sparePtr,
+				yaffs_Tags *tagsPtr)
+{
+	yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
+
+	yaffs_CalcTagsECC(tagsPtr);
+
+	sparePtr->tagByte0 = tu->asBytes[0];
+	sparePtr->tagByte1 = tu->asBytes[1];
+	sparePtr->tagByte2 = tu->asBytes[2];
+	sparePtr->tagByte3 = tu->asBytes[3];
+	sparePtr->tagByte4 = tu->asBytes[4];
+	sparePtr->tagByte5 = tu->asBytes[5];
+	sparePtr->tagByte6 = tu->asBytes[6];
+	sparePtr->tagByte7 = tu->asBytes[7];
+}
+
+static void yaffs_GetTagsFromSpare(yaffs_Device *dev, yaffs_Spare *sparePtr,
+				yaffs_Tags *tagsPtr)
+{
+	yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
+	int result;
+
+	tu->asBytes[0] = sparePtr->tagByte0;
+	tu->asBytes[1] = sparePtr->tagByte1;
+	tu->asBytes[2] = sparePtr->tagByte2;
+	tu->asBytes[3] = sparePtr->tagByte3;
+	tu->asBytes[4] = sparePtr->tagByte4;
+	tu->asBytes[5] = sparePtr->tagByte5;
+	tu->asBytes[6] = sparePtr->tagByte6;
+	tu->asBytes[7] = sparePtr->tagByte7;
+
+	result = yaffs_CheckECCOnTags(tagsPtr);
+	if (result > 0)
+		dev->tagsEccFixed++;
+	else if (result < 0)
+		dev->tagsEccUnfixed++;
+}
+
+static void yaffs_SpareInitialise(yaffs_Spare *spare)
+{
+	memset(spare, 0xFF, sizeof(yaffs_Spare));
+}
+
+static int yaffs_WriteChunkToNAND(struct yaffs_DeviceStruct *dev,
+				int chunkInNAND, const __u8 *data,
+				yaffs_Spare *spare)
+{
+	if (chunkInNAND < dev->param.startBlock * dev->param.nChunksPerBlock) {
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR("**>> yaffs chunk %d is not valid" TENDSTR),
+		   chunkInNAND));
+		return YAFFS_FAIL;
+	}
+
+	return dev->param.writeChunkToNAND(dev, chunkInNAND, data, spare);
+}
+
+static int yaffs_ReadChunkFromNAND(struct yaffs_DeviceStruct *dev,
+				   int chunkInNAND,
+				   __u8 *data,
+				   yaffs_Spare *spare,
+				   yaffs_ECCResult *eccResult,
+				   int doErrorCorrection)
+{
+	int retVal;
+	yaffs_Spare localSpare;
+
+	if (!spare && data) {
+		/* If we don't have a real spare, then we use a local one. */
+		/* Need this for the calculation of the ecc */
+		spare = &localSpare;
+	}
+
+	if (!dev->param.useNANDECC) {
+		retVal = dev->param.readChunkFromNAND(dev, chunkInNAND, data, spare);
+		if (data && doErrorCorrection) {
+			/* Do ECC correction */
+			/* Todo handle any errors */
+			int eccResult1, eccResult2;
+			__u8 calcEcc[3];
+
+			yaffs_ECCCalculate(data, calcEcc);
+			eccResult1 =
+			    yaffs_ECCCorrect(data, spare->ecc1, calcEcc);
+			yaffs_ECCCalculate(&data[256], calcEcc);
+			eccResult2 =
+			    yaffs_ECCCorrect(&data[256], spare->ecc2, calcEcc);
+
+			if (eccResult1 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error fix performed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+				dev->eccFixed++;
+			} else if (eccResult1 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error unfixed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+				dev->eccUnfixed++;
+			}
+
+			if (eccResult2 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error fix performed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+				dev->eccFixed++;
+			} else if (eccResult2 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error unfixed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+				dev->eccUnfixed++;
+			}
+
+			if (eccResult1 || eccResult2) {
+				/* We had a data problem on this page */
+				yaffs_HandleReadDataError(dev, chunkInNAND);
+			}
+
+			if (eccResult1 < 0 || eccResult2 < 0)
+				*eccResult = YAFFS_ECC_RESULT_UNFIXED;
+			else if (eccResult1 > 0 || eccResult2 > 0)
+				*eccResult = YAFFS_ECC_RESULT_FIXED;
+			else
+				*eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+		}
+	} else {
+		/* Must allocate enough memory for spare+2*sizeof(int) */
+		/* for ecc results from device. */
+		struct yaffs_NANDSpare nspare;
+
+		memset(&nspare, 0, sizeof(nspare));
+
+		retVal = dev->param.readChunkFromNAND(dev, chunkInNAND, data,
+					(yaffs_Spare *) &nspare);
+		memcpy(spare, &nspare, sizeof(yaffs_Spare));
+		if (data && doErrorCorrection) {
+			if (nspare.eccres1 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error fix performed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+			} else if (nspare.eccres1 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error unfixed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+			}
+
+			if (nspare.eccres2 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error fix performed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+			} else if (nspare.eccres2 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error unfixed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+			}
+
+			if (nspare.eccres1 || nspare.eccres2) {
+				/* We had a data problem on this page */
+				yaffs_HandleReadDataError(dev, chunkInNAND);
+			}
+
+			if (nspare.eccres1 < 0 || nspare.eccres2 < 0)
+				*eccResult = YAFFS_ECC_RESULT_UNFIXED;
+			else if (nspare.eccres1 > 0 || nspare.eccres2 > 0)
+				*eccResult = YAFFS_ECC_RESULT_FIXED;
+			else
+				*eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+
+		}
+	}
+	return retVal;
+}
+
+#ifdef NOTYET
+static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
+				  int chunkInNAND)
+{
+	static int init;
+	static __u8 cmpbuf[YAFFS_BYTES_PER_CHUNK];
+	static __u8 data[YAFFS_BYTES_PER_CHUNK];
+	/* Might as well always allocate the larger size for */
+	/* dev->param.useNANDECC == true; */
+	static __u8 spare[sizeof(struct yaffs_NANDSpare)];
+
+	dev->param.readChunkFromNAND(dev, chunkInNAND, data, (yaffs_Spare *) spare);
+
+	if (!init) {
+		memset(cmpbuf, 0xff, YAFFS_BYTES_PER_CHUNK);
+		init = 1;
+	}
+
+	if (memcmp(cmpbuf, data, YAFFS_BYTES_PER_CHUNK))
+		return YAFFS_FAIL;
+	if (memcmp(cmpbuf, spare, 16))
+		return YAFFS_FAIL;
+
+	return YAFFS_OK;
+
+}
+#endif
+
+/*
+ * Functions for robustisizing
+ */
+
+static void yaffs_HandleReadDataError(yaffs_Device *dev, int chunkInNAND)
+{
+	int blockInNAND = chunkInNAND / dev->param.nChunksPerBlock;
+
+	/* Mark the block for retirement */
+	yaffs_GetBlockInfo(dev, blockInNAND + dev->blockOffset)->needsRetiring = 1;
+	T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+	  (TSTR("**>>Block %d marked for retirement" TENDSTR), blockInNAND));
+
+	/* TODO:
+	 * Just do a garbage collection on the affected block
+	 * then retire the block
+	 * NB recursion
+	 */
+}
+
+#ifdef NOTYET
+static void yaffs_CheckWrittenBlock(yaffs_Device *dev, int chunkInNAND)
+{
+}
+
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				     const __u8 *data,
+				     const yaffs_Spare *spare)
+{
+}
+
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				    const yaffs_Spare *spare)
+{
+}
+
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND)
+{
+	int blockInNAND = chunkInNAND / dev->param.nChunksPerBlock;
+
+	/* Mark the block for retirement */
+	yaffs_GetBlockInfo(dev, blockInNAND)->needsRetiring = 1;
+	/* Delete the chunk */
+	yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+}
+
+static int yaffs_VerifyCompare(const __u8 *d0, const __u8 *d1,
+			       const yaffs_Spare *s0, const yaffs_Spare *s1)
+{
+
+	if (memcmp(d0, d1, YAFFS_BYTES_PER_CHUNK) != 0 ||
+	    s0->tagByte0 != s1->tagByte0 ||
+	    s0->tagByte1 != s1->tagByte1 ||
+	    s0->tagByte2 != s1->tagByte2 ||
+	    s0->tagByte3 != s1->tagByte3 ||
+	    s0->tagByte4 != s1->tagByte4 ||
+	    s0->tagByte5 != s1->tagByte5 ||
+	    s0->tagByte6 != s1->tagByte6 ||
+	    s0->tagByte7 != s1->tagByte7 ||
+	    s0->ecc1[0] != s1->ecc1[0] ||
+	    s0->ecc1[1] != s1->ecc1[1] ||
+	    s0->ecc1[2] != s1->ecc1[2] ||
+	    s0->ecc2[0] != s1->ecc2[0] ||
+	    s0->ecc2[1] != s1->ecc2[1] || s0->ecc2[2] != s1->ecc2[2]) {
+		return 0;
+	}
+
+	return 1;
+}
+#endif				/* NOTYET */
+
+int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						const __u8 *data,
+						const yaffs_ExtendedTags *eTags)
+{
+	yaffs_Spare spare;
+	yaffs_Tags tags;
+
+	yaffs_SpareInitialise(&spare);
+
+	if (eTags->chunkDeleted)
+		spare.pageStatus = 0;
+	else {
+		tags.objectId = eTags->objectId;
+		tags.chunkId = eTags->chunkId;
+
+		tags.byteCountLSB = eTags->byteCount & 0x3ff;
+
+		if (dev->nDataBytesPerChunk >= 1024)
+			tags.byteCountMSB = (eTags->byteCount >> 10) & 3;
+		else
+			tags.byteCountMSB = 3;
+
+
+		tags.serialNumber = eTags->serialNumber;
+
+		if (!dev->param.useNANDECC && data)
+			yaffs_CalcECC(data, &spare);
+
+		yaffs_LoadTagsIntoSpare(&spare, &tags);
+
+	}
+
+	return yaffs_WriteChunkToNAND(dev, chunkInNAND, data, &spare);
+}
+
+int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device *dev,
+						     int chunkInNAND,
+						     __u8 *data,
+						     yaffs_ExtendedTags *eTags)
+{
+
+	yaffs_Spare spare;
+	yaffs_Tags tags;
+	yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_UNKNOWN;
+
+	static yaffs_Spare spareFF;
+	static int init;
+
+	if (!init) {
+		memset(&spareFF, 0xFF, sizeof(spareFF));
+		init = 1;
+	}
+
+	if (yaffs_ReadChunkFromNAND
+	    (dev, chunkInNAND, data, &spare, &eccResult, 1)) {
+		/* eTags may be NULL */
+		if (eTags) {
+
+			int deleted =
+			    (yaffs_CountBits(spare.pageStatus) < 7) ? 1 : 0;
+
+			eTags->chunkDeleted = deleted;
+			eTags->eccResult = eccResult;
+			eTags->blockBad = 0;	/* We're reading it */
+			/* therefore it is not a bad block */
+			eTags->chunkUsed =
+			    (memcmp(&spareFF, &spare, sizeof(spareFF)) !=
+			     0) ? 1 : 0;
+
+			if (eTags->chunkUsed) {
+				yaffs_GetTagsFromSpare(dev, &spare, &tags);
+
+				eTags->objectId = tags.objectId;
+				eTags->chunkId = tags.chunkId;
+				eTags->byteCount = tags.byteCountLSB;
+
+				if (dev->nDataBytesPerChunk >= 1024)
+					eTags->byteCount |= (((unsigned) tags.byteCountMSB) << 10);
+
+				eTags->serialNumber = tags.serialNumber;
+			}
+		}
+
+		return YAFFS_OK;
+	} else {
+		return YAFFS_FAIL;
+	}
+}
+
+int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
+					    int blockInNAND)
+{
+
+	yaffs_Spare spare;
+
+	memset(&spare, 0xff, sizeof(yaffs_Spare));
+
+	spare.blockStatus = 'Y';
+
+	yaffs_WriteChunkToNAND(dev, blockInNAND * dev->param.nChunksPerBlock, NULL,
+			       &spare);
+	yaffs_WriteChunkToNAND(dev, blockInNAND * dev->param.nChunksPerBlock + 1,
+			       NULL, &spare);
+
+	return YAFFS_OK;
+
+}
+
+int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
+					  int blockNo,
+					  yaffs_BlockState *state,
+					  __u32 *sequenceNumber)
+{
+
+	yaffs_Spare spare0, spare1;
+	static yaffs_Spare spareFF;
+	static int init;
+	yaffs_ECCResult dummy;
+
+	if (!init) {
+		memset(&spareFF, 0xFF, sizeof(spareFF));
+		init = 1;
+	}
+
+	*sequenceNumber = 0;
+
+	yaffs_ReadChunkFromNAND(dev, blockNo * dev->param.nChunksPerBlock, NULL,
+				&spare0, &dummy, 1);
+	yaffs_ReadChunkFromNAND(dev, blockNo * dev->param.nChunksPerBlock + 1, NULL,
+				&spare1, &dummy, 1);
+
+	if (yaffs_CountBits(spare0.blockStatus & spare1.blockStatus) < 7)
+		*state = YAFFS_BLOCK_STATE_DEAD;
+	else if (memcmp(&spareFF, &spare0, sizeof(spareFF)) == 0)
+		*state = YAFFS_BLOCK_STATE_EMPTY;
+	else
+		*state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+
+	return YAFFS_OK;
+}
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_tagscompat.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagscompat.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_tagscompat.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagscompat.h	2011-05-08 18:01:08.000000000 +0800
@@ -0,0 +1,39 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_TAGSCOMPAT_H__
+#define __YAFFS_TAGSCOMPAT_H__
+
+#include "yaffs_guts.h"
+int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						const __u8 *data,
+						const yaffs_ExtendedTags *tags);
+int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						__u8 *data,
+						yaffs_ExtendedTags *tags);
+int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
+					    int blockNo);
+int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
+					  int blockNo,
+					  yaffs_BlockState *state,
+					  __u32 *sequenceNumber);
+
+void yaffs_CalcTagsECC(yaffs_Tags *tags);
+int yaffs_CheckECCOnTags(yaffs_Tags *tags);
+int yaffs_CountBits(__u8 byte);
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_tagsvalidity.c linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagsvalidity.c
--- linux-2.6.27.6/fs/yaffs2/yaffs_tagsvalidity.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagsvalidity.c	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,28 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_tagsvalidity.h"
+
+void yaffs_InitialiseTags(yaffs_ExtendedTags *tags)
+{
+	memset(tags, 0, sizeof(yaffs_ExtendedTags));
+	tags->validMarker0 = 0xAAAAAAAA;
+	tags->validMarker1 = 0x55555555;
+}
+
+int yaffs_ValidateTags(yaffs_ExtendedTags *tags)
+{
+	return (tags->validMarker0 == 0xAAAAAAAA &&
+		tags->validMarker1 == 0x55555555);
+
+}
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_tagsvalidity.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagsvalidity.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_tagsvalidity.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_tagsvalidity.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,24 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YAFFS_TAGS_VALIDITY_H__
+#define __YAFFS_TAGS_VALIDITY_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_InitialiseTags(yaffs_ExtendedTags *tags);
+int yaffs_ValidateTags(yaffs_ExtendedTags *tags);
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yaffs_trace.h linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_trace.h
--- linux-2.6.27.6/fs/yaffs2/yaffs_trace.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yaffs_trace.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,60 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YTRACE_H__
+#define __YTRACE_H__
+
+extern unsigned int yaffs_traceMask;
+extern unsigned int yaffs_wr_attempts;
+
+/*
+ * Tracing flags.
+ * The flags masked in YAFFS_TRACE_ALWAYS are always traced.
+ */
+
+#define YAFFS_TRACE_OS			0x00000002
+#define YAFFS_TRACE_ALLOCATE		0x00000004
+#define YAFFS_TRACE_SCAN		0x00000008
+#define YAFFS_TRACE_BAD_BLOCKS		0x00000010
+#define YAFFS_TRACE_ERASE		0x00000020
+#define YAFFS_TRACE_GC			0x00000040
+#define YAFFS_TRACE_WRITE		0x00000080
+#define YAFFS_TRACE_TRACING		0x00000100
+#define YAFFS_TRACE_DELETION		0x00000200
+#define YAFFS_TRACE_BUFFERS		0x00000400
+#define YAFFS_TRACE_NANDACCESS		0x00000800
+#define YAFFS_TRACE_GC_DETAIL		0x00001000
+#define YAFFS_TRACE_SCAN_DEBUG		0x00002000
+#define YAFFS_TRACE_MTD			0x00004000
+#define YAFFS_TRACE_CHECKPOINT		0x00008000
+
+#define YAFFS_TRACE_VERIFY		0x00010000
+#define YAFFS_TRACE_VERIFY_NAND		0x00020000
+#define YAFFS_TRACE_VERIFY_FULL		0x00040000
+#define YAFFS_TRACE_VERIFY_ALL		0x000F0000
+
+#define YAFFS_TRACE_SYNC		0x00100000
+
+#define YAFFS_TRACE_BACKGROUND		0x00200000
+
+#define YAFFS_TRACE_ERROR		0x40000000
+#define YAFFS_TRACE_BUG			0x80000000
+#define YAFFS_TRACE_ALWAYS		0xF0000000
+
+
+#define T(mask, p) do { if ((mask) & (yaffs_traceMask | YAFFS_TRACE_ALWAYS)) TOUT(p); } while (0)
+
+#endif
diff -uNra linux-2.6.27.6/fs/yaffs2/yportenv.h linux-2.6.27.6.yaffs/fs/yaffs2/yportenv.h
--- linux-2.6.27.6/fs/yaffs2/yportenv.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/fs/yaffs2/yportenv.h	2011-05-08 18:01:07.000000000 +0800
@@ -0,0 +1,166 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YPORTENV_H__
+#define __YPORTENV_H__
+
+/*
+ * Define the MTD version in terms of Linux Kernel versions
+ * This allows yaffs to be used independantly of the kernel
+ * as well as with it.
+ */
+
+#define MTD_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c))
+
+#if defined CONFIG_YAFFS_WINCE
+
+#include "ywinceenv.h"
+
+#elif defined __KERNEL__
+
+#include "moduleconfig.h"
+
+/* Linux kernel */
+
+#include <linux/version.h>
+#define MTD_VERSION_CODE LINUX_VERSION_CODE
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+#include <linux/config.h>
+#endif
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#define YCHAR char
+#define YUCHAR unsigned char
+#define _Y(x)     x
+#define yaffs_strcat(a, b)     strcat(a, b)
+#define yaffs_strcpy(a, b)     strcpy(a, b)
+#define yaffs_strncpy(a, b, c) strncpy(a, b, c)
+#define yaffs_strncmp(a, b, c) strncmp(a, b, c)
+#define yaffs_strnlen(s,m)	strnlen(s,m)
+#define yaffs_sprintf	       sprintf
+#define yaffs_toupper(a)       toupper(a)
+
+#define Y_INLINE inline
+
+#define YAFFS_LOSTNFOUND_NAME		"lost+found"
+#define YAFFS_LOSTNFOUND_PREFIX		"obj"
+
+/* #define YPRINTF(x) printk x */
+#define YMALLOC(x) kmalloc(x, GFP_NOFS)
+#define YFREE(x)   kfree(x)
+#define YMALLOC_ALT(x) vmalloc(x)
+#define YFREE_ALT(x)   vfree(x)
+#define YMALLOC_DMA(x) YMALLOC(x)
+
+/* KR - added for use in scan so processes aren't blocked indefinitely. */
+#define YYIELD() schedule()
+
+#define YAFFS_ROOT_MODE			0755
+#define YAFFS_LOSTNFOUND_MODE		0700
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+#define Y_CURRENT_TIME CURRENT_TIME.tv_sec
+#define Y_TIME_CONVERT(x) (x).tv_sec
+#else
+#define Y_CURRENT_TIME CURRENT_TIME
+#define Y_TIME_CONVERT(x) (x)
+#endif
+
+#define yaffs_SumCompare(x, y) ((x) == (y))
+#define yaffs_strcmp(a, b) strcmp(a, b)
+
+#define TENDSTR "\n"
+#define TSTR(x) KERN_WARNING x
+#define TCONT(x) x
+#define TOUT(p) printk p
+
+#define yaffs_trace(mask, fmt, args...) \
+	do { if ((mask) & (yaffs_traceMask| YAFFS_TRACE_ALWAYS)) \
+		printk(KERN_WARNING "yaffs: " fmt, ## args); \
+	} while (0)
+
+#define compile_time_assertion(assertion) \
+	({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; })
+
+#elif defined CONFIG_YAFFS_DIRECT
+
+#define MTD_VERSION_CODE MTD_VERSION(2, 6, 22)
+
+/* Direct interface */
+#include "ydirectenv.h"
+
+#elif defined CONFIG_YAFFS_UTIL
+
+/* Stuff for YAFFS utilities */
+
+#include "stdlib.h"
+#include "stdio.h"
+#include "string.h"
+
+#include "devextras.h"
+
+#define YMALLOC(x) malloc(x)
+#define YFREE(x)   free(x)
+#define YMALLOC_ALT(x) malloc(x)
+#define YFREE_ALT(x) free(x)
+
+#define YCHAR char
+#define YUCHAR unsigned char
+#define _Y(x)     x
+#define yaffs_strcat(a, b)     strcat(a, b)
+#define yaffs_strcpy(a, b)     strcpy(a, b)
+#define yaffs_strncpy(a, b, c) strncpy(a, b, c)
+#define yaffs_strnlen(s,m)	       strnlen(s,m)
+#define yaffs_sprintf	       sprintf
+#define yaffs_toupper(a)       toupper(a)
+
+#define Y_INLINE inline
+
+/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */
+/* #define YALERT(s) YINFO(s) */
+
+#define TENDSTR "\n"
+#define TSTR(x) x
+#define TOUT(p) printf p
+
+#define YAFFS_LOSTNFOUND_NAME		"lost+found"
+#define YAFFS_LOSTNFOUND_PREFIX		"obj"
+/* #define YPRINTF(x) printf x */
+
+#define YAFFS_ROOT_MODE			0755
+#define YAFFS_LOSTNFOUND_MODE		0700
+
+#define yaffs_SumCompare(x, y) ((x) == (y))
+#define yaffs_strcmp(a, b) strcmp(a, b)
+
+#else
+/* Should have specified a configuration type */
+#error Unknown configuration
+
+#endif
+
+
+#ifndef YBUG
+#define YBUG() do {T(YAFFS_TRACE_BUG, (TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR), __LINE__)); } while (0)
+#endif
+
+#endif
diff -uNra linux-2.6.27.6/g linux-2.6.27.6.yaffs/g
--- linux-2.6.27.6/g	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/g	2011-05-08 18:01:36.000000000 +0800
@@ -0,0 +1,3 @@
+#make modules_install INSTALL_MOD_PATH=./lib_modules/ ARCH=mips CROSS_COMPILE=/home/liuqi/toolchain/gcc-cross-4.4/install/bin/mips64el-linux- -j 8
+#cp -avf vmlinux.32 /srv/tftp/2fspc
+make ARCH=mips  CROSS_COMPILE=/home/liuqi/toolchain/gcc-cross-4.4/install/bin/mips64el-linux- -j 8
diff -uNra linux-2.6.27.6/.gitignore linux-2.6.27.6.yaffs/.gitignore
--- linux-2.6.27.6/.gitignore	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/.gitignore	1970-01-01 08:00:00.000000000 +0800
@@ -1,66 +0,0 @@
-#
-# NOTE! Don't add files that are generated in specific
-# subdirectories here. Add them in the ".gitignore" file
-# in that subdirectory instead.
-#
-# NOTE! Please use 'git-ls-files -i --exclude-standard'
-# command after changing this file, to see if there are
-# any tracked files which get ignored after the change.
-#
-# Normal rules
-#
-.*
-*.o
-*.o.*
-*.a
-*.s
-*.ko
-*.so
-*.so.dbg
-*.mod.c
-*.i
-*.lst
-*.symtypes
-*.order
-*.elf
-*.bin
-*.gz
-
-#
-# Top-level generic files
-#
-tags
-TAGS
-vmlinux
-System.map
-Module.markers
-Module.symvers
-!.gitignore
-!.mailmap
-
-#
-# Generated include files
-#
-include/asm
-include/asm-*/asm-offsets.h
-include/config
-include/linux/autoconf.h
-include/linux/compile.h
-include/linux/version.h
-include/linux/utsrelease.h
-include/linux/bounds.h
-
-# stgit generated dirs
-patches-*
-
-# quilt's files
-patches
-series
-
-# cscope files
-cscope.*
-ncscope.*
-
-*.orig
-*~
-\#*#
diff -uNra linux-2.6.27.6/include/asm-cris/rtc.h linux-2.6.27.6.yaffs/include/asm-cris/rtc.h
--- linux-2.6.27.6/include/asm-cris/rtc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-cris/rtc.h	2011-05-08 18:02:35.000000000 +0800
@@ -7,9 +7,9 @@
 #  define RTC_SECONDS      0
 #  define RTC_MINUTES      1
 #  define RTC_HOURS        2
-#  define RTC_DAY_OF_MONTH 3
-#  define RTC_MONTH        4
-#  define RTC_WEEKDAY      5
+#  define RTC_DAY_OF_MONTH 4
+#  define RTC_MONTH       5 
+#  define RTC_WEEKDAY      3
 #  define RTC_YEAR         6
 #  define RTC_CONTROL      7
 
diff -uNra linux-2.6.27.6/include/asm-mips/delay.h linux-2.6.27.6.yaffs/include/asm-mips/delay.h
--- linux-2.6.27.6/include/asm-mips/delay.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/delay.h	2011-05-08 18:02:30.000000000 +0800
@@ -82,12 +82,14 @@
 		: "=h" (usecs), "=l" (lo)
 		: "r" (usecs), "r" (lpj)
 		: GCC_REG_ACCUM);
-	else if (sizeof(long) == 8 && !R4000_WAR)
-		__asm__("dmultu\t%2, %3"
-		: "=h" (usecs), "=l" (lo)
-		: "r" (usecs), "r" (lpj)
-		: GCC_REG_ACCUM);
-	else if (sizeof(long) == 8 && R4000_WAR)
+	else if (sizeof(long) == 8 && !R4000_WAR){
+		//__asm__("dmultu\t%2, %3"
+		//: "=h" (usecs), "=l" (lo)
+		//: "r" (usecs), "r" (lpj)
+		//: GCC_REG_ACCUM);
+		typedef unsigned int uint128_t __attribute__((mode(TI)));
+		usecs = ((uint128_t) usecs * lpj) >> 64;
+	}else if (sizeof(long) == 8 && R4000_WAR)
 		__asm__("dmultu\t%3, %4\n\tmfhi\t%0"
 		: "=r" (usecs), "=h" (hi), "=l" (lo)
 		: "r" (usecs), "r" (lpj)
diff -uNra linux-2.6.27.6/include/asm-mips/i8259.h linux-2.6.27.6.yaffs/include/asm-mips/i8259.h
--- linux-2.6.27.6/include/asm-mips/i8259.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/i8259.h	2011-05-08 18:02:30.000000000 +0800
@@ -55,7 +55,10 @@
 
 	/* Perform an interrupt acknowledge cycle on controller 1. */
 	outb(0x0C, PIC_MASTER_CMD);		/* prepare for poll */
-	irq = inb(PIC_MASTER_CMD) & 7;
+	__asm__(".set noreorder; sb $0, 0x80(%0);.set reorder"::"r"(mips_io_port_base):"memory");
+	irq = inb(PIC_MASTER_CMD); 
+	printk("i8259_irq %x\n", irq);
+	irq = irq & 0x07;
 	if (irq == PIC_CASCADE_IR) {
 		/*
 		 * Interrupt is cascaded so perform interrupt
diff -uNra linux-2.6.27.6/include/asm-mips/mach-generic/mc146818rtc.h linux-2.6.27.6.yaffs/include/asm-mips/mach-generic/mc146818rtc.h
--- linux-2.6.27.6/include/asm-mips/mach-generic/mc146818rtc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/mach-generic/mc146818rtc.h	2011-05-08 18:02:30.000000000 +0800
@@ -14,7 +14,46 @@
 
 #define RTC_PORT(x)	(0x70 + (x))
 #define RTC_IRQ		8
+#if 1
+#define I2C_SINGLE 0
+dsfasdfasd
+static inline unsigned char CMOS_READ(unsigned char addr)
+{
+    unsigned char val;
+    unsigned char tmp1,tmp2;
+	volatile int tmp;
+	unsigned char value;
+	char i2caddr[] = {(unsigned char)0xd0};
+	if(addr >= 0x0a)
+		return 0;
+	value = value | 0x20;
+	tgt_i2cread(I2C_SINGLE,i2caddr,1,addr,&val,1);
+	tmp1 = ((val >> 4) & 0x0f)*10;
+	tmp2  = val & 0x0f;
+	val = tmp1 + tmp2;
+    return val;
+}
 
+static inline void CMOS_WRITE(unsigned char val, unsigned char addr)
+{
+	char a;
+  	unsigned char tmp1,tmp2;
+	volatile int tmp;
+	char i2caddr[] = {(unsigned char)0xd0};
+	tmp1 = (val / 10) << 4;
+	tmp2  = (val % 10);
+	val = tmp1 | tmp2;
+	if(addr >= 0x0a)
+		return 0;
+	{
+		unsigned char value;
+		value = value | 0x20;
+		tgt_i2cwrite( I2C_SINGLE,i2caddr,1,addr,&val,1);
+	}
+}
+
+
+#else
 static inline unsigned char CMOS_READ(unsigned long addr)
 {
 	outb_p(addr, RTC_PORT(0));
@@ -26,7 +65,7 @@
 	outb_p(addr, RTC_PORT(0));
 	outb_p(data, RTC_PORT(1));
 }
-
+#endif
 #define RTC_ALWAYS_BCD	1
 
 #ifndef mc146818_decode_year
diff -uNra linux-2.6.27.6/include/asm-mips/mach-lemote/dma-coherence.h linux-2.6.27.6.yaffs/include/asm-mips/mach-lemote/dma-coherence.h
--- linux-2.6.27.6/include/asm-mips/mach-lemote/dma-coherence.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/mach-lemote/dma-coherence.h	2011-05-08 18:02:30.000000000 +0800
@@ -27,7 +27,18 @@
 
 static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 {
+#ifdef CONFIG_64BIT
+#ifdef CONFIG_LEMOTE_FULONG2F
+	if(dma_addr > 0x8fffffff)
+		return dma_addr;
+	else
+		return dma_addr & 0x0fffffff;
+#else
 	return dma_addr & 0x7fffffff;
+#endif
+#else
+	return dma_addr & 0x7fffffff;
+#endif
 }
 
 static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
diff -uNra linux-2.6.27.6/include/asm-mips/mach-lemote/mc146818rtc.h linux-2.6.27.6.yaffs/include/asm-mips/mach-lemote/mc146818rtc.h
--- linux-2.6.27.6/include/asm-mips/mach-lemote/mc146818rtc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/mach-lemote/mc146818rtc.h	2011-05-08 18:02:30.000000000 +0800
@@ -14,7 +14,46 @@
 
 #define RTC_PORT(x)	(0x70 + (x))
 #define RTC_IRQ		8
+#if 1
+#define I2C_SINGLE 0
+int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count);
+int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count);
+static inline unsigned char CMOS_READ(unsigned char addr)
+{
+    unsigned char val;
+    unsigned char tmp1,tmp2;
+	volatile int tmp;
+	unsigned char value;
+	char i2caddr[] = {(unsigned char)0xd0};
+	if(addr >= 0x0a)
+		return 0;
+	value = value | 0x20;
+	tgt_i2cread(I2C_SINGLE,i2caddr,1,addr,&val,1);
+	tmp1 = ((val >> 4) & 0x0f)*10;
+	tmp2  = val & 0x0f;
+	val = tmp1 + tmp2;
+    return val;
+}
+
+static inline void CMOS_WRITE(unsigned char val, unsigned char addr)
+{
+	char a;
+  	unsigned char tmp1,tmp2;
+	volatile int tmp;
+	char i2caddr[] = {(unsigned char)0xd0};
+	tmp1 = (val / 10) << 4;
+	tmp2  = (val % 10);
+	val = tmp1 | tmp2;
+	if(addr >= 0x0a)
+		return 0;
+	{
+		unsigned char value;
+		value = value | 0x20;
+		tgt_i2cwrite(I2C_SINGLE,i2caddr,1,addr,&val,1);
+	}
+}
 
+#else
 static inline unsigned char CMOS_READ(unsigned long addr)
 {
 	outb_p(addr, RTC_PORT(0));
@@ -26,7 +65,7 @@
 	outb_p(addr, RTC_PORT(0));
 	outb_p(data, RTC_PORT(1));
 }
-
+#endif
 #define RTC_ALWAYS_BCD	0
 
 #ifndef mc146818_decode_year
diff -uNra linux-2.6.27.6/include/asm-mips/mc146818rtc.h linux-2.6.27.6.yaffs/include/asm-mips/mc146818rtc.h
--- linux-2.6.27.6/include/asm-mips/mc146818rtc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/mc146818rtc.h	2011-05-08 18:02:30.000000000 +0800
@@ -12,5 +12,11 @@
 #define _ASM_MC146818RTC_H
 
 #include <mc146818rtc.h>
+#define lock_cmos_prefix(reg) do {} while (0)
+#define lock_cmos_suffix(reg) do {} while (0)
+#define lock_cmos(reg)
+#define unlock_cmos()
+#define do_i_have_lock_cmos() 0
+#define current_lock_cmos_reg() 0
 
 #endif /* _ASM_MC146818RTC_H */
diff -uNra linux-2.6.27.6/include/asm-mips/mc146818-time.h linux-2.6.27.6.yaffs/include/asm-mips/mc146818-time.h
--- linux-2.6.27.6/include/asm-mips/mc146818-time.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/mc146818-time.h	2011-05-08 18:02:30.000000000 +0800
@@ -85,7 +85,7 @@
 
 	return retval;
 }
-
+void prom_printf(char *fmt, ...);
 static inline unsigned long mc146818_get_cmos_time(void)
 {
 	unsigned int year, mon, day, hour, min, sec;
@@ -93,6 +93,7 @@
 
 	spin_lock_irqsave(&rtc_lock, flags);
 
+//	prom_printf("sec %d, min %d,hour %d,day %d,mon %d, year %d\n",RTC_SECONDS,RTC_MINUTES,RTC_HOURS,RTC_DAY_OF_MONTH,RTC_MONTH,RTC_YEAR);
 	do {
 		sec = CMOS_READ(RTC_SECONDS);
 		min = CMOS_READ(RTC_MINUTES);
@@ -101,7 +102,9 @@
 		mon = CMOS_READ(RTC_MONTH);
 		year = CMOS_READ(RTC_YEAR);
 	} while (sec != CMOS_READ(RTC_SECONDS));
-
+//	prom_printf("sec %d, min %d,hour %d,day %d,mon %d, year %d\n",sec,min,hour,day,mon,year);
+//	prom_printf("sec %d, min %d,hour %d,day %d,mon %d, year %d\n",RTC_SECONDS,RTC_MINUTES,RTC_HOURS,RTC_DAY_OF_MONTH,RTC_MONTH,RTC_YEAR);
+#if 0
 	if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 		BCD_TO_BIN(sec);
 		BCD_TO_BIN(min);
@@ -110,6 +113,7 @@
 		BCD_TO_BIN(mon);
 		BCD_TO_BIN(year);
 	}
+#endif
 	spin_unlock_irqrestore(&rtc_lock, flags);
 	year = mc146818_decode_year(year);
 
diff -uNra linux-2.6.27.6/include/asm-mips/mips-boards/bonito64.h linux-2.6.27.6.yaffs/include/asm-mips/mips-boards/bonito64.h
--- linux-2.6.27.6/include/asm-mips/mips-boards/bonito64.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/mips-boards/bonito64.h	2011-05-08 18:02:29.000000000 +0800
@@ -26,7 +26,7 @@
 /* offsets from base register */
 #define BONITO(x)	(x)
 
-#elif defined(CONFIG_LEMOTE_FULONG)
+#elif defined(CONFIG_LEMOTE_FULONG) ||defined(CONFIG_LEMOTE_FULONG2F)
 
 #define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
 #define BONITO_IRQ_BASE   32
@@ -43,6 +43,7 @@
 
 #endif /* __ASSEMBLY__ */
 
+#define Bonito static char * const _bonito = (char * const )CKSEG1ADDR(BONITO_REG_BASE)
 
 #define BONITO_BOOT_BASE		0x1fc00000
 #define BONITO_BOOT_SIZE		0x00100000
diff -uNra linux-2.6.27.6/include/asm-mips/pci.h linux-2.6.27.6.yaffs/include/asm-mips/pci.h
--- linux-2.6.27.6/include/asm-mips/pci.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/pci.h	2011-05-08 18:02:30.000000000 +0800
@@ -56,7 +56,7 @@
 /*
  * board supplied pci irq fixup routine
  */
-extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
 
 
 /* Can be used to override the logic in pci_scan_bus for skipping
diff -uNra linux-2.6.27.6/include/asm-mips/serial.h linux-2.6.27.6.yaffs/include/asm-mips/serial.h
--- linux-2.6.27.6/include/asm-mips/serial.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/serial.h	2011-05-08 18:02:29.000000000 +0800
@@ -19,4 +19,28 @@
  */
 #define BASE_BAUD (1843200 / 16)
 
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
+#define STD_SERIAL_PORT_DEFNS                   \
+        /* UART CLK   PORT IRQ     FLAGS        */                      \
+        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
+        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
+        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
+        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
+
+#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
+#define STD_SERIAL_PORT_DEFNS
+#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
+
+#define SERIAL_PORT_DFNS                                \
+        STD_SERIAL_PORT_DEFNS  
+
 #endif /* _ASM_SERIAL_H */
diff -uNra linux-2.6.27.6/include/asm-mips/stackframe.h linux-2.6.27.6.yaffs/include/asm-mips/stackframe.h
--- linux-2.6.27.6/include/asm-mips/stackframe.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/stackframe.h	2011-05-08 18:02:30.000000000 +0800
@@ -117,6 +117,24 @@
 		.endm
 #else
 		.macro	get_saved_sp	/* Uniprocessor variation */
+#ifdef CONFIG_CPU_LOONGSON2
+		move k0,ra
+		jal 2008f
+		nop
+		2008:
+		jal 2008f
+		nop
+		2008:
+		jal 2008f
+		nop
+		2008:
+		jal 2008f
+		nop
+		2008:
+		move ra,k0
+		li k0,3
+		mtc0 k0,$22
+#endif
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
 		lui	k1, %hi(kernelsp)
 #else
diff -uNra linux-2.6.27.6/include/asm-mips/time.h linux-2.6.27.6.yaffs/include/asm-mips/time.h
--- linux-2.6.27.6/include/asm-mips/time.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/time.h	2011-05-08 18:02:29.000000000 +0800
@@ -76,4 +76,8 @@
 extern void clockevent_set_clock(struct clock_event_device *cd,
 		unsigned int clock);
 
+#define get_wallclock() mach_get_cmos_time()
+#define set_wallclock(x) mach_set_rtc_mmss(x)
+
+
 #endif /* _ASM_TIME_H */
diff -uNra linux-2.6.27.6/include/asm-mips/vga.h linux-2.6.27.6.yaffs/include/asm-mips/vga.h
--- linux-2.6.27.6/include/asm-mips/vga.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/asm-mips/vga.h	2011-05-08 18:02:30.000000000 +0800
@@ -13,7 +13,7 @@
  *	access the videoram directly without any black magic.
  */
 
-#define VGA_MAP_MEM(x, s)	(0xb0000000L + (unsigned long)(x))
+#define VGA_MAP_MEM(x, s)	(0xffffffffb0000000L + (unsigned long)(x))
 
 #define vga_readb(x)	(*(x))
 #define vga_writeb(x, y)	(*(y) = (x))
diff -uNra linux-2.6.27.6/include/config/auto.conf linux-2.6.27.6.yaffs/include/config/auto.conf
--- linux-2.6.27.6/include/config/auto.conf	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/config/auto.conf	2012-03-14 10:55:20.000000000 +0800
@@ -0,0 +1,792 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.6
+# Wed Mar 14 10:55:20 2012
+#
+CONFIG_USB_PHIDGETMOTORCONTROL=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_SCSI_ACARD_ATP8620=y
+CONFIG_OSF_PARTITION=y
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_FRAME_WARN=2048
+CONFIG_BLK_DEV_HD=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_COMPAT_BRK=y
+CONFIG_JFFS2_CMODE_PRIORITY=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_NF_CT_ACCT=y
+CONFIG_TCP_CONG_VENO=y
+CONFIG_CARDBUS=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_USER_SCHED=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_FLATMEM=y
+CONFIG_PROC_KCORE=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_USB_RTL8150=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_TIMERFD=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_EVENTFD=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_USB_KAWETH=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_HAS_DMA=y
+CONFIG_RAID_ATTRS=m
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_SUN_PARTITION=y
+CONFIG_CODA_FS=m
+CONFIG_NFS_COMMON=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_SND_SM501_SOC_AC97=y
+CONFIG_HW_CONSOLE=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_ATA_SFF=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_USB_NET_PLUSB=m
+CONFIG_NF_NAT_H323=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_MTD_CFI=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_BLK_DEV=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_HAS_IOPORT=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_INET_AH=m
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_CRYPTO_AES=y
+CONFIG_MODULES=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_USBNET=m
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+CONFIG_EXT2_FS=y
+CONFIG_INPUT_MISC=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CPU_HAS_WB=y
+CONFIG_I8253=y
+CONFIG_EXT3_FS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_FB_SM501=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_PREEMPT=y
+CONFIG_UIO_CIF=y
+CONFIG_USB_HID=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_SND_SM501_SOC_AC97_DEVICE=y
+CONFIG_SND_PCI=y
+CONFIG_ICPLUS_PHY=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_RFD_FTL=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_I8259=y
+CONFIG_NET_PCI=y
+CONFIG_SUSPEND=y
+CONFIG_SLAB=y
+CONFIG_INOTIFY=y
+CONFIG_CGROUPS=y
+CONFIG_HOTPLUG=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_SND_PCM=y
+CONFIG_DEVPORT=y
+CONFIG_MTD_RAM=y
+CONFIG_CIFS=m
+CONFIG_WAN_ROUTER=m
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_VFAT_FS=y
+CONFIG_SND_SOC=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_R8169=y
+CONFIG_EMBEDDED=y
+CONFIG_UDF_NLS=y
+CONFIG_FUSE_FS=y
+CONFIG_KMOD=y
+CONFIG_GENERIC_ACL=y
+CONFIG_PROC_FS=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_RT_MUTEXES=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_LOGO=y
+CONFIG_SYSVIPC=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_SCSI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_IP_SCTP=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NTFS_FS=y
+CONFIG_USB_MON=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_IRQ_CPU=y
+CONFIG_NFTL=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_USB_PHIDGETKIT=y
+CONFIG_VIDEO_MEDIA=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_MIPS=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_SWAP=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_NFTL_RW=y
+CONFIG_KEYS=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_AC97_BUS=y
+CONFIG_XFRM=y
+CONFIG_CRC32=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_CRYPTO_XTS=y
+CONFIG_USB_NET_NET1080=m
+CONFIG_CRC16=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_TCP_CONG_VEGAS=y
+CONFIG_PACKET_MMAP=y
+CONFIG_NTFS_RW=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_UIO_SMX=y
+CONFIG_USB_NET_MCS7830=m
+CONFIG_UNIX=y
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_HAMRADIO=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_SERIAL_CORE=y
+CONFIG_LXT_PHY=m
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_BLK_DEV_IDE=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_SIGNALFD=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_64BIT=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_SCSI_WAIT_SCAN=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_IKCONFIG=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_FIB_HASH=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_ANON_INODES=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_USB_PHIDGET=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_SLABINFO=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_VGA_CONSOLE=y
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_JFFS2_FS=y
+CONFIG_DAVICOM_PHY=m
+CONFIG_GROUP_SCHED=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_HAVE_IDE=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_LIBCRC32C=y
+CONFIG_INET_IPCOMP=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_REALTEK_PHY=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_BLK_DEV_SX8=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_MODVERSIONS=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_REISERFS_FS=y
+CONFIG_BINFMT_ELF32=y
+CONFIG_CSRC_R4K=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_IDE_PROC_FS=y
+CONFIG_USB_STORAGE=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ELF_CORE=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_USB_PEGASUS=m
+CONFIG_SSB_PCIHOST=y
+CONFIG_MTD_CHAR=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_CEVT_R4K=y
+CONFIG_MARVELL_PHY=m
+CONFIG_SCSI_DMA=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_RESOURCES_64BIT=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_USB_CATC=m
+CONFIG_EEPROM_93CX6=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_XFRM_IPCOMP=m
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_MTD_NAND=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_INET_TUNNEL=m
+CONFIG_SND_VMASTER=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_8139CP=y
+CONFIG_PROC_EVENTS=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_LEMOTE_FULONG2F=y
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_BLOCK=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_MFD_SM501=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_LOCKD=y
+CONFIG_QUOTACTL=y
+CONFIG_ATALK=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_IP_NF_QUEUE=y
+CONFIG_KALLSYMS=y
+CONFIG_KEXEC=y
+CONFIG_YAFFS_FS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_NLS_UTF8=y
+CONFIG_VITESSE_PHY=m
+CONFIG_SSFDC=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SATA_PMP=y
+CONFIG_AF_RXRPC=m
+CONFIG_PM_SLEEP=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_INET_ESP=m
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_IP_NF_MATCH_RECENT=y
+CONFIG_NET_IPIP=m
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_NF_NAT_PPTP=y
+CONFIG_SHMEM=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_INET_LRO=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_EPOLL=y
+CONFIG_SND_MIPS=y
+CONFIG_INFTL=y
+CONFIG_RELAY=y
+CONFIG_MSDOS_FS=y
+CONFIG_FONT_8x8=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_ROMFS_FS=y
+CONFIG_MDIO_BITBANG=m
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_SYS_HAS_CPU_LOONGSON2=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_YAFFS_YAFFS1=y
+CONFIG_SERIO=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_PCMCIA_PROBE=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_USB_SUPPORT=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SMSC_PHY=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_UIO_PDRV=y
+CONFIG_FB=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_SOUND=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_TMPFS=y
+CONFIG_QUOTA=y
+CONFIG_ASK_IP_FIB_HASH=y
+CONFIG_GENERIC_TIME=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+CONFIG_PLIST=y
+CONFIG_FUTEX=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_WLAN_80211=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_MISC_DEVICES=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_INPUT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_LOCALVERSION="-loongson-2f"
+CONFIG_USB_DEVICEFS=y
+CONFIG_MOUSE_BCM5974=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_BROADCOM_PHY=m
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_SYSFS=y
+CONFIG_HZ_250=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HID_DEBUG=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_PM=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_NO_HZ=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_CRYPTO_CAST6=y
+CONFIG_HZ=250
+CONFIG_INPUT_POWERMATE=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_INET_DIAG=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_SSB_POSSIBLE=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_VT=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_USB_ZD1201=m
+CONFIG_CONNECTOR=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_FONT_8x16=y
+CONFIG_NETFILTER=y
+CONFIG_PCMCIA=m
+CONFIG_PCCARD=m
+CONFIG_BASE_FULL=y
+CONFIG_CRC_CCITT=y
+CONFIG_IP_MULTICAST=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_MTD_BLOCK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_MIPS32_N32=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_MIPS32_O32=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HAS_IOMEM=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_FW_LOADER=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_PNP_DEBUG=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_NLS_ASCII=y
+CONFIG_VIDEO_DEV=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_USB_GSPCA=y
+CONFIG_ISO9660_FS=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_PACKET=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_R8169_VLAN=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_FIB_RULES=y
+CONFIG_CRAMFS=y
+CONFIG_MOUSE_PS2=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NET_IPGRE=m
+CONFIG_SND_SM501_SOC=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_HIDRAW=y
+CONFIG_HW_RANDOM=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_INOTIFY_USER=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_MIPS32_COMPAT=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_COMPAT=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_TIMER=y
+CONFIG_JOLIET=y
+CONFIG_8139TOO=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_PHYLIB=y
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_DEFAULT_CUBIC=y
+CONFIG_SERIAL_8250_EXAR_ST16C554=y
+CONFIG_ISAPNP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_ECRYPT_FS=y
+CONFIG_QSEMI_PHY=m
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_BOOT_ELF32=y
+CONFIG_NFS_V4=y
+CONFIG_JBD=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_BLK_DEV_IDE_SATA=y
+CONFIG_CGROUP_NS=y
+CONFIG_MIPS_MT_DISABLED=y
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_AFS_FS=m
+CONFIG_IDE=y
+CONFIG_BFS_FS=y
+CONFIG_FAT_FS=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_INPUT_UINPUT=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_IP_MROUTE=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_DMADEVICES=y
+CONFIG_HID=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_EFS_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_ATA=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_NF_NAT=y
+CONFIG_UDF_FS=m
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_SSB_SPROM=y
+CONFIG_PRINTK=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NCP_FS=m
+CONFIG_RPCSEC_GSS_SPKM3=m
+CONFIG_POWER_SUPPLY=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_SMB_FS=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_SUNRPC=y
+CONFIG_FS_MBCACHE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_LLC=y
+CONFIG_XFRM_USER=m
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_DEV_APPLETALK=y
+CONFIG_PCI=y
+CONFIG_USB_PHIDGETSERVO=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_MOUSE_APPLETOUCH=y
+CONFIG_INITRAMFS_SOURCE="~/ramfs/cww.cpio.gz"
+CONFIG_IKCONFIG_PROC=y
+CONFIG_ISA=y
+CONFIG_ZISOFS=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_BUG=y
+CONFIG_CRYPTO_HW=y
+CONFIG_NFS_FS=y
+CONFIG_MII=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_CRYPTO=y
+CONFIG_SYSCTL=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_SND=y
+CONFIG_CICADA_PHY=m
+CONFIG_MTD=y
+CONFIG_UFS_FS=y
+CONFIG_WAN=y
+CONFIG_NETDEV_1000=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_NET=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_CPU_LOONGSON2=y
+CONFIG_SSB=m
+CONFIG_FS_XIP=y
+CONFIG_RTC=y
+CONFIG_STANDALONE=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MAC_PARTITION=y
+CONFIG_NETDEVICES=y
+CONFIG_USB=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_SCSI_ACARD=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS=y
+CONFIG_UIO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_PNP=y
+CONFIG_SERIAL_8250=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MMU=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_USB_NET_DM9601=m
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_MTD_CFI_I2=y
+CONFIG_PCI_LEGACY=y
+CONFIG_MTD_NAND_TOPSTAR=y
+CONFIG_IPX=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+CONFIG_IOSCHED_AS=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_BASE_SMALL=0
+CONFIG_SND_AC97_CODEC=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_BINFMT_ELF=y
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_INPUT_ATI_REMOTE=m
+CONFIG_SERIO_I8042=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_USB_NET_GL620A=m
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_BITREVERSE=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CMDLINE=""
+CONFIG_SGI_PARTITION=y
+CONFIG_INPUT_YEALINK=m
+CONFIG_MTD_CONCAT=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_USB_HIDDEV=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_CRYPTO_DEV_HIFN_795X=y
diff -uNra linux-2.6.27.6/include/config/auto.conf.cmd linux-2.6.27.6.yaffs/include/config/auto.conf.cmd
--- linux-2.6.27.6/include/config/auto.conf.cmd	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/config/auto.conf.cmd	2012-03-14 10:55:20.000000000 +0800
@@ -0,0 +1,342 @@
+deps_config := \
+	lib/Kconfig \
+	drivers/crypto/Kconfig \
+	crypto/async_tx/Kconfig \
+	crypto/Kconfig \
+	security/smack/Kconfig \
+	security/selinux/Kconfig \
+	security/Kconfig \
+	lib/Kconfig.kgdb \
+	samples/Kconfig \
+	kernel/trace/Kconfig \
+	lib/Kconfig.debug \
+	arch/mips/Kconfig.debug \
+	fs/dlm/Kconfig \
+	fs/nls/Kconfig \
+	fs/partitions/Kconfig \
+	fs/ncpfs/Kconfig \
+	fs/ubifs/Kconfig \
+	fs/yaffs2/Kconfig \
+	fs/proc/Kconfig \
+	fs/gfs2/Kconfig \
+	fs/xfs/Kconfig \
+	fs/Kconfig \
+	drivers/xen/Kconfig \
+	drivers/uio/Kconfig \
+	drivers/auxdisplay/Kconfig \
+	drivers/dca/Kconfig \
+	drivers/dma/Kconfig \
+	drivers/rtc/Kconfig \
+	drivers/edac/Kconfig \
+	drivers/infiniband/ulp/iser/Kconfig \
+	drivers/infiniband/ulp/srp/Kconfig \
+	drivers/infiniband/ulp/ipoib/Kconfig \
+	drivers/infiniband/hw/nes/Kconfig \
+	drivers/infiniband/hw/mlx4/Kconfig \
+	drivers/infiniband/hw/cxgb3/Kconfig \
+	drivers/infiniband/hw/amso1100/Kconfig \
+	drivers/infiniband/hw/ehca/Kconfig \
+	drivers/infiniband/hw/ipath/Kconfig \
+	drivers/infiniband/hw/mthca/Kconfig \
+	drivers/infiniband/Kconfig \
+	drivers/accessibility/Kconfig \
+	drivers/leds/Kconfig \
+	drivers/memstick/host/Kconfig \
+	drivers/memstick/core/Kconfig \
+	drivers/memstick/Kconfig \
+	drivers/mmc/host/Kconfig \
+	drivers/mmc/card/Kconfig \
+	drivers/mmc/core/Kconfig \
+	drivers/mmc/Kconfig \
+	drivers/usb/gadget/Kconfig \
+	drivers/usb/atm/Kconfig \
+	drivers/usb/misc/sisusbvga/Kconfig \
+	drivers/usb/misc/Kconfig \
+	drivers/usb/serial/Kconfig \
+	drivers/usb/image/Kconfig \
+	drivers/usb/storage/Kconfig \
+	drivers/usb/class/Kconfig \
+	drivers/usb/musb/Kconfig \
+	drivers/usb/host/Kconfig \
+	drivers/usb/mon/Kconfig \
+	drivers/usb/core/Kconfig \
+	drivers/usb/Kconfig \
+	drivers/hid/usbhid/Kconfig \
+	drivers/hid/Kconfig \
+	sound/oss/Kconfig \
+	sound/soc/codecs/Kconfig \
+	sound/soc/sm501/Kconfig \
+	sound/soc/omap/Kconfig \
+	sound/soc/davinci/Kconfig \
+	sound/soc/fsl/Kconfig \
+	sound/soc/sh/Kconfig \
+	sound/soc/s3c24xx/Kconfig \
+	sound/soc/pxa/Kconfig \
+	sound/soc/au1x/Kconfig \
+	sound/soc/at91/Kconfig \
+	sound/soc/at32/Kconfig \
+	sound/soc/Kconfig \
+	sound/parisc/Kconfig \
+	sound/sparc/Kconfig \
+	sound/pcmcia/Kconfig \
+	sound/usb/Kconfig \
+	sound/sh/Kconfig \
+	sound/mips/Kconfig \
+	sound/spi/Kconfig \
+	sound/arm/Kconfig \
+	sound/aoa/soundbus/Kconfig \
+	sound/aoa/codecs/Kconfig \
+	sound/aoa/fabrics/Kconfig \
+	sound/aoa/Kconfig \
+	sound/ppc/Kconfig \
+	sound/pci/Kconfig \
+	sound/isa/Kconfig \
+	sound/drivers/Kconfig \
+	sound/core/Kconfig \
+	sound/oss/dmasound/Kconfig \
+	sound/Kconfig \
+	drivers/video/logo/Kconfig \
+	drivers/video/console/Kconfig \
+	drivers/video/display/Kconfig \
+	drivers/video/backlight/Kconfig \
+	drivers/video/omap/Kconfig \
+	drivers/video/geode/Kconfig \
+	drivers/gpu/drm/Kconfig \
+	drivers/char/agp/Kconfig \
+	drivers/video/Kconfig \
+	drivers/media/dvb/frontends/Kconfig \
+	drivers/media/dvb/pluto2/Kconfig \
+	drivers/media/dvb/bt8xx/Kconfig \
+	drivers/media/dvb/b2c2/Kconfig \
+	drivers/media/dvb/siano/Kconfig \
+	drivers/media/dvb/cinergyT2/Kconfig \
+	drivers/media/dvb/ttusb-dec/Kconfig \
+	drivers/media/dvb/ttusb-budget/Kconfig \
+	drivers/media/dvb/dvb-usb/Kconfig \
+	drivers/media/dvb/ttpci/Kconfig \
+	drivers/media/dvb/Kconfig \
+	drivers/media/radio/Kconfig \
+	drivers/media/video/pwc/Kconfig \
+	drivers/media/video/zc0301/Kconfig \
+	drivers/media/video/sn9c102/Kconfig \
+	drivers/media/video/et61x251/Kconfig \
+	drivers/media/video/usbvideo/Kconfig \
+	drivers/media/video/usbvision/Kconfig \
+	drivers/media/video/em28xx/Kconfig \
+	drivers/media/video/pvrusb2/Kconfig \
+	drivers/media/video/gspca/Kconfig \
+	drivers/media/video/uvc/Kconfig \
+	drivers/media/video/cx18/Kconfig \
+	drivers/media/video/ivtv/Kconfig \
+	drivers/media/video/au0828/Kconfig \
+	drivers/media/video/cx23885/Kconfig \
+	drivers/media/video/cx88/Kconfig \
+	drivers/media/video/saa7134/Kconfig \
+	drivers/media/video/cpia2/Kconfig \
+	drivers/media/video/bt8xx/Kconfig \
+	drivers/media/video/cx25840/Kconfig \
+	drivers/media/video/Kconfig \
+	drivers/media/common/tuners/Kconfig \
+	drivers/media/common/Kconfig \
+	drivers/media/Kconfig \
+	drivers/mfd/Kconfig \
+	drivers/ssb/Kconfig \
+	drivers/watchdog/Kconfig \
+	drivers/thermal/Kconfig \
+	drivers/hwmon/Kconfig \
+	drivers/power/Kconfig \
+	drivers/w1/slaves/Kconfig \
+	drivers/w1/masters/Kconfig \
+	drivers/w1/Kconfig \
+	drivers/gpio/Kconfig \
+	drivers/spi/Kconfig \
+	drivers/i2c/chips/Kconfig \
+	drivers/i2c/busses/Kconfig \
+	drivers/i2c/algos/Kconfig \
+	drivers/i2c/Kconfig \
+	drivers/s390/char/Kconfig \
+	drivers/char/tpm/Kconfig \
+	drivers/char/pcmcia/Kconfig \
+	drivers/char/hw_random/Kconfig \
+	drivers/char/ipmi/Kconfig \
+	drivers/serial/Kconfig \
+	drivers/char/Kconfig \
+	drivers/input/gameport/Kconfig \
+	drivers/input/serio/Kconfig \
+	drivers/input/misc/Kconfig \
+	drivers/input/touchscreen/Kconfig \
+	drivers/input/tablet/Kconfig \
+	drivers/input/joystick/iforce/Kconfig \
+	drivers/input/joystick/Kconfig \
+	drivers/input/mouse/Kconfig \
+	drivers/input/keyboard/Kconfig \
+	drivers/input/Kconfig \
+	drivers/telephony/Kconfig \
+	drivers/isdn/hardware/eicon/Kconfig \
+	drivers/isdn/hardware/avm/Kconfig \
+	drivers/isdn/hardware/Kconfig \
+	drivers/isdn/capi/Kconfig \
+	drivers/isdn/gigaset/Kconfig \
+	drivers/isdn/hysdn/Kconfig \
+	drivers/isdn/act2000/Kconfig \
+	drivers/isdn/sc/Kconfig \
+	drivers/isdn/pcbit/Kconfig \
+	drivers/isdn/icn/Kconfig \
+	drivers/isdn/hisax/Kconfig \
+	drivers/isdn/i4l/Kconfig \
+	drivers/isdn/hardware/mISDN/Kconfig \
+	drivers/isdn/mISDN/Kconfig \
+	drivers/isdn/Kconfig \
+	drivers/s390/net/Kconfig \
+	drivers/atm/Kconfig \
+	drivers/net/wan/Kconfig \
+	drivers/net/pcmcia/Kconfig \
+	drivers/net/usb/Kconfig \
+	drivers/net/wireless/rt2x00/Kconfig \
+	drivers/net/wireless/zd1211rw/Kconfig \
+	drivers/net/wireless/b43legacy/Kconfig \
+	drivers/net/wireless/b43/Kconfig \
+	drivers/net/wireless/hostap/Kconfig \
+	drivers/net/wireless/iwlwifi/Kconfig \
+	drivers/net/wireless/ath9k/Kconfig \
+	drivers/net/wireless/ath5k/Kconfig \
+	drivers/net/wireless/p54/Kconfig \
+	drivers/net/wireless/Kconfig \
+	drivers/net/tokenring/Kconfig \
+	drivers/net/sfc/Kconfig \
+	drivers/net/ixp2000/Kconfig \
+	drivers/net/fs_enet/Kconfig \
+	drivers/net/ibm_newemac/Kconfig \
+	drivers/net/tulip/Kconfig \
+	drivers/net/arm/Kconfig \
+	drivers/net/phy/Kconfig \
+	drivers/net/arcnet/Kconfig \
+	drivers/net/Kconfig \
+	drivers/macintosh/Kconfig \
+	drivers/message/i2o/Kconfig \
+	drivers/firewire/Kconfig \
+	drivers/ieee1394/Kconfig \
+	drivers/message/fusion/Kconfig \
+	drivers/md/Kconfig \
+	drivers/ata/Kconfig \
+	drivers/scsi/device_handler/Kconfig \
+	drivers/scsi/pcmcia/Kconfig \
+	drivers/scsi/arm/Kconfig \
+	drivers/scsi/qla4xxx/Kconfig \
+	drivers/scsi/qla2xxx/Kconfig \
+	drivers/scsi/megaraid/Kconfig.megaraid \
+	drivers/scsi/aic94xx/Kconfig \
+	drivers/scsi/aic7xxx/Kconfig.aic79xx \
+	drivers/scsi/aic7xxx/Kconfig.aic7xxx \
+	drivers/scsi/libsas/Kconfig \
+	drivers/scsi/Kconfig \
+	drivers/ide/Kconfig \
+	drivers/misc/Kconfig \
+	drivers/s390/block/Kconfig \
+	drivers/block/paride/Kconfig \
+	drivers/block/Kconfig \
+	drivers/pnp/pnpacpi/Kconfig \
+	drivers/pnp/pnpbios/Kconfig \
+	drivers/pnp/isapnp/Kconfig \
+	drivers/pnp/Kconfig \
+	drivers/parport/Kconfig \
+	drivers/of/Kconfig \
+	drivers/mtd/ubi/Kconfig.debug \
+	drivers/mtd/ubi/Kconfig \
+	drivers/mtd/onenand/Kconfig \
+	drivers/mtd/nand/Kconfig \
+	drivers/mtd/devices/Kconfig \
+	drivers/mtd/maps/Kconfig \
+	drivers/mtd/chips/Kconfig \
+	drivers/mtd/Kconfig \
+	drivers/connector/Kconfig \
+	drivers/base/Kconfig \
+	drivers/Kconfig \
+	net/9p/Kconfig \
+	net/rfkill/Kconfig \
+	net/ieee80211/Kconfig \
+	net/mac80211/Kconfig \
+	net/wireless/Kconfig \
+	net/rxrpc/Kconfig \
+	drivers/bluetooth/Kconfig \
+	net/bluetooth/hidp/Kconfig \
+	net/bluetooth/cmtp/Kconfig \
+	net/bluetooth/bnep/Kconfig \
+	net/bluetooth/rfcomm/Kconfig \
+	net/bluetooth/Kconfig \
+	drivers/net/irda/Kconfig \
+	net/irda/ircomm/Kconfig \
+	net/irda/irnet/Kconfig \
+	net/irda/irlan/Kconfig \
+	net/irda/Kconfig \
+	drivers/net/can/Kconfig \
+	net/can/Kconfig \
+	drivers/net/hamradio/Kconfig \
+	net/ax25/Kconfig \
+	net/sched/Kconfig \
+	net/wanrouter/Kconfig \
+	net/econet/Kconfig \
+	net/lapb/Kconfig \
+	net/x25/Kconfig \
+	drivers/net/appletalk/Kconfig \
+	net/ipx/Kconfig \
+	net/llc/Kconfig \
+	net/decnet/Kconfig \
+	net/8021q/Kconfig \
+	net/bridge/Kconfig \
+	net/802/Kconfig \
+	net/atm/Kconfig \
+	net/tipc/Kconfig \
+	net/sctp/Kconfig \
+	net/dccp/ccids/Kconfig \
+	net/dccp/Kconfig \
+	net/bridge/netfilter/Kconfig \
+	net/decnet/netfilter/Kconfig \
+	net/ipv6/netfilter/Kconfig \
+	net/ipv4/netfilter/Kconfig \
+	net/netfilter/Kconfig \
+	net/netlabel/Kconfig \
+	net/ipv6/Kconfig \
+	net/ipv4/ipvs/Kconfig \
+	net/ipv4/Kconfig \
+	net/iucv/Kconfig \
+	net/xfrm/Kconfig \
+	net/unix/Kconfig \
+	net/packet/Kconfig \
+	net/Kconfig \
+	kernel/power/Kconfig \
+	fs/Kconfig.binfmt \
+	drivers/pci/hotplug/Kconfig \
+	drivers/pcmcia/Kconfig \
+	drivers/eisa/Kconfig \
+	drivers/pci/Kconfig \
+	block/Kconfig.iosched \
+	block/Kconfig \
+	arch/Kconfig \
+	usr/Kconfig \
+	init/Kconfig \
+	kernel/Kconfig.preempt \
+	kernel/time/Kconfig \
+	mm/Kconfig \
+	arch/mips/vr41xx/Kconfig \
+	arch/mips/txx9/Kconfig \
+	arch/mips/sibyte/Kconfig \
+	arch/mips/sgi-ip27/Kconfig \
+	arch/mips/pmc-sierra/Kconfig \
+	arch/mips/lasat/Kconfig \
+	arch/mips/jazz/Kconfig \
+	arch/mips/basler/excite/Kconfig \
+	arch/mips/au1000/Kconfig \
+	arch/mips/Kconfig
+
+include/config/auto.conf: \
+	$(deps_config)
+
+ifneq "$(KERNELVERSION)" "2.6.27.6"
+include/config/auto.conf: FORCE
+endif
+ifneq "$(ARCH)" "mips"
+include/config/auto.conf: FORCE
+endif
+
+$(deps_config): ;
diff -uNra linux-2.6.27.6/include/config/kernel.release linux-2.6.27.6.yaffs/include/config/kernel.release
--- linux-2.6.27.6/include/config/kernel.release	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/config/kernel.release	2012-03-14 10:55:20.000000000 +0800
@@ -0,0 +1 @@
+2.6.27.6-loongson-2f
diff -uNra linux-2.6.27.6/include/linux/autoconf.h linux-2.6.27.6.yaffs/include/linux/autoconf.h
--- linux-2.6.27.6/include/linux/autoconf.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/autoconf.h	2012-03-14 10:55:20.000000000 +0800
@@ -0,0 +1,793 @@
+/*
+ * Automatically generated C config: don't edit
+ * Linux kernel version: 2.6.27.6
+ * Wed Mar 14 10:55:20 2012
+ */
+#define AUTOCONF_INCLUDED
+#define CONFIG_USB_PHIDGETMOTORCONTROL 1
+#define CONFIG_VIDEO_V4L1_COMPAT 1
+#define CONFIG_SCSI_ACARD_ATP8620 1
+#define CONFIG_OSF_PARTITION 1
+#define CONFIG_INET_XFRM_TUNNEL_MODULE 1
+#define CONFIG_CRYPTO_ANUBIS 1
+#define CONFIG_FRAME_WARN 2048
+#define CONFIG_BLK_DEV_HD 1
+#define CONFIG_TCP_CONG_ADVANCED 1
+#define CONFIG_COMPAT_BRK 1
+#define CONFIG_JFFS2_CMODE_PRIORITY 1
+#define CONFIG_TCP_CONG_SCALABLE 1
+#define CONFIG_VIDEO_HELPER_CHIPS_AUTO 1
+#define CONFIG_NF_CT_ACCT 1
+#define CONFIG_TCP_CONG_VENO 1
+#define CONFIG_CARDBUS 1
+#define CONFIG_CRYPTO_MD4 1
+#define CONFIG_IP_NF_TARGET_TTL 1
+#define CONFIG_NETFILTER_NETLINK_QUEUE 1
+#define CONFIG_USER_SCHED 1
+#define CONFIG_VIDEO_V4L2_COMMON 1
+#define CONFIG_NF_NAT_PROTO_GRE 1
+#define CONFIG_CRYPTO_MD5 1
+#define CONFIG_FLATMEM 1
+#define CONFIG_PROC_KCORE 1
+#define CONFIG_SCSI_FC_ATTRS 1
+#define CONFIG_CRYPTO_CBC 1
+#define CONFIG_USB_RTL8150_MODULE 1
+#define CONFIG_NF_CONNTRACK_NETBIOS_NS 1
+#define CONFIG_CRYPTO_ECB 1
+#define CONFIG_PAGE_SIZE_16KB 1
+#define CONFIG_TIMERFD 1
+#define CONFIG_ENABLE_MUST_CHECK 1
+#define CONFIG_MTD_MAP_BANK_WIDTH_1 1
+#define CONFIG_EVENTFD 1
+#define CONFIG_BROKEN_ON_SMP 1
+#define CONFIG_EXT2_FS_XATTR 1
+#define CONFIG_USB_KAWETH_MODULE 1
+#define CONFIG_BLK_DEV_SD 1
+#define CONFIG_HAS_DMA 1
+#define CONFIG_RAID_ATTRS_MODULE 1
+#define CONFIG_MTD_MAP_BANK_WIDTH_2 1
+#define CONFIG_NETFILTER_XT_MATCH_DSCP 1
+#define CONFIG_EXT3_FS_XATTR 1
+#define CONFIG_NETFILTER_XT_MATCH_MARK 1
+#define CONFIG_SUN_PARTITION 1
+#define CONFIG_CODA_FS_MODULE 1
+#define CONFIG_NFS_COMMON 1
+#define CONFIG_MTD_MAP_BANK_WIDTH_4 1
+#define CONFIG_SND_SM501_SOC_AC97 1
+#define CONFIG_HW_CONSOLE 1
+#define CONFIG_NETFILTER_XT_MATCH_TIME 1
+#define CONFIG_CRYPTO_CCM 1
+#define CONFIG_NF_NAT_IRC 1
+#define CONFIG_MODULE_FORCE_LOAD 1
+#define CONFIG_CONSOLE_TRANSLATIONS 1
+#define CONFIG_ATA_SFF 1
+#define CONFIG_CHR_DEV_SG 1
+#define CONFIG_IP_NF_MATCH_ADDRTYPE 1
+#define CONFIG_NETFILTER_XT_MATCH_PKTTYPE 1
+#define CONFIG_USB_NET_PLUSB_MODULE 1
+#define CONFIG_NF_NAT_H323 1
+#define CONFIG_HW_HAS_PCI 1
+#define CONFIG_CRYPTO_SALSA20 1
+#define CONFIG_CRYPTO_CRYPTD 1
+#define CONFIG_MTD_CFI 1
+#define CONFIG_NET_CLS_ROUTE 1
+#define CONFIG_NF_CT_PROTO_SCTP 1
+#define CONFIG_CRYPTO_GCM 1
+#define CONFIG_BLK_DEV 1
+#define CONFIG_NETFILTER_XT_TARGET_TCPMSS 1
+#define CONFIG_NLS_KOI8_R 1
+#define CONFIG_HAS_IOPORT 1
+#define CONFIG_CRYPTO_FCRYPT 1
+#define CONFIG_NF_CONNTRACK_IPV4 1
+#define CONFIG_INET_AH_MODULE 1
+#define CONFIG_HAVE_ARCH_KGDB 1
+#define CONFIG_SYSCTL_SYSCALL_CHECK 1
+#define CONFIG_JFFS2_FS_DEBUG 0
+#define CONFIG_CRYPTO_AES 1
+#define CONFIG_MODULES 1
+#define CONFIG_CRYPTO_TEA 1
+#define CONFIG_JFFS2_FS_WBUF_VERIFY 1
+#define CONFIG_USB_ARCH_HAS_EHCI 1
+#define CONFIG_USB_USBNET_MODULE 1
+#define CONFIG_MTD_COMPLEX_MAPPINGS 1
+#define CONFIG_NLS_KOI8_U 1
+#define CONFIG_YAFFS_AUTO_YAFFS2 1
+#define CONFIG_EXT2_FS 1
+#define CONFIG_INPUT_MISC 1
+#define CONFIG_BLK_DEV_SR 1
+#define CONFIG_CPU_HAS_WB 1
+#define CONFIG_I8253 1
+#define CONFIG_EXT3_FS 1
+#define CONFIG_VT_CONSOLE 1
+#define CONFIG_NF_CONNTRACK_SANE 1
+#define CONFIG_CRYPTO_DES 1
+#define CONFIG_SND_MIXER_OSS 1
+#define CONFIG_FB_SM501 1
+#define CONFIG_NETFILTER_XT_MATCH_SCTP 1
+#define CONFIG_PREEMPT 1
+#define CONFIG_UIO_CIF 1
+#define CONFIG_USB_HID 1
+#define CONFIG_NF_NAT_FTP 1
+#define CONFIG_NETFILTER_XTABLES 1
+#define CONFIG_GENERIC_IRQ_PROBE 1
+#define CONFIG_SND_SM501_SOC_AC97_DEVICE 1
+#define CONFIG_SND_PCI 1
+#define CONFIG_ICPLUS_PHY_MODULE 1
+#define CONFIG_NF_CONNTRACK_MARK 1
+#define CONFIG_DEFCONFIG_LIST "/lib/modules/$UNAME_RELEASE/.config"
+#define CONFIG_SSB_PCIHOST_POSSIBLE 1
+#define CONFIG_RFD_FTL 1
+#define CONFIG_NF_NAT_SIP 1
+#define CONFIG_NETFILTER_NETLINK 1
+#define CONFIG_I8259 1
+#define CONFIG_NET_PCI 1
+#define CONFIG_SUSPEND 1
+#define CONFIG_SLAB 1
+#define CONFIG_INOTIFY 1
+#define CONFIG_CGROUPS 1
+#define CONFIG_HOTPLUG 1
+#define CONFIG_FLATMEM_MANUAL 1
+#define CONFIG_CPU_LITTLE_ENDIAN 1
+#define CONFIG_HAVE_STD_PC_SERIAL_PORT 1
+#define CONFIG_USB_ARCH_HAS_OHCI 1
+#define CONFIG_SND_PCM 1
+#define CONFIG_DEVPORT 1
+#define CONFIG_MTD_RAM 1
+#define CONFIG_CIFS_MODULE 1
+#define CONFIG_WAN_ROUTER_MODULE 1
+#define CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN 1
+#define CONFIG_SUNRPC_GSS 1
+#define CONFIG_FLAT_NODE_MEM_MAP 1
+#define CONFIG_CRYPTO_CTR 1
+#define CONFIG_VFAT_FS 1
+#define CONFIG_SND_SOC 1
+#define CONFIG_MTD_NAND_PLATFORM 1
+#define CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN 1
+#define CONFIG_CRYPTO_CTS 1
+#define CONFIG_JFFS2_FS_SECURITY 1
+#define CONFIG_INPUT_ATI_REMOTE2_MODULE 1
+#define CONFIG_R8169 1
+#define CONFIG_EMBEDDED 1
+#define CONFIG_UDF_NLS 1
+#define CONFIG_FUSE_FS 1
+#define CONFIG_KMOD 1
+#define CONFIG_GENERIC_ACL 1
+#define CONFIG_PROC_FS 1
+#define CONFIG_INPUT_MOUSEDEV_SCREEN_X 1024
+#define CONFIG_INPUT_MOUSEDEV_SCREEN_Y 768
+#define CONFIG_NET_KEY_MODULE 1
+#define CONFIG_INET 1
+#define CONFIG_RT_MUTEXES 1
+#define CONFIG_ARCH_SPARSEMEM_ENABLE 1
+#define CONFIG_LOGO 1
+#define CONFIG_SYSVIPC 1
+#define CONFIG_REISERFS_FS_SECURITY 1
+#define CONFIG_SCSI 1
+#define CONFIG_MTD_CFI_AMDSTD 1
+#define CONFIG_IP_SCTP 1
+#define CONFIG_TCP_CONG_CUBIC 1
+#define CONFIG_CGROUP_CPUACCT 1
+#define CONFIG_NTFS_FS 1
+#define CONFIG_USB_MON 1
+#define CONFIG_NF_CONNTRACK_TFTP 1
+#define CONFIG_IRQ_CPU 1
+#define CONFIG_NFTL 1
+#define CONFIG_NF_NAT_SNMP_BASIC 1
+#define CONFIG_CRYPTO_LRW 1
+#define CONFIG_CRYPTO_LZO 1
+#define CONFIG_INPUT_KEYSPAN_REMOTE_MODULE 1
+#define CONFIG_CRYPTO_DEFLATE 1
+#define CONFIG_BLK_DEV_INTEGRITY 1
+#define CONFIG_CPU_SUPPORTS_HIGHMEM 1
+#define CONFIG_USB_PHIDGETKIT 1
+#define CONFIG_VIDEO_MEDIA 1
+#define CONFIG_SSB_DRIVER_PCICORE_POSSIBLE 1
+#define CONFIG_PROC_PAGE_MONITOR 1
+#define CONFIG_IOSCHED_CFQ 1
+#define CONFIG_SND_SOC_AC97_CODEC 1
+#define CONFIG_NF_CONNTRACK_PPTP 1
+#define CONFIG_MIPS 1
+#define CONFIG_PAGEFLAGS_EXTENDED 1
+#define CONFIG_JFFS2_RTIME 1
+#define CONFIG_CRYPTO_MANAGER 1
+#define CONFIG_SWAP 1
+#define CONFIG_EXT2_FS_POSIX_ACL 1
+#define CONFIG_NFTL_RW 1
+#define CONFIG_KEYS 1
+#define CONFIG_NETFILTER_XT_MATCH_CONNMARK 1
+#define CONFIG_TCP_CONG_HYBLA 1
+#define CONFIG_EXT3_FS_POSIX_ACL 1
+#define CONFIG_AC97_BUS 1
+#define CONFIG_XFRM 1
+#define CONFIG_CRC32 1
+#define CONFIG_BLK_DEV_RAM_COUNT 16
+#define CONFIG_CRYPTO_XTS 1
+#define CONFIG_USB_NET_NET1080_MODULE 1
+#define CONFIG_CRC16 1
+#define CONFIG_NF_NAT_PROTO_UDPLITE 1
+#define CONFIG_IP_NF_IPTABLES 1
+#define CONFIG_FAT_DEFAULT_IOCHARSET "ascii"
+#define CONFIG_EXTRA_FIRMWARE ""
+#define CONFIG_IP_NF_MATCH_AH 1
+#define CONFIG_TEXTSEARCH_FSM 1
+#define CONFIG_BLK_DEV_INITRD 1
+#define CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER 1
+#define CONFIG_NF_NAT_PROTO_DCCP 1
+#define CONFIG_TEXTSEARCH_KMP 1
+#define CONFIG_NETFILTER_ADVANCED 1
+#define CONFIG_TCP_CONG_VEGAS 1
+#define CONFIG_PACKET_MMAP 1
+#define CONFIG_NTFS_RW 1
+#define CONFIG_SND_SEQUENCER_OSS 1
+#define CONFIG_UIO_SMX 1
+#define CONFIG_USB_NET_MCS7830_MODULE 1
+#define CONFIG_UNIX 1
+#define CONFIG_CRYPTO_DEV_HIFN_795X_RNG 1
+#define CONFIG_JFFS2_FS_XATTR 1
+#define CONFIG_HAMRADIO 1
+#define CONFIG_PCI_DOMAINS 1
+#define CONFIG_INPUT_MOUSEDEV_PSAUX 1
+#define CONFIG_CONFIGFS_FS 1
+#define CONFIG_SERIAL_CORE 1
+#define CONFIG_LXT_PHY_MODULE 1
+#define CONFIG_BLK_DEV_SR_VENDOR 1
+#define CONFIG_BLK_DEV_IDE 1
+#define CONFIG_IP_NF_TARGET_ULOG 1
+#define CONFIG_TCP_CONG_WESTWOOD_MODULE 1
+#define CONFIG_CRYPTO_AUTHENC 1
+#define CONFIG_SIGNALFD 1
+#define CONFIG_LZO_DECOMPRESS 1
+#define CONFIG_LOCK_KERNEL 1
+#define CONFIG_64BIT 1
+#define CONFIG_USB_EHCI_ROOT_HUB_TT 1
+#define CONFIG_SCSI_WAIT_SCAN_MODULE 1
+#define CONFIG_CRYPTO_ARC4 1
+#define CONFIG_IKCONFIG 1
+#define CONFIG_CRYPTO_AEAD 1
+#define CONFIG_USB_ANNOUNCE_NEW_DEVICES 1
+#define CONFIG_CLASSIC_RCU 1
+#define CONFIG_NF_CONNTRACK_PROC_COMPAT 1
+#define CONFIG_IP_FIB_HASH 1
+#define CONFIG_SYS_SUPPORTS_HIGHMEM 1
+#define CONFIG_REISERFS_FS_XATTR 1
+#define CONFIG_CRYPTO_SHA1 1
+#define CONFIG_ANON_INODES 1
+#define CONFIG_SYS_HAS_EARLY_PRINTK 1
+#define CONFIG_USB_PHIDGET 1
+#define CONFIG_TCP_CONG_HSTCP 1
+#define CONFIG_SLABINFO 1
+#define CONFIG_PARTITION_ADVANCED 1
+#define CONFIG_LOGO_LINUX_CLUT224 1
+#define CONFIG_MTD_BLKDEVS 1
+#define CONFIG_NETFILTER_XT_TARGET_NOTRACK 1
+#define CONFIG_VGA_CONSOLE 1
+#define CONFIG_CDROM_PKTCDVD_BUFFERS 8
+#define CONFIG_NLS_DEFAULT "utf8"
+#define CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_BLK_DEV_BSG 1
+#define CONFIG_SPLIT_PTLOCK_CPUS 4
+#define CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ 1
+#define CONFIG_JFFS2_FS 1
+#define CONFIG_DAVICOM_PHY_MODULE 1
+#define CONFIG_GROUP_SCHED 1
+#define CONFIG_NETFILTER_XT_MATCH_REALM 1
+#define CONFIG_SYSVIPC_COMPAT 1
+#define CONFIG_MTD_PLATRAM 1
+#define CONFIG_NETFILTER_XT_TARGET_RATEEST 1
+#define CONFIG_HAVE_IDE 1
+#define CONFIG_CRYPTO_GF128MUL 1
+#define CONFIG_BLK_DEV_RAM 1
+#define CONFIG_NETFILTER_XT_TARGET_NFQUEUE 1
+#define CONFIG_VM_EVENT_COUNTERS 1
+#define CONFIG_INPUT_MOUSEDEV 1
+#define CONFIG_LIBCRC32C 1
+#define CONFIG_INET_IPCOMP_MODULE 1
+#define CONFIG_USB_NET_AX8817X_MODULE 1
+#define CONFIG_REALTEK_PHY 1
+#define CONFIG_CRYPTO_PCBC 1
+#define CONFIG_BLK_DEV_SX8 1
+#define CONFIG_CRYPTO_HMAC 1
+#define CONFIG_MODVERSIONS 1
+#define CONFIG_GENERIC_FIND_NEXT_BIT 1
+#define CONFIG_KERNEL_GZIP 1
+#define CONFIG_REISERFS_FS 1
+#define CONFIG_BINFMT_ELF32 1
+#define CONFIG_CSRC_R4K 1
+#define CONFIG_SYSCTL_SYSCALL 1
+#define CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV 1
+#define CONFIG_IDE_PROC_FS 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_HOTPLUG_PCI 1
+#define CONFIG_SERIAL_8250_RUNTIME_UARTS 6
+#define CONFIG_ARCH_SUSPEND_POSSIBLE 1
+#define CONFIG_ELF_CORE 1
+#define CONFIG_CRYPTO_XCBC 1
+#define CONFIG_CRYPTO_SERPENT 1
+#define CONFIG_CRYPTO_SEED 1
+#define CONFIG_USB_PEGASUS_MODULE 1
+#define CONFIG_SSB_PCIHOST 1
+#define CONFIG_MTD_CHAR 1
+#define CONFIG_NF_NAT_PROTO_SCTP 1
+#define CONFIG_NETFILTER_XT_MATCH_LIMIT 1
+#define CONFIG_NETFILTER_NETLINK_LOG 1
+#define CONFIG_CEVT_R4K 1
+#define CONFIG_MARVELL_PHY_MODULE 1
+#define CONFIG_SCSI_DMA 1
+#define CONFIG_IP_NF_TARGET_REDIRECT 1
+#define CONFIG_DEFAULT_IOSCHED "deadline"
+#define CONFIG_RESOURCES_64BIT 1
+#define CONFIG_CRYPTO_TWOFISH 1
+#define CONFIG_CRYPTO_HASH 1
+#define CONFIG_UNIX98_PTYS 1
+#define CONFIG_USB_CATC_MODULE 1
+#define CONFIG_EEPROM_93CX6 1
+#define CONFIG_NETFILTER_XT_MATCH_STATE 1
+#define CONFIG_IP_PIMSM_V1 1
+#define CONFIG_XFRM_IPCOMP_MODULE 1
+#define CONFIG_FB_CFB_COPYAREA 1
+#define CONFIG_SCSI_SAS_ATTRS 1
+#define CONFIG_MTD_NAND 1
+#define CONFIG_IP_PIMSM_V2 1
+#define CONFIG_INET_TUNNEL_MODULE 1
+#define CONFIG_SND_VMASTER 1
+#define CONFIG_FB_CFB_FILLRECT 1
+#define CONFIG_SYN_COOKIES 1
+#define CONFIG_NETFILTER_XT_TARGET_DSCP 1
+#define CONFIG_VIDEO_CAPTURE_DRIVERS 1
+#define CONFIG_8139CP 1
+#define CONFIG_PROC_EVENTS 1
+#define CONFIG_NETFILTER_XT_TARGET_MARK 1
+#define CONFIG_TCP_CONG_LP 1
+#define CONFIG_LEMOTE_FULONG2F 1
+#define CONFIG_SCSI_SPI_ATTRS 1
+#define CONFIG_SCSI_MULTI_LUN 1
+#define CONFIG_PCMCIA_LOAD_CIS 1
+#define CONFIG_GENERIC_ISA_DMA 1
+#define CONFIG_EXT2_FS_XIP 1
+#define CONFIG_CRYPTO_MICHAEL_MIC 1
+#define CONFIG_BLOCK 1
+#define CONFIG_SND_OSSEMUL 1
+#define CONFIG_MFD_SM501 1
+#define CONFIG_GENERIC_CLOCKEVENTS_BUILD 1
+#define CONFIG_GENERIC_HWEIGHT 1
+#define CONFIG_LOCKD 1
+#define CONFIG_QUOTACTL 1
+#define CONFIG_ATALK 1
+#define CONFIG_NETFILTER_XT_MATCH_QUOTA 1
+#define CONFIG_ENABLE_WARN_DEPRECATED 1
+#define CONFIG_NETFILTER_XT_MATCH_OWNER 1
+#define CONFIG_IP_ADVANCED_ROUTER 1
+#define CONFIG_BOARD_SCACHE 1
+#define CONFIG_YAFFS_SHORT_NAMES_IN_RAM 1
+#define CONFIG_IP_NF_QUEUE 1
+#define CONFIG_KALLSYMS 1
+#define CONFIG_KEXEC 1
+#define CONFIG_YAFFS_FS 1
+#define CONFIG_HID_SUPPORT 1
+#define CONFIG_SYSVIPC_SYSCTL 1
+#define CONFIG_NLS_UTF8 1
+#define CONFIG_VITESSE_PHY_MODULE 1
+#define CONFIG_SSFDC 1
+#define CONFIG_FIRMWARE_IN_KERNEL 1
+#define CONFIG_NF_NAT_TFTP 1
+#define CONFIG_JFFS2_FS_POSIX_ACL 1
+#define CONFIG_VT_HW_CONSOLE_BINDING 1
+#define CONFIG_DMA_NONCOHERENT 1
+#define CONFIG_PROC_SYSCTL 1
+#define CONFIG_SATA_PMP 1
+#define CONFIG_AF_RXRPC_MODULE 1
+#define CONFIG_PM_SLEEP 1
+#define CONFIG_SSB_DRIVER_PCICORE 1
+#define CONFIG_INET_ESP_MODULE 1
+#define CONFIG_CRYPTO_CAMELLIA 1
+#define CONFIG_SND_PCM_OSS 1
+#define CONFIG_INPUT_MOUSE 1
+#define CONFIG_IP_NF_MATCH_RECENT 1
+#define CONFIG_NET_IPIP_MODULE 1
+#define CONFIG_SERIAL_8250_MANY_PORTS 1
+#define CONFIG_USB_NET_ZAURUS_MODULE 1
+#define CONFIG_NF_NAT_PPTP 1
+#define CONFIG_SHMEM 1
+#define CONFIG_CRYPTO_NULL 1
+#define CONFIG_REISERFS_FS_POSIX_ACL 1
+#define CONFIG_INET_LRO_MODULE 1
+#define CONFIG_INET_XFRM_MODE_TRANSPORT_MODULE 1
+#define CONFIG_EPOLL 1
+#define CONFIG_SND_MIPS 1
+#define CONFIG_INFTL 1
+#define CONFIG_RELAY 1
+#define CONFIG_MSDOS_FS 1
+#define CONFIG_FONT_8x8 1
+#define CONFIG_FB_MODE_HELPERS 1
+#define CONFIG_IP_MULTIPLE_TABLES 1
+#define CONFIG_CRYPTO_WP512 1
+#define CONFIG_RPCSEC_GSS_KRB5 1
+#define CONFIG_ROMFS_FS 1
+#define CONFIG_MDIO_BITBANG_MODULE 1
+#define CONFIG_NLS_CODEPAGE_850 1
+#define CONFIG_SCSI_TGT 1
+#define CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS 1
+#define CONFIG_NLS_CODEPAGE_932 1
+#define CONFIG_NLS_CODEPAGE_950 1
+#define CONFIG_NLS_CODEPAGE_860 1
+#define CONFIG_NLS_CODEPAGE_437 1
+#define CONFIG_STACKTRACE_SUPPORT 1
+#define CONFIG_SYS_HAS_CPU_LOONGSON2 1
+#define CONFIG_NLS_CODEPAGE_861 1
+#define CONFIG_NLS_CODEPAGE_852 1
+#define CONFIG_YAFFS_YAFFS1 1
+#define CONFIG_SERIO 1
+#define CONFIG_UEVENT_HELPER_PATH ""
+#define CONFIG_NLS_CODEPAGE_862 1
+#define CONFIG_YAFFS_YAFFS2 1
+#define CONFIG_INITRAMFS_ROOT_GID 0
+#define CONFIG_NLS_CODEPAGE_863 1
+#define CONFIG_NLS_CODEPAGE_737 1
+#define CONFIG_PCMCIA_PROBE 1
+#define CONFIG_NLS_CODEPAGE_936 1
+#define CONFIG_NLS_CODEPAGE_864 1
+#define CONFIG_NLS_CODEPAGE_855 1
+#define CONFIG_ZLIB_DEFLATE 1
+#define CONFIG_INET_XFRM_MODE_TUNNEL_MODULE 1
+#define CONFIG_NLS_CODEPAGE_874 1
+#define CONFIG_NLS_CODEPAGE_865 1
+#define CONFIG_NLS_CODEPAGE_775 1
+#define CONFIG_USB_SUPPORT 1
+#define CONFIG_SND_VERBOSE_PROCFS 1
+#define CONFIG_SMSC_PHY_MODULE 1
+#define CONFIG_NETFILTER_XT_MATCH_HASHLIMIT 1
+#define CONFIG_NETFILTER_XT_MATCH_CONNTRACK 1
+#define CONFIG_NLS_CODEPAGE_866 1
+#define CONFIG_NLS_CODEPAGE_857 1
+#define CONFIG_PCMCIA_IOCTL 1
+#define CONFIG_UIO_PDRV 1
+#define CONFIG_FB 1
+#define CONFIG_NLS_CODEPAGE_949 1
+#define CONFIG_SOUND 1
+#define CONFIG_IP_NF_ARPTABLES 1
+#define CONFIG_ARCH_FLATMEM_ENABLE 1
+#define CONFIG_NLS_CODEPAGE_869 1
+#define CONFIG_TMPFS 1
+#define CONFIG_QUOTA 1
+#define CONFIG_ASK_IP_FIB_HASH 1
+#define CONFIG_GENERIC_TIME 1
+#define CONFIG_CRYPTO_TWOFISH_COMMON 1
+#define CONFIG_PLIST 1
+#define CONFIG_FUTEX 1
+#define CONFIG_SERIO_LIBPS2 1
+#define CONFIG_WLAN_80211 1
+#define CONFIG_IP_NF_MATCH_ECN 1
+#define CONFIG_USB_NET_CDC_SUBSET_MODULE 1
+#define CONFIG_MISC_DEVICES 1
+#define CONFIG_BLOCK_COMPAT 1
+#define CONFIG_EXPERIMENTAL 1
+#define CONFIG_USB_EHCI_HCD 1
+#define CONFIG_INPUT 1
+#define CONFIG_NETFILTER_XT_MATCH_CONNLIMIT 1
+#define CONFIG_VIRT_TO_BUS 1
+#define CONFIG_BLK_DEV_CRYPTOLOOP 1
+#define CONFIG_INITRAMFS_ROOT_UID 0
+#define CONFIG_LOCALVERSION "-loongson-2f"
+#define CONFIG_USB_DEVICEFS 1
+#define CONFIG_MOUSE_BCM5974 1
+#define CONFIG_SCSI_SCAN_ASYNC 1
+#define CONFIG_ZLIB_INFLATE 1
+#define CONFIG_INIT_ENV_ARG_LIMIT 32
+#define CONFIG_IP_NF_ARPFILTER 1
+#define CONFIG_SUSPEND_FREEZER 1
+#define CONFIG_IOSCHED_DEADLINE 1
+#define CONFIG_USB_VIDEO_CLASS 1
+#define CONFIG_SCSI_SAS_LIBSAS 1
+#define CONFIG_NETFILTER_XT_TARGET_CONNMARK 1
+#define CONFIG_NF_CONNTRACK 1
+#define CONFIG_JFFS2_COMPRESSION_OPTIONS 1
+#define CONFIG_FRAMEBUFFER_CONSOLE 1
+#define CONFIG_BROADCOM_PHY_MODULE 1
+#define CONFIG_NF_CONNTRACK_AMANDA 1
+#define CONFIG_PCSPKR_PLATFORM 1
+#define CONFIG_NETFILTER_XT_MATCH_CONNBYTES 1
+#define CONFIG_SYSFS 1
+#define CONFIG_HZ_250 1
+#define CONFIG_USB_OHCI_HCD 1
+#define CONFIG_TCP_CONG_BIC_MODULE 1
+#define CONFIG_DEFAULT_DEADLINE 1
+#define CONFIG_IOSCHED_NOOP 1
+#define CONFIG_CPU_SUPPORTS_32BIT_KERNEL 1
+#define CONFIG_HID_DEBUG 1
+#define CONFIG_NETFILTER_XT_MATCH_STATISTIC 1
+#define CONFIG_NETFILTER_XT_TARGET_CLASSIFY 1
+#define CONFIG_HIGH_RES_TIMERS 1
+#define CONFIG_V4L_USB_DRIVERS 1
+#define CONFIG_NETFILTER_XT_MATCH_U32 1
+#define CONFIG_PM 1
+#define CONFIG_GENERIC_CLOCKEVENTS 1
+#define CONFIG_CRYPTO_BLOWFISH 1
+#define CONFIG_SERIAL_8250_EXTENDED 1
+#define CONFIG_IP_ROUTE_MULTIPATH 1
+#define CONFIG_LOCKDEP_SUPPORT 1
+#define CONFIG_NO_HZ 1
+#define CONFIG_MSDOS_PARTITION 1
+#define CONFIG_FB_CFB_IMAGEBLIT 1
+#define CONFIG_IP_NF_MANGLE 1
+#define CONFIG_CPU_SUPPORTS_64BIT_KERNEL 1
+#define CONFIG_CRYPTO_CAST5 1
+#define CONFIG_USB_UHCI_HCD 1
+#define CONFIG_USB_NET_RNDIS_WLAN_MODULE 1
+#define CONFIG_CRYPTO_CAST6 1
+#define CONFIG_HZ 250
+#define CONFIG_INPUT_POWERMATE_MODULE 1
+#define CONFIG_NETFILTER_XT_MATCH_HELPER 1
+#define CONFIG_MTD_NAND_IDS 1
+#define CONFIG_INET_DIAG 1
+#define CONFIG_NLS_ISO8859_1 1
+#define CONFIG_NET_ETHERNET 1
+#define CONFIG_NETFILTER_XT_MATCH_LENGTH 1
+#define CONFIG_MIPS_L1_CACHE_SHIFT 5
+#define CONFIG_DMA_NEED_PCI_MAP_STATE 1
+#define CONFIG_NLS_ISO8859_2 1
+#define CONFIG_SCSI_NETLINK 1
+#define CONFIG_NLS_ISO8859_3 1
+#define CONFIG_USB_OHCI_LITTLE_ENDIAN 1
+#define CONFIG_NLS_ISO8859_4 1
+#define CONFIG_SSB_POSSIBLE 1
+#define CONFIG_NLS_ISO8859_5 1
+#define CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP 1
+#define CONFIG_NLS_ISO8859_6 1
+#define CONFIG_VT 1
+#define CONFIG_TICK_ONESHOT 1
+#define CONFIG_NLS_ISO8859_7 1
+#define CONFIG_NLS_CODEPAGE_1250 1
+#define CONFIG_TMPFS_POSIX_ACL 1
+#define CONFIG_USB_ZD1201_MODULE 1
+#define CONFIG_CONNECTOR 1
+#define CONFIG_IP_NF_MATCH_TTL 1
+#define CONFIG_NLS_CODEPAGE_1251 1
+#define CONFIG_NLS_ISO8859_8 1
+#define CONFIG_USB_NET_RNDIS_HOST_MODULE 1
+#define CONFIG_VLAN_8021Q 1
+#define CONFIG_NETFILTER_XT_TARGET_TRACE 1
+#define CONFIG_RWSEM_GENERIC_SPINLOCK 1
+#define CONFIG_NLS_ISO8859_9 1
+#define CONFIG_UIO_PDRV_GENIRQ 1
+#define CONFIG_FONT_8x16 1
+#define CONFIG_NETFILTER 1
+#define CONFIG_PCMCIA_MODULE 1
+#define CONFIG_PCCARD_MODULE 1
+#define CONFIG_BASE_FULL 1
+#define CONFIG_CRC_CCITT 1
+#define CONFIG_IP_MULTICAST 1
+#define CONFIG_PREVENT_FIRMWARE_BUILD 1
+#define CONFIG_NET_IPGRE_BROADCAST 1
+#define CONFIG_SYSFS_DEPRECATED_V2 1
+#define CONFIG_MTD_BLOCK 1
+#define CONFIG_BLK_DEV_LOOP 1
+#define CONFIG_MIPS32_N32 1
+#define CONFIG_GENERIC_CMOS_UPDATE 1
+#define CONFIG_IP_NF_FILTER 1
+#define CONFIG_MIPS32_O32 1
+#define CONFIG_GENERIC_CALIBRATE_DELAY 1
+#define CONFIG_SYS_SUPPORTS_32BIT_KERNEL 1
+#define CONFIG_HAS_IOMEM 1
+#define CONFIG_MTD_CFI_UTIL 1
+#define CONFIG_NETFILTER_XT_MATCH_MULTIPORT 1
+#define CONFIG_NETFILTER_XT_MATCH_POLICY 1
+#define CONFIG_NETFILTER_XT_TARGET_NFLOG 1
+#define CONFIG_FW_LOADER 1
+#define CONFIG_CRYPTO_SHA512 1
+#define CONFIG_PNP_DEBUG 1
+#define CONFIG_NETFILTER_XT_MATCH_MAC 1
+#define CONFIG_EARLY_PRINTK 1
+#define CONFIG_NLS_ASCII 1
+#define CONFIG_VIDEO_DEV 1
+#define CONFIG_WIRELESS_EXT_SYSFS 1
+#define CONFIG_MODULE_FORCE_UNLOAD 1
+#define CONFIG_SYS_SUPPORTS_64BIT_KERNEL 1
+#define CONFIG_USB_GSPCA 1
+#define CONFIG_ISO9660_FS 1
+#define CONFIG_LOGO_LINUX_MONO 1
+#define CONFIG_PACKET 1
+#define CONFIG_CRYPTO_SHA256 1
+#define CONFIG_BSD_PROCESS_ACCT_V3 1
+#define CONFIG_FS_POSIX_ACL 1
+#define CONFIG_R8169_VLAN 1
+#define CONFIG_NETFILTER_XT_MATCH_STRING 1
+#define CONFIG_NF_CT_PROTO_GRE 1
+#define CONFIG_GENERIC_HARDIRQS 1
+#define CONFIG_VIDEO_ALLOW_V4L1 1
+#define CONFIG_FIB_RULES 1
+#define CONFIG_CRAMFS 1
+#define CONFIG_MOUSE_PS2 1
+#define CONFIG_SCSI_PROC_FS 1
+#define CONFIG_NETFILTER_XT_MATCH_TCPMSS 1
+#define CONFIG_NET_IPGRE_MODULE 1
+#define CONFIG_SND_SM501_SOC 1
+#define CONFIG_WIRELESS_EXT 1
+#define CONFIG_HIDRAW 1
+#define CONFIG_HW_RANDOM 1
+#define CONFIG_CRC_T10DIF 1
+#define CONFIG_CPU_HAS_SYNC 1
+#define CONFIG_LZO_COMPRESS 1
+#define CONFIG_INOTIFY_USER 1
+#define CONFIG_CRYPTO_CRC32C 1
+#define CONFIG_SYS_SUPPORTS_ARBIT_HZ 1
+#define CONFIG_MIPS32_COMPAT 1
+#define CONFIG_INPUT_PCSPKR_MODULE 1
+#define CONFIG_TRACE_IRQFLAGS_SUPPORT 1
+#define CONFIG_BSD_DISKLABEL 1
+#define CONFIG_LOGO_LINUX_VGA16 1
+#define CONFIG_COMPAT 1
+#define CONFIG_POSIX_MQUEUE 1
+#define CONFIG_USB_HIDINPUT_POWERBOOK 1
+#define CONFIG_SND_SOC_AC97_BUS 1
+#define CONFIG_SND_TIMER 1
+#define CONFIG_JOLIET 1
+#define CONFIG_8139TOO 1
+#define CONFIG_CRYPTO_SEQIV 1
+#define CONFIG_PHYLIB 1
+#define CONFIG_SYSFS_DEPRECATED 1
+#define CONFIG_SELECT_MEMORY_MODEL 1
+#define CONFIG_CRYPTO_TGR192 1
+#define CONFIG_DEFAULT_CUBIC 1
+#define CONFIG_SERIAL_8250_EXAR_ST16C554 1
+#define CONFIG_ISAPNP 1
+#define CONFIG_NETFILTER_XT_MATCH_ESP 1
+#define CONFIG_IP_NF_TARGET_CLUSTERIP 1
+#define CONFIG_ARCH_SUPPORTS_OPROFILE 1
+#define CONFIG_IP_NF_TARGET_REJECT 1
+#define CONFIG_ECRYPT_FS 1
+#define CONFIG_QSEMI_PHY_MODULE 1
+#define CONFIG_BLK_DEV_IDECD 1
+#define CONFIG_INET_XFRM_MODE_BEET 1
+#define CONFIG_BOOT_ELF32 1
+#define CONFIG_NFS_V4 1
+#define CONFIG_JBD 1
+#define CONFIG_USB_ARCH_HAS_HCD 1
+#define CONFIG_BLK_DEV_IDE_SATA 1
+#define CONFIG_CGROUP_NS 1
+#define CONFIG_MIPS_MT_DISABLED 1
+#define CONFIG_USB_NET_CDCETHER_MODULE 1
+#define CONFIG_DEFAULT_TCP_CONG "cubic"
+#define CONFIG_BSD_PROCESS_ACCT 1
+#define CONFIG_AFS_FS_MODULE 1
+#define CONFIG_IDE 1
+#define CONFIG_BFS_FS 1
+#define CONFIG_FAT_FS 1
+#define CONFIG_NF_CONNTRACK_IRC 1
+#define CONFIG_INPUT_UINPUT_MODULE 1
+#define CONFIG_CRYPTO_BLKCIPHER 1
+#define CONFIG_IP_MROUTE 1
+#define CONFIG_FAIR_GROUP_SCHED 1
+#define CONFIG_SPARSEMEM_STATIC 1
+#define CONFIG_DMADEVICES 1
+#define CONFIG_HID 1
+#define CONFIG_IP_NF_RAW 1
+#define CONFIG_NF_CONNTRACK_H323 1
+#define CONFIG_EFS_FS 1
+#define CONFIG_FAT_DEFAULT_CODEPAGE 437
+#define CONFIG_ATA 1
+#define CONFIG_IP_NF_TARGET_NETMAP 1
+#define CONFIG_NF_NAT 1
+#define CONFIG_UDF_FS_MODULE 1
+#define CONFIG_SCTP_HMAC_MD5 1
+#define CONFIG_NF_NAT_AMANDA 1
+#define CONFIG_NLS_ISO8859_13 1
+#define CONFIG_SSB_SPROM 1
+#define CONFIG_PRINTK 1
+#define CONFIG_NLS_ISO8859_14 1
+#define CONFIG_NCP_FS_MODULE 1
+#define CONFIG_RPCSEC_GSS_SPKM3_MODULE 1
+#define CONFIG_POWER_SUPPLY 1
+#define CONFIG_NLS_ISO8859_15 1
+#define CONFIG_SMB_FS_MODULE 1
+#define CONFIG_NF_NAT_NEEDED 1
+#define CONFIG_SUNRPC 1
+#define CONFIG_FS_MBCACHE 1
+#define CONFIG_SERIAL_8250_NR_UARTS 6
+#define CONFIG_LLC 1
+#define CONFIG_XFRM_USER_MODULE 1
+#define CONFIG_SYS_SUPPORTS_ZBOOT 1
+#define CONFIG_CRC_ITU_T 1
+#define CONFIG_DEV_APPLETALK 1
+#define CONFIG_PCI 1
+#define CONFIG_USB_PHIDGETSERVO 1
+#define CONFIG_VIDEO_V4L1 1
+#define CONFIG_MOUSE_APPLETOUCH 1
+#define CONFIG_INITRAMFS_SOURCE "~/ramfs/cww.cpio.gz"
+#define CONFIG_IKCONFIG_PROC 1
+#define CONFIG_ISA 1
+#define CONFIG_ZISOFS 1
+#define CONFIG_VIDEO_V4L2 1
+#define CONFIG_BUG 1
+#define CONFIG_CRYPTO_HW 1
+#define CONFIG_NFS_FS 1
+#define CONFIG_MII 1
+#define CONFIG_NF_CONNTRACK_FTP 1
+#define CONFIG_CGROUP_DEVICE 1
+#define CONFIG_NETWORK_FILESYSTEMS 1
+#define CONFIG_IP_NF_ARP_MANGLE 1
+#define CONFIG_NF_CONNTRACK_SIP 1
+#define CONFIG_CRYPTO 1
+#define CONFIG_SYSCTL 1
+#define CONFIG_HAVE_OPROFILE 1
+#define CONFIG_CDROM_PKTCDVD 1
+#define CONFIG_SND 1
+#define CONFIG_CICADA_PHY_MODULE 1
+#define CONFIG_MTD 1
+#define CONFIG_UFS_FS 1
+#define CONFIG_WAN 1
+#define CONFIG_NETDEV_1000 1
+#define CONFIG_ZONE_DMA_FLAG 0
+#define CONFIG_IP_NF_TARGET_ECN 1
+#define CONFIG_NET 1
+#define CONFIG_JFFS2_SUMMARY 1
+#define CONFIG_MODULE_UNLOAD 1
+#define CONFIG_CPU_LOONGSON2 1
+#define CONFIG_SSB_MODULE 1
+#define CONFIG_FS_XIP 1
+#define CONFIG_RTC 1
+#define CONFIG_STANDALONE 1
+#define CONFIG_TEXTSEARCH_BM 1
+#define CONFIG_NETFILTER_XT_MATCH_IPRANGE 1
+#define CONFIG_KALLSYMS_EXTRA_PASS 1
+#define CONFIG_MAC_PARTITION 1
+#define CONFIG_NETDEVICES 1
+#define CONFIG_USB 1
+#define CONFIG_INET_TCP_DIAG 1
+#define CONFIG_JFFS2_ZLIB 1
+#define CONFIG_PRINT_QUOTA_WARNING 1
+#define CONFIG_SCSI_ACARD 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_NLS 1
+#define CONFIG_UIO 1
+#define CONFIG_CRYPTO_ALGAPI 1
+#define CONFIG_PNP 1
+#define CONFIG_SERIAL_8250 1
+#define CONFIG_SND_SEQUENCER 1
+#define CONFIG_MTD_CFI_I1 1
+#define CONFIG_MMU 1
+#define CONFIG_INPUT_FF_MEMLESS 1
+#define CONFIG_USB_NET_DM9601_MODULE 1
+#define CONFIG_BLK_DEV_RAM_SIZE 32768
+#define CONFIG_MTD_CFI_I2 1
+#define CONFIG_PCI_LEGACY 1
+#define CONFIG_MTD_NAND_TOPSTAR 1
+#define CONFIG_IPX 1
+#define CONFIG_EXT2_FS_SECURITY 1
+#define CONFIG_SSB_PCMCIAHOST_POSSIBLE 1
+#define CONFIG_IOSCHED_AS 1
+#define CONFIG_CRYPTO_KHAZAD 1
+#define CONFIG_EXT3_FS_SECURITY 1
+#define CONFIG_IP_NF_TARGET_LOG 1
+#define CONFIG_NF_CT_PROTO_UDPLITE 1
+#define CONFIG_BASE_SMALL 0
+#define CONFIG_SND_AC97_CODEC 1
+#define CONFIG_MTD_GEN_PROBE 1
+#define CONFIG_NETFILTER_XT_MATCH_COMMENT 1
+#define CONFIG_NF_CT_PROTO_DCCP 1
+#define CONFIG_BINFMT_ELF 1
+#define CONFIG_JFFS2_FS_WRITEBUFFER 1
+#define CONFIG_SND_SUPPORT_OLD_API 1
+#define CONFIG_INPUT_ATI_REMOTE_MODULE 1
+#define CONFIG_SERIO_I8042 1
+#define CONFIG_SND_PCM_OSS_PLUGINS 1
+#define CONFIG_SCSI_ISCSI_ATTRS 1
+#define CONFIG_IP_NF_TARGET_MASQUERADE 1
+#define CONFIG_USB_NET_GL620A_MODULE 1
+#define CONFIG_SCSI_LOWLEVEL 1
+#define CONFIG_BITREVERSE 1
+#define CONFIG_NETFILTER_XT_MATCH_RATEEST 1
+#define CONFIG_TEXTSEARCH 1
+#define CONFIG_TCP_CONG_HTCP 1
+#define CONFIG_LOG_BUF_SHIFT 17
+#define CONFIG_CMDLINE ""
+#define CONFIG_SGI_PARTITION 1
+#define CONFIG_INPUT_YEALINK_MODULE 1
+#define CONFIG_MTD_CONCAT 1
+#define CONFIG_IP_ROUTE_VERBOSE 1
+#define CONFIG_ARCH_POPULATES_NODE_MAP 1
+#define CONFIG_USB_HIDDEV 1
+#define CONFIG_NETFILTER_XT_MATCH_DCCP 1
+#define CONFIG_DUMMY_CONSOLE 1
+#define CONFIG_NF_CT_NETLINK 1
+#define CONFIG_CRYPTO_DEV_HIFN_795X 1
diff -uNra linux-2.6.27.6/include/linux/decompress/bunzip2.h linux-2.6.27.6.yaffs/include/linux/decompress/bunzip2.h
--- linux-2.6.27.6/include/linux/decompress/bunzip2.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/decompress/bunzip2.h	2011-05-16 21:59:10.000000000 +0800
@@ -0,0 +1,10 @@
+#ifndef DECOMPRESS_BUNZIP2_H
+#define DECOMPRESS_BUNZIP2_H
+
+int bunzip2(unsigned char *inbuf, int len,
+	    int(*fill)(void*, unsigned int),
+	    int(*flush)(void*, unsigned int),
+	    unsigned char *output,
+	    int *pos,
+	    void(*error)(char *x));
+#endif
diff -uNra linux-2.6.27.6/include/linux/decompress/generic.h linux-2.6.27.6.yaffs/include/linux/decompress/generic.h
--- linux-2.6.27.6/include/linux/decompress/generic.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/decompress/generic.h	2011-05-16 21:59:10.000000000 +0800
@@ -0,0 +1,39 @@
+#ifndef DECOMPRESS_GENERIC_H
+#define DECOMPRESS_GENERIC_H
+
+typedef int (*decompress_fn) (unsigned char *inbuf, int len,
+			      int(*fill)(void*, unsigned int),
+			      int(*flush)(void*, unsigned int),
+			      unsigned char *outbuf,
+			      int *posp,
+			      void(*error)(char *x));
+
+/* inbuf   - input buffer
+ *len     - len of pre-read data in inbuf
+ *fill    - function to fill inbuf when empty
+ *flush   - function to write out outbuf
+ *outbuf  - output buffer
+ *posp    - if non-null, input position (number of bytes read) will be
+ *	  returned here
+ *
+ *If len != 0, inbuf should contain all the necessary input data, and fill
+ *should be NULL
+ *If len = 0, inbuf can be NULL, in which case the decompressor will allocate
+ *the input buffer.  If inbuf != NULL it must be at least XXX_IOBUF_SIZE bytes.
+ *fill will be called (repeatedly...) to read data, at most XXX_IOBUF_SIZE
+ *bytes should be read per call.  Replace XXX with the appropriate decompressor
+ *name, i.e. LZMA_IOBUF_SIZE.
+ *
+ *If flush = NULL, outbuf must be large enough to buffer all the expected
+ *output.  If flush != NULL, the output buffer will be allocated by the
+ *decompressor (outbuf = NULL), and the flush function will be called to
+ *flush the output buffer at the appropriate time (decompressor and stream
+ *dependent).
+ */
+
+
+/* Utility routine to detect the decompression method */
+decompress_fn decompress_method(const unsigned char *inbuf, int len,
+				const char **name);
+
+#endif
diff -uNra linux-2.6.27.6/include/linux/decompress/inflate.h linux-2.6.27.6.yaffs/include/linux/decompress/inflate.h
--- linux-2.6.27.6/include/linux/decompress/inflate.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/decompress/inflate.h	2011-05-16 21:59:10.000000000 +0800
@@ -0,0 +1,13 @@
+#ifndef INFLATE_H
+#define INFLATE_H
+
+/* Other housekeeping constants */
+#define INBUFSIZ 4096
+
+int gunzip(unsigned char *inbuf, int len,
+	   int(*fill)(void*, unsigned int),
+	   int(*flush)(void*, unsigned int),
+	   unsigned char *output,
+	   int *pos,
+	   void(*error_fn)(char *x));
+#endif
diff -uNra linux-2.6.27.6/include/linux/decompress/mm.h linux-2.6.27.6.yaffs/include/linux/decompress/mm.h
--- linux-2.6.27.6/include/linux/decompress/mm.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/decompress/mm.h	2011-05-16 21:59:10.000000000 +0800
@@ -0,0 +1,97 @@
+/*
+ * linux/compr_mm.h
+ *
+ * Memory management for pre-boot and ramdisk uncompressors
+ *
+ * Authors: Alain Knaff <alain@knaff.lu>
+ *
+ */
+
+#ifndef DECOMPR_MM_H
+#define DECOMPR_MM_H
+
+#ifdef STATIC
+
+/* Code active when included from pre-boot environment: */
+
+/*
+ * Some architectures want to ensure there is no local data in their
+ * pre-boot environment, so that data can arbitarily relocated (via
+ * GOT references).  This is achieved by defining STATIC_RW_DATA to
+ * be null.
+ */
+#ifndef STATIC_RW_DATA
+#define STATIC_RW_DATA static
+#endif
+
+/* A trivial malloc implementation, adapted from
+ *  malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
+ */
+STATIC_RW_DATA unsigned long malloc_ptr;
+STATIC_RW_DATA int malloc_count;
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size < 0)
+		return NULL;
+	if (!malloc_ptr)
+		malloc_ptr = free_mem_ptr;
+
+	malloc_ptr = (malloc_ptr + 3) & ~3;     /* Align */
+
+	p = (void *)malloc_ptr;
+	malloc_ptr += size;
+
+	if (free_mem_end_ptr && malloc_ptr >= free_mem_end_ptr)
+		return NULL;
+
+	malloc_count++;
+	return p;
+}
+
+static void free(void *where)
+{
+	malloc_count--;
+	if (!malloc_count)
+		malloc_ptr = free_mem_ptr;
+}
+
+#define large_malloc(a) malloc(a)
+#define large_free(a) free(a)
+
+#define set_error_fn(x)
+
+#define INIT
+
+#else /* STATIC */
+
+/* Code active when compiled standalone for use when loading ramdisk: */
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/vmalloc.h>
+
+/* Use defines rather than static inline in order to avoid spurious
+ * warnings when not needed (indeed large_malloc / large_free are not
+ * needed by inflate */
+
+#define malloc(a) kmalloc(a, GFP_KERNEL)
+#define free(a) kfree(a)
+
+#define large_malloc(a) vmalloc(a)
+#define large_free(a) vfree(a)
+
+static void(*error)(char *m);
+#define set_error_fn(x) error = x;
+
+#define INIT __init
+#define STATIC
+
+#include <linux/init.h>
+
+#endif /* STATIC */
+
+#endif /* DECOMPR_MM_H */
diff -uNra linux-2.6.27.6/include/linux/decompress/unlzma.h linux-2.6.27.6.yaffs/include/linux/decompress/unlzma.h
--- linux-2.6.27.6/include/linux/decompress/unlzma.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/decompress/unlzma.h	2011-05-16 21:59:10.000000000 +0800
@@ -0,0 +1,12 @@
+#ifndef DECOMPRESS_UNLZMA_H
+#define DECOMPRESS_UNLZMA_H
+
+int unlzma(unsigned char *, int,
+	   int(*fill)(void*, unsigned int),
+	   int(*flush)(void*, unsigned int),
+	   unsigned char *output,
+	   int *posp,
+	   void(*error)(char *x)
+	);
+
+#endif
diff -uNra linux-2.6.27.6/include/linux/decompress/unlzo.h linux-2.6.27.6.yaffs/include/linux/decompress/unlzo.h
--- linux-2.6.27.6/include/linux/decompress/unlzo.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/decompress/unlzo.h	2011-05-16 21:59:10.000000000 +0800
@@ -0,0 +1,10 @@
+#ifndef DECOMPRESS_UNLZO_H
+#define DECOMPRESS_UNLZO_H
+
+int unlzo(unsigned char *inbuf, int len,
+	int(*fill)(void*, unsigned int),
+	int(*flush)(void*, unsigned int),
+	unsigned char *output,
+	int *pos,
+	void(*error)(char *x));
+#endif
diff -uNra linux-2.6.27.6/include/linux/device.h linux-2.6.27.6.yaffs/include/linux/device.h
--- linux-2.6.27.6/include/linux/device.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/device.h	2011-05-08 18:02:36.000000000 +0800
@@ -539,7 +539,8 @@
 #define dev_info(dev, format, arg...)		\
 	dev_printk(KERN_INFO , dev , format , ## arg)
 
-#ifdef DEBUG
+#if 0
+//#ifdef DEBUG
 #define dev_dbg(dev, format, arg...)		\
 	dev_printk(KERN_DEBUG , dev , format , ## arg)
 #else
diff -uNra linux-2.6.27.6/include/linux/input.h linux-2.6.27.6.yaffs/include/linux/input.h
--- linux-2.6.27.6/include/linux/input.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/input.h	2011-05-08 18:02:37.000000000 +0800
@@ -1290,7 +1290,9 @@
 
 static inline void input_sync(struct input_dev *dev)
 {
+//	printk("--->>>----%s----------\n",__func__);
 	input_event(dev, EV_SYN, SYN_REPORT, 0);
+//	printk("---<<<----%s----------\n",__func__);
 }
 
 void input_set_capability(struct input_dev *dev, unsigned int type, unsigned int code);
diff -uNra linux-2.6.27.6/include/linux/interrupt.h linux-2.6.27.6.yaffs/include/linux/interrupt.h
--- linux-2.6.27.6/include/linux/interrupt.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/interrupt.h	2011-05-08 18:02:37.000000000 +0800
@@ -55,6 +55,8 @@
 #define IRQF_NOBALANCING	0x00000800
 #define IRQF_IRQPOLL		0x00001000
 
+#define SA_SHIRQ		IRQF_SHARED 
+
 typedef irqreturn_t (*irq_handler_t)(int, void *);
 
 struct irqaction {
diff -uNra linux-2.6.27.6/include/linux/mc146818rtc.h linux-2.6.27.6.yaffs/include/linux/mc146818rtc.h
--- linux-2.6.27.6/include/linux/mc146818rtc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/mc146818rtc.h	2011-05-08 18:02:36.000000000 +0800
@@ -42,17 +42,17 @@
  **********************************************************************/
 #define RTC_SECONDS		0
 #define RTC_SECONDS_ALARM	1
-#define RTC_MINUTES		2
+#define RTC_MINUTES		1
 #define RTC_MINUTES_ALARM	3
-#define RTC_HOURS		4
+#define RTC_HOURS		2
 #define RTC_HOURS_ALARM		5
 /* RTC_*_alarm is always true if 2 MSBs are set */
 # define RTC_ALARM_DONT_CARE 	0xC0
 
 #define RTC_DAY_OF_WEEK		6
-#define RTC_DAY_OF_MONTH	7
-#define RTC_MONTH		8
-#define RTC_YEAR		9
+#define RTC_DAY_OF_MONTH	4
+#define RTC_MONTH		5
+#define RTC_YEAR		6
 
 /* control registers - Moto names
  */
diff -uNra linux-2.6.27.6/include/linux/parport_2410_16c552.h linux-2.6.27.6.yaffs/include/linux/parport_2410_16c552.h
--- linux-2.6.27.6/include/linux/parport_2410_16c552.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/parport_2410_16c552.h	2011-05-08 18:02:37.000000000 +0800
@@ -0,0 +1,7 @@
+#define brd_16c552_base 0xffffffffbe0000e0 
+//#define brd_16c552_parportbase brd_16c552_base+0x14 
+#define brd_16c552_parportbase brd_16c552_base+0x0 
+#define brd_16c552_parportdata brd_16c552_parportbase+0 
+#define brd_16c552_parportstat brd_16c552_parportbase+1 
+#define brd_16c552_parportctl brd_16c552_parportbase+2 
+ 
diff -uNra linux-2.6.27.6/include/linux/parport_pc.h linux-2.6.27.6.yaffs/include/linux/parport_pc.h
--- linux-2.6.27.6/include/linux/parport_pc.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/parport_pc.h	2011-05-08 18:02:37.000000000 +0800
@@ -64,12 +64,14 @@
 #ifdef DEBUG_PARPORT
 	printk (KERN_DEBUG "parport_pc_write_data(%p,0x%02x)\n", p, d);
 #endif
-	outb(d, DATA(p));
+//printk("-addr: %lx,data:%lx---\n",p,DATA(p));
+	writeb(d, DATA(p));
 }
 
 static __inline__ unsigned char parport_pc_read_data(struct parport *p)
 {
-	unsigned char val = inb (DATA (p));
+	//unsigned char val = inb (DATA (p));
+	unsigned char val = readb (DATA (p));
 #ifdef DEBUG_PARPORT
 	printk (KERN_DEBUG "parport_pc_read_data(%p) = 0x%02x\n",
 		p, val);
@@ -81,9 +83,12 @@
 static inline void dump_parport_state (char *str, struct parport *p)
 {
 	/* here's hoping that reading these ports won't side-effect anything underneath */
-	unsigned char ecr = inb (ECONTROL (p));
-	unsigned char dcr = inb (CONTROL (p));
-	unsigned char dsr = inb (STATUS (p));
+	//unsigned char ecr = inb (ECONTROL (p));
+	unsigned char ecr = readb (ECONTROL (p));
+	//unsigned char dcr = inb (CONTROL (p));
+	unsigned char dcr = readb (CONTROL (p));
+	//unsigned char dsr = inb (STATUS (p));
+	unsigned char dsr = readb (STATUS (p));
 	static const char *const ecr_modes[] = {"SPP", "PS2", "PPFIFO", "ECP", "xXx", "yYy", "TST", "CFG"};
 	const struct parport_pc_private *priv = p->physport->private_data;
 	int i;
@@ -96,7 +101,8 @@
 	if (ecr & 0x01) printk (",f_empty");
 	for (i=0; i<2; i++) {
 		printk ("]  dcr(%s)=[", i ? "soft" : "hard");
-		dcr = i ? priv->ctr : inb (CONTROL (p));
+		//dcr = i ? priv->ctr : inb (CONTROL (p));
+		dcr = i ? priv->ctr : writeb (CONTROL (p));
 	
 		if (dcr & 0x20) {
 			printk ("rev");
@@ -137,7 +143,8 @@
 #endif
 	ctr = (ctr & ~mask) ^ val;
 	ctr &= priv->ctr_writable; /* only write writable bits. */
-	outb (ctr, CONTROL (p));
+	//outb (ctr, CONTROL (p));
+	writeb (ctr, CONTROL (p));
 	priv->ctr = ctr;	/* Update soft copy */
 	return ctr;
 }
@@ -209,7 +216,8 @@
 
 static __inline__ unsigned char parport_pc_read_status(struct parport *p)
 {
-	return inb(STATUS(p));
+	//return inb(STATUS(p));
+	return readb(STATUS(p));
 }
 
 
diff -uNra linux-2.6.27.6/include/linux/sm501.h linux-2.6.27.6.yaffs/include/linux/sm501.h
--- linux-2.6.27.6/include/linux/sm501.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/sm501.h	2011-05-08 18:02:37.000000000 +0800
@@ -1,174 +1,167 @@
-/* include/linux/sm501.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *	Vincent Sanders <vince@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-extern int sm501_unit_power(struct device *dev,
-			    unsigned int unit, unsigned int to);
-
-extern unsigned long sm501_set_clock(struct device *dev,
-				     int clksrc, unsigned long freq);
-
-extern unsigned long sm501_find_clock(struct device *dev,
-				      int clksrc, unsigned long req_freq);
-
-/* sm501_misc_control
- *
- * Modify the SM501's MISC_CONTROL register
-*/
-
-extern int sm501_misc_control(struct device *dev,
-			      unsigned long set, unsigned long clear);
-
-/* sm501_modify_reg
- *
- * Modify a register in the SM501 which may be shared with other
- * drivers.
-*/
-
-extern unsigned long sm501_modify_reg(struct device *dev,
-				      unsigned long reg,
-				      unsigned long set,
-				      unsigned long clear);
-
-
-/* Platform data definitions */
-
-#define SM501FB_FLAG_USE_INIT_MODE	(1<<0)
-#define SM501FB_FLAG_DISABLE_AT_EXIT	(1<<1)
-#define SM501FB_FLAG_USE_HWCURSOR	(1<<2)
-#define SM501FB_FLAG_USE_HWACCEL	(1<<3)
-#define SM501FB_FLAG_PANEL_NO_FPEN	(1<<4)
-#define SM501FB_FLAG_PANEL_NO_VBIASEN	(1<<5)
-#define SM501FB_FLAG_PANEL_INV_FPEN	(1<<6)
-#define SM501FB_FLAG_PANEL_INV_VBIASEN	(1<<7)
-
-struct sm501_platdata_fbsub {
-	struct fb_videomode	*def_mode;
-	unsigned int		 def_bpp;
-	unsigned long		 max_mem;
-	unsigned int		 flags;
-};
-
-enum sm501_fb_routing {
-	SM501_FB_OWN		= 0,	/* CRT=>CRT, Panel=>Panel */
-	SM501_FB_CRT_PANEL	= 1,	/* Panel=>CRT, Panel=>Panel */
-};
-
-/* sm501_platdata_fb flag field bit definitions */
-
-#define SM501_FBPD_SWAP_FB_ENDIAN	(1<<0)	/* need to endian swap */
-
-/* sm501_platdata_fb
- *
- * configuration data for the framebuffer driver
-*/
-
-struct sm501_platdata_fb {
-	enum sm501_fb_routing		 fb_route;
-	unsigned int			 flags;
-	struct sm501_platdata_fbsub	*fb_crt;
-	struct sm501_platdata_fbsub	*fb_pnl;
-};
-
-/* gpio i2c
- *
- * Note, we have to pass in the bus number, as the number used will be
- * passed to the i2c-gpio driver's platform_device.id, subsequently used
- * to register the i2c bus.
-*/
-
-struct sm501_platdata_gpio_i2c {
-	unsigned int		bus_num;
-	unsigned int		pin_sda;
-	unsigned int		pin_scl;
-	int			udelay;
-	int			timeout;
-};
-
-/* sm501_initdata
- *
- * use for initialising values that may not have been setup
- * before the driver is loaded.
-*/
-
-struct sm501_reg_init {
-	unsigned long		set;
-	unsigned long		mask;
-};
-
-#define SM501_USE_USB_HOST	(1<<0)
-#define SM501_USE_USB_SLAVE	(1<<1)
-#define SM501_USE_SSP0		(1<<2)
-#define SM501_USE_SSP1		(1<<3)
-#define SM501_USE_UART0		(1<<4)
-#define SM501_USE_UART1		(1<<5)
-#define SM501_USE_FBACCEL	(1<<6)
-#define SM501_USE_AC97		(1<<7)
-#define SM501_USE_I2S		(1<<8)
-#define SM501_USE_GPIO		(1<<9)
-
-#define SM501_USE_ALL		(0xffffffff)
-
-struct sm501_initdata {
-	struct sm501_reg_init	gpio_low;
-	struct sm501_reg_init	gpio_high;
-	struct sm501_reg_init	misc_timing;
-	struct sm501_reg_init	misc_control;
-
-	unsigned long		devices;
-	unsigned long		mclk;		/* non-zero to modify */
-	unsigned long		m1xclk;		/* non-zero to modify */
-};
-
-/* sm501_init_gpio
- *
- * default gpio settings
-*/
-
-struct sm501_init_gpio {
-	struct sm501_reg_init	gpio_data_low;
-	struct sm501_reg_init	gpio_data_high;
-	struct sm501_reg_init	gpio_ddr_low;
-	struct sm501_reg_init	gpio_ddr_high;
-};
-
-#define SM501_FLAG_SUSPEND_OFF		(1<<4)
-
-/* sm501_platdata
- *
- * This is passed with the platform device to allow the board
- * to control the behaviour of the SM501 driver(s) which attach
- * to the device.
- *
-*/
-
-struct sm501_platdata {
-	struct sm501_initdata		*init;
-	struct sm501_init_gpio		*init_gpiop;
-	struct sm501_platdata_fb	*fb;
-
-	int				 flags;
-	int				 gpio_base;
-
-	int	(*get_power)(struct device *dev);
-	int	(*set_power)(struct device *dev, unsigned int on);
-
-	struct sm501_platdata_gpio_i2c	*gpio_i2c;
-	unsigned int			 gpio_i2c_nr;
-};
+/* include/linux/sm501.h
+ *
+ * Copyright (C) 2010 SiliconMotion Inc.
+ * Copyright (c) 2006 Simtec Electronics
+ *
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	Vincent Sanders <vince@simtec.co.uk>
+  *	Boyod Yang <boyoddev@gmail.com>
+ *	
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+#ifndef _LINUX_SM501_CORE
+#define _LINUX_SM501_CORE
+
+//#define USE_SYSTEM_MEMORY
+//#define B_DEBUG
+//#define SMI_DEBUG
+
+
+#include <linux/fb.h>
+#include <linux/module.h>
+
+#ifdef B_DEBUG
+#define b_dbg printk
+#else
+#define b_dbg(format, arg...) do {} while (0)
+#endif
+#ifdef SMI_DEBUG
+#define smi_dbg printk
+#else
+#define smi_dbg(format, arg...) do {} while (0)
+#endif
+
+#ifndef CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE
+#define CONFIG_SMIVGX_UART_OUTPUT_BUF_SIZE 1024
+#endif
+
+#ifdef CONFIG_SM501_USE_EXTERNAL_MEMORY
+#define USB_DMA_BUFFER_SIZE 0x80000
+#else
+#define USB_DMA_BUFFER_SIZE 0x80000
+#endif
+
+extern resource_size_t sm50x_mem_size;
+extern unsigned long SmRead8(unsigned long nOffset);
+extern unsigned long SmRead16(unsigned long nOffset);
+extern unsigned long SmRead32(unsigned long nOffset);
+extern const unsigned char __iomem *  SmIoAddress();
+
+extern void SmWrite8(unsigned long nOffset, unsigned long nData);
+extern void SmWrite16(unsigned long nOffset, unsigned long nData);
+extern void SmWrite32(unsigned long nOffset, unsigned long nData);
+
+extern void SmMemset(unsigned long nOffset, unsigned char val, int count);
+
+extern unsigned long sm501_find_clock(int clksrc, unsigned long req_freq);
+extern unsigned long sm501_set_clock(struct device *dev, int clksrc, unsigned long req_freq);
+extern void sm501_set_gate( unsigned long gate);
+extern void sm501_configure_gpio(unsigned int gpio, unsigned char mode);
+
+
+#define MHZ (1000 * 1000)
+
+/* Platform data definitions */
+
+#define SM501FB_FLAG_USE_INIT_MODE	(1<<0)
+#define SM501FB_FLAG_DISABLE_AT_EXIT	(1<<1)
+#define SM501FB_FLAG_USE_HWCURSOR	(1<<2)
+#define SM501FB_FLAG_USE_HWACCEL	(1<<3)
+
+
+typedef enum _panel_state_t
+{
+	PANEL_OFF,
+	PANEL_ON,
+}
+panel_state_t;
+
+struct sm501_platdata_fbsub {
+	struct fb_videomode	*def_mode;
+	unsigned int		 def_bpp;
+	unsigned long		 max_mem;
+	unsigned int		 flags;
+};
+
+/* sm501_platdata_fb flag field bit definitions */
+
+#define SM501_FBPD_SWAP_FB_ENDIAN	(1<<0)	/* need to endian swap */
+
+
+enum sm501_fb_routing {
+	SM501_FB_OWN		= 0,	/* CRT=>CRT, Panel=>Panel */
+	SM501_FB_CRT_PANEL	= 1,	/* Panel=>CRT, Panel=>Panel */
+};
+
+/* sm501_platdata_fb
+ *
+ * configuration data for the framebuffer driver
+*/
+
+struct sm501_platdata_fb {
+	enum sm501_fb_routing		 fb_route;
+	unsigned int			 flags;   /*For big endian or other. ...*/
+	struct sm501_platdata_fbsub	*fb_crt;
+	struct sm501_platdata_fbsub	*fb_pnl;
+};
+
+
+#define SM501_USE_USB_HOST	(1<<0)
+#define SM501_USE_FB		(1<<1)
+#define SM501_USE_SSP0		(1<<2)
+#define SM501_USE_SSP1		(1<<3)
+#define SM501_USE_UART0		(1<<4)
+#define SM501_USE_UART1		(1<<5)
+#define SM501_USE_FBACCEL	(1<<6)
+#define SM501_USE_AC97		(1<<7)
+#define SM501_USE_I2S		(1<<8)
+#define SM501_USE_GPIO      (1<<9)
+#define SM501_USE_I2C		(1<<11)
+
+#define SM501_USE_ALL		(0xFFFFFFFF)
+
+/* panel clock */
+#define SM501_CLOCK_P2XCLK		(24)
+/* crt clock */
+#define SM501_CLOCK_V2XCLK		(16)
+/* main clock */
+#define SM501_CLOCK_MCLK		(8)
+/* SDRAM controller clock */
+#define SM501_CLOCK_M1XCLK		(0)
+
+struct sm501_initdata {
+	unsigned int	 	flags;     /*For big endian or other. ...*/
+	unsigned int		devices;
+	unsigned long		mclk;		/* non-zero to modify */
+	unsigned long		m1xclk;		/* non-zero to modify */
+};
+
+
+/* sm501_platdata
+ *
+ * This is passed with the platform device to allow the board
+ * to control the behaviour of the SM501 driver(s) which attach
+ * to the device.
+ *
+*/
+
+struct sm501_platdata {
+	struct sm501_initdata		*init;
+	struct sm501_platdata_fb	*fb;
+	int             gpio_base; 	
+};
+
+
+#endif
+
diff -uNra linux-2.6.27.6/include/linux/sm501.h.bak linux-2.6.27.6.yaffs/include/linux/sm501.h.bak
--- linux-2.6.27.6/include/linux/sm501.h.bak	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/sm501.h.bak	2011-05-08 18:02:37.000000000 +0800
@@ -0,0 +1,174 @@
+/* include/linux/sm501.h
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	Vincent Sanders <vince@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+extern int sm501_unit_power(struct device *dev,
+			    unsigned int unit, unsigned int to);
+
+extern unsigned long sm501_set_clock(struct device *dev,
+				     int clksrc, unsigned long freq);
+
+extern unsigned long sm501_find_clock(struct device *dev,
+				      int clksrc, unsigned long req_freq);
+
+/* sm501_misc_control
+ *
+ * Modify the SM501's MISC_CONTROL register
+*/
+
+extern int sm501_misc_control(struct device *dev,
+			      unsigned long set, unsigned long clear);
+
+/* sm501_modify_reg
+ *
+ * Modify a register in the SM501 which may be shared with other
+ * drivers.
+*/
+
+extern unsigned long sm501_modify_reg(struct device *dev,
+				      unsigned long reg,
+				      unsigned long set,
+				      unsigned long clear);
+
+
+/* Platform data definitions */
+
+#define SM501FB_FLAG_USE_INIT_MODE	(1<<0)
+#define SM501FB_FLAG_DISABLE_AT_EXIT	(1<<1)
+#define SM501FB_FLAG_USE_HWCURSOR	(1<<2)
+#define SM501FB_FLAG_USE_HWACCEL	(1<<3)
+#define SM501FB_FLAG_PANEL_NO_FPEN	(1<<4)
+#define SM501FB_FLAG_PANEL_NO_VBIASEN	(1<<5)
+#define SM501FB_FLAG_PANEL_INV_FPEN	(1<<6)
+#define SM501FB_FLAG_PANEL_INV_VBIASEN	(1<<7)
+
+struct sm501_platdata_fbsub {
+	struct fb_videomode	*def_mode;
+	unsigned int		 def_bpp;
+	unsigned long		 max_mem;
+	unsigned int		 flags;
+};
+
+enum sm501_fb_routing {
+	SM501_FB_OWN		= 0,	/* CRT=>CRT, Panel=>Panel */
+	SM501_FB_CRT_PANEL	= 1,	/* Panel=>CRT, Panel=>Panel */
+};
+
+/* sm501_platdata_fb flag field bit definitions */
+
+#define SM501_FBPD_SWAP_FB_ENDIAN	(1<<0)	/* need to endian swap */
+
+/* sm501_platdata_fb
+ *
+ * configuration data for the framebuffer driver
+*/
+
+struct sm501_platdata_fb {
+	enum sm501_fb_routing		 fb_route;
+	unsigned int			 flags;
+	struct sm501_platdata_fbsub	*fb_crt;
+	struct sm501_platdata_fbsub	*fb_pnl;
+};
+
+/* gpio i2c
+ *
+ * Note, we have to pass in the bus number, as the number used will be
+ * passed to the i2c-gpio driver's platform_device.id, subsequently used
+ * to register the i2c bus.
+*/
+
+struct sm501_platdata_gpio_i2c {
+	unsigned int		bus_num;
+	unsigned int		pin_sda;
+	unsigned int		pin_scl;
+	int			udelay;
+	int			timeout;
+};
+
+/* sm501_initdata
+ *
+ * use for initialising values that may not have been setup
+ * before the driver is loaded.
+*/
+
+struct sm501_reg_init {
+	unsigned long		set;
+	unsigned long		mask;
+};
+
+#define SM501_USE_USB_HOST	(1<<0)
+#define SM501_USE_USB_SLAVE	(1<<1)
+#define SM501_USE_SSP0		(1<<2)
+#define SM501_USE_SSP1		(1<<3)
+#define SM501_USE_UART0		(1<<4)
+#define SM501_USE_UART1		(1<<5)
+#define SM501_USE_FBACCEL	(1<<6)
+#define SM501_USE_AC97		(1<<7)
+#define SM501_USE_I2S		(1<<8)
+#define SM501_USE_GPIO		(1<<9)
+
+#define SM501_USE_ALL		(0xffffffff)
+
+struct sm501_initdata {
+	struct sm501_reg_init	gpio_low;
+	struct sm501_reg_init	gpio_high;
+	struct sm501_reg_init	misc_timing;
+	struct sm501_reg_init	misc_control;
+
+	unsigned long		devices;
+	unsigned long		mclk;		/* non-zero to modify */
+	unsigned long		m1xclk;		/* non-zero to modify */
+};
+
+/* sm501_init_gpio
+ *
+ * default gpio settings
+*/
+
+struct sm501_init_gpio {
+	struct sm501_reg_init	gpio_data_low;
+	struct sm501_reg_init	gpio_data_high;
+	struct sm501_reg_init	gpio_ddr_low;
+	struct sm501_reg_init	gpio_ddr_high;
+};
+
+#define SM501_FLAG_SUSPEND_OFF		(1<<4)
+
+/* sm501_platdata
+ *
+ * This is passed with the platform device to allow the board
+ * to control the behaviour of the SM501 driver(s) which attach
+ * to the device.
+ *
+*/
+
+struct sm501_platdata {
+	struct sm501_initdata		*init;
+	struct sm501_init_gpio		*init_gpiop;
+	struct sm501_platdata_fb	*fb;
+
+	int				 flags;
+	int				 gpio_base;
+
+	int	(*get_power)(struct device *dev);
+	int	(*set_power)(struct device *dev, unsigned int on);
+
+	struct sm501_platdata_gpio_i2c	*gpio_i2c;
+	unsigned int			 gpio_i2c_nr;
+};
diff -uNra linux-2.6.27.6/include/linux/sm501_regs.h linux-2.6.27.6.yaffs/include/linux/sm501_regs.h
--- linux-2.6.27.6/include/linux/sm501_regs.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/sm501_regs.h	2011-05-08 18:02:37.000000000 +0800
@@ -0,0 +1,4154 @@
+/* sm50x_reg.h
+ *
+ * Copyright 2010 SiliconMotion Inc.
+ *	
+ *	Boyod Yang<boyoddev@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ *
+ * Silicon Motion SM50x/SM107 register definitions
+*/
+
+#ifndef _SM50x_H_
+#define _SM50x_H_
+
+/* common registers for panel and the crt */
+#define SM501_OFF_DC_H_TOT		(0x000)
+#define SM501_OFF_DC_V_TOT		(0x008)
+#define SM501_OFF_DC_H_SYNC		(0x004)
+#define SM501_OFF_DC_V_SYNC		(0x00C)
+
+
+#define SM501_HWC_EN			(1<<31)
+
+#define SM501_OFF_HWC_ADDR		(0x00)
+#define SM501_OFF_HWC_LOC		(0x04)
+#define SM501_OFF_HWC_COLOR_1_2		(0x08)
+#define SM501_OFF_HWC_COLOR_3		(0x0C)
+
+
+#define SM501_VIDEOMEMORYSIZE    0x00800000  /*Assume sm50x graphics chip has 8MB VRAM */
+#define SM502_REV_ID             0xC0
+
+
+/******************************************************************************
+* REGISTER ACCESS                                                            *
+******************************************************************************/
+#define LOWORD(x) ((unsigned short) (x))
+#define HIWORD(x) ((unsigned short) ((x) >> 16))
+#define LOBYTE(x) ((unsigned char) (x))
+#define HIBYTE(x) ((unsigned char) ((x) >> 8))
+
+#define MAKEWORD(l,h)  (((unsigned short) (unsigned char) (l)) | \
+		(((unsigned short) (unsigned char) (h)) << 8))
+#define MAKEDWORD(l,h) (((unsigned int) (unsigned short) (l)) | \
+		(((unsigned int) (unsigned short) (h)) << 16))
+
+#define SRAM(x)      (U8051_SRAM + offsetof(FIRMWARE_SRAM, x))
+#define SRAM_SIZE(x) (sizeof(((FIRMWARE_SRAM*) 0)->x))
+
+/*****************************************************************************\
+ *                                FIELD MACROS                               *
+\*****************************************************************************/
+
+#define _LSB(f)             (0 ? f)
+#define _MSB(f)             (1 ? f)
+#define _COUNT(f)           (_MSB(f) - _LSB(f) + 1)
+
+#define RAW_MASK(f)         (0xFFFFFFFF >> (32 - _COUNT(f)))
+#define GET_MASK(f)         (RAW_MASK(f) << _LSB(f))
+#define GET_FIELD(d,f)      (((d) >> _LSB(f)) & RAW_MASK(f))
+#define TEST_FIELD(d,f,v)   (GET_FIELD(d,f) == f ## _ ## v)
+#define SET_FIELD(d,f,v)    (((d) & ~GET_MASK(f)) | \
+                            (((f ## _ ## v) & RAW_MASK(f)) << _LSB(f)))
+#define SET_FIELDV(d,f,v)   (((d) & ~GET_MASK(f)) | \
+                            (((v) & RAW_MASK(f)) << _LSB(f)))
+
+
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+// Internal macros                                                            //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#define _F_START(f)             (0 ? f)
+#define _F_END(f)               (1 ? f)
+#define _F_SIZE(f)              (1 + _F_END(f) - _F_START(f))
+#define _F_MASK(f)              (((1 << _F_SIZE(f)) - 1) << _F_START(f))
+#define _F_NORMALIZE(v, f)      (((v) & _F_MASK(f)) >> _F_START(f))
+#define _F_DENORMALIZE(v, f)    (((v) << _F_START(f)) & _F_MASK(f))
+
+
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+// Global macros                                                              //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#define FIELD_GET(x, reg, field) \
+( \
+    _F_NORMALIZE((x), reg ## _ ## field) \
+)
+
+#define FIELD_SET(x, reg, field, value) \
+( \
+    (x & ~_F_MASK(reg ## _ ## field)) \
+    | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \
+)
+
+#define FIELD_VALUE(x, reg, field, value) \
+( \
+    (x & ~_F_MASK(reg ## _ ## field)) \
+    | _F_DENORMALIZE(value, reg ## _ ## field) \
+)
+
+#define FIELD_CLEAR(reg, field) \
+( \
+    ~ _F_MASK(reg ## _ ## field) \
+)
+
+
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+// Field Macros                                                               //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#define FIELD_START(field)              (0 ? field)
+#define FIELD_END(field)                (1 ? field)
+#define FIELD_SIZE(field)               (1 + FIELD_END(field) - FIELD_START(field))
+#define FIELD_MASK(field)               (((1 << (FIELD_SIZE(field)-1)) | ((1 << (FIELD_SIZE(field)-1)) - 1)) << FIELD_START(field))
+#define FIELD_NORMALIZE(reg, field)     (((reg) & FIELD_MASK(field)) >> FIELD_START(field))
+#define FIELD_DENORMALIZE(field, value) (((value) << FIELD_START(field)) & FIELD_MASK(field))
+
+#define FIELD_INIT(reg, field, value)   FIELD_DENORMALIZE(reg ## _ ## field, \
+                                                          reg ## _ ## field ## _ ## value)
+#define FIELD_INIT_VAL(reg, field, value) \
+                                        (FIELD_DENORMALIZE(reg ## _ ## field, value))
+#define FIELD_VAL_SET(x, r, f, v)       x = x & ~FIELD_MASK(r ## _ ## f) \
+                                              | FIELD_DENORMALIZE(r ## _ ## f, r ## _ ## f ## _ ## v)
+
+
+
+                                              
+/*****************************************************************************\
+ *                            SYSTEM CONFIGURATION                           *
+\*****************************************************************************/
+
+/* System Control */
+#define SYSTEM_CTRL                                     0x000000
+#define SYSTEM_CTRL_DPMS                                31:30
+#define SYSTEM_CTRL_DPMS_VPHP                           0
+#define SYSTEM_CTRL_DPMS_VPHN                           1
+#define SYSTEM_CTRL_DPMS_VNHP                           2
+#define SYSTEM_CTRL_DPMS_VNHN                           3
+#define SYSTEM_CTRL_PCI_BURST                           29:29
+#define SYSTEM_CTRL_PCI_BURST_DISABLE                   0
+#define SYSTEM_CTRL_PCI_BURST_ENABLE                    1
+#define SYSTEM_CTRL_CSC_STATUS                          28:28
+#define SYSTEM_CTRL_CSC_STATUS_IDLE                     0
+#define SYSTEM_CTRL_CSC_STATUS_BUSY                     1
+#define SYSTEM_CTRL_PCI_MASTER                          25:25
+#define SYSTEM_CTRL_PCI_MASTER_STOP                     0
+#define SYSTEM_CTRL_PCI_MASTER_START                    1
+#define SYSTEM_CTRL_LATENCY_TIMER                       24:24
+#define SYSTEM_CTRL_LATENCY_TIMER_ENABLE                0
+#define SYSTEM_CTRL_LATENCY_TIMER_DISABLE               1
+#define SYSTEM_CTRL_PANEL_STATUS                        23:23
+#define SYSTEM_CTRL_PANEL_STATUS_CURRENT                0
+#define SYSTEM_CTRL_PANEL_STATUS_PENDING                1
+#define SYSTEM_CTRL_VIDEO_STATUS                        22:22
+#define SYSTEM_CTRL_VIDEO_STATUS_CURRENT                0
+#define SYSTEM_CTRL_VIDEO_STATUS_PENDING                1
+#define SYSTEM_CTRL_DE_FIFO                             20:20
+#define SYSTEM_CTRL_DE_FIFO_NOT_EMPTY                   0
+#define SYSTEM_CTRL_DE_FIFO_EMPTY                       1
+#define SYSTEM_CTRL_DE_STATUS                           19:19
+#define SYSTEM_CTRL_DE_STATUS_IDLE                      0
+#define SYSTEM_CTRL_DE_STATUS_BUSY                      1
+#define SYSTEM_CTRL_CRT_STATUS                          17:17
+#define SYSTEM_CTRL_CRT_STATUS_CURRENT                  0
+#define SYSTEM_CTRL_CRT_STATUS_PENDING                  1
+#define SYSTEM_CTRL_ZVPORT                              16:16
+#define SYSTEM_CTRL_ZVPORT_0                            0
+#define SYSTEM_CTRL_ZVPORT_1                            1
+#define SYSTEM_CTRL_PCI_BURST_READ                      15:15
+#define SYSTEM_CTRL_PCI_BURST_READ_DISABLE              0
+#define SYSTEM_CTRL_PCI_BURST_READ_ENABLE               1
+#define SYSTEM_CTRL_DE_ABORT                            13:12
+#define SYSTEM_CTRL_DE_ABORT_NORMAL                     0
+#define SYSTEM_CTRL_DE_ABORT_2D_ABORT                   3
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK                     11:11
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_DISABLE             0
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_ENABLE              1
+#define SYSTEM_CTRL_PCI_RETRY                           7:7
+#define SYSTEM_CTRL_PCI_RETRY_ENABLE                    0
+#define SYSTEM_CTRL_PCI_RETRY_DISABLE                   1
+#define SYSTEM_CTRL_PCI_CLOCK_RUN                       6:6
+#define SYSTEM_CTRL_PCI_CLOCK_RUN_DISABLE               0
+#define SYSTEM_CTRL_PCI_CLOCK_RUN_ENABLE                1
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE           5:4
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1         0
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2         1
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4         2
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8         3
+#define SYSTEM_CTRL_CRT_TRISTATE                        2:2
+#define SYSTEM_CTRL_CRT_TRISTATE_DISABLE                0
+#define SYSTEM_CTRL_CRT_TRISTATE_ENABLE                 1
+#define SYSTEM_CTRL_INTMEM_TRISTATE                     1:1
+#define SYSTEM_CTRL_INTMEM_TRISTATE_DISABLE             0
+#define SYSTEM_CTRL_INTMEM_TRISTATE_ENABLE              1
+#define SYSTEM_CTRL_PANEL_TRISTATE                      0:0
+#define SYSTEM_CTRL_PANEL_TRISTATE_DISABLE              0
+#define SYSTEM_CTRL_PANEL_TRISTATE_ENABLE               1
+
+
+/* Miscellaneous Control */
+#define MISC_CTRL                                       0x000004
+#define MISC_CTRL_PCI_PAD                               31:30
+#define MISC_CTRL_PCI_PAD_24MA                          0
+#define MISC_CTRL_PCI_PAD_12MA                          1
+#define MISC_CTRL_PCI_PAD_8MA                           2
+#define MISC_CTRL_48_SELECT                             29:28
+#define MISC_CTRL_48_SELECT_CRYSTAL                     0
+#define MISC_CTRL_48_SELECT_CPU_96                      2
+#define MISC_CTRL_48_SELECT_CPU_48                      3
+#define MISC_CTRL_UART1_SELECT                          27:27
+#define MISC_CTRL_UART1_SELECT_UART                     0
+#define MISC_CTRL_UART1_SELECT_SSP                      1
+#define MISC_CTRL_8051_LATCH                            26:26
+#define MISC_CTRL_8051_LATCH_DISABLE                    0
+#define MISC_CTRL_8051_LATCH_ENABLE                     1
+#define MISC_CTRL_FPDATA                                25:25
+#define MISC_CTRL_FPDATA_18                             0
+#define MISC_CTRL_FPDATA_24                             1
+#define MISC_CTRL_CRYSTAL                               24:24
+#define MISC_CTRL_CRYSTAL_24                            0
+#define MISC_CTRL_CRYSTAL_12                            1
+#define MISC_CTRL_DRAM_REFRESH                          22:21
+#define MISC_CTRL_DRAM_REFRESH_8                        0
+#define MISC_CTRL_DRAM_REFRESH_16                       1
+#define MISC_CTRL_DRAM_REFRESH_32                       2
+#define MISC_CTRL_DRAM_REFRESH_64                       3
+#define MISC_CTRL_BUS_HOLD                              20:18
+#define MISC_CTRL_BUS_HOLD_FIFO_EMPTY                   0
+#define MISC_CTRL_BUS_HOLD_8                            1
+#define MISC_CTRL_BUS_HOLD_16                           2
+#define MISC_CTRL_BUS_HOLD_24                           3
+#define MISC_CTRL_BUS_HOLD_32                           4
+#define MISC_CTRL_HITACHI_READY                         17:17
+#define MISC_CTRL_HITACHI_READY_NEGATIVE                0
+#define MISC_CTRL_HITACHI_READY_POSITIVE                1
+#define MISC_CTRL_INTERRUPT                             16:16
+#define MISC_CTRL_INTERRUPT_NORMAL                      0
+#define MISC_CTRL_INTERRUPT_INVERT                      1
+#define MISC_CTRL_PLL_CLOCK_COUNT                       15:15
+#define MISC_CTRL_PLL_CLOCK_COUNT_DISABLE               0
+#define MISC_CTRL_PLL_CLOCK_COUNT_ENABLE                1
+#define MISC_CTRL_DAC_BAND_GAP                          14:13
+#define MISC_CTRL_DAC_POWER                             12:12
+#define MISC_CTRL_DAC_POWER_ENABLE                      0
+#define MISC_CTRL_DAC_POWER_DISABLE                     1
+#define MISC_CTRL_USB_SLAVE_CONTROLLER                  11:11
+#define MISC_CTRL_USB_SLAVE_CONTROLLER_CPU              0
+#define MISC_CTRL_USB_SLAVE_CONTROLLER_8051             1
+#define MISC_CTRL_BURST_LENGTH                          10:10
+#define MISC_CTRL_BURST_LENGTH_8                        0
+#define MISC_CTRL_BURST_LENGTH_1                        1
+#define MISC_CTRL_USB_SELECT                            9:9
+#define MISC_CTRL_USB_SELECT_MASTER                     0
+#define MISC_CTRL_USB_SELECT_SLAVE                      1
+#define MISC_CTRL_LOOPBACK                              8:8
+#define MISC_CTRL_LOOPBACK_NORMAL                       0
+#define MISC_CTRL_LOOPBACK_USB_HOST                     1
+#define MISC_CTRL_CLOCK_DIVIDER_RESET                   7:7
+#define MISC_CTRL_CLOCK_DIVIDER_RESET_ENABLE            0
+#define MISC_CTRL_CLOCK_DIVIDER_RESET_DISABLE           1
+#define MISC_CTRL_TEST_MODE                             6:5
+#define MISC_CTRL_TEST_MODE_NORMAL                      0
+#define MISC_CTRL_TEST_MODE_DEBUGGING                   1
+#define MISC_CTRL_TEST_MODE_NAND                        2
+#define MISC_CTRL_TEST_MODE_MEMORY                      3
+#define MISC_CTRL_NEC_MMIO                              4:4
+#define MISC_CTRL_NEC_MMIO_30                           0
+#define MISC_CTRL_NEC_MMIO_62                           1
+#define MISC_CTRL_CLOCK                                 3:3
+#define MISC_CTRL_CLOCK_PLL                             0
+#define MISC_CTRL_CLOCK_TEST                            1
+#define MISC_CTRL_HOST_BUS                              2:0
+#define MISC_CTRL_HOST_BUS_HITACHI                      0
+#define MISC_CTRL_HOST_BUS_PCI                          1
+#define MISC_CTRL_HOST_BUS_XSCALE                       2
+#define MISC_CTRL_HOST_BUS_STRONGARM                    4
+#define MISC_CTRL_HOST_BUS_NEC                          6
+
+
+/* GPIO[31:0] Control */
+#define GPIO_CONTROL_LOW                                            0x000008
+#define GPIO_CONTROL_LOW_31                                         31:31
+#define GPIO_CONTROL_LOW_31_GPIO                                    0
+#define GPIO_CONTROL_LOW_31_PWM2                                    1
+#define GPIO_CONTROL_LOW_30                                         30:30
+#define GPIO_CONTROL_LOW_30_GPIO                                    0
+#define GPIO_CONTROL_LOW_30_PWM1                                    1
+#define GPIO_CONTROL_LOW_29                                         29:29
+#define GPIO_CONTROL_LOW_29_GPIO                                    0
+#define GPIO_CONTROL_LOW_29_PWM0                                    1
+#define GPIO_CONTROL_LOW_28                                         28:28
+#define GPIO_CONTROL_LOW_28_GPIO                                    0
+#define GPIO_CONTROL_LOW_28_AC97_RX_I2S                             1
+#define GPIO_CONTROL_LOW_27                                         27:27
+#define GPIO_CONTROL_LOW_27_GPIO                                    0
+#define GPIO_CONTROL_LOW_27_AC97_TX_I2S                             1
+#define GPIO_CONTROL_LOW_26                                         26:26
+#define GPIO_CONTROL_LOW_26_GPIO                                    0
+#define GPIO_CONTROL_LOW_26_AC97_CLOCK_I2S                          1
+#define GPIO_CONTROL_LOW_25                                         25:25
+#define GPIO_CONTROL_LOW_25_GPIO                                    0
+#define GPIO_CONTROL_LOW_25_AC97_SYNC_I2S                           1
+#define GPIO_CONTROL_LOW_24                                         24:24
+#define GPIO_CONTROL_LOW_24_GPIO                                    0
+#define GPIO_CONTROL_LOW_24_AC97_RESET                              1
+#define GPIO_CONTROL_LOW_23                                         23:23
+#define GPIO_CONTROL_LOW_23_GPIO                                    0
+#define GPIO_CONTROL_LOW_23_ZVPORT7                                 1
+#define GPIO_CONTROL_LOW_22                                         22:22
+#define GPIO_CONTROL_LOW_22_GPIO                                    0
+#define GPIO_CONTROL_LOW_22_ZVPORT6                                 1
+#define GPIO_CONTROL_LOW_21                                         21:21
+#define GPIO_CONTROL_LOW_21_GPIO                                    0
+#define GPIO_CONTROL_LOW_21_ZVPORT5                                 1
+#define GPIO_CONTROL_LOW_20                                         20:20
+#define GPIO_CONTROL_LOW_20_GPIO                                    0
+#define GPIO_CONTROL_LOW_20_ZVPORT4                                 1
+#define GPIO_CONTROL_LOW_19                                         19:19
+#define GPIO_CONTROL_LOW_19_GPIO                                    0
+#define GPIO_CONTROL_LOW_19_ZVPORT3                                 1
+#define GPIO_CONTROL_LOW_18                                         18:18
+#define GPIO_CONTROL_LOW_18_GPIO                                    0
+#define GPIO_CONTROL_LOW_18_ZVPORT2                                 1
+#define GPIO_CONTROL_LOW_17                                         17:17
+#define GPIO_CONTROL_LOW_17_GPIO                                    0
+#define GPIO_CONTROL_LOW_17_ZVPORT1                                 1
+#define GPIO_CONTROL_LOW_16                                         16:16
+#define GPIO_CONTROL_LOW_16_GPIO                                    0
+#define GPIO_CONTROL_LOW_16_ZVPORT0                                 1
+#define GPIO_CONTROL_LOW_15                                         15:15
+#define GPIO_CONTROL_LOW_15_GPIO                                    0
+#define GPIO_CONTROL_LOW_15_8051_A11                                1
+#define GPIO_CONTROL_LOW_14                                         14:14
+#define GPIO_CONTROL_LOW_14_GPIO                                    0
+#define GPIO_CONTROL_LOW_14_8051_A10                                1
+#define GPIO_CONTROL_LOW_13                                         13:13
+#define GPIO_CONTROL_LOW_13_GPIO                                    0
+#define GPIO_CONTROL_LOW_13_8051_A9                                 1
+#define GPIO_CONTROL_LOW_12                                         12:12
+#define GPIO_CONTROL_LOW_12_GPIO                                    0
+#define GPIO_CONTROL_LOW_12_8051_A8                                 1
+#define GPIO_CONTROL_LOW_11                                         11:11
+#define GPIO_CONTROL_LOW_11_GPIO                                    0
+#define GPIO_CONTROL_LOW_11_8051_WAIT                               1
+#define GPIO_CONTROL_LOW_10                                         10:10
+#define GPIO_CONTROL_LOW_10_GPIO                                    0
+#define GPIO_CONTROL_LOW_10_8051_ALE                                1
+#define GPIO_CONTROL_LOW_9                                          9:9
+#define GPIO_CONTROL_LOW_9_GPIO                                     0
+#define GPIO_CONTROL_LOW_9_8051_WRITE                               1
+#define GPIO_CONTROL_LOW_8                                          8:8
+#define GPIO_CONTROL_LOW_8_GPIO                                     0
+#define GPIO_CONTROL_LOW_8_8051_READ                                1
+#define GPIO_CONTROL_LOW_7                                          7:7
+#define GPIO_CONTROL_LOW_7_GPIO                                     0
+#define GPIO_CONTROL_LOW_7_8051_AD7                                 1
+#define GPIO_CONTROL_LOW_6                                          6:6
+#define GPIO_CONTROL_LOW_6_GPIO                                     0
+#define GPIO_CONTROL_LOW_6_8051_AD6                                 1
+#define GPIO_CONTROL_LOW_5                                          5:5
+#define GPIO_CONTROL_LOW_5_GPIO                                     0
+#define GPIO_CONTROL_LOW_5_8051_AD5                                 1
+#define GPIO_CONTROL_LOW_4                                          4:4
+#define GPIO_CONTROL_LOW_4_GPIO                                     0
+#define GPIO_CONTROL_LOW_4_8051_AD4                                 1
+#define GPIO_CONTROL_LOW_3                                          3:3
+#define GPIO_CONTROL_LOW_3_GPIO                                     0
+#define GPIO_CONTROL_LOW_3_8051_AD3                                 1
+#define GPIO_CONTROL_LOW_2                                          2:2
+#define GPIO_CONTROL_LOW_2_GPIO                                     0
+#define GPIO_CONTROL_LOW_2_8051_AD2                                 1
+#define GPIO_CONTROL_LOW_1                                          1:1
+#define GPIO_CONTROL_LOW_1_GPIO                                     0
+#define GPIO_CONTROL_LOW_1_8051_AD1                                 1
+#define GPIO_CONTROL_LOW_0                                          0:0
+#define GPIO_CONTROL_LOW_0_GPIO                                     0
+#define GPIO_CONTROL_LOW_0_8051_AD0                                 1
+
+/* GPIO[63:32] Control */
+#define GPIO_CONTROL_HIGH                                           0x00000C
+#define GPIO_CONTROL_HIGH_63                                        31:31
+#define GPIO_CONTROL_HIGH_63_GPIO                                   0
+#define GPIO_CONTROL_HIGH_63_CRT7_ZVPORT15                          1
+#define GPIO_CONTROL_HIGH_62                                        30:30
+#define GPIO_CONTROL_HIGH_62_GPIO                                   0
+#define GPIO_CONTROL_HIGH_62_CRT6_ZVPORT14                          1
+#define GPIO_CONTROL_HIGH_61                                        29:29
+#define GPIO_CONTROL_HIGH_61_GPIO                                   0
+#define GPIO_CONTROL_HIGH_61_CRT5_ZVPORT13_PANEL17                  1
+#define GPIO_CONTROL_HIGH_60                                        28:28
+#define GPIO_CONTROL_HIGH_60_GPIO                                   0
+#define GPIO_CONTROL_HIGH_60_CRT4_ZVPORT12_PANEL16                  1
+#define GPIO_CONTROL_HIGH_59                                        27:27
+#define GPIO_CONTROL_HIGH_59_GPIO                                   0
+#define GPIO_CONTROL_HIGH_59_CRT3_ZVPORT11_PANEL9                   1
+#define GPIO_CONTROL_HIGH_58                                        26:26
+#define GPIO_CONTROL_HIGH_58_GPIO                                   0
+#define GPIO_CONTROL_HIGH_58_CRT2_ZVPORT10_PANEL8                   1
+#define GPIO_CONTROL_HIGH_57                                        25:25
+#define GPIO_CONTROL_HIGH_57_GPIO                                   0
+#define GPIO_CONTROL_HIGH_57_CRT1_ZVPORT9_PANEL1                    1
+#define GPIO_CONTROL_HIGH_56                                        24:24
+#define GPIO_CONTROL_HIGH_56_GPIO                                   0
+#define GPIO_CONTROL_HIGH_56_CRT0_ZVPORT8_PANEL0                    1
+#define GPIO_CONTROL_HIGH_55                                        23:23
+#define GPIO_CONTROL_HIGH_55_GPIO                                   0
+#define GPIO_CONTROL_HIGH_55_CRT_CLOCK                              1
+#define GPIO_CONTROL_HIGH_47                                        15:15
+#define GPIO_CONTROL_HIGH_47_GPIO                                   0
+#define GPIO_CONTROL_HIGH_47_I2C_DATA                               1
+#define GPIO_CONTROL_HIGH_46                                        14:14
+#define GPIO_CONTROL_HIGH_46_GPIO                                   0
+#define GPIO_CONTROL_HIGH_46_I2C_CLOCK                              1
+#define GPIO_CONTROL_HIGH_45                                        13:13
+#define GPIO_CONTROL_HIGH_45_GPIO                                   0
+#define GPIO_CONTROL_HIGH_45_SSP1_CLOCK                             1
+#define GPIO_CONTROL_HIGH_44                                        12:12
+#define GPIO_CONTROL_HIGH_44_GPIO                                   0
+#define GPIO_CONTROL_HIGH_44_UART1_RTS_SSP1_OUT                     1
+#define GPIO_CONTROL_HIGH_43                                        11:11
+#define GPIO_CONTROL_HIGH_43_GPIO                                   0
+#define GPIO_CONTROL_HIGH_43_UART1_CTS_SSP1_IN                      1
+#define GPIO_CONTROL_HIGH_42                                        10:10
+#define GPIO_CONTROL_HIGH_42_GPIO                                   0
+#define GPIO_CONTROL_HIGH_42_UART1_RX_SSP1_RX                       1
+#define GPIO_CONTROL_HIGH_41                                        9:9
+#define GPIO_CONTROL_HIGH_41_GPIO                                   0
+#define GPIO_CONTROL_HIGH_41_UART1_TX_SSP1_TX                       1
+#define GPIO_CONTROL_HIGH_40                                        8:8
+#define GPIO_CONTROL_HIGH_40_GPIO                                   0
+#define GPIO_CONTROL_HIGH_40_UART0_RTS                              1
+#define GPIO_CONTROL_HIGH_39                                        7:7
+#define GPIO_CONTROL_HIGH_39_GPIO                                   0
+#define GPIO_CONTROL_HIGH_39_UART0_CTS                              1
+#define GPIO_CONTROL_HIGH_38                                        6:6
+#define GPIO_CONTROL_HIGH_38_GPIO                                   0
+#define GPIO_CONTROL_HIGH_38_UART0_RX                               1
+#define GPIO_CONTROL_HIGH_37                                        5:5
+#define GPIO_CONTROL_HIGH_37_GPIO                                   0
+#define GPIO_CONTROL_HIGH_37_UART0_TX                               1
+#define GPIO_CONTROL_HIGH_36                                        4:4
+#define GPIO_CONTROL_HIGH_36_GPIO                                   0
+#define GPIO_CONTROL_HIGH_36_SSP0_CLOCK                             1
+#define GPIO_CONTROL_HIGH_35                                        3:3
+#define GPIO_CONTROL_HIGH_35_GPIO                                   0
+#define GPIO_CONTROL_HIGH_35_SSP0_IN                                1
+#define GPIO_CONTROL_HIGH_34                                        2:2
+#define GPIO_CONTROL_HIGH_34_GPIO                                   0
+#define GPIO_CONTROL_HIGH_34_SSP0_OUT                               1
+#define GPIO_CONTROL_HIGH_33                                        1:1
+#define GPIO_CONTROL_HIGH_33_GPIO                                   0
+#define GPIO_CONTROL_HIGH_33_SSP0_RX                                1
+#define GPIO_CONTROL_HIGH_32                                        0:0
+#define GPIO_CONTROL_HIGH_32_GPIO                                   0
+#define GPIO_CONTROL_HIGH_32_SSP0_TX                                1
+
+/* DRAM Control */
+#define DRAM_CONTROL                                                0x000010
+#define DRAM_CONTROL_EMBEDDED_MEMORY                                31:31
+#define DRAM_CONTROL_EMBEDDED_MEMORY_ENABLE                         0
+#define DRAM_CONTROL_EMBEDDED_MEMORY_DISABLE                        1
+#define DRAM_CONTROL_EXTERNAL_BURST                                 30:28
+#define DRAM_CONTROL_EXTERNAL_BURST_1                               0
+#define DRAM_CONTROL_EXTERNAL_BURST_2                               1
+#define DRAM_CONTROL_EXTERNAL_BURST_4                               2
+#define DRAM_CONTROL_EXTERNAL_BURST_8                               3
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY                           27:27
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY_2                         0
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY_3                         1
+#define DRAM_CONTROL_EXTERNAL_SIZE                                  26:24
+#define DRAM_CONTROL_EXTERNAL_SIZE_2MB                              0
+#define DRAM_CONTROL_EXTERNAL_SIZE_4MB                              1
+#define DRAM_CONTROL_EXTERNAL_SIZE_64MB                             4
+#define DRAM_CONTROL_EXTERNAL_SIZE_32MB                             5
+#define DRAM_CONTROL_EXTERNAL_SIZE_16MB                             6
+#define DRAM_CONTROL_EXTERNAL_SIZE_8MB                              7
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE                           23:22
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_1024                      0
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_512                       2
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_256                       3
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE                      21:21
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE_6                    0
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE_7                    1
+#define DRAM_CONTROL_EXTERNAL                                       20:20
+#define DRAM_CONTROL_EXTERNAL_RESET                                 0
+#define DRAM_CONTROL_EXTERNAL_NORMAL                                1
+#define DRAM_CONTROL_EXTERNAL_BANKS                                 19:19
+#define DRAM_CONTROL_EXTERNAL_BANKS_2                               0
+#define DRAM_CONTROL_EXTERNAL_BANKS_4                               1
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE                       18:18
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE_2                     0
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE_1                     1
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE                              17:17
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_DISABLE                      0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_ENABLE                       1
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND                          16:16
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND_10                       0
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND_12                       1
+#define DRAM_CONTROL_LOCAL_SIZE                                     15:13
+#define DRAM_CONTROL_LOCAL_SIZE_4MB                                 0
+#define DRAM_CONTROL_LOCAL_SIZE_8MB                                 1
+#define DRAM_CONTROL_LOCAL_SIZE_16MB                                2
+#define DRAM_CONTROL_LOCAL_SIZE_32MB                                3
+#define DRAM_CONTROL_LOCAL_SIZE_64MB                                4
+#define DRAM_CONTROL_LOCAL_SIZE_2MB                                 5
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE                              12:11
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_256                          0
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_512                          2
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_1024                         3
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME                         10:10
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME_1                       0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME_2                       1
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE                    9:9
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE_4                  0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE_1                  1
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE                         8:8
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE_6                       0
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE_7                       1
+#define DRAM_CONTROL_LOCAL                                          7:7
+#define DRAM_CONTROL_LOCAL_NORMAL                                   0
+#define DRAM_CONTROL_LOCAL_RESET                                    1
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE                            6:6
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE_ENABLE                     0
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE_DISABLE                    1
+#define DRAM_CONTROL_LOCAL_BANKS                                    1:1
+#define DRAM_CONTROL_LOCAL_BANKS_4                                  0
+#define DRAM_CONTROL_LOCAL_BANKS_2                                  1
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE                          0:0
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE_2                        0
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE_1                        1
+
+/* Arbitration Control */
+#define ARBITRATION_CONTROL                                         0x000014
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY                         29:29
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY_FIXED                   0
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY_REVOLVING               1
+#define ARBITRATION_CONTROL_LOCAL_MEMORY                            28:28
+#define ARBITRATION_CONTROL_LOCAL_MEMORY_FIXED                      0
+#define ARBITRATION_CONTROL_LOCAL_MEMORY_REVOLVING                  1
+#define ARBITRATION_CONTROL_USB                                     26:24
+#define ARBITRATION_CONTROL_USB_OFF                                 0
+#define ARBITRATION_CONTROL_USB_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_USB_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_USB_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_USB_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_USB_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_USB_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_USB_PRIORITY_7                          7
+#define ARBITRATION_CONTROL_PANEL                                   22:20
+#define ARBITRATION_CONTROL_PANEL_OFF                               0
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_1                        1
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_2                        2
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_3                        3
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_4                        4
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_5                        5
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_6                        6
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_7                        7
+#define ARBITRATION_CONTROL_ZVPORT                                  18:16
+#define ARBITRATION_CONTROL_ZVPORT_OFF                              0
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_1                       1
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_2                       2
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_3                       3
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_4                       4
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_5                       5
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_6                       6
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_7                       7
+#define ARBITRATION_CONTROL_COMMAND_LIST                            14:12
+#define ARBITRATION_CONTROL_COMMAND_LIST_OFF                        0
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_1                 1
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_2                 2
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_3                 3
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_4                 4
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_5                 5
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_6                 6
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_7                 7
+#define ARBITRATION_CONTROL_DMA                                     10:8
+#define ARBITRATION_CONTROL_DMA_OFF                                 0
+#define ARBITRATION_CONTROL_DMA_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_DMA_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_DMA_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_DMA_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_DMA_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_DMA_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_DMA_PRIORITY_7                          7
+#define ARBITRATION_CONTROL_VIDEO                                   6:4
+#define ARBITRATION_CONTROL_VIDEO_OFF                               0
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_1                        1
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_2                        2
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_3                        3
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_4                        4
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_5                        5
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_6                        6
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_7                        7
+#define ARBITRATION_CONTROL_CRT                                     2:0
+#define ARBITRATION_CONTROL_CRT_OFF                                 0
+#define ARBITRATION_CONTROL_CRT_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_CRT_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_CRT_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_CRT_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_CRT_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_CRT_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_CRT_PRIORITY_7                          7
+
+/* Command List Control */
+#define COMMAND_LIST_CONTROL                                        0x000018
+#define COMMAND_LIST_CONTROL_STATUS                                 31:31
+#define COMMAND_LIST_CONTROL_STATUS_STOPPED                         0
+#define COMMAND_LIST_CONTROL_STATUS_RUNNING                         1
+#define COMMAND_LIST_CONTROL_MEMORY                                 27:26
+#define COMMAND_LIST_CONTROL_MEMORY_LOCAL                           0
+#define COMMAND_LIST_CONTROL_MEMORY_EXTERNAL_CS0                    2
+#define COMMAND_LIST_CONTROL_MEMORY_EXTERNAL_CS1                    3
+#define COMMAND_LIST_CONTROL_ADDRESS                                25:0
+
+/* Command List Conditions */
+#define COMMAND_LIST_CONDITIONS                                     0x00001C
+
+/* Command List Return */
+#define COMMAND_LIST_RETURN                                         0x000020
+#define COMMAND_LIST_RETURN_MEMORY                                  27:26
+#define COMMAND_LIST_RETURN_MEMORY_LOCAL                            0
+#define COMMAND_LIST_RETURN_MEMORY_EXTERNAL_CS0                     2
+#define COMMAND_LIST_RETURN_MEMORY_EXTERNAL_CS1                     3
+#define COMMAND_LIST_RETURN_ADDRESS                                 25:0
+
+/* Command List Status */
+#define SYS_CTRL				                                0x000024
+#define SYS_CTRL_2D_MEMORY_FIFO                 20:20
+#define SYS_CTRL_2D_MEMORY_FIFO_NOT_EMPTY       0
+#define SYS_CTRL_2D_MEMORY_FIFO_EMPTY           1
+#define SYS_CTRL_COMMAND_FIFO                   19:19
+#define SYS_CTRL_COMMAND_FIFO_NOT_EMPTY         0
+#define SYS_CTRL_COMMAND_FIFO_EMPTY             1
+#define SYS_CTRL_CSC_STATUS                     18:18
+#define SYS_CTRL_CSC_STATUS_IDLE                0
+#define SYS_CTRL_CSC_STATUS_BUSY                1
+#define SYS_CTRL_MEMORY_DMA                     17:17
+#define SYS_CTRL_MEMORY_DMA_IDLE                0
+#define SYS_CTRL_MEMORY_DMA_BUSY                1
+#define SYS_CTRL_CRT_STATUS                     16:16
+#define SYS_CTRL_CRT_STATUS_CURRENT             0
+#define SYS_CTRL_CRT_STATUS_PENDING             1
+#define SYS_CTRL_CURRENT_FIELD                  15:15
+#define SYS_CTRL_CURRENT_FIELD_ODD              0
+#define SYS_CTRL_CURRENT_FIELD_EVEN             1
+#define SYS_CTRL_VIDEO_STATUS                   14:14
+#define SYS_CTRL_VIDEO_STATUS_CURRENT           0
+#define SYS_CTRL_VIDEO_STATUS_PENDING           1
+#define SYS_CTRL_PANEL_STATUS                   13:13
+#define SYS_CTRL_PANEL_STATUS_CURRENT           0
+#define SYS_CTRL_PANEL_STATUS_PENDING           1
+#define SYS_CTRL_CRT_SYNC                       12:12
+#define SYS_CTRL_CRT_SYNC_INACTIVE              0
+#define SYS_CTRL_CRT_SYNC_ACTIVE                1
+#define SYS_CTRL_PANEL_SYNC                     11:11
+#define SYS_CTRL_PANEL_SYNC_INACTIVE            0
+#define SYS_CTRL_PANEL_SYNC_ACTIVE              1
+#define SYS_CTRL_2D_SETUP                       2:2
+#define SYS_CTRL_2D_SETUP_IDLE                  0
+#define SYS_CTRL_2D_SETUP_BUSY                  1
+#define SYS_CTRL_2D_FIFO                        1:1
+#define SYS_CTRL_2D_FIFO_NOT_EMPTY              0
+#define SYS_CTRL_2D_FIFO_EMPTY                  1
+#define SYS_CTRL_2D_ENGINE_STATUS                      0:0
+#define SYS_CTRL_2D_ENGINE_STATUS_IDLE                 0
+#define SYS_CTRL_2D_ENGINE_STATUS_BUSY                 1
+
+/* Raw Interrupt Status & Clear */
+#define RAW_INTERRUPT_STATUS                                        0x000028
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN                      5:5
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_NOT_ACTIVE           0
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_ACTIVE               1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_CLEAR                1
+#define RAW_INTERRUPT_STATUS_ZVPORT                                 4:4
+#define RAW_INTERRUPT_STATUS_ZVPORT_NOT_ACTIVE                      0
+#define RAW_INTERRUPT_STATUS_ZVPORT_ACTIVE                          1
+#define RAW_INTERRUPT_STATUS_ZVPORT_CLEAR                           1
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC                      3:3
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE           0
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_ACTIVE               1
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_CLEAR                1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE                              2:2
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_NOT_ACTIVE                   0
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_ACTIVE                       1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_CLEAR                        1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC                    1:1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE         0
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_ACTIVE             1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_CLEAR              1
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST                           0:0
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_NOT_ACTIVE                0
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_ACTIVE                    1
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_CLEAR                     1
+
+/* Interrupt Status */
+#define INTERRUPT_STATUS                                            0x00002C
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN                          31:31
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_NOT_ACTIVE               0
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_ACTIVE                   1
+#define INTERRUPT_STATUS_GPIO54                                     30:30
+#define INTERRUPT_STATUS_GPIO54_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO54_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO53                                     29:29
+#define INTERRUPT_STATUS_GPIO53_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO53_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO52                                     28:28
+#define INTERRUPT_STATUS_GPIO52_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO52_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO51                                     27:27
+#define INTERRUPT_STATUS_GPIO51_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO51_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO50                                     26:26
+#define INTERRUPT_STATUS_GPIO50_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO50_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO49                                     25:25
+#define INTERRUPT_STATUS_GPIO49_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO49_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO48                                     24:24
+#define INTERRUPT_STATUS_GPIO48_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO48_ACTIVE                              1
+#define INTERRUPT_STATUS_I2C                                        23:23
+#define INTERRUPT_STATUS_I2C_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_I2C_ACTIVE                                 1
+#define INTERRUPT_STATUS_PWM                                        22:22
+#define INTERRUPT_STATUS_PWM_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_PWM_ACTIVE                                 1
+#define INTERRUPT_STATUS_DMA                                        20:20
+#define INTERRUPT_STATUS_DMA_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_DMA_ACTIVE                                 1
+#define INTERRUPT_STATUS_PCI                                        19:19
+#define INTERRUPT_STATUS_PCI_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_PCI_ACTIVE                                 1
+#define INTERRUPT_STATUS_I2S                                        18:18
+#define INTERRUPT_STATUS_I2S_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_I2S_ACTIVE                                 1
+#define INTERRUPT_STATUS_AC97                                       17:17
+#define INTERRUPT_STATUS_AC97_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_AC97_ACTIVE                                1
+#define INTERRUPT_STATUS_USB_SLAVE                                  16:16
+#define INTERRUPT_STATUS_USB_SLAVE_NOT_ACTIVE                       0
+#define INTERRUPT_STATUS_USB_SLAVE_ACTIVE                           1
+#define INTERRUPT_STATUS_UART1                                      13:13
+#define INTERRUPT_STATUS_UART1_NOT_ACTIVE                           0
+#define INTERRUPT_STATUS_UART1_ACTIVE                               1
+#define INTERRUPT_STATUS_UART0                                      12:12
+#define INTERRUPT_STATUS_UART0_NOT_ACTIVE                           0
+#define INTERRUPT_STATUS_UART0_ACTIVE                               1
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC                          11:11
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE               0
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC_ACTIVE                   1
+#define INTERRUPT_STATUS_8051                                       10:10
+#define INTERRUPT_STATUS_8051_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_8051_ACTIVE                                1
+#define INTERRUPT_STATUS_SSP1                                       9:9
+#define INTERRUPT_STATUS_SSP1_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_SSP1_ACTIVE                                1
+#define INTERRUPT_STATUS_SSP0                                       8:8
+#define INTERRUPT_STATUS_SSP0_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_SSP0_ACTIVE                                1
+#define INTERRUPT_STATUS_USB_HOST                                   6:6
+#define INTERRUPT_STATUS_USB_HOST_NOT_ACTIVE                        0
+#define INTERRUPT_STATUS_USB_HOST_ACTIVE                            1
+#define INTERRUPT_STATUS_2D                                         3:3
+#define INTERRUPT_STATUS_2D_NOT_ACTIVE                              0
+#define INTERRUPT_STATUS_2D_ACTIVE                                  1
+#define INTERRUPT_STATUS_ZVPORT                                     2:2
+#define INTERRUPT_STATUS_ZVPORT_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_ZVPORT_ACTIVE                              1
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC                        1:1
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE             0
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_ACTIVE                 1
+#define INTERRUPT_STATUS_COMMAND_LIST                               0:0
+#define INTERRUPT_STATUS_COMMAND_LIST_NOT_ACTIVE                    0
+#define INTERRUPT_STATUS_COMMAND_LIST_ACTIVE                        1
+
+/* Interrupt Mask */
+#define INTERRUPT_MASK                                              0x000030
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN                            31:31
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN_DISABLE                    0
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN_ENABLE                     1
+#define INTERRUPT_MASK_GPIO54                                       30:30
+#define INTERRUPT_MASK_GPIO54_DISABLE                               0
+#define INTERRUPT_MASK_GPIO54_ENABLE                                1
+#define INTERRUPT_MASK_GPIO53                                       29:29
+#define INTERRUPT_MASK_GPIO53_DISABLE                               0
+#define INTERRUPT_MASK_GPIO53_ENABLE                                1
+#define INTERRUPT_MASK_GPIO52                                       28:28
+#define INTERRUPT_MASK_GPIO52_DISABLE                               0
+#define INTERRUPT_MASK_GPIO52_ENABLE                                1
+#define INTERRUPT_MASK_GPIO51                                       27:27
+#define INTERRUPT_MASK_GPIO51_DISABLE                               0
+#define INTERRUPT_MASK_GPIO51_ENABLE                                1
+#define INTERRUPT_MASK_GPIO50                                       26:26
+#define INTERRUPT_MASK_GPIO50_DISABLE                               0
+#define INTERRUPT_MASK_GPIO50_ENABLE                                1
+#define INTERRUPT_MASK_GPIO49                                       25:25
+#define INTERRUPT_MASK_GPIO49_DISABLE                               0
+#define INTERRUPT_MASK_GPIO49_ENABLE                                1
+#define INTERRUPT_MASK_GPIO48                                       24:24
+#define INTERRUPT_MASK_GPIO48_DISABLE                               0
+#define INTERRUPT_MASK_GPIO48_ENABLE                                1
+#define INTERRUPT_MASK_I2C                                          23:23
+#define INTERRUPT_MASK_I2C_DISABLE                                  0
+#define INTERRUPT_MASK_I2C_ENABLE                                   1
+#define INTERRUPT_MASK_PWM                                          22:22
+#define INTERRUPT_MASK_PWM_DISABLE                                  0
+#define INTERRUPT_MASK_PWM_ENABLE                                   1
+#define INTERRUPT_MASK_DMA                                          20:20
+#define INTERRUPT_MASK_DMA_DISABLE                                  0
+#define INTERRUPT_MASK_DMA_ENABLE                                   1
+#define INTERRUPT_MASK_PCI                                          19:19
+#define INTERRUPT_MASK_PCI_DISABLE                                  0
+#define INTERRUPT_MASK_PCI_ENABLE                                   1
+#define INTERRUPT_MASK_I2S                                          18:18
+#define INTERRUPT_MASK_I2S_DISABLE                                  0
+#define INTERRUPT_MASK_I2S_ENABLE                                   1
+#define INTERRUPT_MASK_AC97                                         17:17
+#define INTERRUPT_MASK_AC97_DISABLE                                 0
+#define INTERRUPT_MASK_AC97_ENABLE                                  1
+#define INTERRUPT_MASK_USB_SLAVE                                    16:16
+#define INTERRUPT_MASK_USB_SLAVE_DISABLE                            0
+#define INTERRUPT_MASK_USB_SLAVE_ENABLE                             1
+#define INTERRUPT_MASK_UART1                                        13:13
+#define INTERRUPT_MASK_UART1_DISABLE                                0
+#define INTERRUPT_MASK_UART1_ENABLE                                 1
+#define INTERRUPT_MASK_UART0                                        12:12
+#define INTERRUPT_MASK_UART0_DISABLE                                0
+#define INTERRUPT_MASK_UART0_ENABLE                                 1
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC                            11:11
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC_DISABLE                    0
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC_ENABLE                     1
+#define INTERRUPT_MASK_8051                                         10:10
+#define INTERRUPT_MASK_8051_DISABLE                                 0
+#define INTERRUPT_MASK_8051_ENABLE                                  1
+#define INTERRUPT_MASK_SSP1                                         9:9
+#define INTERRUPT_MASK_SSP1_DISABLE                                 0
+#define INTERRUPT_MASK_SSP1_ENABLE                                  1
+#define INTERRUPT_MASK_SSP0                                         8:8
+#define INTERRUPT_MASK_SSP0_DISABLE                                 0
+#define INTERRUPT_MASK_SSP0_ENABLE                                  1
+#define INTERRUPT_MASK_USB_HOST                                     6:6
+#define INTERRUPT_MASK_USB_HOST_DISABLE                             0
+#define INTERRUPT_MASK_USB_HOST_ENABLE                              1
+#define INTERRUPT_MASK_2D                                           3:3
+#define INTERRUPT_MASK_2D_DISABLE                                   0
+#define INTERRUPT_MASK_2D_ENABLE                                    1
+#define INTERRUPT_MASK_ZVPORT                                       2:2
+#define INTERRUPT_MASK_ZVPORT_DISABLE                               0
+#define INTERRUPT_MASK_ZVPORT_ENABLE                                1
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC                          1:1
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC_DISABLE                  0
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC_ENABLE                   1
+#define INTERRUPT_MASK_COMMAND_LIST                                 0:0
+#define INTERRUPT_MASK_COMMAND_LIST_DISABLE                         0
+#define INTERRUPT_MASK_COMMAND_LIST_ENABLE                          1
+
+/* Debug Control */
+#define DEBUG_CONTROL                                               0x000034
+#define DEBUG_CONTROL_MODULE                                        7:5
+#define DEBUG_CONTROL_PARTITION                                     4:0
+#define DEBUG_CONTROL_PARTITION_HIF                                 0
+#define DEBUG_CONTROL_PARTITION_EXTERNAL_MEMORY                     1
+#define DEBUG_CONTROL_PARTITION_PCI                                 2
+#define DEBUG_CONTROL_PARTITION_COMMAND_LIST                        3
+#define DEBUG_CONTROL_PARTITION_DISPLAY                             4
+#define DEBUG_CONTROL_PARTITION_ZVPORT                              5
+#define DEBUG_CONTROL_PARTITION_2D                                  6
+#define DEBUG_CONTROL_PARTITION_LOCAL_MEMORY                        8
+#define DEBUG_CONTROL_PARTITION_USB_HOST                            10
+#define DEBUG_CONTROL_PARTITION_SSP0                                12
+#define DEBUG_CONTROL_PARTITION_SSP1                                13
+#define DEBUG_CONTROL_PARTITION_UART0                               19
+#define DEBUG_CONTROL_PARTITION_UART1                               20
+#define DEBUG_CONTROL_PARTITION_I2C                                 21
+#define DEBUG_CONTROL_PARTITION_8051                                23
+#define DEBUG_CONTROL_PARTITION_AC97                                24
+#define DEBUG_CONTROL_PARTITION_I2S                                 25
+#define DEBUG_CONTROL_PARTITION_INTMEM                              26
+#define DEBUG_CONTROL_PARTITION_DMA                                 27
+#define DEBUG_CONTROL_PARTITION_SIMULATION                          28
+
+/* Current Gate */
+#define CURRENT_GATE                                                0x000038
+#define CURRENT_GATE_AC97_I2S                                       18:18
+#define CURRENT_GATE_AC97_I2S_DISABLE                               0
+#define CURRENT_GATE_AC97_I2S_ENABLE                                1
+#define CURRENT_GATE_8051                                           17:17
+#define CURRENT_GATE_8051_DISABLE                                   0
+#define CURRENT_GATE_8051_ENABLE                                    1
+#define CURRENT_GATE_PLL                                            16:16
+#define CURRENT_GATE_PLL_ENABLE                                     0
+#define CURRENT_GATE_PLL_DISABLE                                    1
+#define CURRENT_GATE_OSCILLATOR                                     15:15
+#define CURRENT_GATE_OSCILLATOR_ENABLE                              0
+#define CURRENT_GATE_OSCILLATOR_DISABLE                             1
+#define CURRENT_GATE_PLL_RECOVERY                                   14:13
+#define CURRENT_GATE_PLL_RECOVERY_1MS                               0
+#define CURRENT_GATE_PLL_RECOVERY_2MS                               1
+#define CURRENT_GATE_PLL_RECOVERY_3MS                               2
+#define CURRENT_GATE_PLL_RECOVERY_4MS                               3
+#define CURRENT_GATE_USB_SLAVE                                      12:12
+#define CURRENT_GATE_USB_SLAVE_DISABLE                              0
+#define CURRENT_GATE_USB_SLAVE_ENABLE                               1
+#define CURRENT_GATE_USB_HOST                                       11:11
+#define CURRENT_GATE_USB_HOST_DISABLE                               0
+#define CURRENT_GATE_USB_HOST_ENABLE                                1
+#define CURRENT_GATE_SSP                                            10:10
+#define CURRENT_GATE_SSP_DISABLE                                    0
+#define CURRENT_GATE_SSP_ENABLE                                     1
+#define CURRENT_GATE_UART1                                          8:8
+#define CURRENT_GATE_UART1_DISABLE                                  0
+#define CURRENT_GATE_UART1_ENABLE                                   1
+#define CURRENT_GATE_UART0                                          7:7
+#define CURRENT_GATE_UART0_DISABLE                                  0
+#define CURRENT_GATE_UART0_ENABLE                                   1
+#define CURRENT_GATE_GPIO_PWM_I2C                                   6:6
+#define CURRENT_GATE_GPIO_PWM_I2C_DISABLE                           0
+#define CURRENT_GATE_GPIO_PWM_I2C_ENABLE                            1
+#define CURRENT_GATE_ZVPORT                                         5:5
+#define CURRENT_GATE_ZVPORT_DISABLE                                 0
+#define CURRENT_GATE_ZVPORT_ENABLE                                  1
+#define CURRENT_GATE_CSC                                            4:4
+#define CURRENT_GATE_CSC_DISABLE                                    0
+#define CURRENT_GATE_CSC_ENABLE                                     1
+#define CURRENT_GATE_2D                                             3:3
+#define CURRENT_GATE_2D_DISABLE                                     0
+#define CURRENT_GATE_2D_ENABLE                                      1
+#define CURRENT_GATE_DISPLAY                                        2:2
+#define CURRENT_GATE_DISPLAY_DISABLE                                0
+#define CURRENT_GATE_DISPLAY_ENABLE                                 1
+#define CURRENT_GATE_MEMORY                                         1:1
+#define CURRENT_GATE_MEMORY_DISABLE                                 0
+#define CURRENT_GATE_MEMORY_ENABLE                                  1
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA                          0:0
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA_DISABLE                  0
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA_ENABLE                   1
+
+/* Current Clock */
+#define CURRENT_POWER_CLOCK                             0x00003C
+#define CURRENT_POWER_CLOCK_P1XCLK			            31:31
+#define CURRENT_POWER_CLOCK_P1XCLK_ENABLE               1
+#define CURRENT_POWER_CLOCK_P1XCLK_DISABLE              0
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT               30:30
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT_ENABLE        1
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT_DISABLE       0
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT               29:29
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288           0
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336           1
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER              28:27
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1            0
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3            1
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5            2
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT                26:24
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0              0
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1              1
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2              2
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3              3
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4              4
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5              5
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6              6
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7              7
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT               20:20
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288           0
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336           1
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER              19:19
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1            0
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3            1
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT                18:16
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0              0
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1              1
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2              2
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3              3
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4              4
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5              5
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6              6
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7              7
+#define CURRENT_POWER_CLOCK_MCLK_SELECT                 12:12
+#define CURRENT_POWER_CLOCK_MCLK_SELECT_288             0
+#define CURRENT_POWER_CLOCK_MCLK_SELECT_336             1
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER                11:11
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1              0
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3              1
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT                  10:8
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0                0
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1                1
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2                2
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3                3
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4                4
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5                5
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6                6
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7                7
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT               4:4
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288           0
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336           1
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER              3:3
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1            0
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3            1
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT                2:0
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0              0
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1              1
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2              2
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3              3
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4              4
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5              5
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6              6
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7              7
+
+
+/* Power Mode 0 Gate */
+#define POWER_MODE0_GATE                                            0x000040
+#define POWER_MODE0_GATE_AC97_I2S                                   18:18
+#define POWER_MODE0_GATE_AC97_I2S_DISABLE                           0
+#define POWER_MODE0_GATE_AC97_I2S_ENABLE                            1
+#define POWER_MODE0_GATE_8051                                       17:17
+#define POWER_MODE0_GATE_8051_DISABLE                               0
+#define POWER_MODE0_GATE_8051_ENABLE                                1
+#define POWER_MODE0_GATE_USB_SLAVE                                  12:12
+#define POWER_MODE0_GATE_USB_SLAVE_DISABLE                          0
+#define POWER_MODE0_GATE_USB_SLAVE_ENABLE                           1
+#define POWER_MODE0_GATE_USB_HOST                                   11:11
+#define POWER_MODE0_GATE_USB_HOST_DISABLE                           0
+#define POWER_MODE0_GATE_USB_HOST_ENABLE                            1
+#define POWER_MODE0_GATE_SSP                                        10:10
+#define POWER_MODE0_GATE_SSP_DISABLE                                0
+#define POWER_MODE0_GATE_SSP_ENABLE                                 1
+#define POWER_MODE0_GATE_UART1                                      8:8
+#define POWER_MODE0_GATE_UART1_DISABLE                              0
+#define POWER_MODE0_GATE_UART1_ENABLE                               1
+#define POWER_MODE0_GATE_UART0                                      7:7
+#define POWER_MODE0_GATE_UART0_DISABLE                              0
+#define POWER_MODE0_GATE_UART0_ENABLE                               1
+#define POWER_MODE0_GATE_GPIO_PWM_I2C                               6:6
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE                       0
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE                        1
+#define POWER_MODE0_GATE_ZVPORT                                     5:5
+#define POWER_MODE0_GATE_ZVPORT_DISABLE                             0
+#define POWER_MODE0_GATE_ZVPORT_ENABLE                              1
+#define POWER_MODE0_GATE_CSC                                        4:4
+#define POWER_MODE0_GATE_CSC_DISABLE                                0
+#define POWER_MODE0_GATE_CSC_ENABLE                                 1
+#define POWER_MODE0_GATE_2D                                         3:3
+#define POWER_MODE0_GATE_2D_DISABLE                                 0
+#define POWER_MODE0_GATE_2D_ENABLE                                  1
+#define POWER_MODE0_GATE_DISPLAY                                    2:2
+#define POWER_MODE0_GATE_DISPLAY_DISABLE                            0
+#define POWER_MODE0_GATE_DISPLAY_ENABLE                             1
+#define POWER_MODE0_GATE_MEMORY                                     1:1
+#define POWER_MODE0_GATE_MEMORY_DISABLE                             0
+#define POWER_MODE0_GATE_MEMORY_ENABLE                              1
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA                      0:0
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA_DISABLE              0
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA_ENABLE               1
+
+/* Power Mode 0 Clock */
+#define POWER_MODE0_CLOCK                               0x000044
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK					31:31
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK_ENABLE			1
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK_DISABLE			0
+#define POWER_MODE0_CLOCK_PLL3							30:30
+#define POWER_MODE0_CLOCK_PLL3_ENABLE					1
+#define POWER_MODE0_CLOCK_PLL3_DISABLE					0							
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT                 29:29
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_288             0
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_336             1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER                28:27
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_1              0
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_3              1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_5              2
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT                  26:24
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_0                0
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_1                1
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_2                2
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_3                3
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_4                4
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_5                5
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_6                6
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_7                7
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT                 20:20
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_288             0
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_336             1
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER                19:19
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_1              0
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_3              1
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT                  18:16
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_0                0
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_1                1
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_2                2
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_3                3
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_4                4
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_5                5
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_6                6
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_7                7
+#define POWER_MODE0_CLOCK_MCLK_SELECT                   12:12
+#define POWER_MODE0_CLOCK_MCLK_SELECT_288               0
+#define POWER_MODE0_CLOCK_MCLK_SELECT_336               1
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER                  11:11
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_1                0
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_3                1
+#define POWER_MODE0_CLOCK_MCLK_SHIFT                    10:8
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_0                  0
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_1                  1
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_2                  2
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_3                  3
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_4                  4
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_5                  5
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_6                  6
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_7                  7
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT                 4:4
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT_288             0
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT_336             1
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER                3:3
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_1              0
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_3              1
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT                  2:0
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_0                0
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_1                1
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_2                2
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_3                3
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_4                4
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_5                5
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_6                6
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_7                7
+
+/* Power Mode 1 Gate */
+#define POWER_MODE1_GATE                                            0x000048
+#define POWER_MODE1_GATE_AC97_I2S                                   18:18
+#define POWER_MODE1_GATE_AC97_I2S_DISABLE                           0
+#define POWER_MODE1_GATE_AC97_I2S_ENABLE                            1
+#define POWER_MODE1_GATE_8051                                       17:17
+#define POWER_MODE1_GATE_8051_DISABLE                               0
+#define POWER_MODE1_GATE_8051_ENABLE                                1
+#define POWER_MODE1_GATE_USB_SLAVE                                  12:12
+#define POWER_MODE1_GATE_USB_SLAVE_DISABLE                          0
+#define POWER_MODE1_GATE_USB_SLAVE_ENABLE                           1
+#define POWER_MODE1_GATE_USB_HOST                                   11:11
+#define POWER_MODE1_GATE_USB_HOST_DISABLE                           0
+#define POWER_MODE1_GATE_USB_HOST_ENABLE                            1
+#define POWER_MODE1_GATE_SSP                                        10:10
+#define POWER_MODE1_GATE_SSP_DISABLE                                0
+#define POWER_MODE1_GATE_SSP_ENABLE                                 1
+#define POWER_MODE1_GATE_UART1                                      8:8
+#define POWER_MODE1_GATE_UART1_DISABLE                              0
+#define POWER_MODE1_GATE_UART1_ENABLE                               1
+#define POWER_MODE1_GATE_UART0                                      7:7
+#define POWER_MODE1_GATE_UART0_DISABLE                              0
+#define POWER_MODE1_GATE_UART0_ENABLE                               1
+#define POWER_MODE1_GATE_GPIO_PWM_I2C                               6:6
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_DISABLE                       0
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_ENABLE                        1
+#define POWER_MODE1_GATE_ZVPORT                                     5:5
+#define POWER_MODE1_GATE_ZVPORT_DISABLE                             0
+#define POWER_MODE1_GATE_ZVPORT_ENABLE                              1
+#define POWER_MODE1_GATE_CSC                                        4:4
+#define POWER_MODE1_GATE_CSC_DISABLE                                0
+#define POWER_MODE1_GATE_CSC_ENABLE                                 1
+#define POWER_MODE1_GATE_2D                                         3:3
+#define POWER_MODE1_GATE_2D_DISABLE                                 0
+#define POWER_MODE1_GATE_2D_ENABLE                                  1
+#define POWER_MODE1_GATE_DISPLAY                                    2:2
+#define POWER_MODE1_GATE_DISPLAY_DISABLE                            0
+#define POWER_MODE1_GATE_DISPLAY_ENABLE                             1
+#define POWER_MODE1_GATE_MEMORY                                     1:1
+#define POWER_MODE1_GATE_MEMORY_DISABLE                             0
+#define POWER_MODE1_GATE_MEMORY_ENABLE                              1
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA                      0:0
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA_DISABLE              0
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA_ENABLE               1
+
+/* Power Mode 1 Clock */
+#define POWER_MODE1_CLOCK                               0x00004C
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK					31:31
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK_ENABLE			1
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK_DISABLE			0
+#define POWER_MODE1_CLOCK_PLL3							30:30
+#define POWER_MODE1_CLOCK_PLL3_ENABLE					1
+#define POWER_MODE1_CLOCK_PLL3_DISABLE					0							
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT                 29:29
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_288             0
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_336             1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER                28:27
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_1              0
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_3              1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_5              2
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT                  26:24
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_0                0
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_1                1
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_2                2
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_3                3
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_4                4
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_5                5
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_6                6
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_7                7
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT                 20:20
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_288             0
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_336             1
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER                19:19
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_1              0
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_3              1
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT                  18:16
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_0                0
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_1                1
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_2                2
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_3                3
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_4                4
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_5                5
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_6                6
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_7                7
+#define POWER_MODE1_CLOCK_MCLK_SELECT                   12:12
+#define POWER_MODE1_CLOCK_MCLK_SELECT_288               0
+#define POWER_MODE1_CLOCK_MCLK_SELECT_336               1
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER                  11:11
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_1                0
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_3                1
+#define POWER_MODE1_CLOCK_MCLK_SHIFT                    10:8
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_0                  0
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_1                  1
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_2                  2
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_3                  3
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_4                  4
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_5                  5
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_6                  6
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_7                  7
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT                 4:4
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT_288             0
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT_336             1
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER                3:3
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_1              0
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_3              1
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT                  2:0
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_0                0
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_1                1
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_2                2
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_3                3
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_4                4
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_5                5
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_6                6
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_7                7
+
+/* Sleep Mode Gate */
+#define SLEEP_MODE_GATE                                             0x000050
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK                          22:19
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_4096                     0
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_2048                     1
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_1024                     2
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_512                      3
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_256                      4
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_128                      5
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_64                       6
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_32                       7
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_16                       8
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_8                        9
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_4                        10
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_2                        11
+#define SLEEP_MODE_GATE_PLL_RECOVERY                                14:13
+#define SLEEP_MODE_GATE_PLL_RECOVERY_1MS                            0
+#define SLEEP_MODE_GATE_PLL_RECOVERY_2MS                            1
+#define SLEEP_MODE_GATE_PLL_RECOVERY_3MS                            2
+#define SLEEP_MODE_GATE_PLL_RECOVERY_4MS                            3
+
+/* Power Mode Control */
+#define POWER_MODE_CTRL                                 0x000054
+#define POWER_MODE_CTRL_SLEEP_STATUS                    2:2
+#define POWER_MODE_CTRL_SLEEP_STATUS_INACTIVE           0
+#define POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE             1
+#define POWER_MODE_CTRL_MODE                            1:0
+#define POWER_MODE_CTRL_MODE_MODE0                      0
+#define POWER_MODE_CTRL_MODE_MODE1                      1
+#define POWER_MODE_CTRL_MODE_SLEEP                      2
+
+
+/* PCI Master Base Address */
+#define PCI_MASTER_BASE                                             0x000058
+#define PCI_MASTER_BASE_ADDRESS                                     31:20
+
+/* Endian Control */
+#define ENDIAN_CONTROL                                              0x00005C
+#define ENDIAN_CONTROL_ENDIAN_SELECT                                0:0
+#define ENDIAN_CONTROL_ENDIAN_SELECT_LITTLE                         0
+#define ENDIAN_CONTROL_ENDIAN_SELECT_BIG                            1
+
+/* Device Id */
+#define DEVICE_ID                                                   0x000060
+#define DEVICE_ID_DEVICE                                            31:16
+#define DEVICE_ID_REVISION                                          7:0
+
+/* PLL Clock Count */
+#define PLL_CLOCK_COUNT                                             0x000064
+#define PLL_CLOCK_COUNT_COUNT                                       15:0
+
+/* Miscellaneous Timing */
+#define MISCELLANEOUS_TIMING                                        0x000068
+#define MISCELLANEOUS_TIMING_EXTEND                                 31:28
+#define MISCELLANEOUS_TIMING_EXTEND_NONE                            0
+#define MISCELLANEOUS_TIMING_EXTEND_16_HCLK                         1
+#define MISCELLANEOUS_TIMING_EXTEND_32_HCLK                         2
+#define MISCELLANEOUS_TIMING_EXTEND_48_HCLK                         3
+#define MISCELLANEOUS_TIMING_EXTEND_64_HCLK                         4
+#define MISCELLANEOUS_TIMING_EXTEND_80_HCLK                         5
+#define MISCELLANEOUS_TIMING_EXTEND_96_HCLK                         6
+#define MISCELLANEOUS_TIMING_EXTEND_112_HCLK                        7
+#define MISCELLANEOUS_TIMING_EXTEND_128_HCLK                        8
+#define MISCELLANEOUS_TIMING_EXTEND_144_HCLK                        9
+#define MISCELLANEOUS_TIMING_EXTEND_160_HCLK                        10
+#define MISCELLANEOUS_TIMING_EXTEND_176_HCLK                        11
+#define MISCELLANEOUS_TIMING_EXTEND_192_HCLK                        12
+#define MISCELLANEOUS_TIMING_EXTEND_208_HCLK                        13
+#define MISCELLANEOUS_TIMING_EXTEND_224_HCLK                        14
+#define MISCELLANEOUS_TIMING_EXTEND_240_HCLK                        15
+#define MISCELLANEOUS_TIMING_UART1_PLL                              27:27
+#define MISCELLANEOUS_TIMING_UART1_PLL_DISABLE                       0
+#define MISCELLANEOUS_TIMING_UART1_PLL_ENABLE                        1
+#define MISCELLANEOUS_TIMING_UART0_PLL                              26:26
+#define MISCELLANEOUS_TIMING_UART0_PLL_DISABLE                       0
+#define MISCELLANEOUS_TIMING_UART0_PLL_ENABLE                        1
+#define MISCELLANEOUS_TIMING_XSCALE                                 25:24
+#define MISCELLANEOUS_TIMING_XSCALE_PLL                             0
+#define MISCELLANEOUS_TIMING_XSCALE_HCLK                            1
+#define MISCELLANEOUS_TIMING_XSCALE_GPIO30                          2
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT                  23:23
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT_DISABLE          0
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT_ENABLE           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1              20:20
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1_288          0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1_336          1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1             19:16
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_1           0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_2           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_4           2
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_8           3
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_16          4
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_32          5
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_64          6
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_128         7
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_3           8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_6           9
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_12          10
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_24          11
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_48          12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_96          13
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_192         14
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_384         15
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0              12:12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0_288          0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0_336          1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0             11:8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_1           0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_2           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_4           2
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_8           3
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_16          4
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_32          5
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_64          6
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_128         7
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_3           8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_6           9
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_12          10
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_24          11
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_48          12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_96          13
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_192         14
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_384         15
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG                        7:7
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG_CHECK_INPUT            0
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG_CHECK_OUTPUT           1
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL                           6:6
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL_DISABLE                   0
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL_ENABLE                    1
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER                            5:4
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_336                        0
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_288                        1
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_240                        2
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_192                        3
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE                          3:3
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE_NORMAL                   0
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE_SIMULATION               1
+#define MISCELLANEOUS_TIMING_DELAY                                  2:0
+#define MISCELLANEOUS_TIMING_DELAY_NONE                             0
+#define MISCELLANEOUS_TIMING_DELAY_500PS                            1
+#define MISCELLANEOUS_TIMING_DELAY_1NS                              2
+#define MISCELLANEOUS_TIMING_DELAY_1500PS                           3
+#define MISCELLANEOUS_TIMING_DELAY_2NS                              4
+#define MISCELLANEOUS_TIMING_DELAY_2500PS                           5
+
+/* Current System SDRAM Clock */
+#define CURRENT_SYSTEM_SDRAM_CLOCK                                  0x00006C
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT                           4:4
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT_288                       0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT_336                       1
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER                          3:0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_1                        0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_2                        1
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_4                        2
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_8                        3
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_16                       4
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_32                       5
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_64                       6
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_128                      7
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_3                        8
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_6                        9
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_12                       10
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_24                       11
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_48                       12
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_96                       13
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_192                      14
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_384                      15
+
+
+
+/* USB Non Cache Access Mapping */
+#define SYSTEM_NON_CACHE			                                  0x000070
+#define SYSTEM_NON_CACHE_ADDRESS			                           13:0
+
+
+/* 502 new PLL Setting */
+
+#define SYSTEM_PLL3_CLOCK                                                               0x000074
+#define SYSTEM_PLL3_CLOCK_M                                                             7:0
+#define SYSTEM_PLL3_CLOCK_N                                                             14:8
+#define SYSTEM_PLL3_CLOCK_DIVIDE                                                15:15
+#define SYSTEM_PLL3_CLOCK_DIVIDE_1                                              0
+#define SYSTEM_PLL3_CLOCK_DIVIDE_2                                              1
+#define SYSTEM_PLL3_CLOCK_INPUT                                                 16:16
+#define SYSTEM_PLL3_CLOCK_INPUT_CRYSTAL                                 0
+#define SYSTEM_PLL3_CLOCK_INPUT_TEST                                    1
+#define SYSTEM_PLL3_CLOCK_POWER                                                 17:17
+#define SYSTEM_PLL3_CLOCK_POWER_OFF                                             0
+#define SYSTEM_PLL3_CLOCK_POWER_ON                                              1
+
+
+
+#define CURRENT_POWER_PLLCLOCK								0x000074
+#define CURRENT_POWER_PLLCLOCK_TEST_OUTPUT            		20:20
+#define CURRENT_POWER_PLLCLOCK_TEST_OUTPUT_ENABLE			1
+#define CURRENT_POWER_PLLCLOCK_TEST_OUTPUT_DISABLE      	0
+#define CURRENT_POWER_PLLCLOCK_TESTMODE						19:18
+#define CURRENT_POWER_PLLCLOCK_TESTMODE_ENABLE             	1
+#define CURRENT_POWER_PLLCLOCK_TESTMODE_DISABLE            	0
+#define CURRENT_POWER_PLLCLOCK_POWER					  	17:17
+#define CURRENT_POWER_PLLCLOCK_POWER_OFF				   	0
+#define CURRENT_POWER_PLLCLOCK_POWER_ON				     	1
+#define CURRENT_POWER_PLLCLOCK_INPUT_SELECT		            16:16
+#define CURRENT_POWER_PLLCLOCK_INPUT_SELECT_TEST	        1
+#define CURRENT_POWER_PLLCLOCK_INPUT_SELECT_CRYSTAL		    0
+#define CURRENT_POWER_PLLCLOCK_DIVIDEBY2                    15:15
+#define CURRENT_POWER_PLLCLOCK_DIVIDE_N                     14:8
+#define CURRENT_POWER_PLLCLOCK_MULTIPLE_M                   7:0
+
+
+/*****************************************************************************\
+ *                              GPIO / PWM / I2C                             *
+\*****************************************************************************/
+
+/* GPIO[31:0] Data */
+#define GPIO_DATA_LOW                                               0x010000
+#define GPIO_DATA_LOW_LOW                                           0
+#define GPIO_DATA_LOW_HIGH                                          1
+#define GPIO_DATA_LOW_0                                             0:0
+#define GPIO_DATA_LOW_0_LOW                                         0
+#define GPIO_DATA_LOW_0_HIGH                                        1
+#define GPIO_DATA_LOW_1                                             1:1
+#define GPIO_DATA_LOW_1_LOW                                         0
+#define GPIO_DATA_LOW_1_HIGH                                        1
+#define GPIO_DATA_LOW_2                                             2:2
+#define GPIO_DATA_LOW_2_LOW                                         0
+#define GPIO_DATA_LOW_2_HIGH                                        1
+#define GPIO_DATA_LOW_3                                             3:3
+#define GPIO_DATA_LOW_3_LOW                                         0
+#define GPIO_DATA_LOW_3_HIGH                                        1
+#define GPIO_DATA_LOW_4                                             4:4
+#define GPIO_DATA_LOW_4_LOW                                         0
+#define GPIO_DATA_LOW_4_HIGH                                        1
+#define GPIO_DATA_LOW_5                                             5:5
+#define GPIO_DATA_LOW_5_LOW                                         0
+#define GPIO_DATA_LOW_5_HIGH                                        1
+#define GPIO_DATA_LOW_6                                             6:6
+#define GPIO_DATA_LOW_6_LOW                                         0
+#define GPIO_DATA_LOW_6_HIGH                                        1
+#define GPIO_DATA_LOW_7                                             7:7
+#define GPIO_DATA_LOW_7_LOW                                         0
+#define GPIO_DATA_LOW_7_HIGH                                        1
+#define GPIO_DATA_LOW_8                                             8:8
+#define GPIO_DATA_LOW_8_LOW                                         0
+#define GPIO_DATA_LOW_8_HIGH                                        1
+#define GPIO_DATA_LOW_9                                             9:9
+#define GPIO_DATA_LOW_9_LOW                                         0
+#define GPIO_DATA_LOW_9_HIGH                                        1
+#define GPIO_DATA_LOW_10                                            10:10
+#define GPIO_DATA_LOW_10_LOW                                        0
+#define GPIO_DATA_LOW_10_HIGH                                       1
+#define GPIO_DATA_LOW_11                                            11:11
+#define GPIO_DATA_LOW_11_LOW                                        0
+#define GPIO_DATA_LOW_11_HIGH                                       1
+#define GPIO_DATA_LOW_12                                            12:12
+#define GPIO_DATA_LOW_12_LOW                                        0
+#define GPIO_DATA_LOW_12_HIGH                                       1
+#define GPIO_DATA_LOW_13                                            13:13
+#define GPIO_DATA_LOW_13_LOW                                        0
+#define GPIO_DATA_LOW_13_HIGH                                       1
+#define GPIO_DATA_LOW_14                                            14:14
+#define GPIO_DATA_LOW_14_LOW                                        0
+#define GPIO_DATA_LOW_14_HIGH                                       1
+#define GPIO_DATA_LOW_15                                            15:15
+#define GPIO_DATA_LOW_15_LOW                                        0
+#define GPIO_DATA_LOW_15_HIGH                                       1
+#define GPIO_DATA_LOW_16                                            16:16
+#define GPIO_DATA_LOW_16_LOW                                        0
+#define GPIO_DATA_LOW_16_HIGH                                       1
+#define GPIO_DATA_LOW_17                                            17:17
+#define GPIO_DATA_LOW_17_LOW                                        0
+#define GPIO_DATA_LOW_17_HIGH                                       1
+#define GPIO_DATA_LOW_18                                            18:18
+#define GPIO_DATA_LOW_18_LOW                                        0
+#define GPIO_DATA_LOW_18_HIGH                                       1
+#define GPIO_DATA_LOW_19                                            19:19
+#define GPIO_DATA_LOW_19_LOW                                        0
+#define GPIO_DATA_LOW_19_HIGH                                       1
+#define GPIO_DATA_LOW_20                                            20:20
+#define GPIO_DATA_LOW_20_LOW                                        0
+#define GPIO_DATA_LOW_20_HIGH                                       1
+#define GPIO_DATA_LOW_21                                            21:21
+#define GPIO_DATA_LOW_21_LOW                                        0
+#define GPIO_DATA_LOW_21_HIGH                                       1
+#define GPIO_DATA_LOW_22                                            22:22
+#define GPIO_DATA_LOW_22_LOW                                        0
+#define GPIO_DATA_LOW_22_HIGH                                       1
+#define GPIO_DATA_LOW_23                                            23:23
+#define GPIO_DATA_LOW_23_LOW                                        0
+#define GPIO_DATA_LOW_23_HIGH                                       1
+#define GPIO_DATA_LOW_24                                            24:24
+#define GPIO_DATA_LOW_24_LOW                                        0
+#define GPIO_DATA_LOW_24_HIGH                                       1
+#define GPIO_DATA_LOW_25                                            25:25
+#define GPIO_DATA_LOW_25_LOW                                        0
+#define GPIO_DATA_LOW_25_HIGH                                       1
+#define GPIO_DATA_LOW_26                                            26:26
+#define GPIO_DATA_LOW_26_LOW                                        0
+#define GPIO_DATA_LOW_26_HIGH                                       1
+#define GPIO_DATA_LOW_27                                            27:27
+#define GPIO_DATA_LOW_27_LOW                                        0
+#define GPIO_DATA_LOW_27_HIGH                                       1
+#define GPIO_DATA_LOW_28                                            28:28
+#define GPIO_DATA_LOW_28_LOW                                        0
+#define GPIO_DATA_LOW_28_HIGH                                       1
+#define GPIO_DATA_LOW_29                                            29:29
+#define GPIO_DATA_LOW_29_LOW                                        0
+#define GPIO_DATA_LOW_29_HIGH                                       1
+#define GPIO_DATA_LOW_30                                            30:30
+#define GPIO_DATA_LOW_30_LOW                                        0
+#define GPIO_DATA_LOW_30_HIGH                                       1
+#define GPIO_DATA_LOW_31                                            31:31
+#define GPIO_DATA_LOW_31_LOW                                        0
+#define GPIO_DATA_LOW_31_HIGH                                       1
+
+/* GPIO[63:32] Data */
+#define GPIO_DATA_HIGH                                              0x010004
+#define GPIO_DATA_HIGH_LOW                                          0
+#define GPIO_DATA_HIGH_HIGH                                         1
+#define GPIO_DATA_HIGH_32                                           0:0
+#define GPIO_DATA_HIGH_32_LOW                                       0
+#define GPIO_DATA_HIGH_32_HIGH                                      1
+#define GPIO_DATA_HIGH_33                                           1:1
+#define GPIO_DATA_HIGH_33_LOW                                       0
+#define GPIO_DATA_HIGH_33_HIGH                                      1
+#define GPIO_DATA_HIGH_34                                           2:2
+#define GPIO_DATA_HIGH_34_LOW                                       0
+#define GPIO_DATA_HIGH_34_HIGH                                      1
+#define GPIO_DATA_HIGH_35                                           3:3
+#define GPIO_DATA_HIGH_35_LOW                                       0
+#define GPIO_DATA_HIGH_35_HIGH                                      1
+#define GPIO_DATA_HIGH_36                                           4:4
+#define GPIO_DATA_HIGH_36_LOW                                       0
+#define GPIO_DATA_HIGH_36_HIGH                                      1
+#define GPIO_DATA_HIGH_37                                           5:5
+#define GPIO_DATA_HIGH_37_LOW                                       0
+#define GPIO_DATA_HIGH_37_HIGH                                      1
+#define GPIO_DATA_HIGH_38                                           6:6
+#define GPIO_DATA_HIGH_38_LOW                                       0
+#define GPIO_DATA_HIGH_38_HIGH                                      1
+#define GPIO_DATA_HIGH_39                                           7:7
+#define GPIO_DATA_HIGH_39_LOW                                       0
+#define GPIO_DATA_HIGH_39_HIGH                                      1
+#define GPIO_DATA_HIGH_40                                           8:8
+#define GPIO_DATA_HIGH_40_LOW                                       0
+#define GPIO_DATA_HIGH_40_HIGH                                      1
+#define GPIO_DATA_HIGH_41                                           9:9
+#define GPIO_DATA_HIGH_41_LOW                                       0
+#define GPIO_DATA_HIGH_41_HIGH                                      1
+#define GPIO_DATA_HIGH_42                                           10:10
+#define GPIO_DATA_HIGH_42_LOW                                       0
+#define GPIO_DATA_HIGH_42_HIGH                                      1
+#define GPIO_DATA_HIGH_43                                           11:11
+#define GPIO_DATA_HIGH_43_LOW                                       0
+#define GPIO_DATA_HIGH_43_HIGH                                      1
+#define GPIO_DATA_HIGH_44                                           12:12
+#define GPIO_DATA_HIGH_44_LOW                                       0
+#define GPIO_DATA_HIGH_44_HIGH                                      1
+#define GPIO_DATA_HIGH_45                                           13:13
+#define GPIO_DATA_HIGH_45_LOW                                       0
+#define GPIO_DATA_HIGH_45_HIGH                                      1
+#define GPIO_DATA_HIGH_46                                           14:14
+#define GPIO_DATA_HIGH_46_LOW                                       0
+#define GPIO_DATA_HIGH_46_HIGH                                      1
+#define GPIO_DATA_HIGH_47                                           15:15
+#define GPIO_DATA_HIGH_47_LOW                                       0
+#define GPIO_DATA_HIGH_47_HIGH                                      1
+#define GPIO_DATA_HIGH_48                                           16:16
+#define GPIO_DATA_HIGH_48_LOW                                       0
+#define GPIO_DATA_HIGH_48_HIGH                                      1
+#define GPIO_DATA_HIGH_49                                           17:17
+#define GPIO_DATA_HIGH_49_LOW                                       0
+#define GPIO_DATA_HIGH_49_HIGH                                      1
+#define GPIO_DATA_HIGH_50                                           18:18
+#define GPIO_DATA_HIGH_50_LOW                                       0
+#define GPIO_DATA_HIGH_50_HIGH                                      1
+#define GPIO_DATA_HIGH_51                                           19:19
+#define GPIO_DATA_HIGH_51_LOW                                       0
+#define GPIO_DATA_HIGH_51_HIGH                                      1
+#define GPIO_DATA_HIGH_52                                           20:20
+#define GPIO_DATA_HIGH_52_LOW                                       0
+#define GPIO_DATA_HIGH_52_HIGH                                      1
+#define GPIO_DATA_HIGH_53                                           21:21
+#define GPIO_DATA_HIGH_53_LOW                                       0
+#define GPIO_DATA_HIGH_53_HIGH                                      1
+#define GPIO_DATA_HIGH_54                                           22:22
+#define GPIO_DATA_HIGH_54_LOW                                       0
+#define GPIO_DATA_HIGH_54_HIGH                                      1
+#define GPIO_DATA_HIGH_55                                           23:23
+#define GPIO_DATA_HIGH_55_LOW                                       0
+#define GPIO_DATA_HIGH_55_HIGH                                      1
+#define GPIO_DATA_HIGH_56                                           24:24
+#define GPIO_DATA_HIGH_56_LOW                                       0
+#define GPIO_DATA_HIGH_56_HIGH                                      1
+#define GPIO_DATA_HIGH_57                                           25:25
+#define GPIO_DATA_HIGH_57_LOW                                       0
+#define GPIO_DATA_HIGH_57_HIGH                                      1
+#define GPIO_DATA_HIGH_58                                           26:26
+#define GPIO_DATA_HIGH_58_LOW                                       0
+#define GPIO_DATA_HIGH_58_HIGH                                      1
+#define GPIO_DATA_HIGH_59                                           27:27
+#define GPIO_DATA_HIGH_59_LOW                                       0
+#define GPIO_DATA_HIGH_59_HIGH                                      1
+#define GPIO_DATA_HIGH_60                                           28:28
+#define GPIO_DATA_HIGH_60_LOW                                       0
+#define GPIO_DATA_HIGH_60_HIGH                                      1
+#define GPIO_DATA_HIGH_61                                           29:29
+#define GPIO_DATA_HIGH_61_LOW                                       0
+#define GPIO_DATA_HIGH_61_HIGH                                      1
+#define GPIO_DATA_HIGH_62                                           30:30
+#define GPIO_DATA_HIGH_62_LOW                                       0
+#define GPIO_DATA_HIGH_62_HIGH                                      1
+#define GPIO_DATA_HIGH_63                                           31:31
+#define GPIO_DATA_HIGH_63_LOW                                       0
+#define GPIO_DATA_HIGH_63_HIGH                                      1
+
+/* GPIO[31:0] Data Direction */
+#define GPIO_DATA_DIRECTION_LOW                         0x010008
+#define GPIO_DATA_DIRECTION_LOW_31                      31:31
+#define GPIO_DATA_DIRECTION_LOW_31_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_31_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_30                      30:30
+#define GPIO_DATA_DIRECTION_LOW_30_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_30_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_29                      29:29
+#define GPIO_DATA_DIRECTION_LOW_29_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_29_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_28                      28:28
+#define GPIO_DATA_DIRECTION_LOW_28_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_28_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_27                      27:27
+#define GPIO_DATA_DIRECTION_LOW_27_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_27_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_26                      26:26
+#define GPIO_DATA_DIRECTION_LOW_26_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_26_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_25                      25:25
+#define GPIO_DATA_DIRECTION_LOW_25_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_25_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_24                      24:24
+#define GPIO_DATA_DIRECTION_LOW_24_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_24_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_23                      23:23
+#define GPIO_DATA_DIRECTION_LOW_23_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_23_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_22                      22:22
+#define GPIO_DATA_DIRECTION_LOW_22_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_22_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_21                      21:21
+#define GPIO_DATA_DIRECTION_LOW_21_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_21_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_20                      20:20
+#define GPIO_DATA_DIRECTION_LOW_20_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_20_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_19                      19:19
+#define GPIO_DATA_DIRECTION_LOW_19_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_19_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_18                      18:18
+#define GPIO_DATA_DIRECTION_LOW_18_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_18_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_17                      17:17
+#define GPIO_DATA_DIRECTION_LOW_17_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_17_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_16                      16:16
+#define GPIO_DATA_DIRECTION_LOW_16_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_16_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_15                      15:15
+#define GPIO_DATA_DIRECTION_LOW_15_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_15_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_14                      14:14
+#define GPIO_DATA_DIRECTION_LOW_14_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_14_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_13                      13:13
+#define GPIO_DATA_DIRECTION_LOW_13_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_13_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_12                      12:12
+#define GPIO_DATA_DIRECTION_LOW_12_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_12_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_11                      11:11
+#define GPIO_DATA_DIRECTION_LOW_11_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_11_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_10                      10:10
+#define GPIO_DATA_DIRECTION_LOW_10_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_10_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_9                       9:9
+#define GPIO_DATA_DIRECTION_LOW_9_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_9_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_8                       8:8
+#define GPIO_DATA_DIRECTION_LOW_8_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_8_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_7                       7:7
+#define GPIO_DATA_DIRECTION_LOW_7_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_7_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_6                       6:6
+#define GPIO_DATA_DIRECTION_LOW_6_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_6_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_5                       5:5
+#define GPIO_DATA_DIRECTION_LOW_5_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_5_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_4                       4:4
+#define GPIO_DATA_DIRECTION_LOW_4_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_4_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_3                       3:3
+#define GPIO_DATA_DIRECTION_LOW_3_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_3_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_2                       2:2
+#define GPIO_DATA_DIRECTION_LOW_2_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_2_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_1                       131
+#define GPIO_DATA_DIRECTION_LOW_1_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_1_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_0                       0:0
+#define GPIO_DATA_DIRECTION_LOW_0_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_0_OUTPUT                1
+
+/* GPIO[63:32] Data Direction */
+#define GPIO_DATA_DIRECTION_HIGH                        0x01000C
+#define GPIO_DATA_DIRECTION_HIGH_63                     31:31
+#define GPIO_DATA_DIRECTION_HIGH_63_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_63_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_62                     30:30
+#define GPIO_DATA_DIRECTION_HIGH_62_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_62_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_61                     29:29
+#define GPIO_DATA_DIRECTION_HIGH_61_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_61_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_60                     28:28
+#define GPIO_DATA_DIRECTION_HIGH_60_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_60_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_59                     27:27
+#define GPIO_DATA_DIRECTION_HIGH_59_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_59_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_58                     26:26
+#define GPIO_DATA_DIRECTION_HIGH_58_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_58_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_57                     25:25
+#define GPIO_DATA_DIRECTION_HIGH_57_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_57_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_56                     24:24
+#define GPIO_DATA_DIRECTION_HIGH_56_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_56_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_55                     23:23
+#define GPIO_DATA_DIRECTION_HIGH_55_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_55_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_54                     22:22
+#define GPIO_DATA_DIRECTION_HIGH_54_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_54_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_53                     21:21
+#define GPIO_DATA_DIRECTION_HIGH_53_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_53_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_52                     20:20
+#define GPIO_DATA_DIRECTION_HIGH_52_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_52_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_51                     19:19
+#define GPIO_DATA_DIRECTION_HIGH_51_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_51_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_50                     18:18
+#define GPIO_DATA_DIRECTION_HIGH_50_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_50_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_49                     17:17
+#define GPIO_DATA_DIRECTION_HIGH_49_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_49_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_48                     16:16
+#define GPIO_DATA_DIRECTION_HIGH_48_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_48_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_47                     15:15
+#define GPIO_DATA_DIRECTION_HIGH_47_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_47_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_46                     14:14
+#define GPIO_DATA_DIRECTION_HIGH_46_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_46_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_45                     13:13
+#define GPIO_DATA_DIRECTION_HIGH_45_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_45_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_44                     12:12
+#define GPIO_DATA_DIRECTION_HIGH_44_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_44_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_43                     11:11
+#define GPIO_DATA_DIRECTION_HIGH_43_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_43_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_42                     10:10
+#define GPIO_DATA_DIRECTION_HIGH_42_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_42_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_41                     9:9
+#define GPIO_DATA_DIRECTION_HIGH_41_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_41_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_40                     8:8
+#define GPIO_DATA_DIRECTION_HIGH_40_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_40_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_39                     7:7
+#define GPIO_DATA_DIRECTION_HIGH_39_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_39_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_38                     6:6
+#define GPIO_DATA_DIRECTION_HIGH_38_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_38_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_37                     5:5
+#define GPIO_DATA_DIRECTION_HIGH_37_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_37_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_36                     4:4
+#define GPIO_DATA_DIRECTION_HIGH_36_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_36_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_35                     3:3
+#define GPIO_DATA_DIRECTION_HIGH_35_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_35_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_34                     2:2
+#define GPIO_DATA_DIRECTION_HIGH_34_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_34_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_33                     1:1
+#define GPIO_DATA_DIRECTION_HIGH_33_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_33_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_32                     0:0
+#define GPIO_DATA_DIRECTION_HIGH_32_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_32_OUTPUT              1
+
+/* GPIO Interrupt Setup */
+#define GPIO_INTERRUPT_SETUP                                        0x010010
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54                             22:22
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53                             21:21
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52                             20:20
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51                             19:19
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50                             18:18
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49                             17:17
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48                             16:16
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54                              14:14
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53                              13:13
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52                              12:12
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51                              11:11
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50                              10:10
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49                              9:9
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48                              8:8
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ENABLE_54                              6:6
+#define GPIO_INTERRUPT_SETUP_ENABLE_54_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_54_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_53                              5:5
+#define GPIO_INTERRUPT_SETUP_ENABLE_53_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_53_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_52                              4:4
+#define GPIO_INTERRUPT_SETUP_ENABLE_52_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_52_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_51                              3:3
+#define GPIO_INTERRUPT_SETUP_ENABLE_51_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_51_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_50                              2:2
+#define GPIO_INTERRUPT_SETUP_ENABLE_50_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_50_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_49                              1:1
+#define GPIO_INTERRUPT_SETUP_ENABLE_49_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_49_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_48                              0:0
+#define GPIO_INTERRUPT_SETUP_ENABLE_48_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_48_INTERRUPT                    1
+
+/* GPIO Interrupt Status & Reset */
+#define GPIO_INTERRUPT_STATUS                                       0x010014
+#define GPIO_INTERRUPT_STATUS_54                                    22:22
+#define GPIO_INTERRUPT_STATUS_54_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_54_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_54_RESET                              1
+#define GPIO_INTERRUPT_STATUS_53                                    21:21
+#define GPIO_INTERRUPT_STATUS_53_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_53_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_53_RESET                              1
+#define GPIO_INTERRUPT_STATUS_52                                    20:20
+#define GPIO_INTERRUPT_STATUS_52_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_52_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_52_RESET                              1
+#define GPIO_INTERRUPT_STATUS_51                                    19:19
+#define GPIO_INTERRUPT_STATUS_51_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_51_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_51_RESET                              1
+#define GPIO_INTERRUPT_STATUS_50                                    18:18
+#define GPIO_INTERRUPT_STATUS_50_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_50_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_50_RESET                              1
+#define GPIO_INTERRUPT_STATUS_49                                    17:17
+#define GPIO_INTERRUPT_STATUS_49_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_49_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_49_RESET                              1
+#define GPIO_INTERRUPT_STATUS_48                                    16:16
+#define GPIO_INTERRUPT_STATUS_48_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_48_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_48_RESET                              1
+
+/* PWM 0 */
+#define PWM0                                                        0x010020
+#define PWM0_HIGH_COUNTER                                           31:20
+#define PWM0_LOW_COUNTER                                            19:8
+#define PWM0_CLOCK_DIVIDE                                           7:4
+#define PWM0_CLOCK_DIVIDE_1                                         0
+#define PWM0_CLOCK_DIVIDE_2                                         1
+#define PWM0_CLOCK_DIVIDE_4                                         2
+#define PWM0_CLOCK_DIVIDE_8                                         3
+#define PWM0_CLOCK_DIVIDE_16                                        4
+#define PWM0_CLOCK_DIVIDE_32                                        5
+#define PWM0_CLOCK_DIVIDE_64                                        6
+#define PWM0_CLOCK_DIVIDE_128                                       7
+#define PWM0_CLOCK_DIVIDE_256                                       8
+#define PWM0_CLOCK_DIVIDE_512                                       9
+#define PWM0_CLOCK_DIVIDE_1024                                      10
+#define PWM0_CLOCK_DIVIDE_2048                                      11
+#define PWM0_CLOCK_DIVIDE_4096                                      12
+#define PWM0_CLOCK_DIVIDE_8192                                      13
+#define PWM0_CLOCK_DIVIDE_16384                                     14
+#define PWM0_CLOCK_DIVIDE_32768                                     15
+#define PWM0_INTERRUPT_STATUS                                       3:3
+#define PWM0_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM0_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM0_INTERRUPT_CONTROL                                      2:2
+#define PWM0_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM0_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM0_CONTROL                                                0:0
+#define PWM0_CONTROL_DISABLE                                        0
+#define PWM0_CONTROL_ENABLE                                         1
+
+/* PWM 1 */
+#define PWM1                                                        0x010024
+#define PWM1_HIGH_COUNTER                                           31:20
+#define PWM1_LOW_COUNTER                                            19:8
+#define PWM1_CLOCK_DIVIDE                                           7:4
+#define PWM1_CLOCK_DIVIDE_1                                         0
+#define PWM1_CLOCK_DIVIDE_2                                         1
+#define PWM1_CLOCK_DIVIDE_4                                         2
+#define PWM1_CLOCK_DIVIDE_8                                         3
+#define PWM1_CLOCK_DIVIDE_16                                        4
+#define PWM1_CLOCK_DIVIDE_32                                        5
+#define PWM1_CLOCK_DIVIDE_64                                        6
+#define PWM1_CLOCK_DIVIDE_128                                       7
+#define PWM1_CLOCK_DIVIDE_256                                       8
+#define PWM1_CLOCK_DIVIDE_512                                       9
+#define PWM1_CLOCK_DIVIDE_1024                                      10
+#define PWM1_CLOCK_DIVIDE_2048                                      11
+#define PWM1_CLOCK_DIVIDE_4096                                      12
+#define PWM1_CLOCK_DIVIDE_8192                                      13
+#define PWM1_CLOCK_DIVIDE_16384                                     14
+#define PWM1_CLOCK_DIVIDE_32768                                     15
+#define PWM1_INTERRUPT_STATUS                                       3:3
+#define PWM1_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM1_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM1_INTERRUPT_CONTROL                                      2:2
+#define PWM1_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM1_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM1_CONTROL                                                0:0
+#define PWM1_CONTROL_DISABLE                                        0
+#define PWM1_CONTROL_ENABLE                                         1
+
+/* PWM 2 */
+#define PWM2                                                        0x010028
+#define PWM2_HIGH_COUNTER                                           31:20
+#define PWM2_LOW_COUNTER                                            19:8
+#define PWM2_CLOCK_DIVIDE                                           7:4
+#define PWM2_CLOCK_DIVIDE_1                                         0
+#define PWM2_CLOCK_DIVIDE_2                                         1
+#define PWM2_CLOCK_DIVIDE_4                                         2
+#define PWM2_CLOCK_DIVIDE_8                                         3
+#define PWM2_CLOCK_DIVIDE_16                                        4
+#define PWM2_CLOCK_DIVIDE_32                                        5
+#define PWM2_CLOCK_DIVIDE_64                                        6
+#define PWM2_CLOCK_DIVIDE_128                                       7
+#define PWM2_CLOCK_DIVIDE_256                                       8
+#define PWM2_CLOCK_DIVIDE_512                                       9
+#define PWM2_CLOCK_DIVIDE_1024                                      10
+#define PWM2_CLOCK_DIVIDE_2048                                      11
+#define PWM2_CLOCK_DIVIDE_4096                                      12
+#define PWM2_CLOCK_DIVIDE_8192                                      13
+#define PWM2_CLOCK_DIVIDE_16384                                     14
+#define PWM2_CLOCK_DIVIDE_32768                                     15
+#define PWM2_INTERRUPT_STATUS                                       3:3
+#define PWM2_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM2_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM2_INTERRUPT_CONTROL                                      2:2
+#define PWM2_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM2_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM2_CONTROL                                                0:0
+#define PWM2_CONTROL_DISABLE                                        0
+#define PWM2_CONTROL_ENABLE                                         1
+
+/* I2C Byte Count */
+#define I2C_BYTE_COUNT                                              0x010040
+#define I2C_BYTE_COUNT_COUNT                                        3:0
+
+/* I2C Control */
+#define I2C_CONTROL                                                 0x010041
+#define I2C_CONTROL_REPEAT                                          6:6
+#define I2C_CONTROL_REPEAT_DISABLE                                  0
+#define I2C_CONTROL_REPEAT_ENABLE                                   1
+#define I2C_CONTROL_INTERRUPT                                       5:5
+#define I2C_CONTROL_INTERRUPT_NOT_ACKNOWLEDGE                       0
+#define I2C_CONTROL_INTERRUPT_ACKNOWLEDGE                           1
+#define I2C_CONTROL_INTERRUPT_CONTROL                               4:4
+#define I2C_CONTROL_INTERRUPT_CONTROL_ENABLE                        1
+#define I2C_CONTROL_INTERRUPT_CONTROL_DISABLE                       0
+#define I2C_CONTROL_STATUS                                          2:2
+#define I2C_CONTROL_STATUS_STOP                                     0
+#define I2C_CONTROL_STATUS_START                                    1
+#define I2C_CONTROL_MODE                                            1:1
+#define I2C_CONTROL_MODE_STANDARD                                   0
+#define I2C_CONTROL_MODE_FAST                                       1
+#define I2C_CONTROL_CONTROL                                         0:0
+#define I2C_CONTROL_CONTROL_DISABLE                                 0
+#define I2C_CONTROL_CONTROL_ENABLE                                  1
+
+/* I2C Status & Reset */
+#define I2C_STATUS                                                  0x010042
+#define I2C_STATUS_TRANSFER                                         3:3
+#define I2C_STATUS_TRANSFER_IN_PROGRESS                             0
+#define I2C_STATUS_TRANSFER_COMPLETED                               1
+#define I2C_STATUS_ERROR                                            2:2
+#define I2C_STATUS_ERROR_NORMAL                                     0
+#define I2C_STATUS_ERROR_BUS_ERROR                                  1
+#define I2C_STATUS_ERROR_CLEAR                                      0
+#define I2C_STATUS_ACKNOWLEDGE                                      1:1
+#define I2C_STATUS_ACKNOWLEDGE_NOT_RECEIVED                         0
+#define I2C_STATUS_ACKNOWLEDGE_RECEIVED                             1
+#define I2C_STATUS_BUSY                                             0:0
+#define I2C_STATUS_BUSY_IDLE                                        0
+#define I2C_STATUS_BUSY_BUSY                                        1
+
+/* I2C Slave Address */
+#define I2C_SLAVE_ADDRESS                                           0x010043
+#define I2C_SLAVE_ADDRESS_ADDRESS                                   7:1
+#define I2C_SLAVE_ADDRESS_ACCESS                                    0:0
+#define I2C_SLAVE_ADDRESS_ACCESS_WRITE                              0
+#define I2C_SLAVE_ADDRESS_ACCESS_READ                               1
+
+/* I2C Data */
+#define I2C_DATA_0                                                  0x010044
+#define I2C_DATA_1                                                  0x010045
+#define I2C_DATA_2                                                  0x010046
+#define I2C_DATA_3                                                  0x010047
+#define I2C_DATA_4                                                  0x010048
+#define I2C_DATA_5                                                  0x010049
+#define I2C_DATA_6                                                  0x01004A
+#define I2C_DATA_7                                                  0x01004B
+#define I2C_DATA_8                                                  0x01004C
+#define I2C_DATA_9                                                  0x01004D
+#define I2C_DATA_10                                                 0x01004E
+#define I2C_DATA_11                                                 0x01004F
+#define I2C_DATA_12                                                 0x010050
+#define I2C_DATA_13                                                 0x010051
+#define I2C_DATA_14                                                 0x010052
+#define I2C_DATA_15                                                 0x010053
+
+
+/*****************************************************************************\
+ *                                    SSP                                    *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                                UART / IRDA                                *
+\*****************************************************************************/
+/*****************************************************************************\
+ *                                                                           *
+ *     REGISTER DESCRIPTION                                                  *
+ *     |========|======|================================|==============|     *
+ *     | Offset | DLAB | Register Name                  |   Comment    |     *
+ *     |========|======|================================|==============|     *
+ *     |  0x00  |  0   | RX Buffer Register             |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x00  |  0   | TX Holding Register            |      WO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x04  |  0   | Interrupt Enable Register      |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  X   | Interrupt Identification Reg.  |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  X   | FIFO Control Register          |      WO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x0C  |  X   | Line Control Register          |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x10  |  X   | Modem Control Register         |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x14  |  X   | Line Status Register           |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x18  |  X   | Modem Status Register          | Partially RO |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x1C  |  X   | Scratch Register               |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x00  |  1   | Divisor Latch (LSB)            |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x04  |  1   | Divisor Latch (MSB)            |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  1   | Enhanced Feature Register      |              |     *
+ *     |--------|------|--------------------------------|              |     *
+ *     |  0x0C  |  1   | XON1 Register                  |      R/W     |     *
+ *     |--------|------|--------------------------------|     Only     |     *
+ *     |  0x10  |  1   | XON2 Register                  |    present   |     *
+ *     |--------|------|--------------------------------|     when     |     *
+ *     |  0x14  |  1   | XOFF1 Register                 |  LCR = 0xBF  |     *
+ *     |--------|------|--------------------------------|              |     *
+ *     |  0x18  |  1   | XOFF2 Register                 |              |     *
+ *     |========|======|================================|==============|     *
+ *                                                                           *
+ *     NOTES:                                                                *
+ *       X   = Don't Care                                                    *
+ *       RO  = Read Only                                                     *
+ *       WO  = Write Only                                                    *
+ *       R/W = Read/Write                                                    *
+ *                                                                           *
+\*****************************************************************************/
+
+
+/*****************************************************************************\
+ * UART 0                                                                    *
+\*****************************************************************************/
+
+/* UART 0 when DLAB = 0 (normal mode), LCR != 0xBF */
+
+#define UART_0_RECEIVE_BUFFER                           0x030000
+#define	UART_0_RECEIVE_BUFFER_DATA						7:0
+
+#define UART_0_TRANSMIT									0x030000
+#define UART_0_TRANSMIT_DATA							7:0
+
+#define UART_0_INTERRUPT                                0x030004
+#define UART_0_INTERRUPT_CTS                            7:7
+#define UART_0_INTERRUPT_CTS_DISABLE                    0
+#define UART_0_INTERRUPT_CTS_ENABLE                     1
+#define UART_0_INTERRUPT_RTS                            6:6
+#define UART_0_INTERRUPT_RTS_DISABLE                    0
+#define UART_0_INTERRUPT_RTS_ENABLE                     1
+#define UART_0_INTERRUPT_XOFF                           5:5
+#define UART_0_INTERRUPT_XOFF_DISABLE                   0
+#define UART_0_INTERRUPT_XOFF_ENABLE                    1
+#define UART_0_INTERRUPT_MODEM_STATUS                   3:3
+#define UART_0_INTERRUPT_MODEM_STATUS_DISABLE           0
+#define UART_0_INTERRUPT_MODEM_STATUS_ENABLE            1
+#define UART_0_INTERRUPT_LINE_STATUS                    2:2
+#define UART_0_INTERRUPT_LINE_STATUS_DISABLE            0
+#define UART_0_INTERRUPT_LINE_STATUS_ENABLE             1
+#define UART_0_INTERRUPT_TX_EMPTY                       1:1
+#define UART_0_INTERRUPT_TX_EMPTY_DISABLE               0
+#define UART_0_INTERRUPT_TX_EMPTY_ENABLE                1
+#define UART_0_INTERRUPT_RX_BUFFER                      0:0
+#define UART_0_INTERRUPT_RX_BUFFER_DISABLE              0
+#define UART_0_INTERRUPT_RX_BUFFER_ENABLE               1
+
+
+/* UART 0 when DLAB = 1 (configuration mode), LCR != 0xBF */
+
+#define	UART_0_DIVISOR_LATCH_LSB						0x030000
+#define	UART_0_DIVISOR_LATCH_LSB_VALUE					7:0
+
+#define	UART_0_DIVISOR_LATCH_MSB						0x030004
+#define	UART_0_DIVISOR_LATCH_MSB_VALUE					7:0
+
+
+/* UART 0 when DLAB = X (don't care), LCR != 0xBF */
+
+#define UART_0_STATUS                                   0x030008
+#define UART_0_STATUS_FIFO                              7:6
+#define UART_0_STATUS_FIFO_DISABLE                      0
+#define UART_0_STATUS_FIFO_ENABLE                       3
+#define UART_0_STATUS_INTERRUPT                         5:1
+#define UART_0_STATUS_INTERRUPT_MODEM_STATUS_CHANGE     0
+#define UART_0_STATUS_INTERRUPT_TX_EMPTY                1
+#define UART_0_STATUS_INTERRUPT_RX_DATA_RECEIVED        2
+#define UART_0_STATUS_INTERRUPT_LINE_STATUS             3
+#define UART_0_STATUS_INTERRUPT_RX_CHAR_TIMEOUT         6
+#define UART_0_STATUS_INTERRUPT_XOFF_RECEIVED           8
+#define UART_0_STATUS_INTERRUPT_CTS_RTS                 16
+#define UART_0_STATUS_INTERRUPT_PENDING                 1:1
+#define UART_0_STATUS_INTERRUPT_PENDING_YES             0
+#define UART_0_STATUS_INTERRUPT_PENDING_NO              1
+
+#define UART_0_FIFO                                     0x030008
+#define UART_0_FIFO_RX_TRIGGER                          7:6
+#define UART_0_FIFO_RX_TRIGGER_DEFAULT                  0
+#define UART_0_FIFO_RX_TRIGGER_QUARTER                  1
+#define UART_0_FIFO_RX_TRIGGER_HALF                     2
+#define UART_0_FIFO_RX_TRIGGER_MINUS_2                  3
+#define UART_0_FIFO_TX_TRIGGER                          5:4
+#define UART_0_FIFO_TX_TRIGGER_DEFAULT                  0
+#define UART_0_FIFO_TX_TRIGGER_QUARTER                  1
+#define UART_0_FIFO_TX_TRIGGER_HALF                     2
+#define UART_0_FIFO_TX_TRIGGER_MINUS_2                  3
+#define UART_0_FIFO_DMA_MODE                            3:3
+#define UART_0_FIFO_DMA_MODE_ZERO                       0
+#define UART_0_FIFO_DMA_MODE_ONE                        1
+#define UART_0_FIFO_TX_CLEAR                            2:2
+#define UART_0_FIFO_TX_CLEAR_NO                         0
+#define UART_0_FIFO_TX_CLEAR_CLEAR                      1
+#define UART_0_FIFO_RX_CLEAR                            1:1
+#define UART_0_FIFO_RX_CLEAR_NO                         0
+#define UART_0_FIFO_RX_CLEAR_CLEAR                      1
+#define UART_0_FIFO_ENABLE                              0:0
+#define UART_0_FIFO_ENABLE_DISABLE                      0
+#define UART_0_FIFO_ENABLE_ENABLE                       1
+
+#define UART_0_LINE_CTRL                                0x03000C
+#define	UART_0_LINE_CTRL_ENHANCED						7:0
+#define	UART_0_LINE_CTRL_ENHANCED_ENABLE				0xBF
+#define UART_0_LINE_CTRL_DLAB                           7:7
+#define UART_0_LINE_CTRL_DLAB_RESET                     0
+#define UART_0_LINE_CTRL_DLAB_SET                       1
+#define UART_0_LINE_CTRL_LINE_BREAK                     6:6
+#define UART_0_LINE_CTRL_LINE_BREAK_RESET               0
+#define UART_0_LINE_CTRL_LINE_BREAK_SET                 1
+#define UART_0_LINE_CTRL_PARITY                         5:3
+#define UART_0_LINE_CTRL_PARITY_DISABLE                 0
+#define UART_0_LINE_CTRL_PARITY_ODD                     1
+#define UART_0_LINE_CTRL_PARITY_EVEN                    3
+#define UART_0_LINE_CTRL_PARITY_MARK                    5
+#define UART_0_LINE_CTRL_PARITY_SPACE                   7
+#define UART_0_LINE_CTRL_STOPBITS                       2:2
+#define UART_0_LINE_CTRL_STOPBITS_ONE                   0
+#define UART_0_LINE_CTRL_STOPBITS_TWO                   1
+#define UART_0_LINE_CTRL_CHARSIZE                       1:0
+#define UART_0_LINE_CTRL_CHARSIZE_5                     0
+#define UART_0_LINE_CTRL_CHARSIZE_6                     1
+#define UART_0_LINE_CTRL_CHARSIZE_7                     2
+#define UART_0_LINE_CTRL_CHARSIZE_8                     3
+
+#define UART_0_MODEM_CTRL                               0x030010
+#define UART_0_MODEM_CTRL_XOFF_STATUS                   7:7
+#define UART_0_MODEM_CTRL_XOFF_STATUS_XON               0
+#define UART_0_MODEM_CTRL_XOFF_STATUS_XOFF              1
+#define UART_0_MODEM_CTRL_INFRARED                      6:6
+#define UART_0_MODEM_CTRL_INFRARED_DISABLE              0
+#define UART_0_MODEM_CTRL_INFRARED_ENABLE               1
+#define UART_0_MODEM_CTRL_LOOPBACK                      4:4
+#define UART_0_MODEM_CTRL_LOOPBACK_DISABLE              0
+#define UART_0_MODEM_CTRL_LOOPBACK_ENABLE               1
+#define UART_0_MODEM_CTRL_OUT2                          3:3
+#define UART_0_MODEM_CTRL_OUT2_RESET                    0
+#define UART_0_MODEM_CTRL_OUT2_SET                      1
+#define UART_0_MODEM_CTRL_OUT1                          2:2
+#define UART_0_MODEM_CTRL_OUT1_RESET                    0
+#define UART_0_MODEM_CTRL_OUT1_SET                      1
+#define UART_0_MODEM_CTRL_RTS                           1:1
+#define UART_0_MODEM_CTRL_RTS_RESET                     0
+#define UART_0_MODEM_CTRL_RTS_SET                       1
+#define UART_0_MODEM_CTRL_DTR                           0:0
+#define UART_0_MODEM_CTRL_DTR_RESET                     0
+#define UART_0_MODEM_CTRL_DTR_SET                       1
+
+#define UART_0_LINE_STATUS                              0x030014
+#define UART_0_LINE_STATUS_RX_FIFO                      7:7
+#define UART_0_LINE_STATUS_RX_FIFO_NO_ERROR             0
+#define UART_0_LINE_STATUS_RX_FIFO_ERROR                1
+#define UART_0_LINE_STATUS_TRANSMITTER                  6:6
+#define UART_0_LINE_STATUS_TRANSMITTER_NOT_EMPTY        0
+#define UART_0_LINE_STATUS_TRANSMITTER_EMPTY            1
+#define UART_0_LINE_STATUS_TX_HOLDING                   5:5
+#define UART_0_LINE_STATUS_TX_HOLDING_NOT_EMPTY         0
+#define UART_0_LINE_STATUS_TX_HOLDING_EMPTY             1
+#define UART_0_LINE_STATUS_BREAK                        4:4
+#define UART_0_LINE_STATUS_BREAK_NO_BREAK               0
+#define UART_0_LINE_STATUS_BREAK_BREAK                  1
+#define UART_0_LINE_STATUS_FRAME                        3:3
+#define UART_0_LINE_STATUS_FRAME_NO_ERROR               0
+#define UART_0_LINE_STATUS_FRAME_ERROR                  1
+#define UART_0_LINE_STATUS_PARITY                       2:2
+#define UART_0_LINE_STATUS_PARITY_NO_ERROR              0
+#define UART_0_LINE_STATUS_PARITY_ERROR                 1
+#define UART_0_LINE_STATUS_OVERRUN                      1:1
+#define UART_0_LINE_STATUS_OVERRUN_NO_ERROR             0
+#define UART_0_LINE_STATUS_OVERRUN_ERROR                1
+#define UART_0_LINE_STATUS_DATA                         0:0
+#define UART_0_LINE_STATUS_DATA_NOT_READY               0
+#define UART_0_LINE_STATUS_DATA_READY                   1
+
+#define UART_0_MODEM_STATUS                             0x030018
+#define UART_0_MODEM_STATUS_DCD                         7:7
+#define UART_0_MODEM_STATUS_DCD_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_DCD_DETECTED                1
+#define UART_0_MODEM_STATUS_RI                          6:6
+#define UART_0_MODEM_STATUS_RI_NOT_DETECTED             0
+#define UART_0_MODEM_STATUS_RI_DETECTED                 1
+#define UART_0_MODEM_STATUS_DSR                         5:5
+#define UART_0_MODEM_STATUS_DSR_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_DSR_DETECTED                1
+#define UART_0_MODEM_STATUS_CTS                         4:4
+#define UART_0_MODEM_STATUS_CTS_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_CTS_DETECTED                1
+#define UART_0_MODEM_STATUS_DELTA_DCD                   3:3
+#define UART_0_MODEM_STATUS_DELTA_DCD_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_DCD_CHANGE            1
+#define UART_0_MODEM_STATUS_TRAILING_RI                 2:2
+#define UART_0_MODEM_STATUS_TRAILING_RI_NO_CHANGE       0
+#define UART_0_MODEM_STATUS_TRAILING_RI_CHANGE          1
+#define UART_0_MODEM_STATUS_DELTA_DSR                   1:1
+#define UART_0_MODEM_STATUS_DELTA_DSR_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_DSR_CHANGE            1
+#define UART_0_MODEM_STATUS_DELTA_CTS                   0:0
+#define UART_0_MODEM_STATUS_DELTA_CTS_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_CTS_CHANGE            1
+
+#define UART_0_SCRATCH                                  0x03001C
+#define	UART_0_SCRATCH_DATA								7:0
+
+
+/* UART 0 when LCR = 0xBF (DLAB = 1) (configuration mode) */
+
+#define	UART_0_FEATURE									0x030008
+#define	UART_0_FEATURE_AUTO_CTS							7:7
+#define	UART_0_FEATURE_AUTO_CTS_DISABLE					0
+#define	UART_0_FEATURE_AUTO_CTS_ENABLE					1
+#define	UART_0_FEATURE_AUTO_RTS							6:6
+#define	UART_0_FEATURE_AUTO_RTS_DISABLE					0
+#define	UART_0_FEATURE_AUTO_RTS_ENABLE					1
+#define	UART_0_FEATURE_ENHANCED							4:4
+#define	UART_0_FEATURE_ENHANCED_DISABLE					0
+#define	UART_0_FEATURE_ENHANCED_ENABLE					1
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1				3:3
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2				2:2
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2_ENABLE		1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1				1:1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2				0:0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2_ENABLE		1
+
+#define	UART_0_XON1_CHAR								0x030010
+#define	UART_0_XON1_CHAR_DATA							7:0
+
+#define	UART_0_XON2_CHAR								0x030014
+#define	UART_0_XON2_CHAR_DATA							7:0
+
+#define	UART_0_XOFF1_CHAR								0x030018
+#define	UART_0_XOFF1_CHAR_DATA							7:0
+
+#define	UART_0_XOFF2_CHAR								0x03001C
+#define	UART_0_XOFF2_CHAR_DATA							7:0
+
+
+/*****************************************************************************\
+ * UART 1                                                                    *
+\*****************************************************************************/
+
+/* UART 1 when DLAB = 0 (normal mode), LCR != 0xBF */
+
+#define UART_1_RECEIVE_BUFFER                           0x030020
+#define	UART_1_RECEIVE_BUFFER_DATA						7:0
+
+#define UART_1_TRANSMIT									0x030020
+#define UART_1_TRANSMIT_DATA							7:0
+
+#define UART_1_INTERRUPT                                0x030024
+#define UART_1_INTERRUPT_CTS                            7:7
+#define UART_1_INTERRUPT_CTS_DISABLE                    0
+#define UART_1_INTERRUPT_CTS_ENABLE                     1
+#define UART_1_INTERRUPT_RTS                            6:6
+#define UART_1_INTERRUPT_RTS_DISABLE                    0
+#define UART_1_INTERRUPT_RTS_ENABLE                     1
+#define UART_1_INTERRUPT_XOFF                           5:5
+#define UART_1_INTERRUPT_XOFF_DISABLE                   0
+#define UART_1_INTERRUPT_XOFF_ENABLE                    1
+#define UART_1_INTERRUPT_MODEM_STATUS                   3:3
+#define UART_1_INTERRUPT_MODEM_STATUS_DISABLE           0
+#define UART_1_INTERRUPT_MODEM_STATUS_ENABLE            1
+#define UART_1_INTERRUPT_LINE_STATUS                    2:2
+#define UART_1_INTERRUPT_LINE_STATUS_DISABLE            0
+#define UART_1_INTERRUPT_LINE_STATUS_ENABLE             1
+#define UART_1_INTERRUPT_TX_EMPTY                       1:1
+#define UART_1_INTERRUPT_TX_EMPTY_DISABLE               0
+#define UART_1_INTERRUPT_TX_EMPTY_ENABLE                1
+#define UART_1_INTERRUPT_RX_BUFFER                      0:0
+#define UART_1_INTERRUPT_RX_BUFFER_DISABLE              0
+#define UART_1_INTERRUPT_RX_BUFFER_ENABLE               1
+
+
+/* UART 0 when DLAB = 1 (configuration mode), LCR != 0xBF */
+
+#define	UART_1_DIVISOR_LATCH_LSB						0x030020
+#define	UART_1_DIVISOR_LATCH_LSB_VALUE					7:0
+
+#define	UART_1_DIVISOR_LATCH_MSB						0x030024
+#define	UART_1_DIVISOR_LATCH_MSB_VALUE					7:0
+
+
+/* UART 1 when DLAB = X (don't care), LCR != 0xBF */
+
+#define UART_1_STATUS                                   0x030028
+#define UART_1_STATUS_FIFO                              7:6
+#define UART_1_STATUS_FIFO_DISABLE                      0
+#define UART_1_STATUS_FIFO_ENABLE                       3
+#define UART_1_STATUS_INTERRUPT                         5:1
+#define UART_1_STATUS_INTERRUPT_MODEM_STATUS_CHANGE     0
+#define UART_1_STATUS_INTERRUPT_TX_EMPTY                1
+#define UART_1_STATUS_INTERRUPT_RX_DATA_RECEIVED        2
+#define UART_1_STATUS_INTERRUPT_LINE_STATUS             3
+#define UART_1_STATUS_INTERRUPT_RX_CHAR_TIMEOUT         6
+#define UART_1_STATUS_INTERRUPT_XOFF_RECEIVED           8
+#define UART_1_STATUS_INTERRUPT_CTS_RTS                 16
+#define UART_1_STATUS_INTERRUPT_PENDING                 1:1
+#define UART_1_STATUS_INTERRUPT_PENDING_YES             0
+#define UART_1_STATUS_INTERRUPT_PENDING_NO              1
+
+#define UART_1_FIFO                                     0x030028
+#define UART_1_FIFO_RX_TRIGGER                          7:6
+#define UART_1_FIFO_RX_TRIGGER_DEFAULT                  0
+#define UART_1_FIFO_RX_TRIGGER_QUARTER                  1
+#define UART_1_FIFO_RX_TRIGGER_HALF                     2
+#define UART_1_FIFO_RX_TRIGGER_MINUS_2                  3
+#define UART_1_FIFO_TX_TRIGGER                          5:4
+#define UART_1_FIFO_TX_TRIGGER_DEFAULT                  0
+#define UART_1_FIFO_TX_TRIGGER_QUARTER                  1
+#define UART_1_FIFO_TX_TRIGGER_HALF                     2
+#define UART_1_FIFO_TX_TRIGGER_MINUS_2                  3
+#define UART_1_FIFO_DMA_MODE                            3:3
+#define UART_1_FIFO_DMA_MODE_ZERO                       0
+#define UART_1_FIFO_DMA_MODE_ONE                        1
+#define UART_1_FIFO_TX_CLEAR                            2:2
+#define UART_1_FIFO_TX_CLEAR_NO                         0
+#define UART_1_FIFO_TX_CLEAR_CLEAR                      1
+#define UART_1_FIFO_RX_CLEAR                            1:1
+#define UART_1_FIFO_RX_CLEAR_NO                         0
+#define UART_1_FIFO_RX_CLEAR_CLEAR                      1
+#define UART_1_FIFO_ENABLE                              0:0
+#define UART_1_FIFO_ENABLE_DISABLE                      0
+#define UART_1_FIFO_ENABLE_ENABLE                       1
+
+#define UART_1_LINE_CTRL                                0x03002C
+#define	UART_1_LINE_CTRL_ENHANCED						7:0
+#define	UART_1_LINE_CTRL_ENHANCED_ENABLE				0xBF
+#define UART_1_LINE_CTRL_DLAB                           7:7
+#define UART_1_LINE_CTRL_DLAB_RESET                     0
+#define UART_1_LINE_CTRL_DLAB_SET                       1
+#define UART_1_LINE_CTRL_LINE_BREAK                     6:6
+#define UART_1_LINE_CTRL_LINE_BREAK_RESET               0
+#define UART_1_LINE_CTRL_LINE_BREAK_SET                 1
+#define UART_1_LINE_CTRL_PARITY                         5:3
+#define UART_1_LINE_CTRL_PARITY_DISABLE                 0
+#define UART_1_LINE_CTRL_PARITY_ODD                     1
+#define UART_1_LINE_CTRL_PARITY_EVEN                    3
+#define UART_1_LINE_CTRL_PARITY_MARK                    5
+#define UART_1_LINE_CTRL_PARITY_SPACE                   7
+#define UART_1_LINE_CTRL_STOPBITS                       2:2
+#define UART_1_LINE_CTRL_STOPBITS_ONE                   0
+#define UART_1_LINE_CTRL_STOPBITS_TWO                   1
+#define UART_1_LINE_CTRL_CHARSIZE                       1:0
+#define UART_1_LINE_CTRL_CHARSIZE_5                     0
+#define UART_1_LINE_CTRL_CHARSIZE_6                     1
+#define UART_1_LINE_CTRL_CHARSIZE_7                     2
+#define UART_1_LINE_CTRL_CHARSIZE_8                     3
+
+#define UART_1_MODEM_CTRL                               0x030030
+#define UART_1_MODEM_CTRL_XOFF_STATUS                   7:7
+#define UART_1_MODEM_CTRL_XOFF_STATUS_XON               0
+#define UART_1_MODEM_CTRL_XOFF_STATUS_XOFF              1
+#define UART_1_MODEM_CTRL_INFRARED                      6:6
+#define UART_1_MODEM_CTRL_INFRARED_DISABLE              0
+#define UART_1_MODEM_CTRL_INFRARED_ENABLE               1
+#define UART_1_MODEM_CTRL_LOOPBACK                      4:4
+#define UART_1_MODEM_CTRL_LOOPBACK_DISABLE              0
+#define UART_1_MODEM_CTRL_LOOPBACK_ENABLE               1
+#define UART_1_MODEM_CTRL_OUT2                          3:3
+#define UART_1_MODEM_CTRL_OUT2_RESET                    0
+#define UART_1_MODEM_CTRL_OUT2_SET                      1
+#define UART_1_MODEM_CTRL_OUT1                          2:2
+#define UART_1_MODEM_CTRL_OUT1_RESET                    0
+#define UART_1_MODEM_CTRL_OUT1_SET                      1
+#define UART_1_MODEM_CTRL_RTS                           1:1
+#define UART_1_MODEM_CTRL_RTS_RESET                     0
+#define UART_1_MODEM_CTRL_RTS_SET                       1
+#define UART_1_MODEM_CTRL_DTR                           0:0
+#define UART_1_MODEM_CTRL_DTR_RESET                     0
+#define UART_1_MODEM_CTRL_DTR_SET                       1
+
+#define UART_1_LINE_STATUS                              0x030034
+#define UART_1_LINE_STATUS_RX_FIFO                      7:7
+#define UART_1_LINE_STATUS_RX_FIFO_NO_ERROR             0
+#define UART_1_LINE_STATUS_RX_FIFO_ERROR                1
+#define UART_1_LINE_STATUS_TRANSMITTER                  6:6
+#define UART_1_LINE_STATUS_TRANSMITTER_NOT_EMPTY        0
+#define UART_1_LINE_STATUS_TRANSMITTER_EMPTY            1
+#define UART_1_LINE_STATUS_TX_HOLDING                   5:5
+#define UART_1_LINE_STATUS_TX_HOLDING_NOT_EMPTY         0
+#define UART_1_LINE_STATUS_TX_HOLDING_EMPTY             1
+#define UART_1_LINE_STATUS_BREAK                        4:4
+#define UART_1_LINE_STATUS_BREAK_NO_BREAK               0
+#define UART_1_LINE_STATUS_BREAK_BREAK                  1
+#define UART_1_LINE_STATUS_FRAME                        3:3
+#define UART_1_LINE_STATUS_FRAME_NO_ERROR               0
+#define UART_1_LINE_STATUS_FRAME_ERROR                  1
+#define UART_1_LINE_STATUS_PARITY                       2:2
+#define UART_1_LINE_STATUS_PARITY_NO_ERROR              0
+#define UART_1_LINE_STATUS_PARITY_ERROR                 1
+#define UART_1_LINE_STATUS_OVERRUN                      1:1
+#define UART_1_LINE_STATUS_OVERRUN_NO_ERROR             0
+#define UART_1_LINE_STATUS_OVERRUN_ERROR                1
+#define UART_1_LINE_STATUS_DATA                         0:0
+#define UART_1_LINE_STATUS_DATA_NOT_READY               0
+#define UART_1_LINE_STATUS_DATA_READY                   1
+
+#define UART_1_MODEM_STATUS                             0x030038
+#define UART_1_MODEM_STATUS_DCD                         7:7
+#define UART_1_MODEM_STATUS_DCD_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_DCD_DETECTED                1
+#define UART_1_MODEM_STATUS_RI                          6:6
+#define UART_1_MODEM_STATUS_RI_NOT_DETECTED             0
+#define UART_1_MODEM_STATUS_RI_DETECTED                 1
+#define UART_1_MODEM_STATUS_DSR                         5:5
+#define UART_1_MODEM_STATUS_DSR_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_DSR_DETECTED                1
+#define UART_1_MODEM_STATUS_CTS                         4:4
+#define UART_1_MODEM_STATUS_CTS_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_CTS_DETECTED                1
+#define UART_1_MODEM_STATUS_DELTA_DCD                   3:3
+#define UART_1_MODEM_STATUS_DELTA_DCD_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_DCD_CHANGE            1
+#define UART_1_MODEM_STATUS_TRAILING_RI                 2:2
+#define UART_1_MODEM_STATUS_TRAILING_RI_NO_CHANGE       0
+#define UART_1_MODEM_STATUS_TRAILING_RI_CHANGE          1
+#define UART_1_MODEM_STATUS_DELTA_DSR                   1:1
+#define UART_1_MODEM_STATUS_DELTA_DSR_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_DSR_CHANGE            1
+#define UART_1_MODEM_STATUS_DELTA_CTS                   0:0
+#define UART_1_MODEM_STATUS_DELTA_CTS_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_CTS_CHANGE            1
+
+#define UART_1_SCRATCH                                  0x03003C
+#define	UART_1_SCRATCH_DATA								7:0
+
+
+/* UART 1 when LCR = 0xBF (DLAB = 1) (configuration mode) */
+
+#define	UART_1_FEATURE									0x030028
+#define	UART_1_FEATURE_AUTO_CTS							7:7
+#define	UART_1_FEATURE_AUTO_CTS_DISABLE					0
+#define	UART_1_FEATURE_AUTO_CTS_ENABLE					1
+#define	UART_1_FEATURE_AUTO_RTS							6:6
+#define	UART_1_FEATURE_AUTO_RTS_DISABLE					0
+#define	UART_1_FEATURE_AUTO_RTS_ENABLE					1
+#define	UART_1_FEATURE_ENHANCED							4:4
+#define	UART_1_FEATURE_ENHANCED_DISABLE					0
+#define	UART_1_FEATURE_ENHANCED_ENABLE					1
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1				3:3
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2				2:2
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2_ENABLE		1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1				1:1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2				0:0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2_ENABLE		1
+
+#define	UART_1_XON1_CHAR								0x030030
+#define	UART_1_XON1_CHAR_DATA							7:0
+
+#define	UART_1_XON2_CHAR								0x030034
+#define	UART_1_XON2_CHAR_DATA							7:0
+
+#define	UART_1_XOFF1_CHAR								0x030038
+#define	UART_1_XOFF1_CHAR_DATA							7:0
+
+#define	UART_1_XOFF2_CHAR								0x03003C
+#define	UART_1_XOFF2_CHAR_DATA							7:0
+
+
+/*****************************************************************************\
+ *                                 USB HOST                                  *
+\*****************************************************************************/
+
+#define USB_HOST_HC_REVISION				0X040000
+#define USB_HOST_HC_CONTROL				0X040004
+#define USB_HOST_HC_COMMANDSTATUS		0X040008
+#define USB_HOST_HC_INTERRUPTSTATUS		0X04000C
+#define USB_HOST_HC_INTERRUPTENABLE		0X040010
+#define USB_HOST_HC_INTERRUPTDISABLE		0X040014
+#define USB_HOST_HC_HCCA					0X040018
+#define USB_HOST_HC_PERIODCURRENTED		0X04001C
+#define USB_HOST_HC_CONTROLHEADED		0X040020
+#define USB_HOST_HC_CONTROLCURRENTED		0X040024
+#define USB_HOST_HC_BULKHEADED			0X040028
+#define USB_HOST_HC_BULKCURRENTED			0X04002C
+#define USB_HOST_HC_DONEHEAD				0X040030
+#define USB_HOST_HC_FMINTERVAL				0X040034
+#define USB_HOST_HC_FMREMAINING			0X040038
+#define USB_HOST_HC_FMNUMBER				0X04003C
+#define USB_HOST_HC_PERIODSTART			0X040040
+#define USB_HOST_HC_LSTHRESHOLD			0X040044
+#define USB_HOST_HC_RHDESCRIPTORA			0X040048
+#define USB_HOST_HC_RHDESCRIPTORB			0X04004C
+#define USB_HOST_HC_RHSTATUS				0X040050
+#define USB_HOST_HC_RHPORT1				0X040054
+
+
+/*****************************************************************************\
+ *                                USB SLAVE                                  *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                            DISPLAY CONTROLLER                             *
+\*****************************************************************************/
+
+// Panel Graphics Control
+
+#define PANEL_DISPLAY_CTRL                              0x080000
+#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK              31:28
+#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE      0
+#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE       0xF
+#define PANEL_DISPLAY_CTRL_FPEN                         27:27
+#define PANEL_DISPLAY_CTRL_FPEN_LOW                     0
+#define PANEL_DISPLAY_CTRL_FPEN_HIGH                    1
+#define PANEL_DISPLAY_CTRL_VBIASEN                      26:26
+#define PANEL_DISPLAY_CTRL_VBIASEN_LOW                  0
+#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH                 1
+#define PANEL_DISPLAY_CTRL_DATA                         25:25
+#define PANEL_DISPLAY_CTRL_DATA_DISABLE                 0
+#define PANEL_DISPLAY_CTRL_DATA_ENABLE                  1
+#define PANEL_DISPLAY_CTRL_FPVDDEN                      24:24
+#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW                  0
+#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH                 1
+#define PANEL_DISPLAY_CTRL_PATTERN                      23:23
+#define PANEL_DISPLAY_CTRL_PATTERN_4                    0
+#define PANEL_DISPLAY_CTRL_PATTERN_8                    1
+#define PANEL_DISPLAY_CTRL_TFT                          22:21
+#define PANEL_DISPLAY_CTRL_TFT_24                       0
+#define PANEL_DISPLAY_CTRL_TFT_9                        1
+#define PANEL_DISPLAY_CTRL_TFT_12                       2
+#define PANEL_DISPLAY_CTRL_DITHER                       20:20
+#define PANEL_DISPLAY_CTRL_DITHER_DISABLE               0
+#define PANEL_DISPLAY_CTRL_DITHER_ENABLE                1
+#define PANEL_DISPLAY_CTRL_LCD                          19:18
+#define PANEL_DISPLAY_CTRL_LCD_TFT                      0
+#define PANEL_DISPLAY_CTRL_LCD_STN_8                    2
+#define PANEL_DISPLAY_CTRL_LCD_STN_12                   3
+#define PANEL_DISPLAY_CTRL_FIFO                         17:16
+#define PANEL_DISPLAY_CTRL_FIFO_1                       0
+#define PANEL_DISPLAY_CTRL_FIFO_3                       1
+#define PANEL_DISPLAY_CTRL_FIFO_7                       2
+#define PANEL_DISPLAY_CTRL_FIFO_11                      3
+#define PANEL_DISPLAY_CTRL_CLOCK_PHASE                  14:14
+#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH      0
+#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW       1
+#define PANEL_DISPLAY_CTRL_VSYNC_PHASE                  13:13
+#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH      0
+#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW       1
+#define PANEL_DISPLAY_CTRL_HSYNC_PHASE                  12:12
+#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH      0
+#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW       1
+#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK              11:11
+#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE      0
+#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE       1
+#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING               10:10
+#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE       0
+#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE        1
+#define PANEL_DISPLAY_CTRL_COLOR_KEY                    9:9
+#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE            0
+#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE             1
+#define PANEL_DISPLAY_CTRL_TIMING                       8:8
+#define PANEL_DISPLAY_CTRL_TIMING_DISABLE               0
+#define PANEL_DISPLAY_CTRL_TIMING_ENABLE                1
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR             7:7
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN        0
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP          1
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN                 6:6
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE         0
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE          1
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR           5:5
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT     0
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT      1
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN               4:4
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE       0
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE        1
+#define PANEL_DISPLAY_CTRL_GAMMA                        3:3
+#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE                0
+#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE                 1
+#define PANEL_DISPLAY_CTRL_PLANE                        2:2
+#define PANEL_DISPLAY_CTRL_PLANE_DISABLE                0
+#define PANEL_DISPLAY_CTRL_PLANE_ENABLE                 1
+#define PANEL_DISPLAY_CTRL_FORMAT                       1:0
+#define PANEL_DISPLAY_CTRL_FORMAT_8                     0
+#define PANEL_DISPLAY_CTRL_FORMAT_16                    1
+#define PANEL_DISPLAY_CTRL_FORMAT_32                    2
+
+#define PANEL_PAN_CTRL                                  0x080004
+#define PANEL_PAN_CTRL_VERTICAL_PAN                     31:24
+#define PANEL_PAN_CTRL_VERTICAL_VSYNC                   21:16
+#define PANEL_PAN_CTRL_HORIZONTAL_PAN                   15:8
+#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC                 5:0
+
+#define PANEL_COLOR_KEY                                 0x080008
+#define PANEL_COLOR_KEY_MASK                            31:16
+#define PANEL_COLOR_KEY_VALUE                           15:0
+
+#define PANEL_FB_ADDRESS                                0x08000C
+#define PANEL_FB_ADDRESS_STATUS                         31:31
+#define PANEL_FB_ADDRESS_STATUS_CURRENT               0
+#define PANEL_FB_ADDRESS_STATUS_FLIP	                 1
+#define PANEL_FB_ADDRESS_EXT                            27:27
+#define PANEL_FB_ADDRESS_EXT_LOCAL                      0
+#define PANEL_FB_ADDRESS_EXT_EXTERNAL                   1
+#define PANEL_FB_ADDRESS_CS                             26:26
+#define PANEL_FB_ADDRESS_CS_0                           0
+#define PANEL_FB_ADDRESS_CS_1                           1
+#define PANEL_FB_ADDRESS_ADDRESS                        25:0
+
+#define PANEL_FB_WIDTH                                  0x080010
+#define PANEL_FB_WIDTH_WIDTH                            29:16
+#define PANEL_FB_WIDTH_OFFSET                           13:0
+
+#define PANEL_WINDOW_WIDTH                              0x080014
+#define PANEL_WINDOW_WIDTH_WIDTH                        27:16
+#define PANEL_WINDOW_WIDTH_X                            11:0
+
+#define PANEL_WINDOW_HEIGHT                             0x080018
+#define PANEL_WINDOW_HEIGHT_HEIGHT                      27:16
+#define PANEL_WINDOW_HEIGHT_Y                           11:0
+
+#define PANEL_PLANE_TL                                  0x08001C
+#define PANEL_PLANE_TL_TOP                              26:16
+#define PANEL_PLANE_TL_LEFT                             10:0
+
+#define PANEL_PLANE_BR                                  0x080020
+#define PANEL_PLANE_BR_BOTTOM                           26:16
+#define PANEL_PLANE_BR_RIGHT                            10:0
+
+#define PANEL_HORIZONTAL_TOTAL                          0x080024
+#define PANEL_HORIZONTAL_TOTAL_TOTAL                    27:16
+#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END              11:0
+
+#define PANEL_HORIZONTAL_SYNC                           0x080028
+#define PANEL_HORIZONTAL_SYNC_WIDTH                     23:16
+#define PANEL_HORIZONTAL_SYNC_START                     11:0
+
+#define PANEL_VERTICAL_TOTAL                            0x08002C
+#define PANEL_VERTICAL_TOTAL_TOTAL                      26:16
+#define PANEL_VERTICAL_TOTAL_DISPLAY_END                10:0
+
+#define PANEL_VERTICAL_SYNC                             0x080030
+#define PANEL_VERTICAL_SYNC_HEIGHT                      21:16
+#define PANEL_VERTICAL_SYNC_START                       10:0
+
+#define PANEL_CURRENT_LINE                              0x080034
+#define PANEL_CURRENT_LINE_LINE                         10:0
+
+// Video Control
+
+#define VIDEO_DISPLAY_CTRL                              0x080040
+#define VIDEO_DISPLAY_CTRL_FIFO                         17:16
+#define VIDEO_DISPLAY_CTRL_FIFO_1                       0
+#define VIDEO_DISPLAY_CTRL_FIFO_3                       1
+#define VIDEO_DISPLAY_CTRL_FIFO_7                       2
+#define VIDEO_DISPLAY_CTRL_FIFO_11                      3
+#define VIDEO_DISPLAY_CTRL_BUFFER                       15:15
+#define VIDEO_DISPLAY_CTRL_BUFFER_0                     0
+#define VIDEO_DISPLAY_CTRL_BUFFER_1                     1
+#define VIDEO_DISPLAY_CTRL_CAPTURE                      14:14
+#define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE              0
+#define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE               1
+#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER                13:13
+#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE        0
+#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE         1
+#define VIDEO_DISPLAY_CTRL_BYTE_SWAP                    12:12
+#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE            0
+#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE             1
+#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE               11:11
+#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL        0
+#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF          1
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE             10:10
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL      0
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF        1
+#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE                9:9
+#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE      0
+#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE    1
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE              8:8
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE    0
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE  1
+#define VIDEO_DISPLAY_CTRL_PIXEL                        7:4
+#define VIDEO_DISPLAY_CTRL_GAMMA                        3:3
+#define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE                0
+#define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE                 1
+#define VIDEO_DISPLAY_CTRL_PLANE                        2:2
+#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE                0
+#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE                 1
+#define VIDEO_DISPLAY_CTRL_FORMAT                       1:0
+#define VIDEO_DISPLAY_CTRL_FORMAT_8                     0
+#define VIDEO_DISPLAY_CTRL_FORMAT_16                    1
+#define VIDEO_DISPLAY_CTRL_FORMAT_32                    2
+#define VIDEO_DISPLAY_CTRL_FORMAT_YUV                   3
+
+#define VIDEO_FB_0_ADDRESS                              0x080044
+#define VIDEO_FB_0_ADDRESS_STATUS                       31:31
+#define VIDEO_FB_0_ADDRESS_STATUS_CURRENT               0
+#define VIDEO_FB_0_ADDRESS_STATUS_PENDING               1
+#define VIDEO_FB_0_ADDRESS_EXT                          27:27
+#define VIDEO_FB_0_ADDRESS_EXT_LOCAL                    0
+#define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL                 1
+#define VIDEO_FB_0_ADDRESS_CS                           26:26
+#define VIDEO_FB_0_ADDRESS_CS_0                         0
+#define VIDEO_FB_0_ADDRESS_CS_1                         1
+#define VIDEO_FB_0_ADDRESS_ADDRESS                      25:0
+
+#define VIDEO_FB_WIDTH                                  0x080048
+#define VIDEO_FB_WIDTH_WIDTH                            29:16
+#define VIDEO_FB_WIDTH_OFFSET                           13:0
+
+#define VIDEO_FB_0_LAST_ADDRESS                         0x08004C
+#define VIDEO_FB_0_LAST_ADDRESS_EXT                     27:27
+#define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL               0
+#define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL            1
+#define VIDEO_FB_0_LAST_ADDRESS_CS                      26:26
+#define VIDEO_FB_0_LAST_ADDRESS_CS_0                    0
+#define VIDEO_FB_0_LAST_ADDRESS_CS_1                    1
+#define VIDEO_FB_0_LAST_ADDRESS_ADDRESS                 25:0
+
+#define VIDEO_PLANE_TL                                  0x080050
+#define VIDEO_PLANE_TL_TOP                              26:16
+#define VIDEO_PLANE_TL_LEFT                             13:0
+
+#define VIDEO_PLANE_BR                                  0x080054
+#define VIDEO_PLANE_BR_BOTTOM                           26:16
+#define VIDEO_PLANE_BR_RIGHT                            13:0
+
+#define VIDEO_SCALE                                     0x080058
+#define VIDEO_SCALE_VERTICAL_MODE                       31:31
+#define VIDEO_SCALE_VERTICAL_MODE_EXPAND                0
+#define VIDEO_SCALE_VERTICAL_MODE_SHRINK                1
+#define VIDEO_SCALE_VERTICAL_SCALE                      27:16
+#define VIDEO_SCALE_HORIZONTAL_MODE                     15:15
+#define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND              0
+#define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK              1
+#define VIDEO_SCALE_HORIZONTAL_SCALE                    11:0
+
+#define VIDEO_INITIAL_SCALE                             0x08005C
+#define VIDEO_INITIAL_SCALE_FB_1                        27:16
+#define VIDEO_INITIAL_SCALE_FB_0                        11:0
+
+#define VIDEO_YUV_CONSTANTS                             0x080060
+#define VIDEO_YUV_CONSTANTS_Y                           31:24
+#define VIDEO_YUV_CONSTANTS_R                           23:16
+#define VIDEO_YUV_CONSTANTS_G                           15:8
+#define VIDEO_YUV_CONSTANTS_B                           7:0
+
+#define VIDEO_FB_1_ADDRESS                              0x080064
+#define VIDEO_FB_1_ADDRESS_STATUS                       31:31
+#define VIDEO_FB_1_ADDRESS_STATUS_CURRENT               0
+#define VIDEO_FB_1_ADDRESS_STATUS_PENDING               1
+#define VIDEO_FB_1_ADDRESS_EXT                          27:27
+#define VIDEO_FB_1_ADDRESS_EXT_LOCAL                    0
+#define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL                 1
+#define VIDEO_FB_1_ADDRESS_CS                           26:26
+#define VIDEO_FB_1_ADDRESS_CS_0                         0
+#define VIDEO_FB_1_ADDRESS_CS_1                         1
+#define VIDEO_FB_1_ADDRESS_ADDRESS                      25:0
+
+#define VIDEO_FB_1_LAST_ADDRESS                         0x080068
+#define VIDEO_FB_1_LAST_ADDRESS_EXT                     27:27
+#define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL               0
+#define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL            1
+#define VIDEO_FB_1_LAST_ADDRESS_CS                      26:26
+#define VIDEO_FB_1_LAST_ADDRESS_CS_0                    0
+#define VIDEO_FB_1_LAST_ADDRESS_CS_1                    1
+#define VIDEO_FB_1_LAST_ADDRESS_ADDRESS                 25:0
+
+// Video Alpha Control
+
+#define VIDEO_ALPHA_DISPLAY_CTRL                        0x080080
+#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT                 28:28
+#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL       0
+#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA           1
+#define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA                  27:24
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO                   17:16
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1                 0
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3                 1
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7                 2
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11                3
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE             11:11
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL      0
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF        1
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE             10:10
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL      0
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF        1
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE              9:9
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE    0
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE  1
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE              8:8
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE    0
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE  1
+#define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL                  7:4
+#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY             3:3
+#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE     0
+#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE      1
+#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE                  2:2
+#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE          0
+#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE           1
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT                 1:0
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8               0
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16              1
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4       2
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4   3
+
+#define VIDEO_ALPHA_FB_ADDRESS                          0x080084
+#define VIDEO_ALPHA_FB_ADDRESS_STATUS                   31:31
+#define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT           0
+#define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING           1
+#define VIDEO_ALPHA_FB_ADDRESS_EXT                      27:27
+#define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL                0
+#define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL             1
+#define VIDEO_ALPHA_FB_ADDRESS_CS                       26:26
+#define VIDEO_ALPHA_FB_ADDRESS_CS_0                     0
+#define VIDEO_ALPHA_FB_ADDRESS_CS_1                     1
+#define VIDEO_ALPHA_FB_ADDRESS_ADDRESS                  25:0
+
+#define VIDEO_ALPHA_FB_WIDTH                            0x080088
+#define VIDEO_ALPHA_FB_WIDTH_WIDTH                      29:16
+#define VIDEO_ALPHA_FB_WIDTH_OFFSET                     13:0
+
+#define VIDEO_ALPHA_FB_LAST_ADDRESS                     0x08008C
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT                 27:27
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL           0
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL        1
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_CS                  26:26
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_CS_0                0
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_CS_1                1
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS             25:0
+
+#define VIDEO_ALPHA_PLANE_TL                            0x080090
+#define VIDEO_ALPHA_PLANE_TL_TOP                        26:16
+#define VIDEO_ALPHA_PLANE_TL_LEFT                       10:0
+
+#define VIDEO_ALPHA_PLANE_BR                            0x080094
+#define VIDEO_ALPHA_PLANE_BR_BOTTOM                     26:16
+#define VIDEO_ALPHA_PLANE_BR_RIGHT                      10:0
+
+#define VIDEO_ALPHA_SCALE                               0x080098
+#define VIDEO_ALPHA_SCALE_VERTICAL_MODE                 31:31
+#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND          0
+#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK          1
+#define VIDEO_ALPHA_SCALE_VERTICAL_SCALE                27:16
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE               15:15
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND        0
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK        1
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE              11:0
+
+#define VIDEO_ALPHA_INITIAL_SCALE                       0x08009C
+#define VIDEO_ALPHA_INITIAL_SCALE_FB                    11:0
+
+#define VIDEO_ALPHA_CHROMA_KEY                          0x0800A0
+#define VIDEO_ALPHA_CHROMA_KEY_MASK                     31:16
+#define VIDEO_ALPHA_CHROMA_KEY_VALUE                    15:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_01                     0x0800A4
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_23                     0x0800A8
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_45                     0x0800AC
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_67                     0x0800B0
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_89                     0x0800B4
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB                     0x0800B8
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD                     0x0800BC
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF                     0x0800C0
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE              4:0
+
+// Panel Cursor Control
+
+#define PANEL_HWC_ADDRESS                               0x0800F0
+#define PANEL_HWC_ADDRESS_ENABLE                        31:31
+#define PANEL_HWC_ADDRESS_ENABLE_DISABLE                0
+#define PANEL_HWC_ADDRESS_ENABLE_ENABLE                 1
+#define PANEL_HWC_ADDRESS_EXT                           27:27
+#define PANEL_HWC_ADDRESS_EXT_LOCAL                     0
+#define PANEL_HWC_ADDRESS_EXT_EXTERNAL                  1
+#define PANEL_HWC_ADDRESS_CS                            26:26
+#define PANEL_HWC_ADDRESS_CS_0                          0
+#define PANEL_HWC_ADDRESS_CS_1                          1
+#define PANEL_HWC_ADDRESS_ADDRESS                       25:0
+
+#define PANEL_HWC_LOCATION                              0x0800F4
+#define PANEL_HWC_LOCATION_TOP                          27:27
+#define PANEL_HWC_LOCATION_TOP_INSIDE                   0
+#define PANEL_HWC_LOCATION_TOP_OUTSIDE                  1
+#define PANEL_HWC_LOCATION_Y                            26:16
+#define PANEL_HWC_LOCATION_LEFT                         11:11
+#define PANEL_HWC_LOCATION_LEFT_INSIDE                  0
+#define PANEL_HWC_LOCATION_LEFT_OUTSIDE                 1
+#define PANEL_HWC_LOCATION_X                            10:0
+
+#define PANEL_HWC_COLOR_12                              0x0800F8
+#define PANEL_HWC_COLOR_12_2_RGB565                     31:16
+#define PANEL_HWC_COLOR_12_1_RGB565                     15:0
+
+#define PANEL_HWC_COLOR_3                               0x0800FC
+#define PANEL_HWC_COLOR_3_RGB565                        15:0
+
+// Old Definitions +++
+#define PANEL_HWC_COLOR_01                              0x0800F8
+#define PANEL_HWC_COLOR_01_1_RED                        31:27
+#define PANEL_HWC_COLOR_01_1_GREEN                      26:21
+#define PANEL_HWC_COLOR_01_1_BLUE                       20:16
+#define PANEL_HWC_COLOR_01_0_RED                        15:11
+#define PANEL_HWC_COLOR_01_0_GREEN                      10:5
+#define PANEL_HWC_COLOR_01_0_BLUE                       4:0
+
+#define PANEL_HWC_COLOR_2                               0x0800FC
+#define PANEL_HWC_COLOR_2_RED                           15:11
+#define PANEL_HWC_COLOR_2_GREEN                         10:5
+#define PANEL_HWC_COLOR_2_BLUE                          4:0
+// Old Definitions ---
+
+// Alpha Control
+
+#define ALPHA_DISPLAY_CTRL                              0x080100
+#define ALPHA_DISPLAY_CTRL_SELECT                       28:28
+#define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL             0
+#define ALPHA_DISPLAY_CTRL_SELECT_ALPHA                 1
+#define ALPHA_DISPLAY_CTRL_ALPHA                        27:24
+#define ALPHA_DISPLAY_CTRL_FIFO                         17:16
+#define ALPHA_DISPLAY_CTRL_FIFO_1                       0
+#define ALPHA_DISPLAY_CTRL_FIFO_3                       1
+#define ALPHA_DISPLAY_CTRL_FIFO_7                       2
+#define ALPHA_DISPLAY_CTRL_FIFO_11                      3
+#define ALPHA_DISPLAY_CTRL_PIXEL                        7:4
+#define ALPHA_DISPLAY_CTRL_CHROMA_KEY                   3:3
+#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE           0
+#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE            1
+#define ALPHA_DISPLAY_CTRL_PLANE                        2:2
+#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE                0
+#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE                 1
+#define ALPHA_DISPLAY_CTRL_FORMAT                       1:0
+#define ALPHA_DISPLAY_CTRL_FORMAT_16                    1
+#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4             2
+#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4         3
+
+#define ALPHA_FB_ADDRESS                                0x080104
+#define ALPHA_FB_ADDRESS_STATUS                         31:31
+#define ALPHA_FB_ADDRESS_STATUS_CURRENT                 0
+#define ALPHA_FB_ADDRESS_STATUS_PENDING                 1
+#define ALPHA_FB_ADDRESS_EXT                            27:27
+#define ALPHA_FB_ADDRESS_EXT_LOCAL                      0
+#define ALPHA_FB_ADDRESS_EXT_EXTERNAL                   1
+#define ALPHA_FB_ADDRESS_CS                             26:26
+#define ALPHA_FB_ADDRESS_CS_0                           0
+#define ALPHA_FB_ADDRESS_CS_1                           1
+#define ALPHA_FB_ADDRESS_ADDRESS                        25:0
+
+#define ALPHA_FB_WIDTH                                  0x080108
+#define ALPHA_FB_WIDTH_WIDTH                            29:16
+#define ALPHA_FB_WIDTH_OFFSET                           13:0
+
+#define ALPHA_PLANE_TL                                  0x08010C
+#define ALPHA_PLANE_TL_TOP                              26:16
+#define ALPHA_PLANE_TL_LEFT                             10:0
+
+#define ALPHA_PLANE_BR                                  0x080110
+#define ALPHA_PLANE_BR_BOTTOM                           26:16
+#define ALPHA_PLANE_BR_RIGHT                            10:0
+
+#define ALPHA_CHROMA_KEY                                0x080114
+#define ALPHA_CHROMA_KEY_MASK                           31:16
+#define ALPHA_CHROMA_KEY_VALUE                          15:0
+
+#define ALPHA_COLOR_LOOKUP_01                           0x080118
+#define ALPHA_COLOR_LOOKUP_01_1_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_01_1_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_01_1_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_01_0_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_01_0_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_01_0_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_23                           0x08011C
+#define ALPHA_COLOR_LOOKUP_23_3_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_23_3_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_23_3_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_23_2_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_23_2_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_23_2_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_45                           0x080120
+#define ALPHA_COLOR_LOOKUP_45_5_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_45_5_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_45_5_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_45_4_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_45_4_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_45_4_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_67                           0x080124
+#define ALPHA_COLOR_LOOKUP_67_7_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_67_7_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_67_7_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_67_6_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_67_6_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_67_6_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_89                           0x080128
+#define ALPHA_COLOR_LOOKUP_89_9_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_89_9_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_89_9_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_89_8_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_89_8_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_89_8_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_AB                           0x08012C
+#define ALPHA_COLOR_LOOKUP_AB_B_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_AB_B_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_AB_B_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_AB_A_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_AB_A_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_AB_A_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_CD                           0x080130
+#define ALPHA_COLOR_LOOKUP_CD_D_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_CD_D_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_CD_D_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_CD_C_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_CD_C_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_CD_C_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_EF                           0x080134
+#define ALPHA_COLOR_LOOKUP_EF_F_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_EF_F_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_EF_F_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_EF_E_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_EF_E_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_EF_E_BLUE                    4:0
+
+// CRT Graphics Control
+
+#define CRT_DISPLAY_CTRL                                0x080200
+#define CRT_DISPLAY_CTRL_FIFO                           17:16
+#define CRT_DISPLAY_CTRL_FIFO_1                         0
+#define CRT_DISPLAY_CTRL_FIFO_3                         1
+#define CRT_DISPLAY_CTRL_FIFO_7                         2
+#define CRT_DISPLAY_CTRL_FIFO_11                        3
+#define CRT_DISPLAY_CTRL_TV_PHASE                       15:15
+#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_HIGH           0
+#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_LOW            1
+#define CRT_DISPLAY_CTRL_CLOCK_PHASE                    14:14
+#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH        0
+#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW         1
+#define CRT_DISPLAY_CTRL_VSYNC_PHASE                    13:13
+#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH        0
+#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW         1
+#define CRT_DISPLAY_CTRL_HSYNC_PHASE                    12:12
+#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH        0
+#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW         1
+#define CRT_DISPLAY_CTRL_BLANK                          10:10
+#define CRT_DISPLAY_CTRL_BLANK_OFF                      0
+#define CRT_DISPLAY_CTRL_BLANK_ON                       1
+#define CRT_DISPLAY_CTRL_SELECT                         9:9
+#define CRT_DISPLAY_CTRL_SELECT_PANEL                   0
+#define CRT_DISPLAY_CTRL_SELECT_CRT                     1
+#define CRT_DISPLAY_CTRL_TIMING                         8:8
+#define CRT_DISPLAY_CTRL_TIMING_DISABLE                 0
+#define CRT_DISPLAY_CTRL_TIMING_ENABLE                  1
+#define CRT_DISPLAY_CTRL_PIXEL                          7:4
+#define CRT_DISPLAY_CTRL_GAMMA                          3:3
+#define CRT_DISPLAY_CTRL_GAMMA_DISABLE                  0
+#define CRT_DISPLAY_CTRL_GAMMA_ENABLE                   1
+#define CRT_DISPLAY_CTRL_PLANE                          2:2
+#define CRT_DISPLAY_CTRL_PLANE_DISABLE                  0
+#define CRT_DISPLAY_CTRL_PLANE_ENABLE                   1
+#define CRT_DISPLAY_CTRL_FORMAT                         1:0
+#define CRT_DISPLAY_CTRL_FORMAT_8                       0
+#define CRT_DISPLAY_CTRL_FORMAT_16                      1
+#define CRT_DISPLAY_CTRL_FORMAT_32                      2
+
+#define CRT_FB_ADDRESS                                  0x080204
+#define CRT_FB_ADDRESS_STATUS                           31:31
+#define CRT_FB_ADDRESS_STATUS_CURRENT                   0
+#define CRT_FB_ADDRESS_STATUS_PENDING                   1
+#define CRT_FB_ADDRESS_EXT                              27:27
+#define CRT_FB_ADDRESS_EXT_LOCAL                        0
+#define CRT_FB_ADDRESS_EXT_EXTERNAL                     1
+#define CRT_FB_ADDRESS_CS                               26:26
+#define CRT_FB_ADDRESS_CS_0                             0
+#define CRT_FB_ADDRESS_CS_1                             1
+#define CRT_FB_ADDRESS_ADDRESS                          25:0
+
+#define CRT_FB_WIDTH                                    0x080208
+#define CRT_FB_WIDTH_WIDTH                              29:16
+#define CRT_FB_WIDTH_OFFSET                             13:0
+
+#define CRT_HORIZONTAL_TOTAL                            0x08020C
+#define CRT_HORIZONTAL_TOTAL_TOTAL                      27:16
+#define CRT_HORIZONTAL_TOTAL_DISPLAY_END                11:0
+
+#define CRT_HORIZONTAL_SYNC                             0x080210
+#define CRT_HORIZONTAL_SYNC_WIDTH                       23:16
+#define CRT_HORIZONTAL_SYNC_START                       11:0
+
+#define CRT_VERTICAL_TOTAL                              0x080214
+#define CRT_VERTICAL_TOTAL_TOTAL                        26:16
+#define CRT_VERTICAL_TOTAL_DISPLAY_END                  10:0
+
+#define CRT_VERTICAL_SYNC                               0x080218
+#define CRT_VERTICAL_SYNC_HEIGHT                        21:16
+#define CRT_VERTICAL_SYNC_START                         10:0
+
+#define CRT_SIGNATURE_ANALYZER                          0x08021C
+#define CRT_SIGNATURE_ANALYZER_STATUS                   31:16
+#define CRT_SIGNATURE_ANALYZER_ENABLE                   3:3
+#define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE           0
+#define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE            1
+#define CRT_SIGNATURE_ANALYZER_RESET                    2:2
+#define CRT_SIGNATURE_ANALYZER_RESET_NORMAL             0
+#define CRT_SIGNATURE_ANALYZER_RESET_RESET              1
+#define CRT_SIGNATURE_ANALYZER_SOURCE                   1:0
+#define CRT_SIGNATURE_ANALYZER_SOURCE_RED               0
+#define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN             1
+#define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE              2
+
+#define CRT_CURRENT_LINE                                0x080220
+#define CRT_CURRENT_LINE_LINE                           10:0
+
+#define CRT_MONITOR_DETECT                              0x080224
+#define CRT_MONITOR_DETECT_ENABLE                       24:24
+#define CRT_MONITOR_DETECT_ENABLE_DISABLE               0
+#define CRT_MONITOR_DETECT_ENABLE_ENABLE                1
+#define CRT_MONITOR_DETECT_RED                          23:16
+#define CRT_MONITOR_DETECT_GREEN                        15:8
+#define CRT_MONITOR_DETECT_BLUE                         7:0
+
+// CRT Cursor Control
+
+#define CRT_HWC_ADDRESS                                 0x080230
+#define CRT_HWC_ADDRESS_ENABLE                          31:31
+#define CRT_HWC_ADDRESS_ENABLE_DISABLE                  0
+#define CRT_HWC_ADDRESS_ENABLE_ENABLE                   1
+#define CRT_HWC_ADDRESS_EXT                             27:27
+#define CRT_HWC_ADDRESS_EXT_LOCAL                       0
+#define CRT_HWC_ADDRESS_EXT_EXTERNAL                    1
+#define CRT_HWC_ADDRESS_CS                              26:26
+#define CRT_HWC_ADDRESS_CS_0                            0
+#define CRT_HWC_ADDRESS_CS_1                            1
+#define CRT_HWC_ADDRESS_ADDRESS                         25:0
+
+#define CRT_HWC_LOCATION                                0x080234
+#define CRT_HWC_LOCATION_TOP                            27:27
+#define CRT_HWC_LOCATION_TOP_INSIDE                     0
+#define CRT_HWC_LOCATION_TOP_OUTSIDE                    1
+#define CRT_HWC_LOCATION_Y                              26:16
+#define CRT_HWC_LOCATION_LEFT                           11:11
+#define CRT_HWC_LOCATION_LEFT_INSIDE                    0
+#define CRT_HWC_LOCATION_LEFT_OUTSIDE                   1
+#define CRT_HWC_LOCATION_X                              10:0
+
+#define CRT_HWC_COLOR_12                                0x080238
+#define CRT_HWC_COLOR_12_2_RGB565                       31:16
+#define CRT_HWC_COLOR_12_1_RGB565                       15:0
+
+#define CRT_HWC_COLOR_3                                 0x08023C
+#define CRT_HWC_COLOR_3_RGB565                          15:0
+
+// Old Definitions +++
+#define CRT_HWC_COLOR_01                                0x080238
+#define CRT_HWC_COLOR_01_1_RED                          31:27
+#define CRT_HWC_COLOR_01_1_GREEN                        26:21
+#define CRT_HWC_COLOR_01_1_BLUE                         20:16
+#define CRT_HWC_COLOR_01_0_RED                          15:11
+#define CRT_HWC_COLOR_01_0_GREEN                        10:5
+#define CRT_HWC_COLOR_01_0_BLUE                         4:0
+
+#define CRT_HWC_COLOR_2                                 0x08023C
+#define CRT_HWC_COLOR_2_RED                             15:11
+#define CRT_HWC_COLOR_2_GREEN                           10:5
+#define CRT_HWC_COLOR_2_BLUE                            4:0
+// Old Definitions ---
+
+// Palette RAM
+
+#define PANEL_PALETTE_RAM                               0x080400
+#define VIDEO_PALETTE_RAM                               0x080800
+#define CRT_PALETTE_RAM                                 0x080C00
+
+
+
+/*****************************************************************************\
+ *                                 ZV PORT                                   *
+\*****************************************************************************/
+
+#define CAPTURE_CONTROL                                 0x090000
+#define CAPTURE_CONTROL_FIELD                           27:27
+#define CAPTURE_CONTROL_FIELD_EVEN						0
+#define CAPTURE_CONTROL_FIELD_ODD						1
+#define CAPTURE_CONTROL_INTERLACE						26:26
+#define CAPTURE_CONTROL_INTERLACE_NON_INTERLACED		0
+#define CAPTURE_CONTROL_INTERLACE_INTERLACED			1
+#define CAPTURE_CONTROL_CAPTURE_BUFFER					25:25
+#define CAPTURE_CONTROL_CAPTURE_BUFFER_0				0
+#define CAPTURE_CONTROL_CAPTURE_BUFFER_1				1
+#define CAPTURE_CONTROL_VSYNC							24:24
+#define CAPTURE_CONTROL_VSYNC_INACTIVE					0
+#define CAPTURE_CONTROL_VSYNC_ACTIVE					1
+#define CAPTURE_CONTROL_ADJ                            19:19
+#define CAPTURE_CONTROL_ADJ_NORMAL                     0
+#define CAPTURE_CONTROL_ADJ_DELAY                      1
+#define CAPTURE_CONTROL_HORIZONTAL_AVE					18:18
+#define CAPTURE_CONTROL_HORIZONTAL_AVE_DISABLE			0
+#define CAPTURE_CONTROL_HORIZONTAL_AVE_ENABLE			1
+#define CAPTURE_CONTROL_2TO1_VERTICAL_SHRINK			17:17
+#define CAPTURE_CONTROL_2TO1_VERTICAL_SHRINK_DISABLE	0
+#define CAPTURE_CONTROL_2TO1_VERTICAL_SHRINK_ENABLE		1
+#define CAPTURE_CONTROL_2TO1_HORIZONTAL_SHRINK			16:16
+#define CAPTURE_CONTROL_2TO1_HORIZONTAL_SHRINK_DISABLE	0
+#define CAPTURE_CONTROL_2TO1_HORIZONTAL_SHRINK_ENABLE	1
+#define CAPTURE_CONTROL_FIELD_DETECT					15:15
+#define CAPTURE_CONTROL_FIELD_DETECT_RISING				0
+#define CAPTURE_CONTROL_FIELD_DETECT_FALLING			1
+#define CAPTURE_CONTROL_VSYNC_PHASE						14:14
+#define CAPTURE_CONTROL_VSYNC_PHASE_ACTIVE_HIGH			0
+#define CAPTURE_CONTROL_VSYNC_PHASE_ACTIVE_LOW			1
+#define CAPTURE_CONTROL_HREF_PHASE						13:13
+#define CAPTURE_CONTROL_HREF_PHASE_ACTIVE_HIGH			0
+#define CAPTURE_CONTROL_HREF_PHASE_ACTIVE_LOW			1
+#define CAPTURE_CONTROL_CLOCK_POLARITY					12:12
+#define CAPTURE_CONTROL_CLOCK_POLARITY_ACTIVE_HIGH		0
+#define CAPTURE_CONTROL_CLOCK_POLARITY_ACTIVE_LOW		1
+#define CAPTURE_CONTROL_UV_SWAP							11:11
+#define CAPTURE_CONTROL_UV_SWAP_DISABLE					0
+#define CAPTURE_CONTROL_UV_SWAP_ENABLE					1
+#define CAPTURE_CONTROL_BYTE_SWAP						10:10
+#define CAPTURE_CONTROL_BYTE_SWAP_DISABLE				0
+#define CAPTURE_CONTROL_BYTE_SWAP_ENABLE				1
+#define CAPTURE_CONTROL_CAPTURE_SIZE					9:9
+#define CAPTURE_CONTROL_CAPTURE_SIZE_16					0
+#define CAPTURE_CONTROL_CAPTURE_SIZE_8					1
+#define CAPTURE_CONTROL_CAPTURE_FORMAT					8:8
+#define CAPTURE_CONTROL_CAPTURE_FORMAT_YUV				0
+#define CAPTURE_CONTROL_CAPTURE_FORMAT_RGB				1
+#define CAPTURE_CONTROL_FIELD_SWAP						7:7
+#define CAPTURE_CONTROL_FIELD_SWAP_DISABLE				0
+#define CAPTURE_CONTROL_FIELD_SWAP_ENABLE				1
+#define CAPTURE_CONTROL_INTERLACE_WEAVE					6:6
+#define CAPTURE_CONTROL_INTERLACE_WEAVE_DISABLE			0
+#define CAPTURE_CONTROL_INTERLACE_WEAVE_ENABLE			1
+#define CAPTURE_CONTROL_INTERLACE_BOB					5:5
+#define CAPTURE_CONTROL_INTERLACE_BOB_DISABLE			0
+#define CAPTURE_CONTROL_INTERLACE_BOB_ENABLE			1
+#define CAPTURE_CONTROL_DOUBLE_BUFFERING				4:4
+#define CAPTURE_CONTROL_DOUBLE_BUFFERING_DISABLE		0
+#define CAPTURE_CONTROL_DOUBLE_BUFFERING_ENABLE			1
+#define CAPTURE_CONTROL_CAPTURE_CONTROL					3:3
+#define CAPTURE_CONTROL_CAPTURE_CONTROL_CONTINUOUS		0
+#define CAPTURE_CONTROL_CAPTURE_CONTROL_CONDITIONAL		1
+#define CAPTURE_CONTROL_RGB                            2:2
+#define CAPTURE_CONTROL_RGB_DISABLE                    0
+#define CAPTURE_CONTROL_RGB_ENABLE                     1
+#define CAPTURE_CONTROL_656                            1:1
+#define CAPTURE_CONTROL_656_DISABLE                    0
+#define CAPTURE_CONTROL_656_ENABLE                     1
+#define CAPTURE_CONTROL_CAPTURE							0:0
+#define CAPTURE_CONTROL_CAPTURE_DISABLE					0
+#define CAPTURE_CONTROL_CAPTURE_ENABLE					1
+
+#define CAPTURE_CLIPPING								0x090004
+#define CAPTURE_CLIPPING_YCLIP							25:16
+#define CAPTURE_CLIPPING_XCLIP							9:0
+
+#define CAPTURE_SIZE									0x90008
+#define CAPTURE_SIZE_HEIGHT								26:16
+#define CAPTURE_SIZE_WIDTH								10:0
+
+#define CAPTURE_BUFFER_0_ADDRESS						0x9000C
+#define CAPTURE_BUFFER_0_ADDRESS_STATUS					31:31
+#define CAPTURE_BUFFER_0_ADDRESS_STATUS_CURRENT			0
+#define CAPTURE_BUFFER_0_ADDRESS_STATUS_PENDING			1
+#define CAPTURE_BUFFER_0_ADDRESS_EXT					27:27
+#define CAPTURE_BUFFER_0_ADDRESS_EXT_LOCAL				0
+#define CAPTURE_BUFFER_0_ADDRESS_EXT_EXTERNAL			1
+#define CAPTURE_BUFFER_0_ADDRESS_CS						26:26
+#define CAPTURE_BUFFER_0_ADDRESS_CS_0					0
+#define CAPTURE_BUFFER_0_ADDRESS_CS_1					1
+#define CAPTURE_BUFFER_0_ADDRESS_ADDRESS				25:0
+
+#define CAPTURE_BUFFER_1_ADDRESS						0x90010
+#define CAPTURE_BUFFER_1_ADDRESS_STATUS					31:31
+#define CAPTURE_BUFFER_1_ADDRESS_STATUS_CURRENT			0
+#define CAPTURE_BUFFER_1_ADDRESS_STATUS_PENDING			1
+#define CAPTURE_BUFFER_1_ADDRESS_EXT					27:27
+#define CAPTURE_BUFFER_1_ADDRESS_EXT_LOCAL				0
+#define CAPTURE_BUFFER_1_ADDRESS_EXT_EXTERNAL			1
+#define CAPTURE_BUFFER_1_ADDRESS_CS						26:26
+#define CAPTURE_BUFFER_1_ADDRESS_CS_0					0
+#define CAPTURE_BUFFER_1_ADDRESS_CS_1					1
+#define CAPTURE_BUFFER_1_ADDRESS_ADDRESS				25:0
+
+#define CAPTURE_BUFFER_OFFSET							0x90014
+#define CAPTURE_BUFFER_OFFSET_OFFSET					15:0
+
+#define CAPTURE_FIFO									0x90018
+#define CAPTURE_FIFO_CONTROL							2:0
+#define CAPTURE_FIFO_CONTROL_2							0
+#define CAPTURE_FIFO_CONTROL_3							1
+#define CAPTURE_FIFO_CONTROL_4							2
+#define CAPTURE_FIFO_CONTROL_5							3
+#define CAPTURE_FIFO_CONTROL_6							4
+#define CAPTURE_FIFO_CONTROL_8							5
+#define CAPTURE_FIFO_CONTROL_10							6
+#define CAPTURE_FIFO_CONTROL_12							7
+
+#define CAPTURE_YRGB_CONST                          0x09001C
+#define CAPTURE_YRGB_CONST_Y                        31:24
+#define CAPTURE_YRGB_CONST_R                        23:16
+#define CAPTURE_YRGB_CONST_G                        15:8
+#define CAPTURE_YRGB_CONST_B                        7:0
+
+
+/*****************************************************************************\
+ *                                AC97 / I2S                                 *
+\*****************************************************************************/
+
+/* AC97 TX Slot 0: TAG */
+#define AC97_TX_SLOT0                                               0x0A0100
+#define AC97_TX_SLOT0_VALID_FRAME_TAG                               15:15
+#define AC97_TX_SLOT0_VALID_FRAME_TAG_IGNORE                        0
+#define AC97_TX_SLOT0_VALID_FRAME_TAG_INTERPRET                     1
+#define AC97_TX_SLOT0_VALID_S1                                      14:14
+#define AC97_TX_SLOT0_VALID_S1_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S1_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S2                                      13:13
+#define AC97_TX_SLOT0_VALID_S2_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S2_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S3                                      12:12
+#define AC97_TX_SLOT0_VALID_S3_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S3_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S4                                      11:11
+#define AC97_TX_SLOT0_VALID_S4_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S4_DATA                                 1
+
+/* AC97 TX Slot 1: Command Address Port */
+#define AC97_TX_SLOT1                                               0x0A0104
+#define AC97_TX_SLOT1_READ_WRITE                                    19:19
+#define AC97_TX_SLOT1_READ_WRITE_WRITE                              0
+#define AC97_TX_SLOT1_READ_WRITE_READ                               1
+#define AC97_TX_SLOT1_CONTROL_REGISTER_INDEX                        18:12
+
+/* AC97 TX Slot 2: Command Address Port */
+#define AC97_TX_SLOT2                                               0x0A0108
+#define AC97_TX_SLOT2_DATA                                          19:4
+
+/* AC97 TX Slot 3: PCM Playback Left Channel */
+#define AC97_TX_SLOT3                                               0x0A010C
+#define AC97_TX_SLOT3_DATA                                          19:0
+
+/* AC97 TX Slot 4: PCM Playback Right Channel */
+#define AC97_TX_SLOT4                                               0x0A0110
+#define AC97_TX_SLOT4_DATA                                          19:0
+
+/* AC97 RX Slot 0: TAG */
+#define AC97_RX_SLOT0                                               0x0A0140
+#define AC97_RX_SLOT0_CODEC_READY_FLAG                              15:15
+#define AC97_RX_SLOT0_CODEC_READY_FLAG_IGNORE                       0
+#define AC97_RX_SLOT0_CODEC_READY_FLAG_READY                        1
+#define AC97_RX_SLOT0_VALID_S1                                      14:14
+#define AC97_RX_SLOT0_VALID_S1_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S1_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S2                                      13:13
+#define AC97_RX_SLOT0_VALID_S2_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S2_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S3                                      12:12
+#define AC97_RX_SLOT0_VALID_S3_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S3_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S4                                      11:11
+#define AC97_RX_SLOT0_VALID_S4_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S4_DATA                                 1
+
+/* AC97 RX Slot 1: Status Address Port */
+#define AC97_RX_SLOT1                                               0x0A0144
+#define AC97_RX_SLOT1_CONTROL_REGISTER_INDEX                        18:12
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3                             11:11
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3_SEND                        0
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3_DO_NOT_SEND                 1
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4                             10:10
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4_SEND                        0
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4_DO_NOT_SEND                 1
+
+/* AC97 RX Slot 2: Status Address Port */
+#define AC97_RX_SLOT2                                               0x0A0148
+#define AC97_RX_SLOT2_DATA                                          19:4
+
+/* AC97 RX Slot 3: PCM Record Left Channel */
+#define AC97_RX_SLOT3                                               0x0A014C
+#define AC97_RX_SLOT3_DATA                                          19:0
+
+/* AC97 RX Slot 4: PCM Record Right Channel */
+#define AC97_RX_SLOT4                                               0x0A0150
+#define AC97_RX_SLOT4_DATA                                          19:0
+
+/* AC97 Control & Status */
+#define AC97_CONTROL_STATUS                                         0x0A0180
+#define AC97_CONTROL_STATUS_DATA_DROPPED_COUNT                      15:10
+#define AC97_CONTROL_STATUS_SYNC_CONTROL                            9:9
+#define AC97_CONTROL_STATUS_SYNC_CONTROL_ENABLE                     0
+#define AC97_CONTROL_STATUS_SYNC_CONTROL_STOP                       1
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL                           8:8
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL_NOT_RUNNING               0
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL_RUNNING                   1
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST                          7:7
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST_DISABLE                  0
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST_ENABLE                   1
+#define AC97_CONTROL_STATUS_STATUS                                  5:4
+#define AC97_CONTROL_STATUS_STATUS_OFF                              0
+#define AC97_CONTROL_STATUS_STATUS_RESET                            1
+#define AC97_CONTROL_STATUS_STATUS_WAITING                          2
+#define AC97_CONTROL_STATUS_STATUS_ACTIVE                           3
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT                        3:3
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT_DISABLED               0
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT_ENABLED                1
+#define AC97_CONTROL_STATUS_WARM_RESET                              2:2
+#define AC97_CONTROL_STATUS_WARM_RESET_NORMAL                       0
+#define AC97_CONTROL_STATUS_WARM_RESET_RESET                        1
+#define AC97_CONTROL_STATUS_COLD_RESET                              1:1
+#define AC97_CONTROL_STATUS_COLD_RESET_NORMAL                       0
+#define AC97_CONTROL_STATUS_COLD_RESET_RESET                        1
+#define AC97_CONTROL_STATUS_CONTROL                                 0:0
+#define AC97_CONTROL_STATUS_CONTROL_DISABLED                        0
+#define AC97_CONTROL_STATUS_CONTROL_ENABLED                         1
+
+/* I2S TX Data Left */
+#define I2S_TX_DATA_LEFT                                            0x0A0200
+#define I2S_TX_DATA_LEFT_DATA                                       15:0
+
+/* I2S TX Data Right */
+#define I2S_TX_DATA_RIGHT                                           0x0A0204
+#define I2S_TX_DATA_RIGHT_DATA                                      15:0
+
+/* I2S RX Data Left */
+#define I2S_RX_DATA_LEFT                                            0x0A0208
+#define I2S_RX_DATA_LEFT_DATA                                       15:0
+
+/* I2S RX Data Right */
+#define I2S_RX_DATA_RIGHT                                           0x0A020C
+#define I2S_RX_DATA_RIGHT_DATA                                      15:0
+
+/* I2S Control & Status */
+#define I2S_CONTROL_STATUS                                          0x0A0210
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS                           11:11
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS_NO_ERROR                  0
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS_OVERFLOW                  1
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS                          10:10
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS_NO_ERROR                 0
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS_UNDERFLOW                1
+#define I2S_CONTROL_STATUS_CONTROL                                  2:2
+#define I2S_CONTROL_STATUS_CONTROL_DISABLED                         0
+#define I2S_CONTROL_STATUS_CONTROL_ENABLED                          1
+
+/* I2S Clock Control */
+#define I2S_CLOCK_CONTROL                                           0x0A0214
+#define I2S_CLOCK_CONTROL_MODE_SELECT                               7:7
+#define I2S_CLOCK_CONTROL_MODE_SELECT_SLAVE                         0
+#define I2S_CLOCK_CONTROL_MODE_SELECT_MASTER                        1
+#define I2S_CLOCK_CONTROL_WORD_SELECT                               6:5
+#define I2S_CLOCK_CONTROL_WORD_SELECT_16BIT                         0
+#define I2S_CLOCK_CONTROL_WORD_SELECT_24BIT                         1
+#define I2S_CLOCK_CONTROL_WORD_SELECT_32BIT                         2
+#define I2S_CLOCK_CONTROL_CLOCK_DIVIDER                             4:0
+
+/*****************************************************************************\
+ *                                    8051                                   *
+\*****************************************************************************/
+
+/* Reset */
+#define U8051_RESET                                                 0x0B0000
+#define U8051_RESET_CONTROL                                         0:0
+#define U8051_RESET_CONTROL_RESET                                   0
+#define U8051_RESET_CONTROL_ENABLE                                  1
+
+/* Mode Select */
+#define U8051_MODE_SELECT                                           0x0B0004
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE                      7:6
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_NONE                 0
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_1WS                  1
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_2WS                  2
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_3WS                  3
+#define U8051_MODE_SELECT_SRAM                                      5:5
+#define U8051_MODE_SELECT_SRAM_ENABLED                              0
+#define U8051_MODE_SELECT_SRAM_DISABLED                             1
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE                        4:4
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE_12BIT                  0
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE_8BIT                   1
+#define U8051_MODE_SELECT_TEST_MODE                                 3:3
+#define U8051_MODE_SELECT_TEST_MODE_NORMAL                          0
+#define U8051_MODE_SELECT_TEST_MODE_ENABLED                         1
+#define U8051_MODE_SELECT_CODEC_SELECT                              2:2
+#define U8051_MODE_SELECT_CODEC_SELECT_AC97                         0
+#define U8051_MODE_SELECT_CODEC_SELECT_I2S                          1
+#define U8051_MODE_SELECT_DIVIDER                                   1:0
+#define U8051_MODE_SELECT_DIVIDER_2                                 0
+#define U8051_MODE_SELECT_DIVIDER_3                                 1
+#define U8051_MODE_SELECT_DIVIDER_4                                 2
+#define U8051_MODE_SELECT_DIVIDER_5                                 3
+
+/* 8051 Protocol Interrupt */
+#define U8051_8051_PROTOCOL_INTERRUPT                               0x0B0008
+#define U8051_8051_PROTOCOL_INTERRUPT_TOKEN                         31:0
+
+/* 8051 Protocol Interrupt */
+#define IRQ_8051_TO_HIF                                0x000B0008
+#define IRQ_8051_TO_HIF_CODE                           7:0
+#define IRQ_8051_TO_HIF_PARAMETER1                     15:8
+#define IRQ_8051_TO_HIF_PARAMETER2                     23:16
+#define IRQ_8051_TO_HIF_PARAMETER3                     31:24
+
+/* CPU Protocol Interrupt */
+#define U8051_CPU_PROTOCOL_INTERRUPT                                0x0B000C
+#define U8051_CPU_PROTOCOL_INTERRUPT_TOKEN                          31:0
+
+/* CPU Protocol Interrupt */
+#define IRQ_HIF_TO_8051                                0x000B000C
+#define IRQ_HIF_TO_8051_CODE                           31:0
+#define IRQ_HIF_TO_8051_CODE1                          7:0
+#define IRQ_HIF_TO_8051_CODE2                          15:8
+#define IRQ_HIF_TO_8051_CODE3                          23:16
+#define IRQ_HIF_TO_8051_CODE4                          31:24
+
+/* SRAM Address Space */
+#define U8051_SRAM                                    0x000C0000	// 8051: 0000-0FFF
+#define U8051_SRAM1                                    0x000C1000	// 8051: 1000-1FFF
+#define U8051_SRAM2                                    0x000C2000	// 8051: 2000-2FFF
+#define U8051_SRAM3                                    0x000C3000	// 8051: 3000-3FFF (dual port SRAM)
+
+#define U8051_SRAM_SIZE                                             0x004000
+
+/*****************************************************************************\
+ *                                     DMA                                   *
+\*****************************************************************************/
+
+/* DMA 0 SDRAM Address */
+#define DMA0_SDRAM                                                  0x0D0000
+#define DMA0_SDRAM_MEMORY                                           27:26
+#define DMA0_SDRAM_MEMORY_LOCAL                                     0
+#define DMA0_SDRAM_MEMORY_EXTERNAL_CS0                              2
+#define DMA0_SDRAM_MEMORY_EXTERNAL_CS1                              3
+#define DMA0_SDRAM_ADDRESS                                          25:0
+
+/* DMA 0 SRAM Address */
+#define DMA0_SRAM                                                   0x0D0004
+#define DMA0_SRAM_ADDRESS                                           15:0
+
+/* DMA 0 Size & Control */
+#define DMA0_SIZE_CONTROL                                           0x0D0008
+#define DMA0_SIZE_CONTROL_ACTIVE                                    31:31
+#define DMA0_SIZE_CONTROL_ACTIVE_IDLE                               0
+#define DMA0_SIZE_CONTROL_ACTIVE_START                              1
+#define DMA0_SIZE_CONTROL_DIRECTION                                 30:30
+#define DMA0_SIZE_CONTROL_DIRECTION_WRITE_SRAM                      0
+#define DMA0_SIZE_CONTROL_DIRECTION_READ_SRAM                       1
+#define DMA0_SIZE_CONTROL_SIZE                                      15:0
+
+/* DMA 1 Source Address */
+#define DMA1_SOURCE                                                 0x0D0010
+#define DMA1_SOURCE_MEMORY                                          27:26
+#define DMA1_SOURCE_MEMORY_LOCAL                                    0
+#define DMA1_SOURCE_MEMORY_EXTERNAL_CS0                             2
+#define DMA1_SOURCE_MEMORY_EXTERNAL_CS1                             3
+#define DMA1_SOURCE_ADDRESS                                         25:0
+
+/* DMA 1 Destination Address */
+#define DMA1_DESTINATION                                            0x0D0014
+#define DMA1_DESTINATION_MEMORY                                     27:26
+#define DMA1_DESTINATION_MEMORY_LOCAL                               0
+#define DMA1_DESTINATION_MEMORY_EXTERNAL_CS0                        2
+#define DMA1_DESTINATION_MEMORY_EXTERNAL_CS1                        3
+#define DMA1_DESTINATION_ADDRESS                                    25:0
+
+/* DMA 1 Size & Control */
+#define DMA1_SIZE_CONTROL                                           0x0D0018
+#define DMA1_SIZE_CONTROL_ACTIVE                                    31:31
+#define DMA1_SIZE_CONTROL_ACTIVE_IDLE                               0
+#define DMA1_SIZE_CONTROL_ACTIVE_START                              1
+#define DMA1_SIZE_CONTROL_SIZE                                      23:0
+
+/* DMA Abort & Interrupt */
+#define DMA_ABORT_INTERRUPT                                         0x0D0020
+#define DMA_ABORT_INTERRUPT_ABORT_1                                 5:5
+#define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE                          0
+#define DMA_ABORT_INTERRUPT_ABORT_1_ABORT                           1
+#define DMA_ABORT_INTERRUPT_ABORT_0                                 4:4
+#define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE                          0
+#define DMA_ABORT_INTERRUPT_ABORT_0_ABORT                           1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1                      1:1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1_NOT_ACTIVE           0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1_ACTIVE               1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0                      0:0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0_NOT_ACTIVE           0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0_ACTIVE               1
+
+
+/*****************************************************************************\
+ *                                  2D ENGINE                                *
+\*****************************************************************************/
+
+#define DE_SOURCE                                       0x000000
+#define DE_SOURCE_WRAP                                  31:31
+#define DE_SOURCE_WRAP_DISABLE                          0
+#define DE_SOURCE_WRAP_ENABLE                           1
+#define DE_SOURCE_X_K1                                  29:16
+#define DE_SOURCE_Y_K2                                  15:0
+
+#define DE_DESTINATION                                  0x000004
+#define DE_DESTINATION_WRAP                             31:31
+#define DE_DESTINATION_WRAP_DISABLE                     0
+#define DE_DESTINATION_WRAP_ENABLE                      1
+#define DE_DESTINATION_X                                28:16
+#define DE_DESTINATION_Y                                15:0
+
+#define DE_DIMENSION                                    0x000008
+#define DE_DIMENSION_X                                  28:16
+#define DE_DIMENSION_Y_ET                               15:0
+
+#define DE_CONTROL                                      0x00000C
+#define DE_CONTROL_STATUS                               31:31
+#define DE_CONTROL_STATUS_STOP                          0
+#define DE_CONTROL_STATUS_START                         1
+#define DE_CONTROL_PATTERN                              30:30
+#define DE_CONTROL_PATTERN_MONO                         0
+#define DE_CONTROL_PATTERN_COLOR                        1
+#define DE_CONTROL_UPDATE_DESTINATION_X                 29:29
+#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE         0
+#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE          1
+#define DE_CONTROL_QUICK_START                          28:28
+#define DE_CONTROL_QUICK_START_DISABLE                  0
+#define DE_CONTROL_QUICK_START_ENABLE                   1
+#define DE_CONTROL_DIRECTION                            27:27
+#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT              0
+#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT              1
+#define DE_CONTROL_MAJOR                                26:26
+#define DE_CONTROL_MAJOR_X                              0
+#define DE_CONTROL_MAJOR_Y                              1
+#define DE_CONTROL_STEP_X                               25:25
+#define DE_CONTROL_STEP_X_POSITIVE                      1
+#define DE_CONTROL_STEP_X_NEGATIVE                      0
+#define DE_CONTROL_STEP_Y                               24:24
+#define DE_CONTROL_STEP_Y_POSITIVE                      1
+#define DE_CONTROL_STEP_Y_NEGATIVE                      0
+#define DE_CONTROL_STRETCH                              23:23
+#define DE_CONTROL_STRETCH_DISABLE                      0
+#define DE_CONTROL_STRETCH_ENABLE                       1
+#define DE_CONTROL_HOST                                 22:22
+#define DE_CONTROL_HOST_COLOR                           0
+#define DE_CONTROL_HOST_MONO                            1
+#define DE_CONTROL_LAST_PIXEL                           21:21
+#define DE_CONTROL_LAST_PIXEL_OFF                       0
+#define DE_CONTROL_LAST_PIXEL_ON                        1
+#define DE_CONTROL_COMMAND                              20:16
+#define DE_CONTROL_COMMAND_BITBLT                       0
+#define DE_CONTROL_COMMAND_RECTANGLE_FILL               1
+#define DE_CONTROL_COMMAND_DE_TILE                      2
+#define DE_CONTROL_COMMAND_TRAPEZOID_FILL               3
+#define DE_CONTROL_COMMAND_ALPHA_BLEND                  4
+#define DE_CONTROL_COMMAND_RLE_STRIP                    5
+#define DE_CONTROL_COMMAND_SHORT_STROKE                 6
+#define DE_CONTROL_COMMAND_LINE_DRAW                    7
+#define DE_CONTROL_COMMAND_HOST_WRITE                   8
+#define DE_CONTROL_COMMAND_HOST_READ                    9
+#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP         10
+#define DE_CONTROL_COMMAND_ROTATE                       11
+#define DE_CONTROL_COMMAND_FONT                         12
+#define DE_CONTROL_COMMAND_TEXTURE_LOAD                 15
+#define DE_CONTROL_ROP_SELECT                           15:15
+#define DE_CONTROL_ROP_SELECT_ROP3                      0
+#define DE_CONTROL_ROP_SELECT_ROP2                      1
+#define DE_CONTROL_ROP2_SOURCE                          14:14
+#define DE_CONTROL_ROP2_SOURCE_BITMAP                   0
+#define DE_CONTROL_ROP2_SOURCE_PATTERN                  1
+#define DE_CONTROL_MONO_DATA                            13:12
+#define DE_CONTROL_MONO_DATA_NOT_PACKED                 0
+#define DE_CONTROL_MONO_DATA_8_PACKED                   1
+#define DE_CONTROL_MONO_DATA_16_PACKED                  2
+#define DE_CONTROL_MONO_DATA_32_PACKED                  3
+#define DE_CONTROL_REPEAT_ROTATE                        11:11
+#define DE_CONTROL_REPEAT_ROTATE_DISABLE                0
+#define DE_CONTROL_REPEAT_ROTATE_ENABLE                 1
+#define DE_CONTROL_TRANSPARENCY_MATCH                   10:10
+#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE            0
+#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT       1
+#define DE_CONTROL_TRANSPARENCY_SELECT                  9:9
+#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE           0
+#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION      1
+#define DE_CONTROL_TRANSPARENCY                         8:8
+#define DE_CONTROL_TRANSPARENCY_DISABLE                 0
+#define DE_CONTROL_TRANSPARENCY_ENABLE                  1
+#define DE_CONTROL_ROP                                  7:0
+
+// Pseudo fields.
+
+#define DE_CONTROL_SHORT_STROKE_DIR                     27:24
+#define DE_CONTROL_SHORT_STROKE_DIR_225                 0
+#define DE_CONTROL_SHORT_STROKE_DIR_135                 1
+#define DE_CONTROL_SHORT_STROKE_DIR_315                 2
+#define DE_CONTROL_SHORT_STROKE_DIR_45                  3
+#define DE_CONTROL_SHORT_STROKE_DIR_270                 4
+#define DE_CONTROL_SHORT_STROKE_DIR_90                  5
+#define DE_CONTROL_SHORT_STROKE_DIR_180                 8
+#define DE_CONTROL_SHORT_STROKE_DIR_0                   10
+#define DE_CONTROL_ROTATION                             25:24
+#define DE_CONTROL_ROTATION_0                           0
+#define DE_CONTROL_ROTATION_270                         1
+#define DE_CONTROL_ROTATION_90                          2
+#define DE_CONTROL_ROTATION_180                         3
+
+#define DE_PITCH                                        0x000010
+#define DE_PITCH_DESTINATION                            28:16
+#define DE_PITCH_SOURCE                                 12:0
+
+#define DE_FOREGROUND                                   0x000014
+#define DE_FOREGROUND_COLOR                             31:0
+
+#define DE_BACKGROUND                                   0x000018
+#define DE_BACKGROUND_COLOR                             31:0
+
+#define DE_STRETCH_FORMAT                               0x00001C
+#define DE_STRETCH_FORMAT_PATTERN_XY                    30:30
+#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL             0
+#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE          1
+#define DE_STRETCH_FORMAT_PATTERN_Y                     29:27
+#define DE_STRETCH_FORMAT_PATTERN_X                     25:23
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT                  21:20
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8                0
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16               1
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32               2
+#define DE_STRETCH_FORMAT_ADDRESSING                    19:16
+#define DE_STRETCH_FORMAT_ADDRESSING_XY                 0
+#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR             15
+#define DE_STRETCH_FORMAT_SOURCE_HEIGHT                 11:0
+
+#define DE_COLOR_COMPARE                                0x000020
+#define DE_COLOR_COMPARE_COLOR                          23:0
+
+#define DE_COLOR_COMPARE_MASK                           0x000024
+#define DE_COLOR_COMPARE_MASK_MASKS                     23:0
+
+#define DE_MASKS                                        0x000028
+#define DE_MASKS_BYTE_MASK                              31:16
+#define DE_MASKS_BIT_MASK                               15:0
+
+#define DE_CLIP_TL                                      0x00002C
+#define DE_CLIP_TL_TOP                                  31:16
+#define DE_CLIP_TL_STATUS                               13:13
+#define DE_CLIP_TL_STATUS_DISABLE                       0
+#define DE_CLIP_TL_STATUS_ENABLE                        1
+#define DE_CLIP_TL_INHIBIT                              12:12
+#define DE_CLIP_TL_INHIBIT_OUTSIDE                      0
+#define DE_CLIP_TL_INHIBIT_INSIDE                       1
+#define DE_CLIP_TL_LEFT                                 11:0
+
+#define DE_CLIP_BR                                      0x000030
+#define DE_CLIP_BR_BOTTOM                               31:16
+#define DE_CLIP_BR_RIGHT                                12:0
+
+#define DE_MONO_PATTERN_LOW                             0x000034
+#define DE_MONO_PATTERN_LOW_PATTERN                     31:0
+
+#define DE_MONO_PATTERN_HIGH                            0x000038
+#define DE_MONO_PATTERN_HIGH_PATTERN                    31:0
+
+#define DE_WINDOW_WIDTH                                 0x00003C
+#define DE_WINDOW_WIDTH_DESTINATION                     28:16
+#define DE_WINDOW_WIDTH_SOURCE                          12:0
+
+#define DE_WINDOW_SOURCE_BASE                           0x000040
+#define DE_WINDOW_SOURCE_BASE_EXT                       27:27
+#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL                 0
+#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL              1
+#define DE_WINDOW_SOURCE_BASE_CS                        26:26
+#define DE_WINDOW_SOURCE_BASE_CS_0                      0
+#define DE_WINDOW_SOURCE_BASE_CS_1                      1
+#define DE_WINDOW_SOURCE_BASE_ADDRESS                   25:0
+
+#define DE_WINDOW_DESTINATION_BASE                      0x000044
+#define DE_WINDOW_DESTINATION_BASE_EXT                  27:27
+#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL            0
+#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL         1
+#define DE_WINDOW_DESTINATION_BASE_CS                   26:26
+#define DE_WINDOW_DESTINATION_BASE_CS_0                 0
+#define DE_WINDOW_DESTINATION_BASE_CS_1                 1
+#define DE_WINDOW_DESTINATION_BASE_ADDRESS              25:0
+
+#define DE_ALPHA                                        0x000048
+#define DE_ALPHA_VALUE                                  7:0
+
+#define DE_WRAP                                         0x00004C
+#define DE_WRAP_X                                       31:16
+#define DE_WRAP_Y                                       15:0
+
+#define DE_STATUS                                       0x000050
+#define DE_STATUS_CSC                                   1:1
+#define DE_STATUS_CSC_CLEAR                             0
+#define DE_STATUS_CSC_NOT_ACTIVE                        0
+#define DE_STATUS_CSC_ACTIVE                            1
+#define DE_STATUS_2D                                    0:0
+#define DE_STATUS_2D_CLEAR                              0
+#define DE_STATUS_2D_NOT_ACTIVE                         0
+#define DE_STATUS_2D_ACTIVE                             1
+
+// Color Space Conversion registers.
+
+#define CSC_Y_SOURCE_BASE                               0x0000C8
+#define CSC_Y_SOURCE_BASE_EXT                           27:27
+#define CSC_Y_SOURCE_BASE_EXT_LOCAL                     0
+#define CSC_Y_SOURCE_BASE_EXT_EXTERNAL                  1
+#define CSC_Y_SOURCE_BASE_CS                            26:26
+#define CSC_Y_SOURCE_BASE_CS_0                          0
+#define CSC_Y_SOURCE_BASE_CS_1                          1
+#define CSC_Y_SOURCE_BASE_ADDRESS                       25:0
+
+#define CSC_CONSTANTS                                   0x0000CC
+#define CSC_CONSTANTS_Y                                 31:24
+#define CSC_CONSTANTS_R                                 23:16
+#define CSC_CONSTANTS_G                                 15:8
+#define CSC_CONSTANTS_B                                 7:0
+
+#define CSC_Y_SOURCE_X                                  0x0000D0
+#define CSC_Y_SOURCE_X_INTEGER                          26:16
+#define CSC_Y_SOURCE_X_FRACTION                         15:3
+
+#define CSC_Y_SOURCE_Y                                  0x0000D4
+#define CSC_Y_SOURCE_Y_INTEGER                          27:16
+#define CSC_Y_SOURCE_Y_FRACTION                         15:3
+
+#define CSC_U_SOURCE_BASE                               0x0000D8
+#define CSC_U_SOURCE_BASE_EXT                           27:27
+#define CSC_U_SOURCE_BASE_EXT_LOCAL                     0
+#define CSC_U_SOURCE_BASE_EXT_EXTERNAL                  1
+#define CSC_U_SOURCE_BASE_CS                            26:26
+#define CSC_U_SOURCE_BASE_CS_0                          0
+#define CSC_U_SOURCE_BASE_CS_1                          1
+#define CSC_U_SOURCE_BASE_ADDRESS                       25:0
+
+#define CSC_V_SOURCE_BASE                               0x0000DC
+#define CSC_V_SOURCE_BASE_EXT                           27:27
+#define CSC_V_SOURCE_BASE_EXT_LOCAL                     0
+#define CSC_V_SOURCE_BASE_EXT_EXTERNAL                  1
+#define CSC_V_SOURCE_BASE_CS                            26:26
+#define CSC_V_SOURCE_BASE_CS_0                          0
+#define CSC_V_SOURCE_BASE_CS_1                          1
+#define CSC_V_SOURCE_BASE_ADDRESS                       25:0
+
+#define CSC_SOURCE_DIMENSION                            0x0000E0
+#define CSC_SOURCE_DIMENSION_X                          31:16
+#define CSC_SOURCE_DIMENSION_Y                          15:0
+
+#define CSC_SOURCE_PITCH                                0x0000E4
+#define CSC_SOURCE_PITCH_Y                              31:16
+#define CSC_SOURCE_PITCH_UV                             15:0
+
+#define CSC_DESTINATION                                 0x0000E8
+#define CSC_DESTINATION_WRAP                            31:31
+#define CSC_DESTINATION_WRAP_DISABLE                    0
+#define CSC_DESTINATION_WRAP_ENABLE                     1
+#define CSC_DESTINATION_X                               27:16
+#define CSC_DESTINATION_Y                               11:0
+
+#define CSC_DESTINATION_DIMENSION                       0x0000EC
+#define CSC_DESTINATION_DIMENSION_X                     31:16
+#define CSC_DESTINATION_DIMENSION_Y                     15:0
+
+#define CSC_DESTINATION_PITCH                           0x0000F0
+#define CSC_DESTINATION_PITCH_X                         31:16
+#define CSC_DESTINATION_PITCH_Y                         15:0
+
+#define CSC_SCALE_FACTOR                                0x0000F4
+#define CSC_SCALE_FACTOR_HORIZONTAL                     31:16
+#define CSC_SCALE_FACTOR_VERTICAL                       15:0
+
+#define CSC_DESTINATION_BASE                            0x0000F8
+#define CSC_DESTINATION_BASE_EXT                        27:27
+#define CSC_DESTINATION_BASE_EXT_LOCAL                  0
+#define CSC_DESTINATION_BASE_EXT_EXTERNAL               1
+#define CSC_DESTINATION_BASE_CS                         26:26
+#define CSC_DESTINATION_BASE_CS_0                       0
+#define CSC_DESTINATION_BASE_CS_1                       1
+#define CSC_DESTINATION_BASE_ADDRESS                    25:0
+
+#define CSC_CONTROL                                     0x0000FC
+#define CSC_CONTROL_STATUS                              31:31
+#define CSC_CONTROL_STATUS_STOP                         0
+#define CSC_CONTROL_STATUS_START                        1
+#define CSC_CONTROL_SOURCE_FORMAT                       30:28
+#define CSC_CONTROL_SOURCE_FORMAT_YUV422                0
+#define CSC_CONTROL_SOURCE_FORMAT_YUV420I               1
+#define CSC_CONTROL_SOURCE_FORMAT_YUV420                2
+#define CSC_CONTROL_SOURCE_FORMAT_YVU9                  3
+#define CSC_CONTROL_SOURCE_FORMAT_IYU1                  4
+#define CSC_CONTROL_SOURCE_FORMAT_IYU2                  5
+#define CSC_CONTROL_SOURCE_FORMAT_RGB565                6
+#define CSC_CONTROL_SOURCE_FORMAT_RGB8888               7
+#define CSC_CONTROL_DESTINATION_FORMAT                  27:26
+#define CSC_CONTROL_DESTINATION_FORMAT_RGB565           0
+#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888          1
+#define CSC_CONTROL_HORIZONTAL_FILTER                   25:25
+#define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE           0
+#define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE            1
+#define CSC_CONTROL_VERTICAL_FILTER                     24:24
+#define CSC_CONTROL_VERTICAL_FILTER_DISABLE             0
+#define CSC_CONTROL_VERTICAL_FILTER_ENABLE              1
+#define CSC_CONTROL_BYTE_ORDER                          23:23
+#define CSC_CONTROL_BYTE_ORDER_YUYV                     0
+#define CSC_CONTROL_BYTE_ORDER_UYVY                     1
+
+/*****************************************************************************\
+ *                             2D ENGINE DATA PORT                           *
+\*****************************************************************************/
+
+#define DE_BASE_ADDRESS	                                          0x100000
+#define DE_DATA_PORT                                                0x110000
+#define DE_DATA_PORT_SIZE                                           0x040000
+
+
+/*****************************************************************************\
+ *                            ZV CONTROL COMMAND                             *
+\*****************************************************************************/
+
+typedef struct regdata
+{
+	unsigned long address;
+	unsigned long data;
+}REGDATA, *PREGDATA;
+
+typedef struct cursordata
+{
+	unsigned long address;
+	unsigned char data[64][16];
+}CURSORDATA, *PCURSORDATA;
+
+#define SM501_CTL_ZV_START	_IOW('Z', 0x01, int)
+#define SM501_IOCTL_SMREAD	_IOWR('I', 0x01, REGDATA)
+#define SM501_IOCTL_SMWRITE	_IOW('I', 0x02, REGDATA)
+#define SM501_GET_CURSOR	_IOWR('I', 0x03, REGDATA)
+#define SM501_SET_CURSOR	_IOW('I', 0x04, REGDATA)
+
+#endif /* _SM50x_H_ */
+
diff -uNra linux-2.6.27.6/include/linux/sm501-regs.h.bak linux-2.6.27.6.yaffs/include/linux/sm501-regs.h.bak
--- linux-2.6.27.6/include/linux/sm501-regs.h.bak	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/sm501-regs.h.bak	2011-05-08 18:02:36.000000000 +0800
@@ -0,0 +1,4485 @@
+/* sm50x_reg.h
+ *
+ * Copyright 2007 SiliconMotion Inc.
+ *	
+ *	Boyod Yang<boyoddev@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Silicon Motion SM50x register definitions
+*/
+
+#ifndef _SM50x_H_
+#define _SM50x_H_
+
+/* System Configuration area */
+/* System config base */
+#define SM501_SYS_CONFIG		(0x000000)
+
+/* config 1 */
+#define SM501_SYSTEM_CONTROL		(0x000000)
+
+#define SM501_SYSCTRL_PANEL_TRISTATE		(1<<0)
+#define SM501_SYSCTRL_MEM_TRISTATE			(1<<1)
+#define SM501_SYSCTRL_CRT_TRISTATE			(1<<2)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK	(3<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_1		(0<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_2		(1<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_4		(2<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_8		(3<<4)
+
+#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN		(1<<6)
+#define SM501_SYSCTRL_PCI_RETRY_DISABLE		(1<<7)
+#define SM501_SYSCTRL_PCI_SUBSYS_LOCK		(1<<11)
+#define SM501_SYSCTRL_PCI_BURST_READ_EN		(1<<15)
+
+#define SM501_MISC_CONTROL		(0x000004)
+
+#define SM501_MISC_BUS_SH		(0x0)
+#define SM501_MISC_BUS_PCI		(0x1)
+#define SM501_MISC_BUS_XSCALE		(0x2)
+#define SM501_MISC_BUS_NEC		(0x6)
+#define SM501_MISC_BUS_MASK		(0x7)
+
+#define SM501_MISC_VR_62MB		(1<<3)
+#define SM501_MISC_CDR_RESET	(1<<7)
+#define SM501_MISC_USB_LB		(1<<8)
+#define SM501_MISC_USB_SLAVE	(1<<9)
+#define SM501_MISC_BL_1			(1<<10)
+#define SM501_MISC_MC			(1<<11)
+#define SM501_MISC_DAC_POWER	(1<<12)
+#define SM501_MISC_IRQ_INVERT	(1<<16)
+#define SM501_MISC_SH			(1<<17)
+
+#define SM501_MISC_HOLD_EMPTY	(0<<18)
+#define SM501_MISC_HOLD_8		(1<<18)
+#define SM501_MISC_HOLD_16		(2<<18)
+#define SM501_MISC_HOLD_24		(3<<18)
+#define SM501_MISC_HOLD_32		(4<<18)
+#define SM501_MISC_HOLD_MASK	(7<<18)
+
+#define SM501_MISC_FREQ_12		(1<<24)
+#define SM501_MISC_PNL_24BIT	(1<<25)
+#define SM501_MISC_8051_LE		(1<<26)
+
+
+#define SM501_GPIO31_0_CONTROL		(0x000008)
+#define SM501_GPIO63_32_CONTROL		(0x00000C)
+#define SM501_DRAM_CONTROL			(0x000010)
+
+/* command list */
+#define SM501_ARBTRTN_CONTROL		(0x000014)
+
+/* command list */
+#define SM501_COMMAND_LIST_STATUS	(0x000024)
+
+/* interrupt debug */
+#define SM501_RAW_IRQ_STATUS		(0x000028)
+#define SM501_RAW_IRQ_CLEAR			(0x000028)
+#define SM501_IRQ_STATUS			(0x00002C)
+#define SM501_IRQ_MASK				(0x000030)
+#define SM501_DEBUG_CONTROL			(0x000034)
+
+/* power management */
+#define SM501_POWERMODE_P2X_SRC		(1<<29)
+#define SM501_POWERMODE_V2X_SRC		(1<<20)
+#define SM501_POWERMODE_M_SRC		(1<<12)
+#define SM501_POWERMODE_M1_SRC		(1<<4)
+
+#define SM501_CURRENT_GATE			(0x000038)
+#define SM501_CURRENT_CLOCK			(0x00003C)
+#define SM501_POWER_MODE_0_GATE		(0x000040)
+#define SM501_POWER_MODE_0_CLOCK	(0x000044)
+#define SM501_POWER_MODE_1_GATE		(0x000048)
+#define SM501_POWER_MODE_1_CLOCK	(0x00004C)
+#define SM501_SLEEP_MODE_GATE		(0x000050)
+#define SM501_POWER_MODE_CONTROL	(0x000054)
+
+/* power gates for units within the 501 */
+#define SM501_GATE_HOST			(0)
+#define SM501_GATE_MEMORY		(1)
+#define SM501_GATE_DISPLAY		(2)
+#define SM501_GATE_2D_ENGINE	(3)
+#define SM501_GATE_CSC			(4)
+#define SM501_GATE_ZVPORT		(5)
+#define SM501_GATE_GPIO			(6)
+#define SM501_GATE_UART0		(7)
+#define SM501_GATE_UART1		(8)
+#define SM501_GATE_SSP		(10)
+#define SM501_GATE_USB_HOST		(11)
+#define SM501_GATE_USB_GADGET		(12)
+#define SM501_GATE_UCONTROLLER		(17)
+#define SM501_GATE_AC97				(18)
+
+/* panel clock */
+#define SM501_CLOCK_P2XCLK		(24)
+/* crt clock */
+#define SM501_CLOCK_V2XCLK		(16)
+/* main clock */
+#define SM501_CLOCK_MCLK		(8)
+/* SDRAM controller clock */
+#define SM501_CLOCK_M1XCLK		(0)
+
+/* config 2 */
+#define SM501_PCI_MASTER_BASE		(0x000058)
+#define SM501_ENDIAN_CONTROL		(0x00005C)
+#define SM501_DEVICEID				(0x000060)
+/* 0x050100A0 */
+
+#define SM501_DEVICEID_SM501		(0x05010000)
+#define SM501_DEVICEID_IDMASK		(0xffff0000)
+#define SM501_DEVICEID_REVMASK		(0x000000ff)
+
+#define SM501_PLLCLOCK_COUNT		(0x000064)
+#define SM501_MISC_TIMING			(0x000068)
+#define SM501_CURRENT_SDRAM_CLOCK	(0x00006C)
+
+#define SM501_PROGRAMMABLE_PLL_CONTROL	(0x000074)
+
+/* GPIO base */
+#define SM501_GPIO				(0x010000)
+#define SM501_GPIO_DATA_LOW		(0x00)
+#define SM501_GPIO_DATA_HIGH	(0x04)
+#define SM501_GPIO_DDR_LOW		(0x08)
+#define SM501_GPIO_DDR_HIGH		(0x0C)
+#define SM501_GPIO_IRQ_SETUP	(0x10)
+#define SM501_GPIO_IRQ_STATUS	(0x14)
+#define SM501_GPIO_IRQ_RESET	(0x14)
+
+/* I2C controller base */
+#define SM501_I2C				(0x010040)
+#define SM501_I2C_BYTE_COUNT	(0x00)
+#define SM501_I2C_CONTROL		(0x01)
+#define SM501_I2C_STATUS		(0x02)
+#define SM501_I2C_RESET			(0x02)
+#define SM501_I2C_SLAVE_ADDRESS	(0x03)
+#define SM501_I2C_DATA			(0x04)
+
+/* SSP base */
+#define SM501_SSP	(0x020000)
+
+/* Uart 0 base */
+#define SM501_UART0			(0x030000)
+
+/* Uart 1 base */
+#define SM501_UART1			(0x030020)
+
+/* USB host port base */
+#define SM501_USB_HOST		(0x040000)
+
+/* USB slave/gadget base */
+#define SM501_USB_GADGET		(0x060000)
+
+/* USB slave/gadget data port base */
+#define SM501_USB_GADGET_DATA	(0x070000)
+
+/* Display controller/video engine base */
+#define SM501_DC				(0x080000)
+
+/* common defines for the SM501 address registers */
+#define SM501_ADDR_FLIP			(1<<31)
+#define SM501_ADDR_EXT			(1<<27)
+#define SM501_ADDR_CS1			(1<<26)
+#define SM501_ADDR_MASK			(0x3f << 26)
+
+#define SM501_FIFO_MASK			(0x3 << 16)
+#define SM501_FIFO_1			(0x0 << 16)
+#define SM501_FIFO_3			(0x1 << 16)
+#define SM501_FIFO_7			(0x2 << 16)
+#define SM501_FIFO_11			(0x3 << 16)
+
+/* common registers for panel and the crt */
+#define SM501_OFF_DC_H_TOT		(0x000)
+#define SM501_OFF_DC_V_TOT		(0x008)
+#define SM501_OFF_DC_H_SYNC		(0x004)
+#define SM501_OFF_DC_V_SYNC		(0x00C)
+
+#define SM501_DC_PANEL_CONTROL		(0x000)
+
+#define SM501_DC_PANEL_CONTROL_FPEN	(1<<27)
+#define SM501_DC_PANEL_CONTROL_BIAS	(1<<26)
+#define SM501_DC_PANEL_CONTROL_DATA	(1<<25)
+#define SM501_DC_PANEL_CONTROL_VDD	(1<<24)
+#define SM501_DC_PANEL_CONTROL_DP	(1<<23)
+
+#define SM501_DC_PANEL_CONTROL_TFT_888	(0<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_333	(1<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_444	(2<<21)
+
+#define SM501_DC_PANEL_CONTROL_DE		(1<<20)
+
+#define SM501_DC_PANEL_CONTROL_LCD_TFT	(0<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN8	(1<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN12	(2<<18)
+
+#define SM501_DC_PANEL_CONTROL_CP		(1<<14)
+#define SM501_DC_PANEL_CONTROL_VSP		(1<<13)
+#define SM501_DC_PANEL_CONTROL_HSP		(1<<12)
+#define SM501_DC_PANEL_CONTROL_CK		(1<<9)
+#define SM501_DC_PANEL_CONTROL_TE		(1<<8)
+#define SM501_DC_PANEL_CONTROL_VPD		(1<<7)
+#define SM501_DC_PANEL_CONTROL_VP		(1<<6)
+#define SM501_DC_PANEL_CONTROL_HPD		(1<<5)
+#define SM501_DC_PANEL_CONTROL_HP		(1<<4)
+#define SM501_DC_PANEL_CONTROL_GAMMA	(1<<3)
+#define SM501_DC_PANEL_CONTROL_EN		(1<<2)
+
+#define SM501_DC_PANEL_CONTROL_8BPP		(0<<0)
+#define SM501_DC_PANEL_CONTROL_16BPP	(1<<0)
+#define SM501_DC_PANEL_CONTROL_32BPP	(2<<0)
+
+
+#define SM501_DC_PANEL_PANNING_CONTROL	(0x004)
+#define SM501_DC_PANEL_COLOR_KEY	(0x008)
+#define SM501_DC_PANEL_FB_ADDR		(0x00C)
+#define SM501_DC_PANEL_FB_OFFSET	(0x010)
+#define SM501_DC_PANEL_FB_WIDTH		(0x014)
+#define SM501_DC_PANEL_FB_HEIGHT	(0x018)
+#define SM501_DC_PANEL_TL_LOC		(0x01C)
+#define SM501_DC_PANEL_BR_LOC		(0x020)
+#define SM501_DC_PANEL_H_TOT		(0x024)
+#define SM501_DC_PANEL_H_SYNC		(0x028)
+#define SM501_DC_PANEL_V_TOT		(0x02C)
+#define SM501_DC_PANEL_V_SYNC		(0x030)
+#define SM501_DC_PANEL_CUR_LINE		(0x034)
+
+#define SM501_DC_VIDEO_CONTROL		(0x040)
+#define SM501_DC_VIDEO_FB0_ADDR		(0x044)
+#define SM501_DC_VIDEO_FB_WIDTH		(0x048)
+#define SM501_DC_VIDEO_FB0_LAST_ADDR	(0x04C)
+#define SM501_DC_VIDEO_TL_LOC		(0x050)
+#define SM501_DC_VIDEO_BR_LOC		(0x054)
+#define SM501_DC_VIDEO_SCALE		(0x058)
+#define SM501_DC_VIDEO_INIT_SCALE	(0x05C)
+#define SM501_DC_VIDEO_YUV_CONSTANTS	(0x060)
+#define SM501_DC_VIDEO_FB1_ADDR			(0x064)
+#define SM501_DC_VIDEO_FB1_LAST_ADDR	(0x068)
+
+#define SM501_DC_VIDEO_ALPHA_CONTROL	(0x080)
+#define SM501_DC_VIDEO_ALPHA_FB_ADDR	(0x084)
+#define SM501_DC_VIDEO_ALPHA_FB_OFFSET	(0x088)
+#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR	(0x08C)
+#define SM501_DC_VIDEO_ALPHA_TL_LOC	(0x090)
+#define SM501_DC_VIDEO_ALPHA_BR_LOC	(0x094)
+#define SM501_DC_VIDEO_ALPHA_SCALE	(0x098)
+#define SM501_DC_VIDEO_ALPHA_INIT_SCALE	(0x09C)
+#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY	(0x0A0)
+#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP	(0x0A4)
+
+#define SM501_DC_PANEL_HWC_BASE		(0x0F0)
+#define SM501_DC_PANEL_HWC_ADDR		(0x0F0)
+#define SM501_DC_PANEL_HWC_LOC		(0x0F4)
+#define SM501_DC_PANEL_HWC_COLOR_1_2	(0x0F8)
+#define SM501_DC_PANEL_HWC_COLOR_3		(0x0FC)
+
+#define SM501_HWC_EN			(1<<31)
+
+#define SM501_OFF_HWC_ADDR		(0x00)
+#define SM501_OFF_HWC_LOC		(0x04)
+#define SM501_OFF_HWC_COLOR_1_2	(0x08)
+#define SM501_OFF_HWC_COLOR_3	(0x0C)
+
+#define SM501_DC_ALPHA_CONTROL	(0x100)
+#define SM501_DC_ALPHA_FB_ADDR	(0x104)
+#define SM501_DC_ALPHA_FB_OFFSET	(0x108)
+#define SM501_DC_ALPHA_TL_LOC		(0x10C)
+#define SM501_DC_ALPHA_BR_LOC		(0x110)
+#define SM501_DC_ALPHA_CHROMA_KEY	(0x114)
+#define SM501_DC_ALPHA_COLOR_LOOKUP	(0x118)
+
+#define SM501_DC_CRT_CONTROL		(0x200)
+
+#define SM501_DC_CRT_CONTROL_TVP	(1<<15)
+#define SM501_DC_CRT_CONTROL_CP		(1<<14)
+#define SM501_DC_CRT_CONTROL_VSP	(1<<13)
+#define SM501_DC_CRT_CONTROL_HSP	(1<<12)
+#define SM501_DC_CRT_CONTROL_VS		(1<<11)
+#define SM501_DC_CRT_CONTROL_BLANK	(1<<10)
+#define SM501_DC_CRT_CONTROL_SEL	(1<<9)
+#define SM501_DC_CRT_CONTROL_TE		(1<<8)
+#define SM501_DC_CRT_CONTROL_PIXEL_MASK	(0xF << 4)
+#define SM501_DC_CRT_CONTROL_GAMMA	(1<<3)
+#define SM501_DC_CRT_CONTROL_ENABLE	(1<<2)
+
+#define SM501_DC_CRT_CONTROL_8BPP	(0<<0)
+#define SM501_DC_CRT_CONTROL_16BPP	(1<<0)
+#define SM501_DC_CRT_CONTROL_32BPP	(2<<0)
+
+#define SM501_DC_CRT_FB_ADDR		(0x204)
+#define SM501_DC_CRT_FB_OFFSET		(0x208)
+#define SM501_DC_CRT_H_TOT		(0x20C)
+#define SM501_DC_CRT_H_SYNC		(0x210)
+#define SM501_DC_CRT_V_TOT		(0x214)
+#define SM501_DC_CRT_V_SYNC		(0x218)
+#define SM501_DC_CRT_SIGNATURE_ANALYZER	(0x21C)
+#define SM501_DC_CRT_CUR_LINE		(0x220)
+#define SM501_DC_CRT_MONITOR_DETECT	(0x224)
+
+#define SM501_DC_CRT_HWC_BASE		(0x230)
+#define SM501_DC_CRT_HWC_ADDR		(0x230)
+#define SM501_DC_CRT_HWC_LOC		(0x234)
+#define SM501_DC_CRT_HWC_COLOR_1_2	(0x238)
+#define SM501_DC_CRT_HWC_COLOR_3	(0x23C)
+
+#define SM501_DC_PANEL_PALETTE		(0x400)
+
+#define SM501_DC_VIDEO_PALETTE		(0x800)
+
+#define SM501_DC_CRT_PALETTE		(0xC00)
+
+/* Zoom Video port base */
+#define SM501_ZVPORT		(0x090000)
+
+/* AC97/I2S base */
+#define SM501_AC97			(0x0A0000)
+
+/* 8051 micro controller base */
+#define SM501_UCONTROLLER	(0x0B0000)
+
+/* 8051 micro controller SRAM base */
+#define SM501_UCONTROLLER_SRAM		(0x0C0000)
+
+/* DMA base */
+#define SM501_DMA				(0x0D0000)
+
+/* 2d engine base */
+#define SM501_2D_ENGINE			(0x100000)
+#define SM501_2D_SOURCE			(0x00)
+#define SM501_2D_DESTINATION	(0x04)
+#define SM501_2D_DIMENSION		(0x08)
+#define SM501_2D_CONTROL		(0x0C)
+#define SM501_2D_PITCH			(0x10)
+#define SM501_2D_FOREGROUND		(0x14)
+#define SM501_2D_BACKGROUND		(0x18)
+#define SM501_2D_STRETCH		(0x1C)
+#define SM501_2D_COLOR_COMPARE	(0x20)
+#define SM501_2D_COLOR_COMPARE_MASK		(0x24)
+#define SM501_2D_MASK			(0x28)
+#define SM501_2D_CLIP_TL		(0x2C)
+#define SM501_2D_CLIP_BR		(0x30)
+#define SM501_2D_MONO_PATTERN_LOW	(0x34)
+#define SM501_2D_MONO_PATTERN_HIGH	(0x38)
+#define SM501_2D_WINDOW_WIDTH		(0x3C)
+#define SM501_2D_SOURCE_BASE		(0x40)
+#define SM501_2D_DESTINATION_BASE	(0x44)
+#define SM501_2D_ALPHA				(0x48)
+#define SM501_2D_WRAP				(0x4C)
+#define SM501_2D_STATUS				(0x50)
+
+#define SM501_CSC_Y_SOURCE_BASE		(0xC8)
+#define SM501_CSC_CONSTANTS			(0xCC)
+#define SM501_CSC_Y_SOURCE_X		(0xD0)
+#define SM501_CSC_Y_SOURCE_Y		(0xD4)
+#define SM501_CSC_U_SOURCE_BASE		(0xD8)
+#define SM501_CSC_V_SOURCE_BASE		(0xDC)
+#define SM501_CSC_SOURCE_DIMENSION	(0xE0)
+#define SM501_CSC_SOURCE_PITCH		(0xE4)
+#define SM501_CSC_DESTINATION		(0xE8)
+#define SM501_CSC_DESTINATION_DIMENSION	(0xEC)
+#define SM501_CSC_DESTINATION_PITCH	(0xF0)
+#define SM501_CSC_SCALE_FACTOR		(0xF4)
+#define SM501_CSC_DESTINATION_BASE	(0xF8)
+#define SM501_CSC_CONTROL			(0xFC)
+
+/* 2d engine data port base */
+#define SM501_2D_ENGINE_DATA		(0x110000)
+
+
+
+
+
+
+
+
+/* common registers for panel and the crt */
+#define SM501_OFF_DC_H_TOT		(0x000)
+#define SM501_OFF_DC_V_TOT		(0x008)
+#define SM501_OFF_DC_H_SYNC		(0x004)
+#define SM501_OFF_DC_V_SYNC		(0x00C)
+
+
+#define SM501_HWC_EN			(1<<31)
+
+#define SM501_OFF_HWC_ADDR		(0x00)
+#define SM501_OFF_HWC_LOC		(0x04)
+#define SM501_OFF_HWC_COLOR_1_2		(0x08)
+#define SM501_OFF_HWC_COLOR_3		(0x0C)
+
+
+#define SM501_VIDEOMEMORYSIZE    0x00800000  /*Assume sm50x graphics chip has 8MB VRAM */
+#define SM502_REV_ID             0xC0
+
+
+/******************************************************************************
+* REGISTER ACCESS                                                            *
+******************************************************************************/
+#define LOWORD(x) ((unsigned short) (x))
+#define HIWORD(x) ((unsigned short) ((x) >> 16))
+#define LOBYTE(x) ((unsigned char) (x))
+#define HIBYTE(x) ((unsigned char) ((x) >> 8))
+
+#define MAKEWORD(l,h)  (((unsigned short) (unsigned char) (l)) | \
+		(((unsigned short) (unsigned char) (h)) << 8))
+#define MAKEDWORD(l,h) (((unsigned int) (unsigned short) (l)) | \
+		(((unsigned int) (unsigned short) (h)) << 16))
+
+#define SRAM(x)      (U8051_SRAM + offsetof(FIRMWARE_SRAM, x))
+#define SRAM_SIZE(x) (sizeof(((FIRMWARE_SRAM*) 0)->x))
+
+/*****************************************************************************\
+ *                                FIELD MACROS                               *
+\*****************************************************************************/
+
+#define _LSB(f)             (0 ? f)
+#define _MSB(f)             (1 ? f)
+#define _COUNT(f)           (_MSB(f) - _LSB(f) + 1)
+
+#define RAW_MASK(f)         (0xFFFFFFFF >> (32 - _COUNT(f)))
+#define GET_MASK(f)         (RAW_MASK(f) << _LSB(f))
+#define GET_FIELD(d,f)      (((d) >> _LSB(f)) & RAW_MASK(f))
+#define TEST_FIELD(d,f,v)   (GET_FIELD(d,f) == f ## _ ## v)
+#define SET_FIELD(d,f,v)    (((d) & ~GET_MASK(f)) | \
+                            (((f ## _ ## v) & RAW_MASK(f)) << _LSB(f)))
+#define SET_FIELDV(d,f,v)   (((d) & ~GET_MASK(f)) | \
+                            (((v) & RAW_MASK(f)) << _LSB(f)))
+
+
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+// Internal macros                                                            //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#define _F_START(f)             (0 ? f)
+#define _F_END(f)               (1 ? f)
+#define _F_SIZE(f)              (1 + _F_END(f) - _F_START(f))
+#define _F_MASK(f)              (((1 << _F_SIZE(f)) - 1) << _F_START(f))
+#define _F_NORMALIZE(v, f)      (((v) & _F_MASK(f)) >> _F_START(f))
+#define _F_DENORMALIZE(v, f)    (((v) << _F_START(f)) & _F_MASK(f))
+
+
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+// Global macros                                                              //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#define FIELD_GET(x, reg, field) \
+( \
+    _F_NORMALIZE((x), reg ## _ ## field) \
+)
+
+#define FIELD_SET(x, reg, field, value) \
+( \
+    (x & ~_F_MASK(reg ## _ ## field)) \
+    | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \
+)
+
+#define FIELD_VALUE(x, reg, field, value) \
+( \
+    (x & ~_F_MASK(reg ## _ ## field)) \
+    | _F_DENORMALIZE(value, reg ## _ ## field) \
+)
+
+#define FIELD_CLEAR(reg, field) \
+( \
+    ~ _F_MASK(reg ## _ ## field) \
+)
+
+
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+// Field Macros                                                               //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#define FIELD_START(field)              (0 ? field)
+#define FIELD_END(field)                (1 ? field)
+#define FIELD_SIZE(field)               (1 + FIELD_END(field) - FIELD_START(field))
+#define FIELD_MASK(field)               (((1 << (FIELD_SIZE(field)-1)) | ((1 << (FIELD_SIZE(field)-1)) - 1)) << FIELD_START(field))
+#define FIELD_NORMALIZE(reg, field)     (((reg) & FIELD_MASK(field)) >> FIELD_START(field))
+#define FIELD_DENORMALIZE(field, value) (((value) << FIELD_START(field)) & FIELD_MASK(field))
+
+#define FIELD_INIT(reg, field, value)   FIELD_DENORMALIZE(reg ## _ ## field, \
+                                                          reg ## _ ## field ## _ ## value)
+#define FIELD_INIT_VAL(reg, field, value) \
+                                        (FIELD_DENORMALIZE(reg ## _ ## field, value))
+#define FIELD_VAL_SET(x, r, f, v)       x = x & ~FIELD_MASK(r ## _ ## f) \
+                                              | FIELD_DENORMALIZE(r ## _ ## f, r ## _ ## f ## _ ## v)
+
+
+
+                                              
+/*****************************************************************************\
+ *                            SYSTEM CONFIGURATION                           *
+\*****************************************************************************/
+
+/* System Control */
+#define SYSTEM_CTRL                                     0x000000
+#define SYSTEM_CTRL_DPMS                                31:30
+#define SYSTEM_CTRL_DPMS_VPHP                           0
+#define SYSTEM_CTRL_DPMS_VPHN                           1
+#define SYSTEM_CTRL_DPMS_VNHP                           2
+#define SYSTEM_CTRL_DPMS_VNHN                           3
+#define SYSTEM_CTRL_PCI_BURST                           29:29
+#define SYSTEM_CTRL_PCI_BURST_DISABLE                   0
+#define SYSTEM_CTRL_PCI_BURST_ENABLE                    1
+#define SYSTEM_CTRL_CSC_STATUS                          28:28
+#define SYSTEM_CTRL_CSC_STATUS_IDLE                     0
+#define SYSTEM_CTRL_CSC_STATUS_BUSY                     1
+#define SYSTEM_CTRL_PCI_MASTER                          25:25
+#define SYSTEM_CTRL_PCI_MASTER_STOP                     0
+#define SYSTEM_CTRL_PCI_MASTER_START                    1
+#define SYSTEM_CTRL_LATENCY_TIMER                       24:24
+#define SYSTEM_CTRL_LATENCY_TIMER_ENABLE                0
+#define SYSTEM_CTRL_LATENCY_TIMER_DISABLE               1
+#define SYSTEM_CTRL_PANEL_STATUS                        23:23
+#define SYSTEM_CTRL_PANEL_STATUS_CURRENT                0
+#define SYSTEM_CTRL_PANEL_STATUS_PENDING                1
+#define SYSTEM_CTRL_VIDEO_STATUS                        22:22
+#define SYSTEM_CTRL_VIDEO_STATUS_CURRENT                0
+#define SYSTEM_CTRL_VIDEO_STATUS_PENDING                1
+#define SYSTEM_CTRL_DE_FIFO                             20:20
+#define SYSTEM_CTRL_DE_FIFO_NOT_EMPTY                   0
+#define SYSTEM_CTRL_DE_FIFO_EMPTY                       1
+#define SYSTEM_CTRL_DE_STATUS                           19:19
+#define SYSTEM_CTRL_DE_STATUS_IDLE                      0
+#define SYSTEM_CTRL_DE_STATUS_BUSY                      1
+#define SYSTEM_CTRL_CRT_STATUS                          17:17
+#define SYSTEM_CTRL_CRT_STATUS_CURRENT                  0
+#define SYSTEM_CTRL_CRT_STATUS_PENDING                  1
+#define SYSTEM_CTRL_ZVPORT                              16:16
+#define SYSTEM_CTRL_ZVPORT_0                            0
+#define SYSTEM_CTRL_ZVPORT_1                            1
+#define SYSTEM_CTRL_PCI_BURST_READ                      15:15
+#define SYSTEM_CTRL_PCI_BURST_READ_DISABLE              0
+#define SYSTEM_CTRL_PCI_BURST_READ_ENABLE               1
+#define SYSTEM_CTRL_DE_ABORT                            13:12
+#define SYSTEM_CTRL_DE_ABORT_NORMAL                     0
+#define SYSTEM_CTRL_DE_ABORT_2D_ABORT                   3
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK                     11:11
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_DISABLE             0
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_ENABLE              1
+#define SYSTEM_CTRL_PCI_RETRY                           7:7
+#define SYSTEM_CTRL_PCI_RETRY_ENABLE                    0
+#define SYSTEM_CTRL_PCI_RETRY_DISABLE                   1
+#define SYSTEM_CTRL_PCI_CLOCK_RUN                       6:6
+#define SYSTEM_CTRL_PCI_CLOCK_RUN_DISABLE               0
+#define SYSTEM_CTRL_PCI_CLOCK_RUN_ENABLE                1
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE           5:4
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1         0
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2         1
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4         2
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8         3
+#define SYSTEM_CTRL_CRT_TRISTATE                        2:2
+#define SYSTEM_CTRL_CRT_TRISTATE_DISABLE                0
+#define SYSTEM_CTRL_CRT_TRISTATE_ENABLE                 1
+#define SYSTEM_CTRL_INTMEM_TRISTATE                     1:1
+#define SYSTEM_CTRL_INTMEM_TRISTATE_DISABLE             0
+#define SYSTEM_CTRL_INTMEM_TRISTATE_ENABLE              1
+#define SYSTEM_CTRL_PANEL_TRISTATE                      0:0
+#define SYSTEM_CTRL_PANEL_TRISTATE_DISABLE              0
+#define SYSTEM_CTRL_PANEL_TRISTATE_ENABLE               1
+
+
+/* Miscellaneous Control */
+#define MISC_CTRL                                       0x000004
+#define MISC_CTRL_PCI_PAD                               31:30
+#define MISC_CTRL_PCI_PAD_24MA                          0
+#define MISC_CTRL_PCI_PAD_12MA                          1
+#define MISC_CTRL_PCI_PAD_8MA                           2
+#define MISC_CTRL_48_SELECT                             29:28
+#define MISC_CTRL_48_SELECT_CRYSTAL                     0
+#define MISC_CTRL_48_SELECT_CPU_96                      2
+#define MISC_CTRL_48_SELECT_CPU_48                      3
+#define MISC_CTRL_UART1_SELECT                          27:27
+#define MISC_CTRL_UART1_SELECT_UART                     0
+#define MISC_CTRL_UART1_SELECT_SSP                      1
+#define MISC_CTRL_8051_LATCH                            26:26
+#define MISC_CTRL_8051_LATCH_DISABLE                    0
+#define MISC_CTRL_8051_LATCH_ENABLE                     1
+#define MISC_CTRL_FPDATA                                25:25
+#define MISC_CTRL_FPDATA_18                             0
+#define MISC_CTRL_FPDATA_24                             1
+#define MISC_CTRL_CRYSTAL                               24:24
+#define MISC_CTRL_CRYSTAL_24                            0
+#define MISC_CTRL_CRYSTAL_12                            1
+#define MISC_CTRL_DRAM_REFRESH                          22:21
+#define MISC_CTRL_DRAM_REFRESH_8                        0
+#define MISC_CTRL_DRAM_REFRESH_16                       1
+#define MISC_CTRL_DRAM_REFRESH_32                       2
+#define MISC_CTRL_DRAM_REFRESH_64                       3
+#define MISC_CTRL_BUS_HOLD                              20:18
+#define MISC_CTRL_BUS_HOLD_FIFO_EMPTY                   0
+#define MISC_CTRL_BUS_HOLD_8                            1
+#define MISC_CTRL_BUS_HOLD_16                           2
+#define MISC_CTRL_BUS_HOLD_24                           3
+#define MISC_CTRL_BUS_HOLD_32                           4
+#define MISC_CTRL_HITACHI_READY                         17:17
+#define MISC_CTRL_HITACHI_READY_NEGATIVE                0
+#define MISC_CTRL_HITACHI_READY_POSITIVE                1
+#define MISC_CTRL_INTERRUPT                             16:16
+#define MISC_CTRL_INTERRUPT_NORMAL                      0
+#define MISC_CTRL_INTERRUPT_INVERT                      1
+#define MISC_CTRL_PLL_CLOCK_COUNT                       15:15
+#define MISC_CTRL_PLL_CLOCK_COUNT_DISABLE               0
+#define MISC_CTRL_PLL_CLOCK_COUNT_ENABLE                1
+#define MISC_CTRL_DAC_BAND_GAP                          14:13
+#define MISC_CTRL_DAC_POWER                             12:12
+#define MISC_CTRL_DAC_POWER_ENABLE                      0
+#define MISC_CTRL_DAC_POWER_DISABLE                     1
+#define MISC_CTRL_USB_SLAVE_CONTROLLER                  11:11
+#define MISC_CTRL_USB_SLAVE_CONTROLLER_CPU              0
+#define MISC_CTRL_USB_SLAVE_CONTROLLER_8051             1
+#define MISC_CTRL_BURST_LENGTH                          10:10
+#define MISC_CTRL_BURST_LENGTH_8                        0
+#define MISC_CTRL_BURST_LENGTH_1                        1
+#define MISC_CTRL_USB_SELECT                            9:9
+#define MISC_CTRL_USB_SELECT_MASTER                     0
+#define MISC_CTRL_USB_SELECT_SLAVE                      1
+#define MISC_CTRL_LOOPBACK                              8:8
+#define MISC_CTRL_LOOPBACK_NORMAL                       0
+#define MISC_CTRL_LOOPBACK_USB_HOST                     1
+#define MISC_CTRL_CLOCK_DIVIDER_RESET                   7:7
+#define MISC_CTRL_CLOCK_DIVIDER_RESET_ENABLE            0
+#define MISC_CTRL_CLOCK_DIVIDER_RESET_DISABLE           1
+#define MISC_CTRL_TEST_MODE                             6:5
+#define MISC_CTRL_TEST_MODE_NORMAL                      0
+#define MISC_CTRL_TEST_MODE_DEBUGGING                   1
+#define MISC_CTRL_TEST_MODE_NAND                        2
+#define MISC_CTRL_TEST_MODE_MEMORY                      3
+#define MISC_CTRL_NEC_MMIO                              4:4
+#define MISC_CTRL_NEC_MMIO_30                           0
+#define MISC_CTRL_NEC_MMIO_62                           1
+#define MISC_CTRL_CLOCK                                 3:3
+#define MISC_CTRL_CLOCK_PLL                             0
+#define MISC_CTRL_CLOCK_TEST                            1
+#define MISC_CTRL_HOST_BUS                              2:0
+#define MISC_CTRL_HOST_BUS_HITACHI                      0
+#define MISC_CTRL_HOST_BUS_PCI                          1
+#define MISC_CTRL_HOST_BUS_XSCALE                       2
+#define MISC_CTRL_HOST_BUS_STRONGARM                    4
+#define MISC_CTRL_HOST_BUS_NEC                          6
+
+
+/* GPIO[31:0] Control */
+#define GPIO_CONTROL_LOW                                            0x000008
+#define GPIO_CONTROL_LOW_31                                         31:31
+#define GPIO_CONTROL_LOW_31_GPIO                                    0
+#define GPIO_CONTROL_LOW_31_PWM2                                    1
+#define GPIO_CONTROL_LOW_30                                         30:30
+#define GPIO_CONTROL_LOW_30_GPIO                                    0
+#define GPIO_CONTROL_LOW_30_PWM1                                    1
+#define GPIO_CONTROL_LOW_29                                         29:29
+#define GPIO_CONTROL_LOW_29_GPIO                                    0
+#define GPIO_CONTROL_LOW_29_PWM0                                    1
+#define GPIO_CONTROL_LOW_28                                         28:28
+#define GPIO_CONTROL_LOW_28_GPIO                                    0
+#define GPIO_CONTROL_LOW_28_AC97_RX_I2S                             1
+#define GPIO_CONTROL_LOW_27                                         27:27
+#define GPIO_CONTROL_LOW_27_GPIO                                    0
+#define GPIO_CONTROL_LOW_27_AC97_TX_I2S                             1
+#define GPIO_CONTROL_LOW_26                                         26:26
+#define GPIO_CONTROL_LOW_26_GPIO                                    0
+#define GPIO_CONTROL_LOW_26_AC97_CLOCK_I2S                          1
+#define GPIO_CONTROL_LOW_25                                         25:25
+#define GPIO_CONTROL_LOW_25_GPIO                                    0
+#define GPIO_CONTROL_LOW_25_AC97_SYNC_I2S                           1
+#define GPIO_CONTROL_LOW_24                                         24:24
+#define GPIO_CONTROL_LOW_24_GPIO                                    0
+#define GPIO_CONTROL_LOW_24_AC97_RESET                              1
+#define GPIO_CONTROL_LOW_23                                         23:23
+#define GPIO_CONTROL_LOW_23_GPIO                                    0
+#define GPIO_CONTROL_LOW_23_ZVPORT7                                 1
+#define GPIO_CONTROL_LOW_22                                         22:22
+#define GPIO_CONTROL_LOW_22_GPIO                                    0
+#define GPIO_CONTROL_LOW_22_ZVPORT6                                 1
+#define GPIO_CONTROL_LOW_21                                         21:21
+#define GPIO_CONTROL_LOW_21_GPIO                                    0
+#define GPIO_CONTROL_LOW_21_ZVPORT5                                 1
+#define GPIO_CONTROL_LOW_20                                         20:20
+#define GPIO_CONTROL_LOW_20_GPIO                                    0
+#define GPIO_CONTROL_LOW_20_ZVPORT4                                 1
+#define GPIO_CONTROL_LOW_19                                         19:19
+#define GPIO_CONTROL_LOW_19_GPIO                                    0
+#define GPIO_CONTROL_LOW_19_ZVPORT3                                 1
+#define GPIO_CONTROL_LOW_18                                         18:18
+#define GPIO_CONTROL_LOW_18_GPIO                                    0
+#define GPIO_CONTROL_LOW_18_ZVPORT2                                 1
+#define GPIO_CONTROL_LOW_17                                         17:17
+#define GPIO_CONTROL_LOW_17_GPIO                                    0
+#define GPIO_CONTROL_LOW_17_ZVPORT1                                 1
+#define GPIO_CONTROL_LOW_16                                         16:16
+#define GPIO_CONTROL_LOW_16_GPIO                                    0
+#define GPIO_CONTROL_LOW_16_ZVPORT0                                 1
+#define GPIO_CONTROL_LOW_15                                         15:15
+#define GPIO_CONTROL_LOW_15_GPIO                                    0
+#define GPIO_CONTROL_LOW_15_8051_A11                                1
+#define GPIO_CONTROL_LOW_14                                         14:14
+#define GPIO_CONTROL_LOW_14_GPIO                                    0
+#define GPIO_CONTROL_LOW_14_8051_A10                                1
+#define GPIO_CONTROL_LOW_13                                         13:13
+#define GPIO_CONTROL_LOW_13_GPIO                                    0
+#define GPIO_CONTROL_LOW_13_8051_A9                                 1
+#define GPIO_CONTROL_LOW_12                                         12:12
+#define GPIO_CONTROL_LOW_12_GPIO                                    0
+#define GPIO_CONTROL_LOW_12_8051_A8                                 1
+#define GPIO_CONTROL_LOW_11                                         11:11
+#define GPIO_CONTROL_LOW_11_GPIO                                    0
+#define GPIO_CONTROL_LOW_11_8051_WAIT                               1
+#define GPIO_CONTROL_LOW_10                                         10:10
+#define GPIO_CONTROL_LOW_10_GPIO                                    0
+#define GPIO_CONTROL_LOW_10_8051_ALE                                1
+#define GPIO_CONTROL_LOW_9                                          9:9
+#define GPIO_CONTROL_LOW_9_GPIO                                     0
+#define GPIO_CONTROL_LOW_9_8051_WRITE                               1
+#define GPIO_CONTROL_LOW_8                                          8:8
+#define GPIO_CONTROL_LOW_8_GPIO                                     0
+#define GPIO_CONTROL_LOW_8_8051_READ                                1
+#define GPIO_CONTROL_LOW_7                                          7:7
+#define GPIO_CONTROL_LOW_7_GPIO                                     0
+#define GPIO_CONTROL_LOW_7_8051_AD7                                 1
+#define GPIO_CONTROL_LOW_6                                          6:6
+#define GPIO_CONTROL_LOW_6_GPIO                                     0
+#define GPIO_CONTROL_LOW_6_8051_AD6                                 1
+#define GPIO_CONTROL_LOW_5                                          5:5
+#define GPIO_CONTROL_LOW_5_GPIO                                     0
+#define GPIO_CONTROL_LOW_5_8051_AD5                                 1
+#define GPIO_CONTROL_LOW_4                                          4:4
+#define GPIO_CONTROL_LOW_4_GPIO                                     0
+#define GPIO_CONTROL_LOW_4_8051_AD4                                 1
+#define GPIO_CONTROL_LOW_3                                          3:3
+#define GPIO_CONTROL_LOW_3_GPIO                                     0
+#define GPIO_CONTROL_LOW_3_8051_AD3                                 1
+#define GPIO_CONTROL_LOW_2                                          2:2
+#define GPIO_CONTROL_LOW_2_GPIO                                     0
+#define GPIO_CONTROL_LOW_2_8051_AD2                                 1
+#define GPIO_CONTROL_LOW_1                                          1:1
+#define GPIO_CONTROL_LOW_1_GPIO                                     0
+#define GPIO_CONTROL_LOW_1_8051_AD1                                 1
+#define GPIO_CONTROL_LOW_0                                          0:0
+#define GPIO_CONTROL_LOW_0_GPIO                                     0
+#define GPIO_CONTROL_LOW_0_8051_AD0                                 1
+
+/* GPIO[63:32] Control */
+#define GPIO_CONTROL_HIGH                                           0x00000C
+#define GPIO_CONTROL_HIGH_63                                        31:31
+#define GPIO_CONTROL_HIGH_63_GPIO                                   0
+#define GPIO_CONTROL_HIGH_63_CRT7_ZVPORT15                          1
+#define GPIO_CONTROL_HIGH_62                                        30:30
+#define GPIO_CONTROL_HIGH_62_GPIO                                   0
+#define GPIO_CONTROL_HIGH_62_CRT6_ZVPORT14                          1
+#define GPIO_CONTROL_HIGH_61                                        29:29
+#define GPIO_CONTROL_HIGH_61_GPIO                                   0
+#define GPIO_CONTROL_HIGH_61_CRT5_ZVPORT13_PANEL17                  1
+#define GPIO_CONTROL_HIGH_60                                        28:28
+#define GPIO_CONTROL_HIGH_60_GPIO                                   0
+#define GPIO_CONTROL_HIGH_60_CRT4_ZVPORT12_PANEL16                  1
+#define GPIO_CONTROL_HIGH_59                                        27:27
+#define GPIO_CONTROL_HIGH_59_GPIO                                   0
+#define GPIO_CONTROL_HIGH_59_CRT3_ZVPORT11_PANEL9                   1
+#define GPIO_CONTROL_HIGH_58                                        26:26
+#define GPIO_CONTROL_HIGH_58_GPIO                                   0
+#define GPIO_CONTROL_HIGH_58_CRT2_ZVPORT10_PANEL8                   1
+#define GPIO_CONTROL_HIGH_57                                        25:25
+#define GPIO_CONTROL_HIGH_57_GPIO                                   0
+#define GPIO_CONTROL_HIGH_57_CRT1_ZVPORT9_PANEL1                    1
+#define GPIO_CONTROL_HIGH_56                                        24:24
+#define GPIO_CONTROL_HIGH_56_GPIO                                   0
+#define GPIO_CONTROL_HIGH_56_CRT0_ZVPORT8_PANEL0                    1
+#define GPIO_CONTROL_HIGH_55                                        23:23
+#define GPIO_CONTROL_HIGH_55_GPIO                                   0
+#define GPIO_CONTROL_HIGH_55_CRT_CLOCK                              1
+#define GPIO_CONTROL_HIGH_47                                        15:15
+#define GPIO_CONTROL_HIGH_47_GPIO                                   0
+#define GPIO_CONTROL_HIGH_47_I2C_DATA                               1
+#define GPIO_CONTROL_HIGH_46                                        14:14
+#define GPIO_CONTROL_HIGH_46_GPIO                                   0
+#define GPIO_CONTROL_HIGH_46_I2C_CLOCK                              1
+#define GPIO_CONTROL_HIGH_45                                        13:13
+#define GPIO_CONTROL_HIGH_45_GPIO                                   0
+#define GPIO_CONTROL_HIGH_45_SSP1_CLOCK                             1
+#define GPIO_CONTROL_HIGH_44                                        12:12
+#define GPIO_CONTROL_HIGH_44_GPIO                                   0
+#define GPIO_CONTROL_HIGH_44_UART1_RTS_SSP1_OUT                     1
+#define GPIO_CONTROL_HIGH_43                                        11:11
+#define GPIO_CONTROL_HIGH_43_GPIO                                   0
+#define GPIO_CONTROL_HIGH_43_UART1_CTS_SSP1_IN                      1
+#define GPIO_CONTROL_HIGH_42                                        10:10
+#define GPIO_CONTROL_HIGH_42_GPIO                                   0
+#define GPIO_CONTROL_HIGH_42_UART1_RX_SSP1_RX                       1
+#define GPIO_CONTROL_HIGH_41                                        9:9
+#define GPIO_CONTROL_HIGH_41_GPIO                                   0
+#define GPIO_CONTROL_HIGH_41_UART1_TX_SSP1_TX                       1
+#define GPIO_CONTROL_HIGH_40                                        8:8
+#define GPIO_CONTROL_HIGH_40_GPIO                                   0
+#define GPIO_CONTROL_HIGH_40_UART0_RTS                              1
+#define GPIO_CONTROL_HIGH_39                                        7:7
+#define GPIO_CONTROL_HIGH_39_GPIO                                   0
+#define GPIO_CONTROL_HIGH_39_UART0_CTS                              1
+#define GPIO_CONTROL_HIGH_38                                        6:6
+#define GPIO_CONTROL_HIGH_38_GPIO                                   0
+#define GPIO_CONTROL_HIGH_38_UART0_RX                               1
+#define GPIO_CONTROL_HIGH_37                                        5:5
+#define GPIO_CONTROL_HIGH_37_GPIO                                   0
+#define GPIO_CONTROL_HIGH_37_UART0_TX                               1
+#define GPIO_CONTROL_HIGH_36                                        4:4
+#define GPIO_CONTROL_HIGH_36_GPIO                                   0
+#define GPIO_CONTROL_HIGH_36_SSP0_CLOCK                             1
+#define GPIO_CONTROL_HIGH_35                                        3:3
+#define GPIO_CONTROL_HIGH_35_GPIO                                   0
+#define GPIO_CONTROL_HIGH_35_SSP0_IN                                1
+#define GPIO_CONTROL_HIGH_34                                        2:2
+#define GPIO_CONTROL_HIGH_34_GPIO                                   0
+#define GPIO_CONTROL_HIGH_34_SSP0_OUT                               1
+#define GPIO_CONTROL_HIGH_33                                        1:1
+#define GPIO_CONTROL_HIGH_33_GPIO                                   0
+#define GPIO_CONTROL_HIGH_33_SSP0_RX                                1
+#define GPIO_CONTROL_HIGH_32                                        0:0
+#define GPIO_CONTROL_HIGH_32_GPIO                                   0
+#define GPIO_CONTROL_HIGH_32_SSP0_TX                                1
+
+/* DRAM Control */
+#define DRAM_CONTROL                                                0x000010
+#define DRAM_CONTROL_EMBEDDED_MEMORY                                31:31
+#define DRAM_CONTROL_EMBEDDED_MEMORY_ENABLE                         0
+#define DRAM_CONTROL_EMBEDDED_MEMORY_DISABLE                        1
+#define DRAM_CONTROL_EXTERNAL_BURST                                 30:28
+#define DRAM_CONTROL_EXTERNAL_BURST_1                               0
+#define DRAM_CONTROL_EXTERNAL_BURST_2                               1
+#define DRAM_CONTROL_EXTERNAL_BURST_4                               2
+#define DRAM_CONTROL_EXTERNAL_BURST_8                               3
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY                           27:27
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY_2                         0
+#define DRAM_CONTROL_EXTERNAL_CAS_LATENCY_3                         1
+#define DRAM_CONTROL_EXTERNAL_SIZE                                  26:24
+#define DRAM_CONTROL_EXTERNAL_SIZE_2MB                              0
+#define DRAM_CONTROL_EXTERNAL_SIZE_4MB                              1
+#define DRAM_CONTROL_EXTERNAL_SIZE_64MB                             4
+#define DRAM_CONTROL_EXTERNAL_SIZE_32MB                             5
+#define DRAM_CONTROL_EXTERNAL_SIZE_16MB                             6
+#define DRAM_CONTROL_EXTERNAL_SIZE_8MB                              7
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE                           23:22
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_1024                      0
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_512                       2
+#define DRAM_CONTROL_EXTERNAL_COLUMN_SIZE_256                       3
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE                      21:21
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE_6                    0
+#define DRAM_CONTROL_EXTERNAL_ACTIVE_PRECHARGE_7                    1
+#define DRAM_CONTROL_EXTERNAL                                       20:20
+#define DRAM_CONTROL_EXTERNAL_RESET                                 0
+#define DRAM_CONTROL_EXTERNAL_NORMAL                                1
+#define DRAM_CONTROL_EXTERNAL_BANKS                                 19:19
+#define DRAM_CONTROL_EXTERNAL_BANKS_2                               0
+#define DRAM_CONTROL_EXTERNAL_BANKS_4                               1
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE                       18:18
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE_2                     0
+#define DRAM_CONTROL_EXTERNAL_WRITE_PRECHARGE_1                     1
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE                              17:17
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_DISABLE                      0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_ENABLE                       1
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND                          16:16
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND_10                       0
+#define DRAM_CONTROL_LOCAL_REFRESH_COMMAND_12                       1
+#define DRAM_CONTROL_LOCAL_SIZE                                     15:13
+#define DRAM_CONTROL_LOCAL_SIZE_4MB                                 0
+#define DRAM_CONTROL_LOCAL_SIZE_8MB                                 1
+#define DRAM_CONTROL_LOCAL_SIZE_16MB                                2
+#define DRAM_CONTROL_LOCAL_SIZE_32MB                                3
+#define DRAM_CONTROL_LOCAL_SIZE_64MB                                4
+#define DRAM_CONTROL_LOCAL_SIZE_2MB                                 5
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE                              12:11
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_256                          0
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_512                          2
+#define DRAM_CONTROL_LOCAL_COLUMN_SIZE_1024                         3
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME                         10:10
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME_1                       0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_TIME_2                       1
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE                    9:9
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE_4                  0
+#define DRAM_CONTROL_LOCAL_BLOCK_WRITE_PRECHARGE_1                  1
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE                         8:8
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE_6                       0
+#define DRAM_CONTROL_LOCAL_ACTIVE_PRECHARGE_7                       1
+#define DRAM_CONTROL_LOCAL                                          7:7
+#define DRAM_CONTROL_LOCAL_NORMAL                                   0
+#define DRAM_CONTROL_LOCAL_RESET                                    1
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE                            6:6
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE_ENABLE                     0
+#define DRAM_CONTROL_LOCAL_REMAIN_ACTIVE_DISABLE                    1
+#define DRAM_CONTROL_LOCAL_BANKS                                    1:1
+#define DRAM_CONTROL_LOCAL_BANKS_4                                  0
+#define DRAM_CONTROL_LOCAL_BANKS_2                                  1
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE                          0:0
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE_2                        0
+#define DRAM_CONTROL_LOCAL_WRITE_PRECHARGE_1                        1
+
+/* Arbitration Control */
+#define ARBITRATION_CONTROL                                         0x000014
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY                         29:29
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY_FIXED                   0
+#define ARBITRATION_CONTROL_EXTERNAL_MEMORY_REVOLVING               1
+#define ARBITRATION_CONTROL_LOCAL_MEMORY                            28:28
+#define ARBITRATION_CONTROL_LOCAL_MEMORY_FIXED                      0
+#define ARBITRATION_CONTROL_LOCAL_MEMORY_REVOLVING                  1
+#define ARBITRATION_CONTROL_USB                                     26:24
+#define ARBITRATION_CONTROL_USB_OFF                                 0
+#define ARBITRATION_CONTROL_USB_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_USB_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_USB_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_USB_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_USB_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_USB_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_USB_PRIORITY_7                          7
+#define ARBITRATION_CONTROL_PANEL                                   22:20
+#define ARBITRATION_CONTROL_PANEL_OFF                               0
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_1                        1
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_2                        2
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_3                        3
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_4                        4
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_5                        5
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_6                        6
+#define ARBITRATION_CONTROL_PANEL_PRIORITY_7                        7
+#define ARBITRATION_CONTROL_ZVPORT                                  18:16
+#define ARBITRATION_CONTROL_ZVPORT_OFF                              0
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_1                       1
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_2                       2
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_3                       3
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_4                       4
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_5                       5
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_6                       6
+#define ARBITRATION_CONTROL_ZVPORT_PRIORITY_7                       7
+#define ARBITRATION_CONTROL_COMMAND_LIST                            14:12
+#define ARBITRATION_CONTROL_COMMAND_LIST_OFF                        0
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_1                 1
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_2                 2
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_3                 3
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_4                 4
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_5                 5
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_6                 6
+#define ARBITRATION_CONTROL_COMMAND_LIST_PRIORITY_7                 7
+#define ARBITRATION_CONTROL_DMA                                     10:8
+#define ARBITRATION_CONTROL_DMA_OFF                                 0
+#define ARBITRATION_CONTROL_DMA_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_DMA_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_DMA_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_DMA_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_DMA_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_DMA_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_DMA_PRIORITY_7                          7
+#define ARBITRATION_CONTROL_VIDEO                                   6:4
+#define ARBITRATION_CONTROL_VIDEO_OFF                               0
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_1                        1
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_2                        2
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_3                        3
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_4                        4
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_5                        5
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_6                        6
+#define ARBITRATION_CONTROL_VIDEO_PRIORITY_7                        7
+#define ARBITRATION_CONTROL_CRT                                     2:0
+#define ARBITRATION_CONTROL_CRT_OFF                                 0
+#define ARBITRATION_CONTROL_CRT_PRIORITY_1                          1
+#define ARBITRATION_CONTROL_CRT_PRIORITY_2                          2
+#define ARBITRATION_CONTROL_CRT_PRIORITY_3                          3
+#define ARBITRATION_CONTROL_CRT_PRIORITY_4                          4
+#define ARBITRATION_CONTROL_CRT_PRIORITY_5                          5
+#define ARBITRATION_CONTROL_CRT_PRIORITY_6                          6
+#define ARBITRATION_CONTROL_CRT_PRIORITY_7                          7
+
+/* Command List Control */
+#define COMMAND_LIST_CONTROL                                        0x000018
+#define COMMAND_LIST_CONTROL_STATUS                                 31:31
+#define COMMAND_LIST_CONTROL_STATUS_STOPPED                         0
+#define COMMAND_LIST_CONTROL_STATUS_RUNNING                         1
+#define COMMAND_LIST_CONTROL_MEMORY                                 27:26
+#define COMMAND_LIST_CONTROL_MEMORY_LOCAL                           0
+#define COMMAND_LIST_CONTROL_MEMORY_EXTERNAL_CS0                    2
+#define COMMAND_LIST_CONTROL_MEMORY_EXTERNAL_CS1                    3
+#define COMMAND_LIST_CONTROL_ADDRESS                                25:0
+
+/* Command List Conditions */
+#define COMMAND_LIST_CONDITIONS                                     0x00001C
+
+/* Command List Return */
+#define COMMAND_LIST_RETURN                                         0x000020
+#define COMMAND_LIST_RETURN_MEMORY                                  27:26
+#define COMMAND_LIST_RETURN_MEMORY_LOCAL                            0
+#define COMMAND_LIST_RETURN_MEMORY_EXTERNAL_CS0                     2
+#define COMMAND_LIST_RETURN_MEMORY_EXTERNAL_CS1                     3
+#define COMMAND_LIST_RETURN_ADDRESS                                 25:0
+
+/* Command List Status */
+#define CMD_INTPR_STATUS                                0x000024
+#define CMD_INTPR_STATUS_2D_MEMORY_FIFO                 20:20
+#define CMD_INTPR_STATUS_2D_MEMORY_FIFO_NOT_EMPTY       0
+#define CMD_INTPR_STATUS_2D_MEMORY_FIFO_EMPTY           1
+#define CMD_INTPR_STATUS_COMMAND_FIFO                   19:19
+#define CMD_INTPR_STATUS_COMMAND_FIFO_NOT_EMPTY         0
+#define CMD_INTPR_STATUS_COMMAND_FIFO_EMPTY             1
+#define CMD_INTPR_STATUS_CSC_STATUS                     18:18
+#define CMD_INTPR_STATUS_CSC_STATUS_IDLE                0
+#define CMD_INTPR_STATUS_CSC_STATUS_BUSY                1
+#define CMD_INTPR_STATUS_MEMORY_DMA                     17:17
+#define CMD_INTPR_STATUS_MEMORY_DMA_IDLE                0
+#define CMD_INTPR_STATUS_MEMORY_DMA_BUSY                1
+#define CMD_INTPR_STATUS_CRT_STATUS                     16:16
+#define CMD_INTPR_STATUS_CRT_STATUS_CURRENT             0
+#define CMD_INTPR_STATUS_CRT_STATUS_PENDING             1
+#define CMD_INTPR_STATUS_CURRENT_FIELD                  15:15
+#define CMD_INTPR_STATUS_CURRENT_FIELD_ODD              0
+#define CMD_INTPR_STATUS_CURRENT_FIELD_EVEN             1
+#define CMD_INTPR_STATUS_VIDEO_STATUS                   14:14
+#define CMD_INTPR_STATUS_VIDEO_STATUS_CURRENT           0
+#define CMD_INTPR_STATUS_VIDEO_STATUS_PENDING           1
+#define CMD_INTPR_STATUS_PANEL_STATUS                   13:13
+#define CMD_INTPR_STATUS_PANEL_STATUS_CURRENT           0
+#define CMD_INTPR_STATUS_PANEL_STATUS_PENDING           1
+#define CMD_INTPR_STATUS_CRT_SYNC                       12:12
+#define CMD_INTPR_STATUS_CRT_SYNC_INACTIVE              0
+#define CMD_INTPR_STATUS_CRT_SYNC_ACTIVE                1
+#define CMD_INTPR_STATUS_PANEL_SYNC                     11:11
+#define CMD_INTPR_STATUS_PANEL_SYNC_INACTIVE            0
+#define CMD_INTPR_STATUS_PANEL_SYNC_ACTIVE              1
+#define CMD_INTPR_STATUS_2D_SETUP                       2:2
+#define CMD_INTPR_STATUS_2D_SETUP_IDLE                  0
+#define CMD_INTPR_STATUS_2D_SETUP_BUSY                  1
+#define CMD_INTPR_STATUS_2D_FIFO                        1:1
+#define CMD_INTPR_STATUS_2D_FIFO_NOT_EMPTY              0
+#define CMD_INTPR_STATUS_2D_FIFO_EMPTY                  1
+#define CMD_INTPR_STATUS_2D_ENGINE                      0:0
+#define CMD_INTPR_STATUS_2D_ENGINE_IDLE                 0
+#define CMD_INTPR_STATUS_2D_ENGINE_BUSY                 1
+
+/* Raw Interrupt Status & Clear */
+#define RAW_INTERRUPT_STATUS                                        0x000028
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN                      5:5
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_NOT_ACTIVE           0
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_ACTIVE               1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_CLEAR                1
+#define RAW_INTERRUPT_STATUS_ZVPORT                                 4:4
+#define RAW_INTERRUPT_STATUS_ZVPORT_NOT_ACTIVE                      0
+#define RAW_INTERRUPT_STATUS_ZVPORT_ACTIVE                          1
+#define RAW_INTERRUPT_STATUS_ZVPORT_CLEAR                           1
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC                      3:3
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE           0
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_ACTIVE               1
+#define RAW_INTERRUPT_STATUS_CRT_VERTICAL_SYNC_CLEAR                1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE                              2:2
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_NOT_ACTIVE                   0
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_ACTIVE                       1
+#define RAW_INTERRUPT_STATUS_USB_SLAVE_CLEAR                        1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC                    1:1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE         0
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_ACTIVE             1
+#define RAW_INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_CLEAR              1
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST                           0:0
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_NOT_ACTIVE                0
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_ACTIVE                    1
+#define RAW_INTERRUPT_STATUS_COMMAND_LIST_CLEAR                     1
+
+/* Interrupt Status */
+#define INTERRUPT_STATUS                                            0x00002C
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN                          31:31
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_NOT_ACTIVE               0
+#define INTERRUPT_STATUS_USB_SLAVE_PLUG_IN_ACTIVE                   1
+#define INTERRUPT_STATUS_GPIO54                                     30:30
+#define INTERRUPT_STATUS_GPIO54_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO54_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO53                                     29:29
+#define INTERRUPT_STATUS_GPIO53_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO53_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO52                                     28:28
+#define INTERRUPT_STATUS_GPIO52_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO52_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO51                                     27:27
+#define INTERRUPT_STATUS_GPIO51_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO51_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO50                                     26:26
+#define INTERRUPT_STATUS_GPIO50_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO50_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO49                                     25:25
+#define INTERRUPT_STATUS_GPIO49_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO49_ACTIVE                              1
+#define INTERRUPT_STATUS_GPIO48                                     24:24
+#define INTERRUPT_STATUS_GPIO48_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_GPIO48_ACTIVE                              1
+#define INTERRUPT_STATUS_I2C                                        23:23
+#define INTERRUPT_STATUS_I2C_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_I2C_ACTIVE                                 1
+#define INTERRUPT_STATUS_PWM                                        22:22
+#define INTERRUPT_STATUS_PWM_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_PWM_ACTIVE                                 1
+#define INTERRUPT_STATUS_DMA                                        20:20
+#define INTERRUPT_STATUS_DMA_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_DMA_ACTIVE                                 1
+#define INTERRUPT_STATUS_PCI                                        19:19
+#define INTERRUPT_STATUS_PCI_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_PCI_ACTIVE                                 1
+#define INTERRUPT_STATUS_I2S                                        18:18
+#define INTERRUPT_STATUS_I2S_NOT_ACTIVE                             0
+#define INTERRUPT_STATUS_I2S_ACTIVE                                 1
+#define INTERRUPT_STATUS_AC97                                       17:17
+#define INTERRUPT_STATUS_AC97_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_AC97_ACTIVE                                1
+#define INTERRUPT_STATUS_USB_SLAVE                                  16:16
+#define INTERRUPT_STATUS_USB_SLAVE_NOT_ACTIVE                       0
+#define INTERRUPT_STATUS_USB_SLAVE_ACTIVE                           1
+#define INTERRUPT_STATUS_UART1                                      13:13
+#define INTERRUPT_STATUS_UART1_NOT_ACTIVE                           0
+#define INTERRUPT_STATUS_UART1_ACTIVE                               1
+#define INTERRUPT_STATUS_UART0                                      12:12
+#define INTERRUPT_STATUS_UART0_NOT_ACTIVE                           0
+#define INTERRUPT_STATUS_UART0_ACTIVE                               1
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC                          11:11
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC_NOT_ACTIVE               0
+#define INTERRUPT_STATUS_CRT_VERTICAL_SYNC_ACTIVE                   1
+#define INTERRUPT_STATUS_8051                                       10:10
+#define INTERRUPT_STATUS_8051_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_8051_ACTIVE                                1
+#define INTERRUPT_STATUS_SSP1                                       9:9
+#define INTERRUPT_STATUS_SSP1_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_SSP1_ACTIVE                                1
+#define INTERRUPT_STATUS_SSP0                                       8:8
+#define INTERRUPT_STATUS_SSP0_NOT_ACTIVE                            0
+#define INTERRUPT_STATUS_SSP0_ACTIVE                                1
+#define INTERRUPT_STATUS_USB_HOST                                   6:6
+#define INTERRUPT_STATUS_USB_HOST_NOT_ACTIVE                        0
+#define INTERRUPT_STATUS_USB_HOST_ACTIVE                            1
+#define INTERRUPT_STATUS_2D                                         3:3
+#define INTERRUPT_STATUS_2D_NOT_ACTIVE                              0
+#define INTERRUPT_STATUS_2D_ACTIVE                                  1
+#define INTERRUPT_STATUS_ZVPORT                                     2:2
+#define INTERRUPT_STATUS_ZVPORT_NOT_ACTIVE                          0
+#define INTERRUPT_STATUS_ZVPORT_ACTIVE                              1
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC                        1:1
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_NOT_ACTIVE             0
+#define INTERRUPT_STATUS_PANEL_VERTICAL_SYNC_ACTIVE                 1
+#define INTERRUPT_STATUS_COMMAND_LIST                               0:0
+#define INTERRUPT_STATUS_COMMAND_LIST_NOT_ACTIVE                    0
+#define INTERRUPT_STATUS_COMMAND_LIST_ACTIVE                        1
+
+/* Interrupt Mask */
+#define INTERRUPT_MASK                                              0x000030
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN                            31:31
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN_DISABLE                    0
+#define INTERRUPT_MASK_USB_SLAVE_PLUG_IN_ENABLE                     1
+#define INTERRUPT_MASK_GPIO54                                       30:30
+#define INTERRUPT_MASK_GPIO54_DISABLE                               0
+#define INTERRUPT_MASK_GPIO54_ENABLE                                1
+#define INTERRUPT_MASK_GPIO53                                       29:29
+#define INTERRUPT_MASK_GPIO53_DISABLE                               0
+#define INTERRUPT_MASK_GPIO53_ENABLE                                1
+#define INTERRUPT_MASK_GPIO52                                       28:28
+#define INTERRUPT_MASK_GPIO52_DISABLE                               0
+#define INTERRUPT_MASK_GPIO52_ENABLE                                1
+#define INTERRUPT_MASK_GPIO51                                       27:27
+#define INTERRUPT_MASK_GPIO51_DISABLE                               0
+#define INTERRUPT_MASK_GPIO51_ENABLE                                1
+#define INTERRUPT_MASK_GPIO50                                       26:26
+#define INTERRUPT_MASK_GPIO50_DISABLE                               0
+#define INTERRUPT_MASK_GPIO50_ENABLE                                1
+#define INTERRUPT_MASK_GPIO49                                       25:25
+#define INTERRUPT_MASK_GPIO49_DISABLE                               0
+#define INTERRUPT_MASK_GPIO49_ENABLE                                1
+#define INTERRUPT_MASK_GPIO48                                       24:24
+#define INTERRUPT_MASK_GPIO48_DISABLE                               0
+#define INTERRUPT_MASK_GPIO48_ENABLE                                1
+#define INTERRUPT_MASK_I2C                                          23:23
+#define INTERRUPT_MASK_I2C_DISABLE                                  0
+#define INTERRUPT_MASK_I2C_ENABLE                                   1
+#define INTERRUPT_MASK_PWM                                          22:22
+#define INTERRUPT_MASK_PWM_DISABLE                                  0
+#define INTERRUPT_MASK_PWM_ENABLE                                   1
+#define INTERRUPT_MASK_DMA                                          20:20
+#define INTERRUPT_MASK_DMA_DISABLE                                  0
+#define INTERRUPT_MASK_DMA_ENABLE                                   1
+#define INTERRUPT_MASK_PCI                                          19:19
+#define INTERRUPT_MASK_PCI_DISABLE                                  0
+#define INTERRUPT_MASK_PCI_ENABLE                                   1
+#define INTERRUPT_MASK_I2S                                          18:18
+#define INTERRUPT_MASK_I2S_DISABLE                                  0
+#define INTERRUPT_MASK_I2S_ENABLE                                   1
+#define INTERRUPT_MASK_AC97                                         17:17
+#define INTERRUPT_MASK_AC97_DISABLE                                 0
+#define INTERRUPT_MASK_AC97_ENABLE                                  1
+#define INTERRUPT_MASK_USB_SLAVE                                    16:16
+#define INTERRUPT_MASK_USB_SLAVE_DISABLE                            0
+#define INTERRUPT_MASK_USB_SLAVE_ENABLE                             1
+#define INTERRUPT_MASK_UART1                                        13:13
+#define INTERRUPT_MASK_UART1_DISABLE                                0
+#define INTERRUPT_MASK_UART1_ENABLE                                 1
+#define INTERRUPT_MASK_UART0                                        12:12
+#define INTERRUPT_MASK_UART0_DISABLE                                0
+#define INTERRUPT_MASK_UART0_ENABLE                                 1
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC                            11:11
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC_DISABLE                    0
+#define INTERRUPT_MASK_CRT_VERTICAL_SYNC_ENABLE                     1
+#define INTERRUPT_MASK_8051                                         10:10
+#define INTERRUPT_MASK_8051_DISABLE                                 0
+#define INTERRUPT_MASK_8051_ENABLE                                  1
+#define INTERRUPT_MASK_SSP1                                         9:9
+#define INTERRUPT_MASK_SSP1_DISABLE                                 0
+#define INTERRUPT_MASK_SSP1_ENABLE                                  1
+#define INTERRUPT_MASK_SSP0                                         8:8
+#define INTERRUPT_MASK_SSP0_DISABLE                                 0
+#define INTERRUPT_MASK_SSP0_ENABLE                                  1
+#define INTERRUPT_MASK_USB_HOST                                     6:6
+#define INTERRUPT_MASK_USB_HOST_DISABLE                             0
+#define INTERRUPT_MASK_USB_HOST_ENABLE                              1
+#define INTERRUPT_MASK_2D                                           3:3
+#define INTERRUPT_MASK_2D_DISABLE                                   0
+#define INTERRUPT_MASK_2D_ENABLE                                    1
+#define INTERRUPT_MASK_ZVPORT                                       2:2
+#define INTERRUPT_MASK_ZVPORT_DISABLE                               0
+#define INTERRUPT_MASK_ZVPORT_ENABLE                                1
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC                          1:1
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC_DISABLE                  0
+#define INTERRUPT_MASK_PANEL_VERTICAL_SYNC_ENABLE                   1
+#define INTERRUPT_MASK_COMMAND_LIST                                 0:0
+#define INTERRUPT_MASK_COMMAND_LIST_DISABLE                         0
+#define INTERRUPT_MASK_COMMAND_LIST_ENABLE                          1
+
+/* Debug Control */
+#define DEBUG_CONTROL                                               0x000034
+#define DEBUG_CONTROL_MODULE                                        7:5
+#define DEBUG_CONTROL_PARTITION                                     4:0
+#define DEBUG_CONTROL_PARTITION_HIF                                 0
+#define DEBUG_CONTROL_PARTITION_EXTERNAL_MEMORY                     1
+#define DEBUG_CONTROL_PARTITION_PCI                                 2
+#define DEBUG_CONTROL_PARTITION_COMMAND_LIST                        3
+#define DEBUG_CONTROL_PARTITION_DISPLAY                             4
+#define DEBUG_CONTROL_PARTITION_ZVPORT                              5
+#define DEBUG_CONTROL_PARTITION_2D                                  6
+#define DEBUG_CONTROL_PARTITION_LOCAL_MEMORY                        8
+#define DEBUG_CONTROL_PARTITION_USB_HOST                            10
+#define DEBUG_CONTROL_PARTITION_SSP0                                12
+#define DEBUG_CONTROL_PARTITION_SSP1                                13
+#define DEBUG_CONTROL_PARTITION_UART0                               19
+#define DEBUG_CONTROL_PARTITION_UART1                               20
+#define DEBUG_CONTROL_PARTITION_I2C                                 21
+#define DEBUG_CONTROL_PARTITION_8051                                23
+#define DEBUG_CONTROL_PARTITION_AC97                                24
+#define DEBUG_CONTROL_PARTITION_I2S                                 25
+#define DEBUG_CONTROL_PARTITION_INTMEM                              26
+#define DEBUG_CONTROL_PARTITION_DMA                                 27
+#define DEBUG_CONTROL_PARTITION_SIMULATION                          28
+
+/* Current Gate */
+#define CURRENT_GATE                                                0x000038
+#define CURRENT_GATE_AC97_I2S                                       18:18
+#define CURRENT_GATE_AC97_I2S_DISABLE                               0
+#define CURRENT_GATE_AC97_I2S_ENABLE                                1
+#define CURRENT_GATE_8051                                           17:17
+#define CURRENT_GATE_8051_DISABLE                                   0
+#define CURRENT_GATE_8051_ENABLE                                    1
+#define CURRENT_GATE_PLL                                            16:16
+#define CURRENT_GATE_PLL_ENABLE                                     0
+#define CURRENT_GATE_PLL_DISABLE                                    1
+#define CURRENT_GATE_OSCILLATOR                                     15:15
+#define CURRENT_GATE_OSCILLATOR_ENABLE                              0
+#define CURRENT_GATE_OSCILLATOR_DISABLE                             1
+#define CURRENT_GATE_PLL_RECOVERY                                   14:13
+#define CURRENT_GATE_PLL_RECOVERY_1MS                               0
+#define CURRENT_GATE_PLL_RECOVERY_2MS                               1
+#define CURRENT_GATE_PLL_RECOVERY_3MS                               2
+#define CURRENT_GATE_PLL_RECOVERY_4MS                               3
+#define CURRENT_GATE_USB_SLAVE                                      12:12
+#define CURRENT_GATE_USB_SLAVE_DISABLE                              0
+#define CURRENT_GATE_USB_SLAVE_ENABLE                               1
+#define CURRENT_GATE_USB_HOST                                       11:11
+#define CURRENT_GATE_USB_HOST_DISABLE                               0
+#define CURRENT_GATE_USB_HOST_ENABLE                                1
+#define CURRENT_GATE_SSP                                            10:10
+#define CURRENT_GATE_SSP_DISABLE                                    0
+#define CURRENT_GATE_SSP_ENABLE                                     1
+#define CURRENT_GATE_UART1                                          8:8
+#define CURRENT_GATE_UART1_DISABLE                                  0
+#define CURRENT_GATE_UART1_ENABLE                                   1
+#define CURRENT_GATE_UART0                                          7:7
+#define CURRENT_GATE_UART0_DISABLE                                  0
+#define CURRENT_GATE_UART0_ENABLE                                   1
+#define CURRENT_GATE_GPIO_PWM_I2C                                   6:6
+#define CURRENT_GATE_GPIO_PWM_I2C_DISABLE                           0
+#define CURRENT_GATE_GPIO_PWM_I2C_ENABLE                            1
+#define CURRENT_GATE_ZVPORT                                         5:5
+#define CURRENT_GATE_ZVPORT_DISABLE                                 0
+#define CURRENT_GATE_ZVPORT_ENABLE                                  1
+#define CURRENT_GATE_CSC                                            4:4
+#define CURRENT_GATE_CSC_DISABLE                                    0
+#define CURRENT_GATE_CSC_ENABLE                                     1
+#define CURRENT_GATE_2D                                             3:3
+#define CURRENT_GATE_2D_DISABLE                                     0
+#define CURRENT_GATE_2D_ENABLE                                      1
+#define CURRENT_GATE_DISPLAY                                        2:2
+#define CURRENT_GATE_DISPLAY_DISABLE                                0
+#define CURRENT_GATE_DISPLAY_ENABLE                                 1
+#define CURRENT_GATE_MEMORY                                         1:1
+#define CURRENT_GATE_MEMORY_DISABLE                                 0
+#define CURRENT_GATE_MEMORY_ENABLE                                  1
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA                          0:0
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA_DISABLE                  0
+#define CURRENT_GATE_HOST_COMMAND_LIST_DMA_ENABLE                   1
+
+/* Current Clock */
+#define CURRENT_POWER_CLOCK                             0x00003C
+#define CURRENT_POWER_CLOCK_P1XCLK			            31:31
+#define CURRENT_POWER_CLOCK_P1XCLK_ENABLE               1
+#define CURRENT_POWER_CLOCK_P1XCLK_DISABLE              0
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT               30:30
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT_ENABLE        1
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT_DISABLE       0
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT               29:29
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288           0
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336           1
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER              28:27
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1            0
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3            1
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5            2
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT                26:24
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0              0
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1              1
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2              2
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3              3
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4              4
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5              5
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6              6
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7              7
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT               20:20
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288           0
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336           1
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER              19:19
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1            0
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3            1
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT                18:16
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0              0
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1              1
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2              2
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3              3
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4              4
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5              5
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6              6
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7              7
+#define CURRENT_POWER_CLOCK_MCLK_SELECT                 12:12
+#define CURRENT_POWER_CLOCK_MCLK_SELECT_288             0
+#define CURRENT_POWER_CLOCK_MCLK_SELECT_336             1
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER                11:11
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1              0
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3              1
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT                  10:8
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0                0
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1                1
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2                2
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3                3
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4                4
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5                5
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6                6
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7                7
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT               4:4
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288           0
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336           1
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER              3:3
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1            0
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3            1
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT                2:0
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0              0
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1              1
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2              2
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3              3
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4              4
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5              5
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6              6
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7              7
+
+
+/* Power Mode 0 Gate */
+#define POWER_MODE0_GATE                                            0x000040
+#define POWER_MODE0_GATE_AC97_I2S                                   18:18
+#define POWER_MODE0_GATE_AC97_I2S_DISABLE                           0
+#define POWER_MODE0_GATE_AC97_I2S_ENABLE                            1
+#define POWER_MODE0_GATE_8051                                       17:17
+#define POWER_MODE0_GATE_8051_DISABLE                               0
+#define POWER_MODE0_GATE_8051_ENABLE                                1
+#define POWER_MODE0_GATE_USB_SLAVE                                  12:12
+#define POWER_MODE0_GATE_USB_SLAVE_DISABLE                          0
+#define POWER_MODE0_GATE_USB_SLAVE_ENABLE                           1
+#define POWER_MODE0_GATE_USB_HOST                                   11:11
+#define POWER_MODE0_GATE_USB_HOST_DISABLE                           0
+#define POWER_MODE0_GATE_USB_HOST_ENABLE                            1
+#define POWER_MODE0_GATE_SSP                                        10:10
+#define POWER_MODE0_GATE_SSP_DISABLE                                0
+#define POWER_MODE0_GATE_SSP_ENABLE                                 1
+#define POWER_MODE0_GATE_UART1                                      8:8
+#define POWER_MODE0_GATE_UART1_DISABLE                              0
+#define POWER_MODE0_GATE_UART1_ENABLE                               1
+#define POWER_MODE0_GATE_UART0                                      7:7
+#define POWER_MODE0_GATE_UART0_DISABLE                              0
+#define POWER_MODE0_GATE_UART0_ENABLE                               1
+#define POWER_MODE0_GATE_GPIO_PWM_I2C                               6:6
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE                       0
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE                        1
+#define POWER_MODE0_GATE_ZVPORT                                     5:5
+#define POWER_MODE0_GATE_ZVPORT_DISABLE                             0
+#define POWER_MODE0_GATE_ZVPORT_ENABLE                              1
+#define POWER_MODE0_GATE_CSC                                        4:4
+#define POWER_MODE0_GATE_CSC_DISABLE                                0
+#define POWER_MODE0_GATE_CSC_ENABLE                                 1
+#define POWER_MODE0_GATE_2D                                         3:3
+#define POWER_MODE0_GATE_2D_DISABLE                                 0
+#define POWER_MODE0_GATE_2D_ENABLE                                  1
+#define POWER_MODE0_GATE_DISPLAY                                    2:2
+#define POWER_MODE0_GATE_DISPLAY_DISABLE                            0
+#define POWER_MODE0_GATE_DISPLAY_ENABLE                             1
+#define POWER_MODE0_GATE_MEMORY                                     1:1
+#define POWER_MODE0_GATE_MEMORY_DISABLE                             0
+#define POWER_MODE0_GATE_MEMORY_ENABLE                              1
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA                      0:0
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA_DISABLE              0
+#define POWER_MODE0_GATE_HOST_COMMAND_LIST_DMA_ENABLE               1
+
+/* Power Mode 0 Clock */
+#define POWER_MODE0_CLOCK                               0x000044
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK					31:31
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK_ENABLE			1
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK_DISABLE			0
+#define POWER_MODE0_CLOCK_PLL3							30:30
+#define POWER_MODE0_CLOCK_PLL3_ENABLE					1
+#define POWER_MODE0_CLOCK_PLL3_DISABLE					0							
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT                 29:29
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_288             0
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_336             1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER                28:27
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_1              0
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_3              1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_5              2
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT                  26:24
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_0                0
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_1                1
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_2                2
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_3                3
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_4                4
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_5                5
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_6                6
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_7                7
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT                 20:20
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_288             0
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_336             1
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER                19:19
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_1              0
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_3              1
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT                  18:16
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_0                0
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_1                1
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_2                2
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_3                3
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_4                4
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_5                5
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_6                6
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_7                7
+#define POWER_MODE0_CLOCK_MCLK_SELECT                   12:12
+#define POWER_MODE0_CLOCK_MCLK_SELECT_288               0
+#define POWER_MODE0_CLOCK_MCLK_SELECT_336               1
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER                  11:11
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_1                0
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_3                1
+#define POWER_MODE0_CLOCK_MCLK_SHIFT                    10:8
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_0                  0
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_1                  1
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_2                  2
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_3                  3
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_4                  4
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_5                  5
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_6                  6
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_7                  7
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT                 4:4
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT_288             0
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT_336             1
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER                3:3
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_1              0
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_3              1
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT                  2:0
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_0                0
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_1                1
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_2                2
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_3                3
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_4                4
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_5                5
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_6                6
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_7                7
+
+/* Power Mode 1 Gate */
+#define POWER_MODE1_GATE                                            0x000048
+#define POWER_MODE1_GATE_AC97_I2S                                   18:18
+#define POWER_MODE1_GATE_AC97_I2S_DISABLE                           0
+#define POWER_MODE1_GATE_AC97_I2S_ENABLE                            1
+#define POWER_MODE1_GATE_8051                                       17:17
+#define POWER_MODE1_GATE_8051_DISABLE                               0
+#define POWER_MODE1_GATE_8051_ENABLE                                1
+#define POWER_MODE1_GATE_USB_SLAVE                                  12:12
+#define POWER_MODE1_GATE_USB_SLAVE_DISABLE                          0
+#define POWER_MODE1_GATE_USB_SLAVE_ENABLE                           1
+#define POWER_MODE1_GATE_USB_HOST                                   11:11
+#define POWER_MODE1_GATE_USB_HOST_DISABLE                           0
+#define POWER_MODE1_GATE_USB_HOST_ENABLE                            1
+#define POWER_MODE1_GATE_SSP                                        10:10
+#define POWER_MODE1_GATE_SSP_DISABLE                                0
+#define POWER_MODE1_GATE_SSP_ENABLE                                 1
+#define POWER_MODE1_GATE_UART1                                      8:8
+#define POWER_MODE1_GATE_UART1_DISABLE                              0
+#define POWER_MODE1_GATE_UART1_ENABLE                               1
+#define POWER_MODE1_GATE_UART0                                      7:7
+#define POWER_MODE1_GATE_UART0_DISABLE                              0
+#define POWER_MODE1_GATE_UART0_ENABLE                               1
+#define POWER_MODE1_GATE_GPIO_PWM_I2C                               6:6
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_DISABLE                       0
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_ENABLE                        1
+#define POWER_MODE1_GATE_ZVPORT                                     5:5
+#define POWER_MODE1_GATE_ZVPORT_DISABLE                             0
+#define POWER_MODE1_GATE_ZVPORT_ENABLE                              1
+#define POWER_MODE1_GATE_CSC                                        4:4
+#define POWER_MODE1_GATE_CSC_DISABLE                                0
+#define POWER_MODE1_GATE_CSC_ENABLE                                 1
+#define POWER_MODE1_GATE_2D                                         3:3
+#define POWER_MODE1_GATE_2D_DISABLE                                 0
+#define POWER_MODE1_GATE_2D_ENABLE                                  1
+#define POWER_MODE1_GATE_DISPLAY                                    2:2
+#define POWER_MODE1_GATE_DISPLAY_DISABLE                            0
+#define POWER_MODE1_GATE_DISPLAY_ENABLE                             1
+#define POWER_MODE1_GATE_MEMORY                                     1:1
+#define POWER_MODE1_GATE_MEMORY_DISABLE                             0
+#define POWER_MODE1_GATE_MEMORY_ENABLE                              1
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA                      0:0
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA_DISABLE              0
+#define POWER_MODE1_GATE_HOST_COMMAND_LIST_DMA_ENABLE               1
+
+/* Power Mode 1 Clock */
+#define POWER_MODE1_CLOCK                               0x00004C
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK					31:31
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK_ENABLE			1
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK_DISABLE			0
+#define POWER_MODE1_CLOCK_PLL3							30:30
+#define POWER_MODE1_CLOCK_PLL3_ENABLE					1
+#define POWER_MODE1_CLOCK_PLL3_DISABLE					0							
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT                 29:29
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_288             0
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_336             1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER                28:27
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_1              0
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_3              1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_5              2
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT                  26:24
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_0                0
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_1                1
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_2                2
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_3                3
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_4                4
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_5                5
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_6                6
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_7                7
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT                 20:20
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_288             0
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_336             1
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER                19:19
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_1              0
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_3              1
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT                  18:16
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_0                0
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_1                1
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_2                2
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_3                3
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_4                4
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_5                5
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_6                6
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_7                7
+#define POWER_MODE1_CLOCK_MCLK_SELECT                   12:12
+#define POWER_MODE1_CLOCK_MCLK_SELECT_288               0
+#define POWER_MODE1_CLOCK_MCLK_SELECT_336               1
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER                  11:11
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_1                0
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_3                1
+#define POWER_MODE1_CLOCK_MCLK_SHIFT                    10:8
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_0                  0
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_1                  1
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_2                  2
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_3                  3
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_4                  4
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_5                  5
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_6                  6
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_7                  7
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT                 4:4
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT_288             0
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT_336             1
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER                3:3
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_1              0
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_3              1
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT                  2:0
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_0                0
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_1                1
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_2                2
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_3                3
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_4                4
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_5                5
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_6                6
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_7                7
+
+/* Sleep Mode Gate */
+#define SLEEP_MODE_GATE                                             0x000050
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK                          22:19
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_4096                     0
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_2048                     1
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_1024                     2
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_512                      3
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_256                      4
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_128                      5
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_64                       6
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_32                       7
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_16                       8
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_8                        9
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_4                        10
+#define SLEEP_MODE_GATE_PLL_RECOVERY_CLOCK_2                        11
+#define SLEEP_MODE_GATE_PLL_RECOVERY                                14:13
+#define SLEEP_MODE_GATE_PLL_RECOVERY_1MS                            0
+#define SLEEP_MODE_GATE_PLL_RECOVERY_2MS                            1
+#define SLEEP_MODE_GATE_PLL_RECOVERY_3MS                            2
+#define SLEEP_MODE_GATE_PLL_RECOVERY_4MS                            3
+
+/* Power Mode Control */
+#define POWER_MODE_CTRL                                 0x000054
+#define POWER_MODE_CTRL_SLEEP_STATUS                    2:2
+#define POWER_MODE_CTRL_SLEEP_STATUS_INACTIVE           0
+#define POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE             1
+#define POWER_MODE_CTRL_MODE                            1:0
+#define POWER_MODE_CTRL_MODE_MODE0                      0
+#define POWER_MODE_CTRL_MODE_MODE1                      1
+#define POWER_MODE_CTRL_MODE_SLEEP                      2
+
+
+/* PCI Master Base Address */
+#define PCI_MASTER_BASE                                             0x000058
+#define PCI_MASTER_BASE_ADDRESS                                     31:20
+
+/* Endian Control */
+#define ENDIAN_CONTROL                                              0x00005C
+#define ENDIAN_CONTROL_ENDIAN_SELECT                                0:0
+#define ENDIAN_CONTROL_ENDIAN_SELECT_LITTLE                         0
+#define ENDIAN_CONTROL_ENDIAN_SELECT_BIG                            1
+
+/* Device Id */
+#define DEVICE_ID                                                   0x000060
+#define DEVICE_ID_DEVICE                                            31:16
+#define DEVICE_ID_REVISION                                          7:0
+
+/* PLL Clock Count */
+#define PLL_CLOCK_COUNT                                             0x000064
+#define PLL_CLOCK_COUNT_COUNT                                       15:0
+
+/* Miscellaneous Timing */
+#define MISCELLANEOUS_TIMING                                        0x000068
+#define MISCELLANEOUS_TIMING_EXTEND                                 31:28
+#define MISCELLANEOUS_TIMING_EXTEND_NONE                            0
+#define MISCELLANEOUS_TIMING_EXTEND_16_HCLK                         1
+#define MISCELLANEOUS_TIMING_EXTEND_32_HCLK                         2
+#define MISCELLANEOUS_TIMING_EXTEND_48_HCLK                         3
+#define MISCELLANEOUS_TIMING_EXTEND_64_HCLK                         4
+#define MISCELLANEOUS_TIMING_EXTEND_80_HCLK                         5
+#define MISCELLANEOUS_TIMING_EXTEND_96_HCLK                         6
+#define MISCELLANEOUS_TIMING_EXTEND_112_HCLK                        7
+#define MISCELLANEOUS_TIMING_EXTEND_128_HCLK                        8
+#define MISCELLANEOUS_TIMING_EXTEND_144_HCLK                        9
+#define MISCELLANEOUS_TIMING_EXTEND_160_HCLK                        10
+#define MISCELLANEOUS_TIMING_EXTEND_176_HCLK                        11
+#define MISCELLANEOUS_TIMING_EXTEND_192_HCLK                        12
+#define MISCELLANEOUS_TIMING_EXTEND_208_HCLK                        13
+#define MISCELLANEOUS_TIMING_EXTEND_224_HCLK                        14
+#define MISCELLANEOUS_TIMING_EXTEND_240_HCLK                        15
+#define MISCELLANEOUS_TIMING_UART1_PLL                              27:27
+#define MISCELLANEOUS_TIMING_UART1_PLL_DISABLE                       0
+#define MISCELLANEOUS_TIMING_UART1_PLL_ENABLE                        1
+#define MISCELLANEOUS_TIMING_UART0_PLL                              26:26
+#define MISCELLANEOUS_TIMING_UART0_PLL_DISABLE                       0
+#define MISCELLANEOUS_TIMING_UART0_PLL_ENABLE                        1
+#define MISCELLANEOUS_TIMING_XSCALE                                 25:24
+#define MISCELLANEOUS_TIMING_XSCALE_PLL                             0
+#define MISCELLANEOUS_TIMING_XSCALE_HCLK                            1
+#define MISCELLANEOUS_TIMING_XSCALE_GPIO30                          2
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT                  23:23
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT_DISABLE          0
+#define MISCELLANEOUS_TIMING_USB_HOST_OVER_CURRENT_ENABLE           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1              20:20
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1_288          0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE1_336          1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1             19:16
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_1           0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_2           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_4           2
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_8           3
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_16          4
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_32          5
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_64          6
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_128         7
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_3           8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_6           9
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_12          10
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_24          11
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_48          12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_96          13
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_192         14
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE1_384         15
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0              12:12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0_288          0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_SELECT_MODE0_336          1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0             11:8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_1           0
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_2           1
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_4           2
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_8           3
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_16          4
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_32          5
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_64          6
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_128         7
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_3           8
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_6           9
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_12          10
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_24          11
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_48          12
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_96          13
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_192         14
+#define MISCELLANEOUS_TIMING_SYSTEM_SDRAM_DIVIDER_MODE0_384         15
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG                        7:7
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG_CHECK_INPUT            0
+#define MISCELLANEOUS_TIMING_96MHZ_PLL_DEBUG_CHECK_OUTPUT           1
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL                           6:6
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL_DISABLE                   0
+#define MISCELLANEOUS_TIMING_ACPI_CONTROL_ENABLE                    1
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER                            5:4
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_336                        0
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_288                        1
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_240                        2
+#define MISCELLANEOUS_TIMING_PLL_DIVIDER_192                        3
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE                          3:3
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE_NORMAL                   0
+#define MISCELLANEOUS_TIMING_USB_HOST_MODE_SIMULATION               1
+#define MISCELLANEOUS_TIMING_DELAY                                  2:0
+#define MISCELLANEOUS_TIMING_DELAY_NONE                             0
+#define MISCELLANEOUS_TIMING_DELAY_500PS                            1
+#define MISCELLANEOUS_TIMING_DELAY_1NS                              2
+#define MISCELLANEOUS_TIMING_DELAY_1500PS                           3
+#define MISCELLANEOUS_TIMING_DELAY_2NS                              4
+#define MISCELLANEOUS_TIMING_DELAY_2500PS                           5
+
+/* Current System SDRAM Clock */
+#define CURRENT_SYSTEM_SDRAM_CLOCK                                  0x00006C
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT                           4:4
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT_288                       0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_SELECT_336                       1
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER                          3:0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_1                        0
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_2                        1
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_4                        2
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_8                        3
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_16                       4
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_32                       5
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_64                       6
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_128                      7
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_3                        8
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_6                        9
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_12                       10
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_24                       11
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_48                       12
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_96                       13
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_192                      14
+#define CURRENT_SYSTEM_SDRAM_CLOCK_DIVIDER_384                      15
+
+
+
+/* USB Non Cache Access Mapping */
+#define SYSTEM_NON_CACHE			                                  0x000070
+#define SYSTEM_NON_CACHE_ADDRESS			                           13:0
+
+
+/* 502 new PLL Setting */
+
+#define SYSTEM_PLL3_CLOCK                                                               0x000074
+#define SYSTEM_PLL3_CLOCK_M                                                             7:0
+#define SYSTEM_PLL3_CLOCK_N                                                             14:8
+#define SYSTEM_PLL3_CLOCK_DIVIDE                                                15:15
+#define SYSTEM_PLL3_CLOCK_DIVIDE_1                                              0
+#define SYSTEM_PLL3_CLOCK_DIVIDE_2                                              1
+#define SYSTEM_PLL3_CLOCK_INPUT                                                 16:16
+#define SYSTEM_PLL3_CLOCK_INPUT_CRYSTAL                                 0
+#define SYSTEM_PLL3_CLOCK_INPUT_TEST                                    1
+#define SYSTEM_PLL3_CLOCK_POWER                                                 17:17
+#define SYSTEM_PLL3_CLOCK_POWER_OFF                                             0
+#define SYSTEM_PLL3_CLOCK_POWER_ON                                              1
+
+
+
+#define CURRENT_POWER_PLLCLOCK								0x000074
+#define CURRENT_POWER_PLLCLOCK_TEST_OUTPUT            		20:20
+#define CURRENT_POWER_PLLCLOCK_TEST_OUTPUT_ENABLE			1
+#define CURRENT_POWER_PLLCLOCK_TEST_OUTPUT_DISABLE      	0
+#define CURRENT_POWER_PLLCLOCK_TESTMODE						19:18
+#define CURRENT_POWER_PLLCLOCK_TESTMODE_ENABLE             	1
+#define CURRENT_POWER_PLLCLOCK_TESTMODE_DISABLE            	0
+#define CURRENT_POWER_PLLCLOCK_POWER					  	17:17
+#define CURRENT_POWER_PLLCLOCK_POWER_OFF				   	0
+#define CURRENT_POWER_PLLCLOCK_POWER_ON				     	1
+#define CURRENT_POWER_PLLCLOCK_INPUT_SELECT		            16:16
+#define CURRENT_POWER_PLLCLOCK_INPUT_SELECT_TEST	        1
+#define CURRENT_POWER_PLLCLOCK_INPUT_SELECT_CRYSTAL		    0
+#define CURRENT_POWER_PLLCLOCK_DIVIDEBY2                    15:15
+#define CURRENT_POWER_PLLCLOCK_DIVIDE_N                     14:8
+#define CURRENT_POWER_PLLCLOCK_MULTIPLE_M                   7:0
+
+
+/*****************************************************************************\
+ *                              GPIO / PWM / I2C                             *
+\*****************************************************************************/
+
+/* GPIO[31:0] Data */
+#define GPIO_DATA_LOW                                               0x010000
+#define GPIO_DATA_LOW_LOW                                           0
+#define GPIO_DATA_LOW_HIGH                                          1
+#define GPIO_DATA_LOW_0                                             0:0
+#define GPIO_DATA_LOW_0_LOW                                         0
+#define GPIO_DATA_LOW_0_HIGH                                        1
+#define GPIO_DATA_LOW_1                                             1:1
+#define GPIO_DATA_LOW_1_LOW                                         0
+#define GPIO_DATA_LOW_1_HIGH                                        1
+#define GPIO_DATA_LOW_2                                             2:2
+#define GPIO_DATA_LOW_2_LOW                                         0
+#define GPIO_DATA_LOW_2_HIGH                                        1
+#define GPIO_DATA_LOW_3                                             3:3
+#define GPIO_DATA_LOW_3_LOW                                         0
+#define GPIO_DATA_LOW_3_HIGH                                        1
+#define GPIO_DATA_LOW_4                                             4:4
+#define GPIO_DATA_LOW_4_LOW                                         0
+#define GPIO_DATA_LOW_4_HIGH                                        1
+#define GPIO_DATA_LOW_5                                             5:5
+#define GPIO_DATA_LOW_5_LOW                                         0
+#define GPIO_DATA_LOW_5_HIGH                                        1
+#define GPIO_DATA_LOW_6                                             6:6
+#define GPIO_DATA_LOW_6_LOW                                         0
+#define GPIO_DATA_LOW_6_HIGH                                        1
+#define GPIO_DATA_LOW_7                                             7:7
+#define GPIO_DATA_LOW_7_LOW                                         0
+#define GPIO_DATA_LOW_7_HIGH                                        1
+#define GPIO_DATA_LOW_8                                             8:8
+#define GPIO_DATA_LOW_8_LOW                                         0
+#define GPIO_DATA_LOW_8_HIGH                                        1
+#define GPIO_DATA_LOW_9                                             9:9
+#define GPIO_DATA_LOW_9_LOW                                         0
+#define GPIO_DATA_LOW_9_HIGH                                        1
+#define GPIO_DATA_LOW_10                                            10:10
+#define GPIO_DATA_LOW_10_LOW                                        0
+#define GPIO_DATA_LOW_10_HIGH                                       1
+#define GPIO_DATA_LOW_11                                            11:11
+#define GPIO_DATA_LOW_11_LOW                                        0
+#define GPIO_DATA_LOW_11_HIGH                                       1
+#define GPIO_DATA_LOW_12                                            12:12
+#define GPIO_DATA_LOW_12_LOW                                        0
+#define GPIO_DATA_LOW_12_HIGH                                       1
+#define GPIO_DATA_LOW_13                                            13:13
+#define GPIO_DATA_LOW_13_LOW                                        0
+#define GPIO_DATA_LOW_13_HIGH                                       1
+#define GPIO_DATA_LOW_14                                            14:14
+#define GPIO_DATA_LOW_14_LOW                                        0
+#define GPIO_DATA_LOW_14_HIGH                                       1
+#define GPIO_DATA_LOW_15                                            15:15
+#define GPIO_DATA_LOW_15_LOW                                        0
+#define GPIO_DATA_LOW_15_HIGH                                       1
+#define GPIO_DATA_LOW_16                                            16:16
+#define GPIO_DATA_LOW_16_LOW                                        0
+#define GPIO_DATA_LOW_16_HIGH                                       1
+#define GPIO_DATA_LOW_17                                            17:17
+#define GPIO_DATA_LOW_17_LOW                                        0
+#define GPIO_DATA_LOW_17_HIGH                                       1
+#define GPIO_DATA_LOW_18                                            18:18
+#define GPIO_DATA_LOW_18_LOW                                        0
+#define GPIO_DATA_LOW_18_HIGH                                       1
+#define GPIO_DATA_LOW_19                                            19:19
+#define GPIO_DATA_LOW_19_LOW                                        0
+#define GPIO_DATA_LOW_19_HIGH                                       1
+#define GPIO_DATA_LOW_20                                            20:20
+#define GPIO_DATA_LOW_20_LOW                                        0
+#define GPIO_DATA_LOW_20_HIGH                                       1
+#define GPIO_DATA_LOW_21                                            21:21
+#define GPIO_DATA_LOW_21_LOW                                        0
+#define GPIO_DATA_LOW_21_HIGH                                       1
+#define GPIO_DATA_LOW_22                                            22:22
+#define GPIO_DATA_LOW_22_LOW                                        0
+#define GPIO_DATA_LOW_22_HIGH                                       1
+#define GPIO_DATA_LOW_23                                            23:23
+#define GPIO_DATA_LOW_23_LOW                                        0
+#define GPIO_DATA_LOW_23_HIGH                                       1
+#define GPIO_DATA_LOW_24                                            24:24
+#define GPIO_DATA_LOW_24_LOW                                        0
+#define GPIO_DATA_LOW_24_HIGH                                       1
+#define GPIO_DATA_LOW_25                                            25:25
+#define GPIO_DATA_LOW_25_LOW                                        0
+#define GPIO_DATA_LOW_25_HIGH                                       1
+#define GPIO_DATA_LOW_26                                            26:26
+#define GPIO_DATA_LOW_26_LOW                                        0
+#define GPIO_DATA_LOW_26_HIGH                                       1
+#define GPIO_DATA_LOW_27                                            27:27
+#define GPIO_DATA_LOW_27_LOW                                        0
+#define GPIO_DATA_LOW_27_HIGH                                       1
+#define GPIO_DATA_LOW_28                                            28:28
+#define GPIO_DATA_LOW_28_LOW                                        0
+#define GPIO_DATA_LOW_28_HIGH                                       1
+#define GPIO_DATA_LOW_29                                            29:29
+#define GPIO_DATA_LOW_29_LOW                                        0
+#define GPIO_DATA_LOW_29_HIGH                                       1
+#define GPIO_DATA_LOW_30                                            30:30
+#define GPIO_DATA_LOW_30_LOW                                        0
+#define GPIO_DATA_LOW_30_HIGH                                       1
+#define GPIO_DATA_LOW_31                                            31:31
+#define GPIO_DATA_LOW_31_LOW                                        0
+#define GPIO_DATA_LOW_31_HIGH                                       1
+
+/* GPIO[63:32] Data */
+#define GPIO_DATA_HIGH                                              0x010004
+#define GPIO_DATA_HIGH_LOW                                          0
+#define GPIO_DATA_HIGH_HIGH                                         1
+#define GPIO_DATA_HIGH_32                                           0:0
+#define GPIO_DATA_HIGH_32_LOW                                       0
+#define GPIO_DATA_HIGH_32_HIGH                                      1
+#define GPIO_DATA_HIGH_33                                           1:1
+#define GPIO_DATA_HIGH_33_LOW                                       0
+#define GPIO_DATA_HIGH_33_HIGH                                      1
+#define GPIO_DATA_HIGH_34                                           2:2
+#define GPIO_DATA_HIGH_34_LOW                                       0
+#define GPIO_DATA_HIGH_34_HIGH                                      1
+#define GPIO_DATA_HIGH_35                                           3:3
+#define GPIO_DATA_HIGH_35_LOW                                       0
+#define GPIO_DATA_HIGH_35_HIGH                                      1
+#define GPIO_DATA_HIGH_36                                           4:4
+#define GPIO_DATA_HIGH_36_LOW                                       0
+#define GPIO_DATA_HIGH_36_HIGH                                      1
+#define GPIO_DATA_HIGH_37                                           5:5
+#define GPIO_DATA_HIGH_37_LOW                                       0
+#define GPIO_DATA_HIGH_37_HIGH                                      1
+#define GPIO_DATA_HIGH_38                                           6:6
+#define GPIO_DATA_HIGH_38_LOW                                       0
+#define GPIO_DATA_HIGH_38_HIGH                                      1
+#define GPIO_DATA_HIGH_39                                           7:7
+#define GPIO_DATA_HIGH_39_LOW                                       0
+#define GPIO_DATA_HIGH_39_HIGH                                      1
+#define GPIO_DATA_HIGH_40                                           8:8
+#define GPIO_DATA_HIGH_40_LOW                                       0
+#define GPIO_DATA_HIGH_40_HIGH                                      1
+#define GPIO_DATA_HIGH_41                                           9:9
+#define GPIO_DATA_HIGH_41_LOW                                       0
+#define GPIO_DATA_HIGH_41_HIGH                                      1
+#define GPIO_DATA_HIGH_42                                           10:10
+#define GPIO_DATA_HIGH_42_LOW                                       0
+#define GPIO_DATA_HIGH_42_HIGH                                      1
+#define GPIO_DATA_HIGH_43                                           11:11
+#define GPIO_DATA_HIGH_43_LOW                                       0
+#define GPIO_DATA_HIGH_43_HIGH                                      1
+#define GPIO_DATA_HIGH_44                                           12:12
+#define GPIO_DATA_HIGH_44_LOW                                       0
+#define GPIO_DATA_HIGH_44_HIGH                                      1
+#define GPIO_DATA_HIGH_45                                           13:13
+#define GPIO_DATA_HIGH_45_LOW                                       0
+#define GPIO_DATA_HIGH_45_HIGH                                      1
+#define GPIO_DATA_HIGH_46                                           14:14
+#define GPIO_DATA_HIGH_46_LOW                                       0
+#define GPIO_DATA_HIGH_46_HIGH                                      1
+#define GPIO_DATA_HIGH_47                                           15:15
+#define GPIO_DATA_HIGH_47_LOW                                       0
+#define GPIO_DATA_HIGH_47_HIGH                                      1
+#define GPIO_DATA_HIGH_48                                           16:16
+#define GPIO_DATA_HIGH_48_LOW                                       0
+#define GPIO_DATA_HIGH_48_HIGH                                      1
+#define GPIO_DATA_HIGH_49                                           17:17
+#define GPIO_DATA_HIGH_49_LOW                                       0
+#define GPIO_DATA_HIGH_49_HIGH                                      1
+#define GPIO_DATA_HIGH_50                                           18:18
+#define GPIO_DATA_HIGH_50_LOW                                       0
+#define GPIO_DATA_HIGH_50_HIGH                                      1
+#define GPIO_DATA_HIGH_51                                           19:19
+#define GPIO_DATA_HIGH_51_LOW                                       0
+#define GPIO_DATA_HIGH_51_HIGH                                      1
+#define GPIO_DATA_HIGH_52                                           20:20
+#define GPIO_DATA_HIGH_52_LOW                                       0
+#define GPIO_DATA_HIGH_52_HIGH                                      1
+#define GPIO_DATA_HIGH_53                                           21:21
+#define GPIO_DATA_HIGH_53_LOW                                       0
+#define GPIO_DATA_HIGH_53_HIGH                                      1
+#define GPIO_DATA_HIGH_54                                           22:22
+#define GPIO_DATA_HIGH_54_LOW                                       0
+#define GPIO_DATA_HIGH_54_HIGH                                      1
+#define GPIO_DATA_HIGH_55                                           23:23
+#define GPIO_DATA_HIGH_55_LOW                                       0
+#define GPIO_DATA_HIGH_55_HIGH                                      1
+#define GPIO_DATA_HIGH_56                                           24:24
+#define GPIO_DATA_HIGH_56_LOW                                       0
+#define GPIO_DATA_HIGH_56_HIGH                                      1
+#define GPIO_DATA_HIGH_57                                           25:25
+#define GPIO_DATA_HIGH_57_LOW                                       0
+#define GPIO_DATA_HIGH_57_HIGH                                      1
+#define GPIO_DATA_HIGH_58                                           26:26
+#define GPIO_DATA_HIGH_58_LOW                                       0
+#define GPIO_DATA_HIGH_58_HIGH                                      1
+#define GPIO_DATA_HIGH_59                                           27:27
+#define GPIO_DATA_HIGH_59_LOW                                       0
+#define GPIO_DATA_HIGH_59_HIGH                                      1
+#define GPIO_DATA_HIGH_60                                           28:28
+#define GPIO_DATA_HIGH_60_LOW                                       0
+#define GPIO_DATA_HIGH_60_HIGH                                      1
+#define GPIO_DATA_HIGH_61                                           29:29
+#define GPIO_DATA_HIGH_61_LOW                                       0
+#define GPIO_DATA_HIGH_61_HIGH                                      1
+#define GPIO_DATA_HIGH_62                                           30:30
+#define GPIO_DATA_HIGH_62_LOW                                       0
+#define GPIO_DATA_HIGH_62_HIGH                                      1
+#define GPIO_DATA_HIGH_63                                           31:31
+#define GPIO_DATA_HIGH_63_LOW                                       0
+#define GPIO_DATA_HIGH_63_HIGH                                      1
+
+/* GPIO[31:0] Data Direction */
+#define GPIO_DATA_DIRECTION_LOW                         0x010008
+#define GPIO_DATA_DIRECTION_LOW_31                      31:31
+#define GPIO_DATA_DIRECTION_LOW_31_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_31_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_30                      30:30
+#define GPIO_DATA_DIRECTION_LOW_30_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_30_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_29                      29:29
+#define GPIO_DATA_DIRECTION_LOW_29_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_29_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_28                      28:28
+#define GPIO_DATA_DIRECTION_LOW_28_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_28_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_27                      27:27
+#define GPIO_DATA_DIRECTION_LOW_27_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_27_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_26                      26:26
+#define GPIO_DATA_DIRECTION_LOW_26_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_26_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_25                      25:25
+#define GPIO_DATA_DIRECTION_LOW_25_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_25_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_24                      24:24
+#define GPIO_DATA_DIRECTION_LOW_24_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_24_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_23                      23:23
+#define GPIO_DATA_DIRECTION_LOW_23_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_23_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_22                      22:22
+#define GPIO_DATA_DIRECTION_LOW_22_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_22_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_21                      21:21
+#define GPIO_DATA_DIRECTION_LOW_21_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_21_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_20                      20:20
+#define GPIO_DATA_DIRECTION_LOW_20_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_20_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_19                      19:19
+#define GPIO_DATA_DIRECTION_LOW_19_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_19_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_18                      18:18
+#define GPIO_DATA_DIRECTION_LOW_18_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_18_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_17                      17:17
+#define GPIO_DATA_DIRECTION_LOW_17_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_17_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_16                      16:16
+#define GPIO_DATA_DIRECTION_LOW_16_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_16_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_15                      15:15
+#define GPIO_DATA_DIRECTION_LOW_15_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_15_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_14                      14:14
+#define GPIO_DATA_DIRECTION_LOW_14_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_14_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_13                      13:13
+#define GPIO_DATA_DIRECTION_LOW_13_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_13_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_12                      12:12
+#define GPIO_DATA_DIRECTION_LOW_12_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_12_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_11                      11:11
+#define GPIO_DATA_DIRECTION_LOW_11_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_11_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_10                      10:10
+#define GPIO_DATA_DIRECTION_LOW_10_INPUT                0
+#define GPIO_DATA_DIRECTION_LOW_10_OUTPUT               1
+#define GPIO_DATA_DIRECTION_LOW_9                       9:9
+#define GPIO_DATA_DIRECTION_LOW_9_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_9_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_8                       8:8
+#define GPIO_DATA_DIRECTION_LOW_8_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_8_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_7                       7:7
+#define GPIO_DATA_DIRECTION_LOW_7_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_7_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_6                       6:6
+#define GPIO_DATA_DIRECTION_LOW_6_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_6_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_5                       5:5
+#define GPIO_DATA_DIRECTION_LOW_5_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_5_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_4                       4:4
+#define GPIO_DATA_DIRECTION_LOW_4_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_4_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_3                       3:3
+#define GPIO_DATA_DIRECTION_LOW_3_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_3_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_2                       2:2
+#define GPIO_DATA_DIRECTION_LOW_2_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_2_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_1                       131
+#define GPIO_DATA_DIRECTION_LOW_1_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_1_OUTPUT                1
+#define GPIO_DATA_DIRECTION_LOW_0                       0:0
+#define GPIO_DATA_DIRECTION_LOW_0_INPUT                 0
+#define GPIO_DATA_DIRECTION_LOW_0_OUTPUT                1
+
+/* GPIO[63:32] Data Direction */
+#define GPIO_DATA_DIRECTION_HIGH                        0x01000C
+#define GPIO_DATA_DIRECTION_HIGH_63                     31:31
+#define GPIO_DATA_DIRECTION_HIGH_63_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_63_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_62                     30:30
+#define GPIO_DATA_DIRECTION_HIGH_62_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_62_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_61                     29:29
+#define GPIO_DATA_DIRECTION_HIGH_61_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_61_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_60                     28:28
+#define GPIO_DATA_DIRECTION_HIGH_60_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_60_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_59                     27:27
+#define GPIO_DATA_DIRECTION_HIGH_59_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_59_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_58                     26:26
+#define GPIO_DATA_DIRECTION_HIGH_58_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_58_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_57                     25:25
+#define GPIO_DATA_DIRECTION_HIGH_57_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_57_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_56                     24:24
+#define GPIO_DATA_DIRECTION_HIGH_56_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_56_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_55                     23:23
+#define GPIO_DATA_DIRECTION_HIGH_55_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_55_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_54                     22:22
+#define GPIO_DATA_DIRECTION_HIGH_54_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_54_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_53                     21:21
+#define GPIO_DATA_DIRECTION_HIGH_53_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_53_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_52                     20:20
+#define GPIO_DATA_DIRECTION_HIGH_52_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_52_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_51                     19:19
+#define GPIO_DATA_DIRECTION_HIGH_51_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_51_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_50                     18:18
+#define GPIO_DATA_DIRECTION_HIGH_50_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_50_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_49                     17:17
+#define GPIO_DATA_DIRECTION_HIGH_49_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_49_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_48                     16:16
+#define GPIO_DATA_DIRECTION_HIGH_48_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_48_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_47                     15:15
+#define GPIO_DATA_DIRECTION_HIGH_47_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_47_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_46                     14:14
+#define GPIO_DATA_DIRECTION_HIGH_46_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_46_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_45                     13:13
+#define GPIO_DATA_DIRECTION_HIGH_45_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_45_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_44                     12:12
+#define GPIO_DATA_DIRECTION_HIGH_44_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_44_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_43                     11:11
+#define GPIO_DATA_DIRECTION_HIGH_43_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_43_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_42                     10:10
+#define GPIO_DATA_DIRECTION_HIGH_42_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_42_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_41                     9:9
+#define GPIO_DATA_DIRECTION_HIGH_41_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_41_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_40                     8:8
+#define GPIO_DATA_DIRECTION_HIGH_40_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_40_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_39                     7:7
+#define GPIO_DATA_DIRECTION_HIGH_39_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_39_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_38                     6:6
+#define GPIO_DATA_DIRECTION_HIGH_38_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_38_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_37                     5:5
+#define GPIO_DATA_DIRECTION_HIGH_37_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_37_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_36                     4:4
+#define GPIO_DATA_DIRECTION_HIGH_36_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_36_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_35                     3:3
+#define GPIO_DATA_DIRECTION_HIGH_35_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_35_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_34                     2:2
+#define GPIO_DATA_DIRECTION_HIGH_34_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_34_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_33                     1:1
+#define GPIO_DATA_DIRECTION_HIGH_33_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_33_OUTPUT              1
+#define GPIO_DATA_DIRECTION_HIGH_32                     0:0
+#define GPIO_DATA_DIRECTION_HIGH_32_INPUT               0
+#define GPIO_DATA_DIRECTION_HIGH_32_OUTPUT              1
+
+/* GPIO Interrupt Setup */
+#define GPIO_INTERRUPT_SETUP                                        0x010010
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54                             22:22
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_54_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53                             21:21
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_53_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52                             20:20
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_52_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51                             19:19
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_51_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50                             18:18
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_50_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49                             17:17
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_49_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48                             16:16
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48_EDGE                        0
+#define GPIO_INTERRUPT_SETUP_TRIGGER_48_LEVEL                       1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54                              14:14
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_54_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53                              13:13
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_53_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52                              12:12
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_52_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51                              11:11
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_51_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50                              10:10
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_50_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49                              9:9
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_49_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48                              8:8
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48_LOW_FALLING_EDGE             0
+#define GPIO_INTERRUPT_SETUP_ACTIVE_48_HIGH_RISING_EDGE             1
+#define GPIO_INTERRUPT_SETUP_ENABLE_54                              6:6
+#define GPIO_INTERRUPT_SETUP_ENABLE_54_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_54_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_53                              5:5
+#define GPIO_INTERRUPT_SETUP_ENABLE_53_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_53_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_52                              4:4
+#define GPIO_INTERRUPT_SETUP_ENABLE_52_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_52_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_51                              3:3
+#define GPIO_INTERRUPT_SETUP_ENABLE_51_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_51_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_50                              2:2
+#define GPIO_INTERRUPT_SETUP_ENABLE_50_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_50_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_49                              1:1
+#define GPIO_INTERRUPT_SETUP_ENABLE_49_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_49_INTERRUPT                    1
+#define GPIO_INTERRUPT_SETUP_ENABLE_48                              0:0
+#define GPIO_INTERRUPT_SETUP_ENABLE_48_INPUT_OUTPUT                 0
+#define GPIO_INTERRUPT_SETUP_ENABLE_48_INTERRUPT                    1
+
+/* GPIO Interrupt Status & Reset */
+#define GPIO_INTERRUPT_STATUS                                       0x010014
+#define GPIO_INTERRUPT_STATUS_54                                    22:22
+#define GPIO_INTERRUPT_STATUS_54_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_54_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_54_RESET                              1
+#define GPIO_INTERRUPT_STATUS_53                                    21:21
+#define GPIO_INTERRUPT_STATUS_53_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_53_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_53_RESET                              1
+#define GPIO_INTERRUPT_STATUS_52                                    20:20
+#define GPIO_INTERRUPT_STATUS_52_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_52_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_52_RESET                              1
+#define GPIO_INTERRUPT_STATUS_51                                    19:19
+#define GPIO_INTERRUPT_STATUS_51_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_51_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_51_RESET                              1
+#define GPIO_INTERRUPT_STATUS_50                                    18:18
+#define GPIO_INTERRUPT_STATUS_50_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_50_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_50_RESET                              1
+#define GPIO_INTERRUPT_STATUS_49                                    17:17
+#define GPIO_INTERRUPT_STATUS_49_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_49_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_49_RESET                              1
+#define GPIO_INTERRUPT_STATUS_48                                    16:16
+#define GPIO_INTERRUPT_STATUS_48_NOT_ACTIVE                         0
+#define GPIO_INTERRUPT_STATUS_48_ACTIVE                             1
+#define GPIO_INTERRUPT_STATUS_48_RESET                              1
+
+/* PWM 0 */
+#define PWM0                                                        0x010020
+#define PWM0_HIGH_COUNTER                                           31:20
+#define PWM0_LOW_COUNTER                                            19:8
+#define PWM0_CLOCK_DIVIDE                                           7:4
+#define PWM0_CLOCK_DIVIDE_1                                         0
+#define PWM0_CLOCK_DIVIDE_2                                         1
+#define PWM0_CLOCK_DIVIDE_4                                         2
+#define PWM0_CLOCK_DIVIDE_8                                         3
+#define PWM0_CLOCK_DIVIDE_16                                        4
+#define PWM0_CLOCK_DIVIDE_32                                        5
+#define PWM0_CLOCK_DIVIDE_64                                        6
+#define PWM0_CLOCK_DIVIDE_128                                       7
+#define PWM0_CLOCK_DIVIDE_256                                       8
+#define PWM0_CLOCK_DIVIDE_512                                       9
+#define PWM0_CLOCK_DIVIDE_1024                                      10
+#define PWM0_CLOCK_DIVIDE_2048                                      11
+#define PWM0_CLOCK_DIVIDE_4096                                      12
+#define PWM0_CLOCK_DIVIDE_8192                                      13
+#define PWM0_CLOCK_DIVIDE_16384                                     14
+#define PWM0_CLOCK_DIVIDE_32768                                     15
+#define PWM0_INTERRUPT_STATUS                                       3:3
+#define PWM0_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM0_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM0_INTERRUPT_CONTROL                                      2:2
+#define PWM0_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM0_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM0_CONTROL                                                0:0
+#define PWM0_CONTROL_DISABLE                                        0
+#define PWM0_CONTROL_ENABLE                                         1
+
+/* PWM 1 */
+#define PWM1                                                        0x010024
+#define PWM1_HIGH_COUNTER                                           31:20
+#define PWM1_LOW_COUNTER                                            19:8
+#define PWM1_CLOCK_DIVIDE                                           7:4
+#define PWM1_CLOCK_DIVIDE_1                                         0
+#define PWM1_CLOCK_DIVIDE_2                                         1
+#define PWM1_CLOCK_DIVIDE_4                                         2
+#define PWM1_CLOCK_DIVIDE_8                                         3
+#define PWM1_CLOCK_DIVIDE_16                                        4
+#define PWM1_CLOCK_DIVIDE_32                                        5
+#define PWM1_CLOCK_DIVIDE_64                                        6
+#define PWM1_CLOCK_DIVIDE_128                                       7
+#define PWM1_CLOCK_DIVIDE_256                                       8
+#define PWM1_CLOCK_DIVIDE_512                                       9
+#define PWM1_CLOCK_DIVIDE_1024                                      10
+#define PWM1_CLOCK_DIVIDE_2048                                      11
+#define PWM1_CLOCK_DIVIDE_4096                                      12
+#define PWM1_CLOCK_DIVIDE_8192                                      13
+#define PWM1_CLOCK_DIVIDE_16384                                     14
+#define PWM1_CLOCK_DIVIDE_32768                                     15
+#define PWM1_INTERRUPT_STATUS                                       3:3
+#define PWM1_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM1_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM1_INTERRUPT_CONTROL                                      2:2
+#define PWM1_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM1_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM1_CONTROL                                                0:0
+#define PWM1_CONTROL_DISABLE                                        0
+#define PWM1_CONTROL_ENABLE                                         1
+
+/* PWM 2 */
+#define PWM2                                                        0x010028
+#define PWM2_HIGH_COUNTER                                           31:20
+#define PWM2_LOW_COUNTER                                            19:8
+#define PWM2_CLOCK_DIVIDE                                           7:4
+#define PWM2_CLOCK_DIVIDE_1                                         0
+#define PWM2_CLOCK_DIVIDE_2                                         1
+#define PWM2_CLOCK_DIVIDE_4                                         2
+#define PWM2_CLOCK_DIVIDE_8                                         3
+#define PWM2_CLOCK_DIVIDE_16                                        4
+#define PWM2_CLOCK_DIVIDE_32                                        5
+#define PWM2_CLOCK_DIVIDE_64                                        6
+#define PWM2_CLOCK_DIVIDE_128                                       7
+#define PWM2_CLOCK_DIVIDE_256                                       8
+#define PWM2_CLOCK_DIVIDE_512                                       9
+#define PWM2_CLOCK_DIVIDE_1024                                      10
+#define PWM2_CLOCK_DIVIDE_2048                                      11
+#define PWM2_CLOCK_DIVIDE_4096                                      12
+#define PWM2_CLOCK_DIVIDE_8192                                      13
+#define PWM2_CLOCK_DIVIDE_16384                                     14
+#define PWM2_CLOCK_DIVIDE_32768                                     15
+#define PWM2_INTERRUPT_STATUS                                       3:3
+#define PWM2_INTERRUPT_STATUS_NOT_ACTIVE                            0
+#define PWM2_INTERRUPT_STATUS_ACTIVE                                1
+#define PWM2_INTERRUPT_CONTROL                                      2:2
+#define PWM2_INTERRUPT_CONTROL_DISABLE                              0
+#define PWM2_INTERRUPT_CONTROL_ENABLE                               1
+#define PWM2_CONTROL                                                0:0
+#define PWM2_CONTROL_DISABLE                                        0
+#define PWM2_CONTROL_ENABLE                                         1
+
+/* I2C Byte Count */
+#define I2C_BYTE_COUNT                                              0x010040
+#define I2C_BYTE_COUNT_COUNT                                        3:0
+
+/* I2C Control */
+#define I2C_CONTROL                                                 0x010041
+#define I2C_CONTROL_REPEAT                                          6:6
+#define I2C_CONTROL_REPEAT_DISABLE                                  0
+#define I2C_CONTROL_REPEAT_ENABLE                                   1
+#define I2C_CONTROL_INTERRUPT                                       5:5
+#define I2C_CONTROL_INTERRUPT_NOT_ACKNOWLEDGE                       0
+#define I2C_CONTROL_INTERRUPT_ACKNOWLEDGE                           1
+#define I2C_CONTROL_INTERRUPT_CONTROL                               4:4
+#define I2C_CONTROL_INTERRUPT_CONTROL_ENABLE                        0
+#define I2C_CONTROL_INTERRUPT_CONTROL_DISABLE                       1
+#define I2C_CONTROL_STATUS                                          2:2
+#define I2C_CONTROL_STATUS_STOP                                     0
+#define I2C_CONTROL_STATUS_START                                    1
+#define I2C_CONTROL_MODE                                            1:1
+#define I2C_CONTROL_MODE_STANDARD                                   0
+#define I2C_CONTROL_MODE_FAST                                       1
+#define I2C_CONTROL_CONTROL                                         0:0
+#define I2C_CONTROL_CONTROL_DISABLE                                 0
+#define I2C_CONTROL_CONTROL_ENABLE                                  1
+
+/* I2C Status & Reset */
+#define I2C_STATUS                                                  0x010042
+#define I2C_STATUS_TRANSFER                                         3:3
+#define I2C_STATUS_TRANSFER_IN_PROGRESS                             0
+#define I2C_STATUS_TRANSFER_COMPLETED                               1
+#define I2C_STATUS_ERROR                                            2:2
+#define I2C_STATUS_ERROR_NORMAL                                     0
+#define I2C_STATUS_ERROR_BUS_ERROR                                  1
+#define I2C_STATUS_ERROR_CLEAR                                      0
+#define I2C_STATUS_ACKNOWLEDGE                                      1:1
+#define I2C_STATUS_ACKNOWLEDGE_NOT_RECEIVED                         0
+#define I2C_STATUS_ACKNOWLEDGE_RECEIVED                             1
+#define I2C_STATUS_BUSY                                             0:0
+#define I2C_STATUS_BUSY_IDLE                                        0
+#define I2C_STATUS_BUSY_BUSY                                        1
+
+/* I2C Slave Address */
+#define I2C_SLAVE_ADDRESS                                           0x010043
+#define I2C_SLAVE_ADDRESS_ADDRESS                                   7:1
+#define I2C_SLAVE_ADDRESS_ACCESS                                    0:0
+#define I2C_SLAVE_ADDRESS_ACCESS_WRITE                              0
+#define I2C_SLAVE_ADDRESS_ACCESS_READ                               1
+
+/* I2C Data */
+#define I2C_DATA_0                                                  0x010044
+#define I2C_DATA_1                                                  0x010045
+#define I2C_DATA_2                                                  0x010046
+#define I2C_DATA_3                                                  0x010047
+#define I2C_DATA_4                                                  0x010048
+#define I2C_DATA_5                                                  0x010049
+#define I2C_DATA_6                                                  0x01004A
+#define I2C_DATA_7                                                  0x01004B
+#define I2C_DATA_8                                                  0x01004C
+#define I2C_DATA_9                                                  0x01004D
+#define I2C_DATA_10                                                 0x01004E
+#define I2C_DATA_11                                                 0x01004F
+#define I2C_DATA_12                                                 0x010050
+#define I2C_DATA_13                                                 0x010051
+#define I2C_DATA_14                                                 0x010052
+#define I2C_DATA_15                                                 0x010053
+
+
+/*****************************************************************************\
+ *                                    SSP                                    *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                                UART / IRDA                                *
+\*****************************************************************************/
+/*****************************************************************************\
+ *                                                                           *
+ *     REGISTER DESCRIPTION                                                  *
+ *     |========|======|================================|==============|     *
+ *     | Offset | DLAB | Register Name                  |   Comment    |     *
+ *     |========|======|================================|==============|     *
+ *     |  0x00  |  0   | RX Buffer Register             |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x00  |  0   | TX Holding Register            |      WO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x04  |  0   | Interrupt Enable Register      |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  X   | Interrupt Identification Reg.  |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  X   | FIFO Control Register          |      WO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x0C  |  X   | Line Control Register          |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x10  |  X   | Modem Control Register         |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x14  |  X   | Line Status Register           |      RO      |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x18  |  X   | Modem Status Register          | Partially RO |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x1C  |  X   | Scratch Register               |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x00  |  1   | Divisor Latch (LSB)            |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x04  |  1   | Divisor Latch (MSB)            |      R/W     |     *
+ *     |--------|------|--------------------------------|--------------|     *
+ *     |  0x08  |  1   | Enhanced Feature Register      |              |     *
+ *     |--------|------|--------------------------------|              |     *
+ *     |  0x0C  |  1   | XON1 Register                  |      R/W     |     *
+ *     |--------|------|--------------------------------|     Only     |     *
+ *     |  0x10  |  1   | XON2 Register                  |    present   |     *
+ *     |--------|------|--------------------------------|     when     |     *
+ *     |  0x14  |  1   | XOFF1 Register                 |  LCR = 0xBF  |     *
+ *     |--------|------|--------------------------------|              |     *
+ *     |  0x18  |  1   | XOFF2 Register                 |              |     *
+ *     |========|======|================================|==============|     *
+ *                                                                           *
+ *     NOTES:                                                                *
+ *       X   = Don't Care                                                    *
+ *       RO  = Read Only                                                     *
+ *       WO  = Write Only                                                    *
+ *       R/W = Read/Write                                                    *
+ *                                                                           *
+\*****************************************************************************/
+
+
+/*****************************************************************************\
+ * UART 0                                                                    *
+\*****************************************************************************/
+
+/* UART 0 when DLAB = 0 (normal mode), LCR != 0xBF */
+
+#define UART_0_RECEIVE_BUFFER                           0x030000
+#define	UART_0_RECEIVE_BUFFER_DATA						7:0
+
+#define UART_0_TRANSMIT									0x030000
+#define UART_0_TRANSMIT_DATA							7:0
+
+#define UART_0_INTERRUPT                                0x030004
+#define UART_0_INTERRUPT_CTS                            7:7
+#define UART_0_INTERRUPT_CTS_DISABLE                    0
+#define UART_0_INTERRUPT_CTS_ENABLE                     1
+#define UART_0_INTERRUPT_RTS                            6:6
+#define UART_0_INTERRUPT_RTS_DISABLE                    0
+#define UART_0_INTERRUPT_RTS_ENABLE                     1
+#define UART_0_INTERRUPT_XOFF                           5:5
+#define UART_0_INTERRUPT_XOFF_DISABLE                   0
+#define UART_0_INTERRUPT_XOFF_ENABLE                    1
+#define UART_0_INTERRUPT_MODEM_STATUS                   3:3
+#define UART_0_INTERRUPT_MODEM_STATUS_DISABLE           0
+#define UART_0_INTERRUPT_MODEM_STATUS_ENABLE            1
+#define UART_0_INTERRUPT_LINE_STATUS                    2:2
+#define UART_0_INTERRUPT_LINE_STATUS_DISABLE            0
+#define UART_0_INTERRUPT_LINE_STATUS_ENABLE             1
+#define UART_0_INTERRUPT_TX_EMPTY                       1:1
+#define UART_0_INTERRUPT_TX_EMPTY_DISABLE               0
+#define UART_0_INTERRUPT_TX_EMPTY_ENABLE                1
+#define UART_0_INTERRUPT_RX_BUFFER                      0:0
+#define UART_0_INTERRUPT_RX_BUFFER_DISABLE              0
+#define UART_0_INTERRUPT_RX_BUFFER_ENABLE               1
+
+
+/* UART 0 when DLAB = 1 (configuration mode), LCR != 0xBF */
+
+#define	UART_0_DIVISOR_LATCH_LSB						0x030000
+#define	UART_0_DIVISOR_LATCH_LSB_VALUE					7:0
+
+#define	UART_0_DIVISOR_LATCH_MSB						0x030004
+#define	UART_0_DIVISOR_LATCH_MSB_VALUE					7:0
+
+
+/* UART 0 when DLAB = X (don't care), LCR != 0xBF */
+
+#define UART_0_STATUS                                   0x030008
+#define UART_0_STATUS_FIFO                              7:6
+#define UART_0_STATUS_FIFO_DISABLE                      0
+#define UART_0_STATUS_FIFO_ENABLE                       3
+#define UART_0_STATUS_INTERRUPT                         5:1
+#define UART_0_STATUS_INTERRUPT_MODEM_STATUS_CHANGE     0
+#define UART_0_STATUS_INTERRUPT_TX_EMPTY                1
+#define UART_0_STATUS_INTERRUPT_RX_DATA_RECEIVED        2
+#define UART_0_STATUS_INTERRUPT_LINE_STATUS             3
+#define UART_0_STATUS_INTERRUPT_RX_CHAR_TIMEOUT         6
+#define UART_0_STATUS_INTERRUPT_XOFF_RECEIVED           8
+#define UART_0_STATUS_INTERRUPT_CTS_RTS                 16
+#define UART_0_STATUS_INTERRUPT_PENDING                 1:1
+#define UART_0_STATUS_INTERRUPT_PENDING_YES             0
+#define UART_0_STATUS_INTERRUPT_PENDING_NO              1
+
+#define UART_0_FIFO                                     0x030008
+#define UART_0_FIFO_RX_TRIGGER                          7:6
+#define UART_0_FIFO_RX_TRIGGER_DEFAULT                  0
+#define UART_0_FIFO_RX_TRIGGER_QUARTER                  1
+#define UART_0_FIFO_RX_TRIGGER_HALF                     2
+#define UART_0_FIFO_RX_TRIGGER_MINUS_2                  3
+#define UART_0_FIFO_TX_TRIGGER                          5:4
+#define UART_0_FIFO_TX_TRIGGER_DEFAULT                  0
+#define UART_0_FIFO_TX_TRIGGER_QUARTER                  1
+#define UART_0_FIFO_TX_TRIGGER_HALF                     2
+#define UART_0_FIFO_TX_TRIGGER_MINUS_2                  3
+#define UART_0_FIFO_DMA_MODE                            3:3
+#define UART_0_FIFO_DMA_MODE_ZERO                       0
+#define UART_0_FIFO_DMA_MODE_ONE                        1
+#define UART_0_FIFO_TX_CLEAR                            2:2
+#define UART_0_FIFO_TX_CLEAR_NO                         0
+#define UART_0_FIFO_TX_CLEAR_CLEAR                      1
+#define UART_0_FIFO_RX_CLEAR                            1:1
+#define UART_0_FIFO_RX_CLEAR_NO                         0
+#define UART_0_FIFO_RX_CLEAR_CLEAR                      1
+#define UART_0_FIFO_ENABLE                              0:0
+#define UART_0_FIFO_ENABLE_DISABLE                      0
+#define UART_0_FIFO_ENABLE_ENABLE                       1
+
+#define UART_0_LINE_CTRL                                0x03000C
+#define	UART_0_LINE_CTRL_ENHANCED						7:0
+#define	UART_0_LINE_CTRL_ENHANCED_ENABLE				0xBF
+#define UART_0_LINE_CTRL_DLAB                           7:7
+#define UART_0_LINE_CTRL_DLAB_RESET                     0
+#define UART_0_LINE_CTRL_DLAB_SET                       1
+#define UART_0_LINE_CTRL_LINE_BREAK                     6:6
+#define UART_0_LINE_CTRL_LINE_BREAK_RESET               0
+#define UART_0_LINE_CTRL_LINE_BREAK_SET                 1
+#define UART_0_LINE_CTRL_PARITY                         5:3
+#define UART_0_LINE_CTRL_PARITY_DISABLE                 0
+#define UART_0_LINE_CTRL_PARITY_ODD                     1
+#define UART_0_LINE_CTRL_PARITY_EVEN                    3
+#define UART_0_LINE_CTRL_PARITY_MARK                    5
+#define UART_0_LINE_CTRL_PARITY_SPACE                   7
+#define UART_0_LINE_CTRL_STOPBITS                       2:2
+#define UART_0_LINE_CTRL_STOPBITS_ONE                   0
+#define UART_0_LINE_CTRL_STOPBITS_TWO                   1
+#define UART_0_LINE_CTRL_CHARSIZE                       1:0
+#define UART_0_LINE_CTRL_CHARSIZE_5                     0
+#define UART_0_LINE_CTRL_CHARSIZE_6                     1
+#define UART_0_LINE_CTRL_CHARSIZE_7                     2
+#define UART_0_LINE_CTRL_CHARSIZE_8                     3
+
+#define UART_0_MODEM_CTRL                               0x030010
+#define UART_0_MODEM_CTRL_XOFF_STATUS                   7:7
+#define UART_0_MODEM_CTRL_XOFF_STATUS_XON               0
+#define UART_0_MODEM_CTRL_XOFF_STATUS_XOFF              1
+#define UART_0_MODEM_CTRL_INFRARED                      6:6
+#define UART_0_MODEM_CTRL_INFRARED_DISABLE              0
+#define UART_0_MODEM_CTRL_INFRARED_ENABLE               1
+#define UART_0_MODEM_CTRL_LOOPBACK                      4:4
+#define UART_0_MODEM_CTRL_LOOPBACK_DISABLE              0
+#define UART_0_MODEM_CTRL_LOOPBACK_ENABLE               1
+#define UART_0_MODEM_CTRL_OUT2                          3:3
+#define UART_0_MODEM_CTRL_OUT2_RESET                    0
+#define UART_0_MODEM_CTRL_OUT2_SET                      1
+#define UART_0_MODEM_CTRL_OUT1                          2:2
+#define UART_0_MODEM_CTRL_OUT1_RESET                    0
+#define UART_0_MODEM_CTRL_OUT1_SET                      1
+#define UART_0_MODEM_CTRL_RTS                           1:1
+#define UART_0_MODEM_CTRL_RTS_RESET                     0
+#define UART_0_MODEM_CTRL_RTS_SET                       1
+#define UART_0_MODEM_CTRL_DTR                           0:0
+#define UART_0_MODEM_CTRL_DTR_RESET                     0
+#define UART_0_MODEM_CTRL_DTR_SET                       1
+
+#define UART_0_LINE_STATUS                              0x030014
+#define UART_0_LINE_STATUS_RX_FIFO                      7:7
+#define UART_0_LINE_STATUS_RX_FIFO_NO_ERROR             0
+#define UART_0_LINE_STATUS_RX_FIFO_ERROR                1
+#define UART_0_LINE_STATUS_TRANSMITTER                  6:6
+#define UART_0_LINE_STATUS_TRANSMITTER_NOT_EMPTY        0
+#define UART_0_LINE_STATUS_TRANSMITTER_EMPTY            1
+#define UART_0_LINE_STATUS_TX_HOLDING                   5:5
+#define UART_0_LINE_STATUS_TX_HOLDING_NOT_EMPTY         0
+#define UART_0_LINE_STATUS_TX_HOLDING_EMPTY             1
+#define UART_0_LINE_STATUS_BREAK                        4:4
+#define UART_0_LINE_STATUS_BREAK_NO_BREAK               0
+#define UART_0_LINE_STATUS_BREAK_BREAK                  1
+#define UART_0_LINE_STATUS_FRAME                        3:3
+#define UART_0_LINE_STATUS_FRAME_NO_ERROR               0
+#define UART_0_LINE_STATUS_FRAME_ERROR                  1
+#define UART_0_LINE_STATUS_PARITY                       2:2
+#define UART_0_LINE_STATUS_PARITY_NO_ERROR              0
+#define UART_0_LINE_STATUS_PARITY_ERROR                 1
+#define UART_0_LINE_STATUS_OVERRUN                      1:1
+#define UART_0_LINE_STATUS_OVERRUN_NO_ERROR             0
+#define UART_0_LINE_STATUS_OVERRUN_ERROR                1
+#define UART_0_LINE_STATUS_DATA                         0:0
+#define UART_0_LINE_STATUS_DATA_NOT_READY               0
+#define UART_0_LINE_STATUS_DATA_READY                   1
+
+#define UART_0_MODEM_STATUS                             0x030018
+#define UART_0_MODEM_STATUS_DCD                         7:7
+#define UART_0_MODEM_STATUS_DCD_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_DCD_DETECTED                1
+#define UART_0_MODEM_STATUS_RI                          6:6
+#define UART_0_MODEM_STATUS_RI_NOT_DETECTED             0
+#define UART_0_MODEM_STATUS_RI_DETECTED                 1
+#define UART_0_MODEM_STATUS_DSR                         5:5
+#define UART_0_MODEM_STATUS_DSR_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_DSR_DETECTED                1
+#define UART_0_MODEM_STATUS_CTS                         4:4
+#define UART_0_MODEM_STATUS_CTS_NOT_DETECTED            0
+#define UART_0_MODEM_STATUS_CTS_DETECTED                1
+#define UART_0_MODEM_STATUS_DELTA_DCD                   3:3
+#define UART_0_MODEM_STATUS_DELTA_DCD_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_DCD_CHANGE            1
+#define UART_0_MODEM_STATUS_TRAILING_RI                 2:2
+#define UART_0_MODEM_STATUS_TRAILING_RI_NO_CHANGE       0
+#define UART_0_MODEM_STATUS_TRAILING_RI_CHANGE          1
+#define UART_0_MODEM_STATUS_DELTA_DSR                   1:1
+#define UART_0_MODEM_STATUS_DELTA_DSR_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_DSR_CHANGE            1
+#define UART_0_MODEM_STATUS_DELTA_CTS                   0:0
+#define UART_0_MODEM_STATUS_DELTA_CTS_NO_CHANGE         0
+#define UART_0_MODEM_STATUS_DELTA_CTS_CHANGE            1
+
+#define UART_0_SCRATCH                                  0x03001C
+#define	UART_0_SCRATCH_DATA								7:0
+
+
+/* UART 0 when LCR = 0xBF (DLAB = 1) (configuration mode) */
+
+#define	UART_0_FEATURE									0x030008
+#define	UART_0_FEATURE_AUTO_CTS							7:7
+#define	UART_0_FEATURE_AUTO_CTS_DISABLE					0
+#define	UART_0_FEATURE_AUTO_CTS_ENABLE					1
+#define	UART_0_FEATURE_AUTO_RTS							6:6
+#define	UART_0_FEATURE_AUTO_RTS_DISABLE					0
+#define	UART_0_FEATURE_AUTO_RTS_ENABLE					1
+#define	UART_0_FEATURE_ENHANCED							4:4
+#define	UART_0_FEATURE_ENHANCED_DISABLE					0
+#define	UART_0_FEATURE_ENHANCED_ENABLE					1
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1				3:3
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2				2:2
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_0_FEATURE_SW_TX_FLOW_CTRL_XON2_ENABLE		1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1				1:1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2				0:0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_0_FEATURE_SW_RX_FLOW_CTRL_XON2_ENABLE		1
+
+#define	UART_0_XON1_CHAR								0x030010
+#define	UART_0_XON1_CHAR_DATA							7:0
+
+#define	UART_0_XON2_CHAR								0x030014
+#define	UART_0_XON2_CHAR_DATA							7:0
+
+#define	UART_0_XOFF1_CHAR								0x030018
+#define	UART_0_XOFF1_CHAR_DATA							7:0
+
+#define	UART_0_XOFF2_CHAR								0x03001C
+#define	UART_0_XOFF2_CHAR_DATA							7:0
+
+
+/*****************************************************************************\
+ * UART 1                                                                    *
+\*****************************************************************************/
+
+/* UART 1 when DLAB = 0 (normal mode), LCR != 0xBF */
+
+#define UART_1_RECEIVE_BUFFER                           0x030020
+#define	UART_1_RECEIVE_BUFFER_DATA						7:0
+
+#define UART_1_TRANSMIT									0x030020
+#define UART_1_TRANSMIT_DATA							7:0
+
+#define UART_1_INTERRUPT                                0x030024
+#define UART_1_INTERRUPT_CTS                            7:7
+#define UART_1_INTERRUPT_CTS_DISABLE                    0
+#define UART_1_INTERRUPT_CTS_ENABLE                     1
+#define UART_1_INTERRUPT_RTS                            6:6
+#define UART_1_INTERRUPT_RTS_DISABLE                    0
+#define UART_1_INTERRUPT_RTS_ENABLE                     1
+#define UART_1_INTERRUPT_XOFF                           5:5
+#define UART_1_INTERRUPT_XOFF_DISABLE                   0
+#define UART_1_INTERRUPT_XOFF_ENABLE                    1
+#define UART_1_INTERRUPT_MODEM_STATUS                   3:3
+#define UART_1_INTERRUPT_MODEM_STATUS_DISABLE           0
+#define UART_1_INTERRUPT_MODEM_STATUS_ENABLE            1
+#define UART_1_INTERRUPT_LINE_STATUS                    2:2
+#define UART_1_INTERRUPT_LINE_STATUS_DISABLE            0
+#define UART_1_INTERRUPT_LINE_STATUS_ENABLE             1
+#define UART_1_INTERRUPT_TX_EMPTY                       1:1
+#define UART_1_INTERRUPT_TX_EMPTY_DISABLE               0
+#define UART_1_INTERRUPT_TX_EMPTY_ENABLE                1
+#define UART_1_INTERRUPT_RX_BUFFER                      0:0
+#define UART_1_INTERRUPT_RX_BUFFER_DISABLE              0
+#define UART_1_INTERRUPT_RX_BUFFER_ENABLE               1
+
+
+/* UART 0 when DLAB = 1 (configuration mode), LCR != 0xBF */
+
+#define	UART_1_DIVISOR_LATCH_LSB						0x030020
+#define	UART_1_DIVISOR_LATCH_LSB_VALUE					7:0
+
+#define	UART_1_DIVISOR_LATCH_MSB						0x030024
+#define	UART_1_DIVISOR_LATCH_MSB_VALUE					7:0
+
+
+/* UART 1 when DLAB = X (don't care), LCR != 0xBF */
+
+#define UART_1_STATUS                                   0x030028
+#define UART_1_STATUS_FIFO                              7:6
+#define UART_1_STATUS_FIFO_DISABLE                      0
+#define UART_1_STATUS_FIFO_ENABLE                       3
+#define UART_1_STATUS_INTERRUPT                         5:1
+#define UART_1_STATUS_INTERRUPT_MODEM_STATUS_CHANGE     0
+#define UART_1_STATUS_INTERRUPT_TX_EMPTY                1
+#define UART_1_STATUS_INTERRUPT_RX_DATA_RECEIVED        2
+#define UART_1_STATUS_INTERRUPT_LINE_STATUS             3
+#define UART_1_STATUS_INTERRUPT_RX_CHAR_TIMEOUT         6
+#define UART_1_STATUS_INTERRUPT_XOFF_RECEIVED           8
+#define UART_1_STATUS_INTERRUPT_CTS_RTS                 16
+#define UART_1_STATUS_INTERRUPT_PENDING                 1:1
+#define UART_1_STATUS_INTERRUPT_PENDING_YES             0
+#define UART_1_STATUS_INTERRUPT_PENDING_NO              1
+
+#define UART_1_FIFO                                     0x030028
+#define UART_1_FIFO_RX_TRIGGER                          7:6
+#define UART_1_FIFO_RX_TRIGGER_DEFAULT                  0
+#define UART_1_FIFO_RX_TRIGGER_QUARTER                  1
+#define UART_1_FIFO_RX_TRIGGER_HALF                     2
+#define UART_1_FIFO_RX_TRIGGER_MINUS_2                  3
+#define UART_1_FIFO_TX_TRIGGER                          5:4
+#define UART_1_FIFO_TX_TRIGGER_DEFAULT                  0
+#define UART_1_FIFO_TX_TRIGGER_QUARTER                  1
+#define UART_1_FIFO_TX_TRIGGER_HALF                     2
+#define UART_1_FIFO_TX_TRIGGER_MINUS_2                  3
+#define UART_1_FIFO_DMA_MODE                            3:3
+#define UART_1_FIFO_DMA_MODE_ZERO                       0
+#define UART_1_FIFO_DMA_MODE_ONE                        1
+#define UART_1_FIFO_TX_CLEAR                            2:2
+#define UART_1_FIFO_TX_CLEAR_NO                         0
+#define UART_1_FIFO_TX_CLEAR_CLEAR                      1
+#define UART_1_FIFO_RX_CLEAR                            1:1
+#define UART_1_FIFO_RX_CLEAR_NO                         0
+#define UART_1_FIFO_RX_CLEAR_CLEAR                      1
+#define UART_1_FIFO_ENABLE                              0:0
+#define UART_1_FIFO_ENABLE_DISABLE                      0
+#define UART_1_FIFO_ENABLE_ENABLE                       1
+
+#define UART_1_LINE_CTRL                                0x03002C
+#define	UART_1_LINE_CTRL_ENHANCED						7:0
+#define	UART_1_LINE_CTRL_ENHANCED_ENABLE				0xBF
+#define UART_1_LINE_CTRL_DLAB                           7:7
+#define UART_1_LINE_CTRL_DLAB_RESET                     0
+#define UART_1_LINE_CTRL_DLAB_SET                       1
+#define UART_1_LINE_CTRL_LINE_BREAK                     6:6
+#define UART_1_LINE_CTRL_LINE_BREAK_RESET               0
+#define UART_1_LINE_CTRL_LINE_BREAK_SET                 1
+#define UART_1_LINE_CTRL_PARITY                         5:3
+#define UART_1_LINE_CTRL_PARITY_DISABLE                 0
+#define UART_1_LINE_CTRL_PARITY_ODD                     1
+#define UART_1_LINE_CTRL_PARITY_EVEN                    3
+#define UART_1_LINE_CTRL_PARITY_MARK                    5
+#define UART_1_LINE_CTRL_PARITY_SPACE                   7
+#define UART_1_LINE_CTRL_STOPBITS                       2:2
+#define UART_1_LINE_CTRL_STOPBITS_ONE                   0
+#define UART_1_LINE_CTRL_STOPBITS_TWO                   1
+#define UART_1_LINE_CTRL_CHARSIZE                       1:0
+#define UART_1_LINE_CTRL_CHARSIZE_5                     0
+#define UART_1_LINE_CTRL_CHARSIZE_6                     1
+#define UART_1_LINE_CTRL_CHARSIZE_7                     2
+#define UART_1_LINE_CTRL_CHARSIZE_8                     3
+
+#define UART_1_MODEM_CTRL                               0x030030
+#define UART_1_MODEM_CTRL_XOFF_STATUS                   7:7
+#define UART_1_MODEM_CTRL_XOFF_STATUS_XON               0
+#define UART_1_MODEM_CTRL_XOFF_STATUS_XOFF              1
+#define UART_1_MODEM_CTRL_INFRARED                      6:6
+#define UART_1_MODEM_CTRL_INFRARED_DISABLE              0
+#define UART_1_MODEM_CTRL_INFRARED_ENABLE               1
+#define UART_1_MODEM_CTRL_LOOPBACK                      4:4
+#define UART_1_MODEM_CTRL_LOOPBACK_DISABLE              0
+#define UART_1_MODEM_CTRL_LOOPBACK_ENABLE               1
+#define UART_1_MODEM_CTRL_OUT2                          3:3
+#define UART_1_MODEM_CTRL_OUT2_RESET                    0
+#define UART_1_MODEM_CTRL_OUT2_SET                      1
+#define UART_1_MODEM_CTRL_OUT1                          2:2
+#define UART_1_MODEM_CTRL_OUT1_RESET                    0
+#define UART_1_MODEM_CTRL_OUT1_SET                      1
+#define UART_1_MODEM_CTRL_RTS                           1:1
+#define UART_1_MODEM_CTRL_RTS_RESET                     0
+#define UART_1_MODEM_CTRL_RTS_SET                       1
+#define UART_1_MODEM_CTRL_DTR                           0:0
+#define UART_1_MODEM_CTRL_DTR_RESET                     0
+#define UART_1_MODEM_CTRL_DTR_SET                       1
+
+#define UART_1_LINE_STATUS                              0x030034
+#define UART_1_LINE_STATUS_RX_FIFO                      7:7
+#define UART_1_LINE_STATUS_RX_FIFO_NO_ERROR             0
+#define UART_1_LINE_STATUS_RX_FIFO_ERROR                1
+#define UART_1_LINE_STATUS_TRANSMITTER                  6:6
+#define UART_1_LINE_STATUS_TRANSMITTER_NOT_EMPTY        0
+#define UART_1_LINE_STATUS_TRANSMITTER_EMPTY            1
+#define UART_1_LINE_STATUS_TX_HOLDING                   5:5
+#define UART_1_LINE_STATUS_TX_HOLDING_NOT_EMPTY         0
+#define UART_1_LINE_STATUS_TX_HOLDING_EMPTY             1
+#define UART_1_LINE_STATUS_BREAK                        4:4
+#define UART_1_LINE_STATUS_BREAK_NO_BREAK               0
+#define UART_1_LINE_STATUS_BREAK_BREAK                  1
+#define UART_1_LINE_STATUS_FRAME                        3:3
+#define UART_1_LINE_STATUS_FRAME_NO_ERROR               0
+#define UART_1_LINE_STATUS_FRAME_ERROR                  1
+#define UART_1_LINE_STATUS_PARITY                       2:2
+#define UART_1_LINE_STATUS_PARITY_NO_ERROR              0
+#define UART_1_LINE_STATUS_PARITY_ERROR                 1
+#define UART_1_LINE_STATUS_OVERRUN                      1:1
+#define UART_1_LINE_STATUS_OVERRUN_NO_ERROR             0
+#define UART_1_LINE_STATUS_OVERRUN_ERROR                1
+#define UART_1_LINE_STATUS_DATA                         0:0
+#define UART_1_LINE_STATUS_DATA_NOT_READY               0
+#define UART_1_LINE_STATUS_DATA_READY                   1
+
+#define UART_1_MODEM_STATUS                             0x030038
+#define UART_1_MODEM_STATUS_DCD                         7:7
+#define UART_1_MODEM_STATUS_DCD_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_DCD_DETECTED                1
+#define UART_1_MODEM_STATUS_RI                          6:6
+#define UART_1_MODEM_STATUS_RI_NOT_DETECTED             0
+#define UART_1_MODEM_STATUS_RI_DETECTED                 1
+#define UART_1_MODEM_STATUS_DSR                         5:5
+#define UART_1_MODEM_STATUS_DSR_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_DSR_DETECTED                1
+#define UART_1_MODEM_STATUS_CTS                         4:4
+#define UART_1_MODEM_STATUS_CTS_NOT_DETECTED            0
+#define UART_1_MODEM_STATUS_CTS_DETECTED                1
+#define UART_1_MODEM_STATUS_DELTA_DCD                   3:3
+#define UART_1_MODEM_STATUS_DELTA_DCD_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_DCD_CHANGE            1
+#define UART_1_MODEM_STATUS_TRAILING_RI                 2:2
+#define UART_1_MODEM_STATUS_TRAILING_RI_NO_CHANGE       0
+#define UART_1_MODEM_STATUS_TRAILING_RI_CHANGE          1
+#define UART_1_MODEM_STATUS_DELTA_DSR                   1:1
+#define UART_1_MODEM_STATUS_DELTA_DSR_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_DSR_CHANGE            1
+#define UART_1_MODEM_STATUS_DELTA_CTS                   0:0
+#define UART_1_MODEM_STATUS_DELTA_CTS_NO_CHANGE         0
+#define UART_1_MODEM_STATUS_DELTA_CTS_CHANGE            1
+
+#define UART_1_SCRATCH                                  0x03003C
+#define	UART_1_SCRATCH_DATA								7:0
+
+
+/* UART 1 when LCR = 0xBF (DLAB = 1) (configuration mode) */
+
+#define	UART_1_FEATURE									0x030028
+#define	UART_1_FEATURE_AUTO_CTS							7:7
+#define	UART_1_FEATURE_AUTO_CTS_DISABLE					0
+#define	UART_1_FEATURE_AUTO_CTS_ENABLE					1
+#define	UART_1_FEATURE_AUTO_RTS							6:6
+#define	UART_1_FEATURE_AUTO_RTS_DISABLE					0
+#define	UART_1_FEATURE_AUTO_RTS_ENABLE					1
+#define	UART_1_FEATURE_ENHANCED							4:4
+#define	UART_1_FEATURE_ENHANCED_DISABLE					0
+#define	UART_1_FEATURE_ENHANCED_ENABLE					1
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1				3:3
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2				2:2
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_1_FEATURE_SW_TX_FLOW_CTRL_XON2_ENABLE		1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1				1:1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1_DISABLE		0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON1_ENABLE		1
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2				0:0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2_DISABLE		0
+#define	UART_1_FEATURE_SW_RX_FLOW_CTRL_XON2_ENABLE		1
+
+#define	UART_1_XON1_CHAR								0x030030
+#define	UART_1_XON1_CHAR_DATA							7:0
+
+#define	UART_1_XON2_CHAR								0x030034
+#define	UART_1_XON2_CHAR_DATA							7:0
+
+#define	UART_1_XOFF1_CHAR								0x030038
+#define	UART_1_XOFF1_CHAR_DATA							7:0
+
+#define	UART_1_XOFF2_CHAR								0x03003C
+#define	UART_1_XOFF2_CHAR_DATA							7:0
+
+
+/*****************************************************************************\
+ *                                 USB HOST                                  *
+\*****************************************************************************/
+
+#define USB_HOST_HC_REVISION				0X040000
+#define USB_HOST_HC_CONTROL				0X040004
+#define USB_HOST_HC_COMMANDSTATUS		0X040008
+#define USB_HOST_HC_INTERRUPTSTATUS		0X04000C
+#define USB_HOST_HC_INTERRUPTENABLE		0X040010
+#define USB_HOST_HC_INTERRUPTDISABLE		0X040014
+#define USB_HOST_HC_HCCA					0X040018
+#define USB_HOST_HC_PERIODCURRENTED		0X04001C
+#define USB_HOST_HC_CONTROLHEADED		0X040020
+#define USB_HOST_HC_CONTROLCURRENTED		0X040024
+#define USB_HOST_HC_BULKHEADED			0X040028
+#define USB_HOST_HC_BULKCURRENTED			0X04002C
+#define USB_HOST_HC_DONEHEAD				0X040030
+#define USB_HOST_HC_FMINTERVAL				0X040034
+#define USB_HOST_HC_FMREMAINING			0X040038
+#define USB_HOST_HC_FMNUMBER				0X04003C
+#define USB_HOST_HC_PERIODSTART			0X040040
+#define USB_HOST_HC_LSTHRESHOLD			0X040044
+#define USB_HOST_HC_RHDESCRIPTORA			0X040048
+#define USB_HOST_HC_RHDESCRIPTORB			0X04004C
+#define USB_HOST_HC_RHSTATUS				0X040050
+#define USB_HOST_HC_RHPORT1				0X040054
+
+
+/*****************************************************************************\
+ *                                USB SLAVE                                  *
+\*****************************************************************************/
+
+/* TBD */
+
+
+/*****************************************************************************\
+ *                            DISPLAY CONTROLLER                             *
+\*****************************************************************************/
+
+// Panel Graphics Control
+
+#define PANEL_DISPLAY_CTRL                              0x080000
+#define PANEL_DISPLAY_CTRL_FPEN                         27:27
+#define PANEL_DISPLAY_CTRL_FPEN_LOW                     0
+#define PANEL_DISPLAY_CTRL_FPEN_HIGH                    1
+#define PANEL_DISPLAY_CTRL_VBIASEN                      26:26
+#define PANEL_DISPLAY_CTRL_VBIASEN_LOW                  0
+#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH                 1
+#define PANEL_DISPLAY_CTRL_DATA                         25:25
+#define PANEL_DISPLAY_CTRL_DATA_DISABLE                 0
+#define PANEL_DISPLAY_CTRL_DATA_ENABLE                  1
+#define PANEL_DISPLAY_CTRL_FPVDDEN                      24:24
+#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW                  0
+#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH                 1
+#define PANEL_DISPLAY_CTRL_PATTERN                      23:23
+#define PANEL_DISPLAY_CTRL_PATTERN_4                    0
+#define PANEL_DISPLAY_CTRL_PATTERN_8                    1
+#define PANEL_DISPLAY_CTRL_TFT                          22:21
+#define PANEL_DISPLAY_CTRL_TFT_24                       0
+#define PANEL_DISPLAY_CTRL_TFT_9                        1
+#define PANEL_DISPLAY_CTRL_TFT_12                       2
+#define PANEL_DISPLAY_CTRL_DITHER                       20:20
+#define PANEL_DISPLAY_CTRL_DITHER_DISABLE               0
+#define PANEL_DISPLAY_CTRL_DITHER_ENABLE                1
+#define PANEL_DISPLAY_CTRL_LCD                          19:18
+#define PANEL_DISPLAY_CTRL_LCD_TFT                      0
+#define PANEL_DISPLAY_CTRL_LCD_STN_8                    2
+#define PANEL_DISPLAY_CTRL_LCD_STN_12                   3
+#define PANEL_DISPLAY_CTRL_FIFO                         17:16
+#define PANEL_DISPLAY_CTRL_FIFO_1                       0
+#define PANEL_DISPLAY_CTRL_FIFO_3                       1
+#define PANEL_DISPLAY_CTRL_FIFO_7                       2
+#define PANEL_DISPLAY_CTRL_FIFO_11                      3
+#define PANEL_DISPLAY_CTRL_CLOCK_PHASE                  14:14
+#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH      0
+#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW       1
+#define PANEL_DISPLAY_CTRL_VSYNC_PHASE                  13:13
+#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH      0
+#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW       1
+#define PANEL_DISPLAY_CTRL_HSYNC_PHASE                  12:12
+#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH      0
+#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW       1
+#define PANEL_DISPLAY_CTRL_COLOR_KEY                    9:9
+#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE            0
+#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE             1
+#define PANEL_DISPLAY_CTRL_TIMING                       8:8
+#define PANEL_DISPLAY_CTRL_TIMING_DISABLE               0
+#define PANEL_DISPLAY_CTRL_TIMING_ENABLE                1
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR             7:7
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN        0
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP          1
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN                 6:6
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE         0
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE          1
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR           5:5
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT     0
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT      1
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN               4:4
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE       0
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE        1
+#define PANEL_DISPLAY_CTRL_GAMMA                        3:3
+#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE                0
+#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE                 1
+#define PANEL_DISPLAY_CTRL_PLANE                        2:2
+#define PANEL_DISPLAY_CTRL_PLANE_DISABLE                0
+#define PANEL_DISPLAY_CTRL_PLANE_ENABLE                 1
+#define PANEL_DISPLAY_CTRL_FORMAT                       1:0
+#define PANEL_DISPLAY_CTRL_FORMAT_8                     0
+#define PANEL_DISPLAY_CTRL_FORMAT_16                    1
+#define PANEL_DISPLAY_CTRL_FORMAT_32                    2
+
+#define PANEL_PAN_CTRL                                  0x080004
+#define PANEL_PAN_CTRL_VERTICAL_PAN                     31:24
+#define PANEL_PAN_CTRL_VERTICAL_VSYNC                   21:16
+#define PANEL_PAN_CTRL_HORIZONTAL_PAN                   15:8
+#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC                 5:0
+
+#define PANEL_COLOR_KEY                                 0x080008
+#define PANEL_COLOR_KEY_MASK                            31:16
+#define PANEL_COLOR_KEY_VALUE                           15:0
+
+#define PANEL_FB_ADDRESS                                0x08000C
+#define PANEL_FB_ADDRESS_STATUS                         31:31
+#define PANEL_FB_ADDRESS_STATUS_CURRENT               0
+#define PANEL_FB_ADDRESS_STATUS_FLIP	                 1
+#define PANEL_FB_ADDRESS_EXT                            27:27
+#define PANEL_FB_ADDRESS_EXT_LOCAL                      0
+#define PANEL_FB_ADDRESS_EXT_EXTERNAL                   1
+#define PANEL_FB_ADDRESS_CS                             26:26
+#define PANEL_FB_ADDRESS_CS_0                           0
+#define PANEL_FB_ADDRESS_CS_1                           1
+#define PANEL_FB_ADDRESS_ADDRESS                        25:0
+
+#define PANEL_FB_WIDTH                                  0x080010
+#define PANEL_FB_WIDTH_WIDTH                            29:16
+#define PANEL_FB_WIDTH_OFFSET                           13:0
+
+#define PANEL_WINDOW_WIDTH                              0x080014
+#define PANEL_WINDOW_WIDTH_WIDTH                        27:16
+#define PANEL_WINDOW_WIDTH_X                            11:0
+
+#define PANEL_WINDOW_HEIGHT                             0x080018
+#define PANEL_WINDOW_HEIGHT_HEIGHT                      27:16
+#define PANEL_WINDOW_HEIGHT_Y                           11:0
+
+#define PANEL_PLANE_TL                                  0x08001C
+#define PANEL_PLANE_TL_TOP                              26:16
+#define PANEL_PLANE_TL_LEFT                             10:0
+
+#define PANEL_PLANE_BR                                  0x080020
+#define PANEL_PLANE_BR_BOTTOM                           26:16
+#define PANEL_PLANE_BR_RIGHT                            10:0
+
+#define PANEL_HORIZONTAL_TOTAL                          0x080024
+#define PANEL_HORIZONTAL_TOTAL_TOTAL                    27:16
+#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END              11:0
+
+#define PANEL_HORIZONTAL_SYNC                           0x080028
+#define PANEL_HORIZONTAL_SYNC_WIDTH                     23:16
+#define PANEL_HORIZONTAL_SYNC_START                     11:0
+
+#define PANEL_VERTICAL_TOTAL                            0x08002C
+#define PANEL_VERTICAL_TOTAL_TOTAL                      26:16
+#define PANEL_VERTICAL_TOTAL_DISPLAY_END                10:0
+
+#define PANEL_VERTICAL_SYNC                             0x080030
+#define PANEL_VERTICAL_SYNC_HEIGHT                      21:16
+#define PANEL_VERTICAL_SYNC_START                       10:0
+
+#define PANEL_CURRENT_LINE                              0x080034
+#define PANEL_CURRENT_LINE_LINE                         10:0
+
+// Video Control
+
+#define VIDEO_DISPLAY_CTRL                              0x080040
+#define VIDEO_DISPLAY_CTRL_FIFO                         17:16
+#define VIDEO_DISPLAY_CTRL_FIFO_1                       0
+#define VIDEO_DISPLAY_CTRL_FIFO_3                       1
+#define VIDEO_DISPLAY_CTRL_FIFO_7                       2
+#define VIDEO_DISPLAY_CTRL_FIFO_11                      3
+#define VIDEO_DISPLAY_CTRL_BUFFER                       15:15
+#define VIDEO_DISPLAY_CTRL_BUFFER_0                     0
+#define VIDEO_DISPLAY_CTRL_BUFFER_1                     1
+#define VIDEO_DISPLAY_CTRL_CAPTURE                      14:14
+#define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE              0
+#define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE               1
+#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER                13:13
+#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE        0
+#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE         1
+#define VIDEO_DISPLAY_CTRL_BYTE_SWAP                    12:12
+#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE            0
+#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE             1
+#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE               11:11
+#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL        0
+#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF          1
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE             10:10
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL      0
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF        1
+#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE                9:9
+#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE      0
+#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE    1
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE              8:8
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE    0
+#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE  1
+#define VIDEO_DISPLAY_CTRL_PIXEL                        7:4
+#define VIDEO_DISPLAY_CTRL_GAMMA                        3:3
+#define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE                0
+#define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE                 1
+#define VIDEO_DISPLAY_CTRL_PLANE                        2:2
+#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE                0
+#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE                 1
+#define VIDEO_DISPLAY_CTRL_FORMAT                       1:0
+#define VIDEO_DISPLAY_CTRL_FORMAT_8                     0
+#define VIDEO_DISPLAY_CTRL_FORMAT_16                    1
+#define VIDEO_DISPLAY_CTRL_FORMAT_32                    2
+#define VIDEO_DISPLAY_CTRL_FORMAT_YUV                   3
+
+#define VIDEO_FB_0_ADDRESS                              0x080044
+#define VIDEO_FB_0_ADDRESS_STATUS                       31:31
+#define VIDEO_FB_0_ADDRESS_STATUS_CURRENT               0
+#define VIDEO_FB_0_ADDRESS_STATUS_PENDING               1
+#define VIDEO_FB_0_ADDRESS_EXT                          27:27
+#define VIDEO_FB_0_ADDRESS_EXT_LOCAL                    0
+#define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL                 1
+#define VIDEO_FB_0_ADDRESS_CS                           26:26
+#define VIDEO_FB_0_ADDRESS_CS_0                         0
+#define VIDEO_FB_0_ADDRESS_CS_1                         1
+#define VIDEO_FB_0_ADDRESS_ADDRESS                      25:0
+
+#define VIDEO_FB_WIDTH                                  0x080048
+#define VIDEO_FB_WIDTH_WIDTH                            29:16
+#define VIDEO_FB_WIDTH_OFFSET                           13:0
+
+#define VIDEO_FB_0_LAST_ADDRESS                         0x08004C
+#define VIDEO_FB_0_LAST_ADDRESS_EXT                     27:27
+#define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL               0
+#define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL            1
+#define VIDEO_FB_0_LAST_ADDRESS_CS                      26:26
+#define VIDEO_FB_0_LAST_ADDRESS_CS_0                    0
+#define VIDEO_FB_0_LAST_ADDRESS_CS_1                    1
+#define VIDEO_FB_0_LAST_ADDRESS_ADDRESS                 25:0
+
+#define VIDEO_PLANE_TL                                  0x080050
+#define VIDEO_PLANE_TL_TOP                              26:16
+#define VIDEO_PLANE_TL_LEFT                             13:0
+
+#define VIDEO_PLANE_BR                                  0x080054
+#define VIDEO_PLANE_BR_BOTTOM                           26:16
+#define VIDEO_PLANE_BR_RIGHT                            13:0
+
+#define VIDEO_SCALE                                     0x080058
+#define VIDEO_SCALE_VERTICAL_MODE                       31:31
+#define VIDEO_SCALE_VERTICAL_MODE_EXPAND                0
+#define VIDEO_SCALE_VERTICAL_MODE_SHRINK                1
+#define VIDEO_SCALE_VERTICAL_SCALE                      27:16
+#define VIDEO_SCALE_HORIZONTAL_MODE                     15:15
+#define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND              0
+#define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK              1
+#define VIDEO_SCALE_HORIZONTAL_SCALE                    11:0
+
+#define VIDEO_INITIAL_SCALE                             0x08005C
+#define VIDEO_INITIAL_SCALE_FB_1                        27:16
+#define VIDEO_INITIAL_SCALE_FB_0                        11:0
+
+#define VIDEO_YUV_CONSTANTS                             0x080060
+#define VIDEO_YUV_CONSTANTS_Y                           31:24
+#define VIDEO_YUV_CONSTANTS_R                           23:16
+#define VIDEO_YUV_CONSTANTS_G                           15:8
+#define VIDEO_YUV_CONSTANTS_B                           7:0
+
+#define VIDEO_FB_1_ADDRESS                              0x080064
+#define VIDEO_FB_1_ADDRESS_STATUS                       31:31
+#define VIDEO_FB_1_ADDRESS_STATUS_CURRENT               0
+#define VIDEO_FB_1_ADDRESS_STATUS_PENDING               1
+#define VIDEO_FB_1_ADDRESS_EXT                          27:27
+#define VIDEO_FB_1_ADDRESS_EXT_LOCAL                    0
+#define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL                 1
+#define VIDEO_FB_1_ADDRESS_CS                           26:26
+#define VIDEO_FB_1_ADDRESS_CS_0                         0
+#define VIDEO_FB_1_ADDRESS_CS_1                         1
+#define VIDEO_FB_1_ADDRESS_ADDRESS                      25:0
+
+#define VIDEO_FB_1_LAST_ADDRESS                         0x080068
+#define VIDEO_FB_1_LAST_ADDRESS_EXT                     27:27
+#define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL               0
+#define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL            1
+#define VIDEO_FB_1_LAST_ADDRESS_CS                      26:26
+#define VIDEO_FB_1_LAST_ADDRESS_CS_0                    0
+#define VIDEO_FB_1_LAST_ADDRESS_CS_1                    1
+#define VIDEO_FB_1_LAST_ADDRESS_ADDRESS                 25:0
+
+// Video Alpha Control
+
+#define VIDEO_ALPHA_DISPLAY_CTRL                        0x080080
+#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT                 28:28
+#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL       0
+#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA           1
+#define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA                  27:24
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO                   17:16
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1                 0
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3                 1
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7                 2
+#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11                3
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE             11:11
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL      0
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF        1
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE             10:10
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL      0
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF        1
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE              9:9
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE    0
+#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE  1
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE              8:8
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE    0
+#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE  1
+#define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL                  7:4
+#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY             3:3
+#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE     0
+#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE      1
+#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE                  2:2
+#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE          0
+#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE           1
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT                 1:0
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8               0
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16              1
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4       2
+#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4   3
+
+#define VIDEO_ALPHA_FB_ADDRESS                          0x080084
+#define VIDEO_ALPHA_FB_ADDRESS_STATUS                   31:31
+#define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT           0
+#define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING           1
+#define VIDEO_ALPHA_FB_ADDRESS_EXT                      27:27
+#define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL                0
+#define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL             1
+#define VIDEO_ALPHA_FB_ADDRESS_CS                       26:26
+#define VIDEO_ALPHA_FB_ADDRESS_CS_0                     0
+#define VIDEO_ALPHA_FB_ADDRESS_CS_1                     1
+#define VIDEO_ALPHA_FB_ADDRESS_ADDRESS                  25:0
+
+#define VIDEO_ALPHA_FB_WIDTH                            0x080088
+#define VIDEO_ALPHA_FB_WIDTH_WIDTH                      29:16
+#define VIDEO_ALPHA_FB_WIDTH_OFFSET                     13:0
+
+#define VIDEO_ALPHA_FB_LAST_ADDRESS                     0x08008C
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT                 27:27
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL           0
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL        1
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_CS                  26:26
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_CS_0                0
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_CS_1                1
+#define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS             25:0
+
+#define VIDEO_ALPHA_PLANE_TL                            0x080090
+#define VIDEO_ALPHA_PLANE_TL_TOP                        26:16
+#define VIDEO_ALPHA_PLANE_TL_LEFT                       10:0
+
+#define VIDEO_ALPHA_PLANE_BR                            0x080094
+#define VIDEO_ALPHA_PLANE_BR_BOTTOM                     26:16
+#define VIDEO_ALPHA_PLANE_BR_RIGHT                      10:0
+
+#define VIDEO_ALPHA_SCALE                               0x080098
+#define VIDEO_ALPHA_SCALE_VERTICAL_MODE                 31:31
+#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND          0
+#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK          1
+#define VIDEO_ALPHA_SCALE_VERTICAL_SCALE                27:16
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE               15:15
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND        0
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK        1
+#define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE              11:0
+
+#define VIDEO_ALPHA_INITIAL_SCALE                       0x08009C
+#define VIDEO_ALPHA_INITIAL_SCALE_FB                    11:0
+
+#define VIDEO_ALPHA_CHROMA_KEY                          0x0800A0
+#define VIDEO_ALPHA_CHROMA_KEY_MASK                     31:16
+#define VIDEO_ALPHA_CHROMA_KEY_VALUE                    15:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_01                     0x0800A4
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_23                     0x0800A8
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_45                     0x0800AC
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_67                     0x0800B0
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_89                     0x0800B4
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB                     0x0800B8
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD                     0x0800BC
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE              4:0
+
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF                     0x0800C0
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED               31:27
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN             26:21
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE              20:16
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED               15:11
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN             10:5
+#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE              4:0
+
+// Panel Cursor Control
+
+#define PANEL_HWC_ADDRESS                               0x0800F0
+#define PANEL_HWC_ADDRESS_ENABLE                        31:31
+#define PANEL_HWC_ADDRESS_ENABLE_DISABLE                0
+#define PANEL_HWC_ADDRESS_ENABLE_ENABLE                 1
+#define PANEL_HWC_ADDRESS_EXT                           27:27
+#define PANEL_HWC_ADDRESS_EXT_LOCAL                     0
+#define PANEL_HWC_ADDRESS_EXT_EXTERNAL                  1
+#define PANEL_HWC_ADDRESS_CS                            26:26
+#define PANEL_HWC_ADDRESS_CS_0                          0
+#define PANEL_HWC_ADDRESS_CS_1                          1
+#define PANEL_HWC_ADDRESS_ADDRESS                       25:0
+
+#define PANEL_HWC_LOCATION                              0x0800F4
+#define PANEL_HWC_LOCATION_TOP                          27:27
+#define PANEL_HWC_LOCATION_TOP_INSIDE                   0
+#define PANEL_HWC_LOCATION_TOP_OUTSIDE                  1
+#define PANEL_HWC_LOCATION_Y                            26:16
+#define PANEL_HWC_LOCATION_LEFT                         11:11
+#define PANEL_HWC_LOCATION_LEFT_INSIDE                  0
+#define PANEL_HWC_LOCATION_LEFT_OUTSIDE                 1
+#define PANEL_HWC_LOCATION_X                            10:0
+
+#define PANEL_HWC_COLOR_12                              0x0800F8
+#define PANEL_HWC_COLOR_12_2_RGB565                     31:16
+#define PANEL_HWC_COLOR_12_1_RGB565                     15:0
+
+#define PANEL_HWC_COLOR_3                               0x0800FC
+#define PANEL_HWC_COLOR_3_RGB565                        15:0
+
+// Old Definitions +++
+#define PANEL_HWC_COLOR_01                              0x0800F8
+#define PANEL_HWC_COLOR_01_1_RED                        31:27
+#define PANEL_HWC_COLOR_01_1_GREEN                      26:21
+#define PANEL_HWC_COLOR_01_1_BLUE                       20:16
+#define PANEL_HWC_COLOR_01_0_RED                        15:11
+#define PANEL_HWC_COLOR_01_0_GREEN                      10:5
+#define PANEL_HWC_COLOR_01_0_BLUE                       4:0
+
+#define PANEL_HWC_COLOR_2                               0x0800FC
+#define PANEL_HWC_COLOR_2_RED                           15:11
+#define PANEL_HWC_COLOR_2_GREEN                         10:5
+#define PANEL_HWC_COLOR_2_BLUE                          4:0
+// Old Definitions ---
+
+// Alpha Control
+
+#define ALPHA_DISPLAY_CTRL                              0x080100
+#define ALPHA_DISPLAY_CTRL_SELECT                       28:28
+#define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL             0
+#define ALPHA_DISPLAY_CTRL_SELECT_ALPHA                 1
+#define ALPHA_DISPLAY_CTRL_ALPHA                        27:24
+#define ALPHA_DISPLAY_CTRL_FIFO                         17:16
+#define ALPHA_DISPLAY_CTRL_FIFO_1                       0
+#define ALPHA_DISPLAY_CTRL_FIFO_3                       1
+#define ALPHA_DISPLAY_CTRL_FIFO_7                       2
+#define ALPHA_DISPLAY_CTRL_FIFO_11                      3
+#define ALPHA_DISPLAY_CTRL_PIXEL                        7:4
+#define ALPHA_DISPLAY_CTRL_CHROMA_KEY                   3:3
+#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE           0
+#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE            1
+#define ALPHA_DISPLAY_CTRL_PLANE                        2:2
+#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE                0
+#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE                 1
+#define ALPHA_DISPLAY_CTRL_FORMAT                       1:0
+#define ALPHA_DISPLAY_CTRL_FORMAT_16                    1
+#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4             2
+#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4         3
+
+#define ALPHA_FB_ADDRESS                                0x080104
+#define ALPHA_FB_ADDRESS_STATUS                         31:31
+#define ALPHA_FB_ADDRESS_STATUS_CURRENT                 0
+#define ALPHA_FB_ADDRESS_STATUS_PENDING                 1
+#define ALPHA_FB_ADDRESS_EXT                            27:27
+#define ALPHA_FB_ADDRESS_EXT_LOCAL                      0
+#define ALPHA_FB_ADDRESS_EXT_EXTERNAL                   1
+#define ALPHA_FB_ADDRESS_CS                             26:26
+#define ALPHA_FB_ADDRESS_CS_0                           0
+#define ALPHA_FB_ADDRESS_CS_1                           1
+#define ALPHA_FB_ADDRESS_ADDRESS                        25:0
+
+#define ALPHA_FB_WIDTH                                  0x080108
+#define ALPHA_FB_WIDTH_WIDTH                            29:16
+#define ALPHA_FB_WIDTH_OFFSET                           13:0
+
+#define ALPHA_PLANE_TL                                  0x08010C
+#define ALPHA_PLANE_TL_TOP                              26:16
+#define ALPHA_PLANE_TL_LEFT                             10:0
+
+#define ALPHA_PLANE_BR                                  0x080110
+#define ALPHA_PLANE_BR_BOTTOM                           26:16
+#define ALPHA_PLANE_BR_RIGHT                            10:0
+
+#define ALPHA_CHROMA_KEY                                0x080114
+#define ALPHA_CHROMA_KEY_MASK                           31:16
+#define ALPHA_CHROMA_KEY_VALUE                          15:0
+
+#define ALPHA_COLOR_LOOKUP_01                           0x080118
+#define ALPHA_COLOR_LOOKUP_01_1_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_01_1_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_01_1_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_01_0_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_01_0_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_01_0_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_23                           0x08011C
+#define ALPHA_COLOR_LOOKUP_23_3_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_23_3_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_23_3_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_23_2_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_23_2_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_23_2_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_45                           0x080120
+#define ALPHA_COLOR_LOOKUP_45_5_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_45_5_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_45_5_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_45_4_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_45_4_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_45_4_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_67                           0x080124
+#define ALPHA_COLOR_LOOKUP_67_7_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_67_7_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_67_7_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_67_6_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_67_6_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_67_6_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_89                           0x080128
+#define ALPHA_COLOR_LOOKUP_89_9_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_89_9_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_89_9_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_89_8_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_89_8_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_89_8_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_AB                           0x08012C
+#define ALPHA_COLOR_LOOKUP_AB_B_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_AB_B_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_AB_B_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_AB_A_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_AB_A_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_AB_A_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_CD                           0x080130
+#define ALPHA_COLOR_LOOKUP_CD_D_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_CD_D_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_CD_D_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_CD_C_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_CD_C_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_CD_C_BLUE                    4:0
+
+#define ALPHA_COLOR_LOOKUP_EF                           0x080134
+#define ALPHA_COLOR_LOOKUP_EF_F_RED                     31:27
+#define ALPHA_COLOR_LOOKUP_EF_F_GREEN                   26:21
+#define ALPHA_COLOR_LOOKUP_EF_F_BLUE                    20:16
+#define ALPHA_COLOR_LOOKUP_EF_E_RED                     15:11
+#define ALPHA_COLOR_LOOKUP_EF_E_GREEN                   10:5
+#define ALPHA_COLOR_LOOKUP_EF_E_BLUE                    4:0
+
+// CRT Graphics Control
+
+#define CRT_DISPLAY_CTRL                                0x080200
+#define CRT_DISPLAY_CTRL_FIFO                           17:16
+#define CRT_DISPLAY_CTRL_FIFO_1                         0
+#define CRT_DISPLAY_CTRL_FIFO_3                         1
+#define CRT_DISPLAY_CTRL_FIFO_7                         2
+#define CRT_DISPLAY_CTRL_FIFO_11                        3
+#define CRT_DISPLAY_CTRL_TV_PHASE                       15:15
+#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_HIGH           0
+#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_LOW            1
+#define CRT_DISPLAY_CTRL_CLOCK_PHASE                    14:14
+#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH        0
+#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW         1
+#define CRT_DISPLAY_CTRL_VSYNC_PHASE                    13:13
+#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH        0
+#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW         1
+#define CRT_DISPLAY_CTRL_HSYNC_PHASE                    12:12
+#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH        0
+#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW         1
+#define CRT_DISPLAY_CTRL_BLANK                          10:10
+#define CRT_DISPLAY_CTRL_BLANK_OFF                      0
+#define CRT_DISPLAY_CTRL_BLANK_ON                       1
+#define CRT_DISPLAY_CTRL_SELECT                         9:9
+#define CRT_DISPLAY_CTRL_SELECT_PANEL                   0
+#define CRT_DISPLAY_CTRL_SELECT_CRT                     1
+#define CRT_DISPLAY_CTRL_TIMING                         8:8
+#define CRT_DISPLAY_CTRL_TIMING_DISABLE                 0
+#define CRT_DISPLAY_CTRL_TIMING_ENABLE                  1
+#define CRT_DISPLAY_CTRL_PIXEL                          7:4
+#define CRT_DISPLAY_CTRL_GAMMA                          3:3
+#define CRT_DISPLAY_CTRL_GAMMA_DISABLE                  0
+#define CRT_DISPLAY_CTRL_GAMMA_ENABLE                   1
+#define CRT_DISPLAY_CTRL_PLANE                          2:2
+#define CRT_DISPLAY_CTRL_PLANE_DISABLE                  0
+#define CRT_DISPLAY_CTRL_PLANE_ENABLE                   1
+#define CRT_DISPLAY_CTRL_FORMAT                         1:0
+#define CRT_DISPLAY_CTRL_FORMAT_8                       0
+#define CRT_DISPLAY_CTRL_FORMAT_16                      1
+#define CRT_DISPLAY_CTRL_FORMAT_32                      2
+
+#define CRT_FB_ADDRESS                                  0x080204
+#define CRT_FB_ADDRESS_STATUS                           31:31
+#define CRT_FB_ADDRESS_STATUS_CURRENT                   0
+#define CRT_FB_ADDRESS_STATUS_PENDING                   1
+#define CRT_FB_ADDRESS_EXT                              27:27
+#define CRT_FB_ADDRESS_EXT_LOCAL                        0
+#define CRT_FB_ADDRESS_EXT_EXTERNAL                     1
+#define CRT_FB_ADDRESS_CS                               26:26
+#define CRT_FB_ADDRESS_CS_0                             0
+#define CRT_FB_ADDRESS_CS_1                             1
+#define CRT_FB_ADDRESS_ADDRESS                          25:0
+
+#define CRT_FB_WIDTH                                    0x080208
+#define CRT_FB_WIDTH_WIDTH                              29:16
+#define CRT_FB_WIDTH_OFFSET                             13:0
+
+#define CRT_HORIZONTAL_TOTAL                            0x08020C
+#define CRT_HORIZONTAL_TOTAL_TOTAL                      27:16
+#define CRT_HORIZONTAL_TOTAL_DISPLAY_END                11:0
+
+#define CRT_HORIZONTAL_SYNC                             0x080210
+#define CRT_HORIZONTAL_SYNC_WIDTH                       23:16
+#define CRT_HORIZONTAL_SYNC_START                       11:0
+
+#define CRT_VERTICAL_TOTAL                              0x080214
+#define CRT_VERTICAL_TOTAL_TOTAL                        26:16
+#define CRT_VERTICAL_TOTAL_DISPLAY_END                  10:0
+
+#define CRT_VERTICAL_SYNC                               0x080218
+#define CRT_VERTICAL_SYNC_HEIGHT                        21:16
+#define CRT_VERTICAL_SYNC_START                         10:0
+
+#define CRT_SIGNATURE_ANALYZER                          0x08021C
+#define CRT_SIGNATURE_ANALYZER_STATUS                   31:16
+#define CRT_SIGNATURE_ANALYZER_ENABLE                   3:3
+#define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE           0
+#define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE            1
+#define CRT_SIGNATURE_ANALYZER_RESET                    2:2
+#define CRT_SIGNATURE_ANALYZER_RESET_NORMAL             0
+#define CRT_SIGNATURE_ANALYZER_RESET_RESET              1
+#define CRT_SIGNATURE_ANALYZER_SOURCE                   1:0
+#define CRT_SIGNATURE_ANALYZER_SOURCE_RED               0
+#define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN             1
+#define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE              2
+
+#define CRT_CURRENT_LINE                                0x080220
+#define CRT_CURRENT_LINE_LINE                           10:0
+
+#define CRT_MONITOR_DETECT                              0x080224
+#define CRT_MONITOR_DETECT_ENABLE                       24:24
+#define CRT_MONITOR_DETECT_ENABLE_DISABLE               0
+#define CRT_MONITOR_DETECT_ENABLE_ENABLE                1
+#define CRT_MONITOR_DETECT_RED                          23:16
+#define CRT_MONITOR_DETECT_GREEN                        15:8
+#define CRT_MONITOR_DETECT_BLUE                         7:0
+
+// CRT Cursor Control
+
+#define CRT_HWC_ADDRESS                                 0x080230
+#define CRT_HWC_ADDRESS_ENABLE                          31:31
+#define CRT_HWC_ADDRESS_ENABLE_DISABLE                  0
+#define CRT_HWC_ADDRESS_ENABLE_ENABLE                   1
+#define CRT_HWC_ADDRESS_EXT                             27:27
+#define CRT_HWC_ADDRESS_EXT_LOCAL                       0
+#define CRT_HWC_ADDRESS_EXT_EXTERNAL                    1
+#define CRT_HWC_ADDRESS_CS                              26:26
+#define CRT_HWC_ADDRESS_CS_0                            0
+#define CRT_HWC_ADDRESS_CS_1                            1
+#define CRT_HWC_ADDRESS_ADDRESS                         25:0
+
+#define CRT_HWC_LOCATION                                0x080234
+#define CRT_HWC_LOCATION_TOP                            27:27
+#define CRT_HWC_LOCATION_TOP_INSIDE                     0
+#define CRT_HWC_LOCATION_TOP_OUTSIDE                    1
+#define CRT_HWC_LOCATION_Y                              26:16
+#define CRT_HWC_LOCATION_LEFT                           11:11
+#define CRT_HWC_LOCATION_LEFT_INSIDE                    0
+#define CRT_HWC_LOCATION_LEFT_OUTSIDE                   1
+#define CRT_HWC_LOCATION_X                              10:0
+
+#define CRT_HWC_COLOR_12                                0x080238
+#define CRT_HWC_COLOR_12_2_RGB565                       31:16
+#define CRT_HWC_COLOR_12_1_RGB565                       15:0
+
+#define CRT_HWC_COLOR_3                                 0x08023C
+#define CRT_HWC_COLOR_3_RGB565                          15:0
+
+// Old Definitions +++
+#define CRT_HWC_COLOR_01                                0x080238
+#define CRT_HWC_COLOR_01_1_RED                          31:27
+#define CRT_HWC_COLOR_01_1_GREEN                        26:21
+#define CRT_HWC_COLOR_01_1_BLUE                         20:16
+#define CRT_HWC_COLOR_01_0_RED                          15:11
+#define CRT_HWC_COLOR_01_0_GREEN                        10:5
+#define CRT_HWC_COLOR_01_0_BLUE                         4:0
+
+#define CRT_HWC_COLOR_2                                 0x08023C
+#define CRT_HWC_COLOR_2_RED                             15:11
+#define CRT_HWC_COLOR_2_GREEN                           10:5
+#define CRT_HWC_COLOR_2_BLUE                            4:0
+// Old Definitions ---
+
+// Palette RAM
+
+#define PANEL_PALETTE_RAM                               0x080400
+#define VIDEO_PALETTE_RAM                               0x080800
+#define CRT_PALETTE_RAM                                 0x080C00
+
+
+
+/*****************************************************************************\
+ *                                 ZV PORT                                   *
+\*****************************************************************************/
+
+#define CAPTURE_CONTROL                                 0x090000
+#define CAPTURE_CONTROL_FIELD                           27:27
+#define CAPTURE_CONTROL_FIELD_EVEN						0
+#define CAPTURE_CONTROL_FIELD_ODD						1
+#define CAPTURE_CONTROL_INTERLACE						26:26
+#define CAPTURE_CONTROL_INTERLACE_NON_INTERLACED		0
+#define CAPTURE_CONTROL_INTERLACE_INTERLACED			1
+#define CAPTURE_CONTROL_CAPTURE_BUFFER					25:25
+#define CAPTURE_CONTROL_CAPTURE_BUFFER_0				0
+#define CAPTURE_CONTROL_CAPTURE_BUFFER_1				1
+#define CAPTURE_CONTROL_VSYNC							24:24
+#define CAPTURE_CONTROL_VSYNC_INACTIVE					0
+#define CAPTURE_CONTROL_VSYNC_ACTIVE					1
+#define CAPTURE_CONTROL_HORIZONTAL_AVE					18:18
+#define CAPTURE_CONTROL_HORIZONTAL_AVE_DISABLE			0
+#define CAPTURE_CONTROL_HORIZONTAL_AVE_ENABLE			1
+#define CAPTURE_CONTROL_2TO1_VERTICAL_SHRINK			17:17
+#define CAPTURE_CONTROL_2TO1_VERTICAL_SHRINK_DISABLE	0
+#define CAPTURE_CONTROL_2TO1_VERTICAL_SHRINK_ENABLE		1
+#define CAPTURE_CONTROL_2TO1_HORIZONTAL_SHRINK			16:16
+#define CAPTURE_CONTROL_2TO1_HORIZONTAL_SHRINK_DISABLE	0
+#define CAPTURE_CONTROL_2TO1_HORIZONTAL_SHRINK_ENABLE	1
+#define CAPTURE_CONTROL_FIELD_DETECT					15:15
+#define CAPTURE_CONTROL_FIELD_DETECT_RISING				0
+#define CAPTURE_CONTROL_FIELD_DETECT_FALLING			1
+#define CAPTURE_CONTROL_VSYNC_PHASE						14:14
+#define CAPTURE_CONTROL_VSYNC_PHASE_ACTIVE_HIGH			0
+#define CAPTURE_CONTROL_VSYNC_PHASE_ACTIVE_LOW			1
+#define CAPTURE_CONTROL_HREF_PHASE						13:13
+#define CAPTURE_CONTROL_HREF_PHASE_ACTIVE_HIGH			0
+#define CAPTURE_CONTROL_HREF_PHASE_ACTIVE_LOW			1
+#define CAPTURE_CONTROL_CLOCK_POLARITY					12:12
+#define CAPTURE_CONTROL_CLOCK_POLARITY_ACTIVE_HIGH		0
+#define CAPTURE_CONTROL_CLOCK_POLARITY_ACTIVE_LOW		1
+#define CAPTURE_CONTROL_UV_SWAP							11:11
+#define CAPTURE_CONTROL_UV_SWAP_DISABLE					0
+#define CAPTURE_CONTROL_UV_SWAP_ENABLE					1
+#define CAPTURE_CONTROL_BYTE_SWAP						10:10
+#define CAPTURE_CONTROL_BYTE_SWAP_DISABLE				0
+#define CAPTURE_CONTROL_BYTE_SWAP_ENABLE				1
+#define CAPTURE_CONTROL_CAPTURE_SIZE					9:9
+#define CAPTURE_CONTROL_CAPTURE_SIZE_16					0
+#define CAPTURE_CONTROL_CAPTURE_SIZE_8					1
+#define CAPTURE_CONTROL_CAPTURE_FORMAT					8:8
+#define CAPTURE_CONTROL_CAPTURE_FORMAT_YUV				0
+#define CAPTURE_CONTROL_CAPTURE_FORMAT_RGB				1
+#define CAPTURE_CONTROL_FIELD_SWAP						7:7
+#define CAPTURE_CONTROL_FIELD_SWAP_DISABLE				0
+#define CAPTURE_CONTROL_FIELD_SWAP_ENABLE				1
+#define CAPTURE_CONTROL_INTERLACE_WEAVE					6:6
+#define CAPTURE_CONTROL_INTERLACE_WEAVE_DISABLE			0
+#define CAPTURE_CONTROL_INTERLACE_WEAVE_ENABLE			1
+#define CAPTURE_CONTROL_INTERLACE_BOB					5:5
+#define CAPTURE_CONTROL_INTERLACE_BOB_DISABLE			0
+#define CAPTURE_CONTROL_INTERLACE_BOB_ENABLE			1
+#define CAPTURE_CONTROL_DOUBLE_BUFFERING				4:4
+#define CAPTURE_CONTROL_DOUBLE_BUFFERING_DISABLE		0
+#define CAPTURE_CONTROL_DOUBLE_BUFFERING_ENABLE			1
+#define CAPTURE_CONTROL_CAPTURE_CONTROL					3:3
+#define CAPTURE_CONTROL_CAPTURE_CONTROL_CONTINUOUS		0
+#define CAPTURE_CONTROL_CAPTURE_CONTROL_CONDITIONAL		1
+#define CAPTURE_CONTROL_CAPTURE							0:0
+#define CAPTURE_CONTROL_CAPTURE_DISABLE					0
+#define CAPTURE_CONTROL_CAPTURE_ENABLE					1
+
+#define CAPTURE_CLIPPING								0x090004
+#define CAPTURE_CLIPPING_YCLIP							25:16
+#define CAPTURE_CLIPPING_XCLIP							9:0
+
+#define CAPTURE_SIZE									0x90008
+#define CAPTURE_SIZE_HEIGHT								26:16
+#define CAPTURE_SIZE_WIDTH								10:0
+
+#define CAPTURE_BUFFER_0_ADDRESS						0x9000C
+#define CAPTURE_BUFFER_0_ADDRESS_STATUS					31:31
+#define CAPTURE_BUFFER_0_ADDRESS_STATUS_CURRENT			0
+#define CAPTURE_BUFFER_0_ADDRESS_STATUS_PENDING			1
+#define CAPTURE_BUFFER_0_ADDRESS_EXT					27:27
+#define CAPTURE_BUFFER_0_ADDRESS_EXT_LOCAL				0
+#define CAPTURE_BUFFER_0_ADDRESS_EXT_EXTERNAL			1
+#define CAPTURE_BUFFER_0_ADDRESS_CS						26:26
+#define CAPTURE_BUFFER_0_ADDRESS_CS_0					0
+#define CAPTURE_BUFFER_0_ADDRESS_CS_1					1
+#define CAPTURE_BUFFER_0_ADDRESS_ADDRESS				25:0
+
+#define CAPTURE_BUFFER_1_ADDRESS						0x90010
+#define CAPTURE_BUFFER_1_ADDRESS_STATUS					31:31
+#define CAPTURE_BUFFER_1_ADDRESS_STATUS_CURRENT			0
+#define CAPTURE_BUFFER_1_ADDRESS_STATUS_PENDING			1
+#define CAPTURE_BUFFER_1_ADDRESS_EXT					27:27
+#define CAPTURE_BUFFER_1_ADDRESS_EXT_LOCAL				0
+#define CAPTURE_BUFFER_1_ADDRESS_EXT_EXTERNAL			1
+#define CAPTURE_BUFFER_1_ADDRESS_CS						26:26
+#define CAPTURE_BUFFER_1_ADDRESS_CS_0					0
+#define CAPTURE_BUFFER_1_ADDRESS_CS_1					1
+#define CAPTURE_BUFFER_1_ADDRESS_ADDRESS				25:0
+
+#define CAPTURE_BUFFER_OFFSET							0x90014
+#define CAPTURE_BUFFER_OFFSET_OFFSET					15:0
+
+#define CAPTURE_FIFO									0x90018
+#define CAPTURE_FIFO_CONTROL							2:0
+#define CAPTURE_FIFO_CONTROL_2							0
+#define CAPTURE_FIFO_CONTROL_3							1
+#define CAPTURE_FIFO_CONTROL_4							2
+#define CAPTURE_FIFO_CONTROL_5							3
+#define CAPTURE_FIFO_CONTROL_6							4
+#define CAPTURE_FIFO_CONTROL_8							5
+#define CAPTURE_FIFO_CONTROL_10							6
+#define CAPTURE_FIFO_CONTROL_12							7
+
+
+/*****************************************************************************\
+ *                                AC97 / I2S                                 *
+\*****************************************************************************/
+
+/* AC97 TX Slot 0: TAG */
+#define AC97_TX_SLOT0                                               0x0A0100
+#define AC97_TX_SLOT0_VALID_FRAME_TAG                               15:15
+#define AC97_TX_SLOT0_VALID_FRAME_TAG_IGNORE                        0
+#define AC97_TX_SLOT0_VALID_FRAME_TAG_INTERPRET                     1
+#define AC97_TX_SLOT0_VALID_S1                                      14:14
+#define AC97_TX_SLOT0_VALID_S1_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S1_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S2                                      13:13
+#define AC97_TX_SLOT0_VALID_S2_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S2_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S3                                      12:12
+#define AC97_TX_SLOT0_VALID_S3_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S3_DATA                                 1
+#define AC97_TX_SLOT0_VALID_S4                                      11:11
+#define AC97_TX_SLOT0_VALID_S4_NO_DATA                              0
+#define AC97_TX_SLOT0_VALID_S4_DATA                                 1
+
+/* AC97 TX Slot 1: Command Address Port */
+#define AC97_TX_SLOT1                                               0x0A0104
+#define AC97_TX_SLOT1_READ_WRITE                                    19:19
+#define AC97_TX_SLOT1_READ_WRITE_WRITE                              0
+#define AC97_TX_SLOT1_READ_WRITE_READ                               1
+#define AC97_TX_SLOT1_CONTROL_REGISTER_INDEX                        18:12
+
+/* AC97 TX Slot 2: Command Address Port */
+#define AC97_TX_SLOT2                                               0x0A0108
+#define AC97_TX_SLOT2_DATA                                          19:4
+
+/* AC97 TX Slot 3: PCM Playback Left Channel */
+#define AC97_TX_SLOT3                                               0x0A010C
+#define AC97_TX_SLOT3_DATA                                          19:0
+
+/* AC97 TX Slot 4: PCM Playback Right Channel */
+#define AC97_TX_SLOT4                                               0x0A0110
+#define AC97_TX_SLOT4_DATA                                          19:0
+
+/* AC97 RX Slot 0: TAG */
+#define AC97_RX_SLOT0                                               0x0A0140
+#define AC97_RX_SLOT0_CODEC_READY_FLAG                              15:15
+#define AC97_RX_SLOT0_CODEC_READY_FLAG_IGNORE                       0
+#define AC97_RX_SLOT0_CODEC_READY_FLAG_READY                        1
+#define AC97_RX_SLOT0_VALID_S1                                      14:14
+#define AC97_RX_SLOT0_VALID_S1_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S1_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S2                                      13:13
+#define AC97_RX_SLOT0_VALID_S2_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S2_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S3                                      12:12
+#define AC97_RX_SLOT0_VALID_S3_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S3_DATA                                 1
+#define AC97_RX_SLOT0_VALID_S4                                      11:11
+#define AC97_RX_SLOT0_VALID_S4_NO_DATA                              0
+#define AC97_RX_SLOT0_VALID_S4_DATA                                 1
+
+/* AC97 RX Slot 1: Status Address Port */
+#define AC97_RX_SLOT1                                               0x0A0144
+#define AC97_RX_SLOT1_CONTROL_REGISTER_INDEX                        18:12
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3                             11:11
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3_SEND                        0
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S3_DO_NOT_SEND                 1
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4                             10:10
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4_SEND                        0
+#define AC97_RX_SLOT1_ON_DEMAND_DATA_S4_DO_NOT_SEND                 1
+
+/* AC97 RX Slot 2: Status Address Port */
+#define AC97_RX_SLOT2                                               0x0A0148
+#define AC97_RX_SLOT2_DATA                                          19:4
+
+/* AC97 RX Slot 3: PCM Record Left Channel */
+#define AC97_RX_SLOT3                                               0x0A014C
+#define AC97_RX_SLOT3_DATA                                          19:0
+
+/* AC97 RX Slot 4: PCM Record Right Channel */
+#define AC97_RX_SLOT4                                               0x0A0150
+#define AC97_RX_SLOT4_DATA                                          19:0
+
+/* AC97 Control & Status */
+#define AC97_CONTROL_STATUS                                         0x0A0180
+#define AC97_CONTROL_STATUS_DATA_DROPPED_COUNT                      15:10
+#define AC97_CONTROL_STATUS_SYNC_CONTROL                            9:9
+#define AC97_CONTROL_STATUS_SYNC_CONTROL_ENABLE                     0
+#define AC97_CONTROL_STATUS_SYNC_CONTROL_STOP                       1
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL                           8:8
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL_NOT_RUNNING               0
+#define AC97_CONTROL_STATUS_CLOCK_CONTROL_RUNNING                   1
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST                          7:7
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST_DISABLE                  0
+#define AC97_CONTROL_STATUS_WAKEUP_REQUEST_ENABLE                   1
+#define AC97_CONTROL_STATUS_STATUS                                  5:4
+#define AC97_CONTROL_STATUS_STATUS_OFF                              0
+#define AC97_CONTROL_STATUS_STATUS_RESET                            1
+#define AC97_CONTROL_STATUS_STATUS_WAITING                          2
+#define AC97_CONTROL_STATUS_STATUS_ACTIVE                           3
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT                        3:3
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT_DISABLED               0
+#define AC97_CONTROL_STATUS_WAKEUP_INTERRUPT_ENABLED                1
+#define AC97_CONTROL_STATUS_WARM_RESET                              2:2
+#define AC97_CONTROL_STATUS_WARM_RESET_NORMAL                       0
+#define AC97_CONTROL_STATUS_WARM_RESET_RESET                        1
+#define AC97_CONTROL_STATUS_COLD_RESET                              1:1
+#define AC97_CONTROL_STATUS_COLD_RESET_NORMAL                       0
+#define AC97_CONTROL_STATUS_COLD_RESET_RESET                        1
+#define AC97_CONTROL_STATUS_CONTROL                                 0:0
+#define AC97_CONTROL_STATUS_CONTROL_DISABLED                        0
+#define AC97_CONTROL_STATUS_CONTROL_ENABLED                         1
+
+/* I2S TX Data Left */
+#define I2S_TX_DATA_LEFT                                            0x0A0200
+#define I2S_TX_DATA_LEFT_DATA                                       15:0
+
+/* I2S TX Data Right */
+#define I2S_TX_DATA_RIGHT                                           0x0A0204
+#define I2S_TX_DATA_RIGHT_DATA                                      15:0
+
+/* I2S RX Data Left */
+#define I2S_RX_DATA_LEFT                                            0x0A0208
+#define I2S_RX_DATA_LEFT_DATA                                       15:0
+
+/* I2S RX Data Right */
+#define I2S_RX_DATA_RIGHT                                           0x0A020C
+#define I2S_RX_DATA_RIGHT_DATA                                      15:0
+
+/* I2S Control & Status */
+#define I2S_CONTROL_STATUS                                          0x0A0210
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS                           11:11
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS_NO_ERROR                  0
+#define I2S_CONTROL_STATUS_RECEIVE_STATUS_OVERFLOW                  1
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS                          10:10
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS_NO_ERROR                 0
+#define I2S_CONTROL_STATUS_TRANSMIT_STATUS_UNDERFLOW                1
+#define I2S_CONTROL_STATUS_CONTROL                                  2:2
+#define I2S_CONTROL_STATUS_CONTROL_DISABLED                         0
+#define I2S_CONTROL_STATUS_CONTROL_ENABLED                          1
+
+/* I2S Clock Control */
+#define I2S_CLOCK_CONTROL                                           0x0A0214
+#define I2S_CLOCK_CONTROL_MODE_SELECT                               7:7
+#define I2S_CLOCK_CONTROL_MODE_SELECT_SLAVE                         0
+#define I2S_CLOCK_CONTROL_MODE_SELECT_MASTER                        1
+#define I2S_CLOCK_CONTROL_WORD_SELECT                               6:5
+#define I2S_CLOCK_CONTROL_WORD_SELECT_16BIT                         0
+#define I2S_CLOCK_CONTROL_WORD_SELECT_24BIT                         1
+#define I2S_CLOCK_CONTROL_WORD_SELECT_32BIT                         2
+#define I2S_CLOCK_CONTROL_CLOCK_DIVIDER                             4:0
+
+/*****************************************************************************\
+ *                                    8051                                   *
+\*****************************************************************************/
+
+/* Reset */
+#define U8051_RESET                                                 0x0B0000
+#define U8051_RESET_CONTROL                                         0:0
+#define U8051_RESET_CONTROL_RESET                                   0
+#define U8051_RESET_CONTROL_ENABLE                                  1
+
+/* Mode Select */
+#define U8051_MODE_SELECT                                           0x0B0004
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE                      7:6
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_NONE                 0
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_1WS                  1
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_2WS                  2
+#define U8051_MODE_SELECT_USB_SLAVE_WAIT_STATE_3WS                  3
+#define U8051_MODE_SELECT_SRAM                                      5:5
+#define U8051_MODE_SELECT_SRAM_ENABLED                              0
+#define U8051_MODE_SELECT_SRAM_DISABLED                             1
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE                        4:4
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE_12BIT                  0
+#define U8051_MODE_SELECT_EXTERNAL_INTERFACE_8BIT                   1
+#define U8051_MODE_SELECT_TEST_MODE                                 3:3
+#define U8051_MODE_SELECT_TEST_MODE_NORMAL                          0
+#define U8051_MODE_SELECT_TEST_MODE_ENABLED                         1
+#define U8051_MODE_SELECT_CODEC_SELECT                              2:2
+#define U8051_MODE_SELECT_CODEC_SELECT_AC97                         0
+#define U8051_MODE_SELECT_CODEC_SELECT_I2S                          1
+#define U8051_MODE_SELECT_DIVIDER                                   1:0
+#define U8051_MODE_SELECT_DIVIDER_2                                 0
+#define U8051_MODE_SELECT_DIVIDER_3                                 1
+#define U8051_MODE_SELECT_DIVIDER_4                                 2
+#define U8051_MODE_SELECT_DIVIDER_5                                 3
+
+/* 8051 Protocol Interrupt */
+#define U8051_8051_PROTOCOL_INTERRUPT                               0x0B0008
+#define U8051_8051_PROTOCOL_INTERRUPT_TOKEN                         31:0
+
+/* 8051 Protocol Interrupt */
+#define IRQ_8051_TO_HIF                                0x000B0008
+#define IRQ_8051_TO_HIF_CODE                           7:0
+#define IRQ_8051_TO_HIF_PARAMETER1                     15:8
+#define IRQ_8051_TO_HIF_PARAMETER2                     23:16
+#define IRQ_8051_TO_HIF_PARAMETER3                     31:24
+
+/* CPU Protocol Interrupt */
+#define U8051_CPU_PROTOCOL_INTERRUPT                                0x0B000C
+#define U8051_CPU_PROTOCOL_INTERRUPT_TOKEN                          31:0
+
+/* CPU Protocol Interrupt */
+#define IRQ_HIF_TO_8051                                0x000B000C
+#define IRQ_HIF_TO_8051_CODE                           31:0
+#define IRQ_HIF_TO_8051_CODE1                          7:0
+#define IRQ_HIF_TO_8051_CODE2                          15:8
+#define IRQ_HIF_TO_8051_CODE3                          23:16
+#define IRQ_HIF_TO_8051_CODE4                          31:24
+
+/* SRAM Address Space */
+#define U8051_SRAM                                    0x000C0000	// 8051: 0000-0FFF
+#define U8051_SRAM1                                    0x000C1000	// 8051: 1000-1FFF
+#define U8051_SRAM2                                    0x000C2000	// 8051: 2000-2FFF
+#define U8051_SRAM3                                    0x000C3000	// 8051: 3000-3FFF (dual port SRAM)
+
+#define U8051_SRAM_SIZE                                             0x004000
+
+/*****************************************************************************\
+ *                                     DMA                                   *
+\*****************************************************************************/
+
+/* DMA 0 SDRAM Address */
+#define DMA0_SDRAM                                                  0x0D0000
+#define DMA0_SDRAM_MEMORY                                           27:26
+#define DMA0_SDRAM_MEMORY_LOCAL                                     0
+#define DMA0_SDRAM_MEMORY_EXTERNAL_CS0                              2
+#define DMA0_SDRAM_MEMORY_EXTERNAL_CS1                              3
+#define DMA0_SDRAM_ADDRESS                                          25:0
+
+/* DMA 0 SRAM Address */
+#define DMA0_SRAM                                                   0x0D0004
+#define DMA0_SRAM_ADDRESS                                           15:0
+
+/* DMA 0 Size & Control */
+#define DMA0_SIZE_CONTROL                                           0x0D0008
+#define DMA0_SIZE_CONTROL_ACTIVE                                    31:31
+#define DMA0_SIZE_CONTROL_ACTIVE_IDLE                               0
+#define DMA0_SIZE_CONTROL_ACTIVE_START                              1
+#define DMA0_SIZE_CONTROL_DIRECTION                                 30:30
+#define DMA0_SIZE_CONTROL_DIRECTION_WRITE_SRAM                      0
+#define DMA0_SIZE_CONTROL_DIRECTION_READ_SRAM                       1
+#define DMA0_SIZE_CONTROL_SIZE                                      15:0
+
+/* DMA 1 Source Address */
+#define DMA1_SOURCE                                                 0x0D0010
+#define DMA1_SOURCE_MEMORY                                          27:26
+#define DMA1_SOURCE_MEMORY_LOCAL                                    0
+#define DMA1_SOURCE_MEMORY_EXTERNAL_CS0                             2
+#define DMA1_SOURCE_MEMORY_EXTERNAL_CS1                             3
+#define DMA1_SOURCE_ADDRESS                                         25:0
+
+/* DMA 1 Destination Address */
+#define DMA1_DESTINATION                                            0x0D0014
+#define DMA1_DESTINATION_MEMORY                                     27:26
+#define DMA1_DESTINATION_MEMORY_LOCAL                               0
+#define DMA1_DESTINATION_MEMORY_EXTERNAL_CS0                        2
+#define DMA1_DESTINATION_MEMORY_EXTERNAL_CS1                        3
+#define DMA1_DESTINATION_ADDRESS                                    25:0
+
+/* DMA 1 Size & Control */
+#define DMA1_SIZE_CONTROL                                           0x0D0018
+#define DMA1_SIZE_CONTROL_ACTIVE                                    31:31
+#define DMA1_SIZE_CONTROL_ACTIVE_IDLE                               0
+#define DMA1_SIZE_CONTROL_ACTIVE_START                              1
+#define DMA1_SIZE_CONTROL_SIZE                                      23:0
+
+/* DMA Abort & Interrupt */
+#define DMA_ABORT_INTERRUPT                                         0x0D0020
+#define DMA_ABORT_INTERRUPT_ABORT_1                                 5:5
+#define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE                          0
+#define DMA_ABORT_INTERRUPT_ABORT_1_ABORT                           1
+#define DMA_ABORT_INTERRUPT_ABORT_0                                 4:4
+#define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE                          0
+#define DMA_ABORT_INTERRUPT_ABORT_0_ABORT                           1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1                      1:1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1_NOT_ACTIVE           0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_1_ACTIVE               1
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0                      0:0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0_NOT_ACTIVE           0
+#define DMA_ABORT_INTERRUPT_INTERRUPT_STATUS_0_ACTIVE               1
+
+
+/*****************************************************************************\
+ *                                  2D ENGINE                                *
+\*****************************************************************************/
+
+#define DE_SOURCE                                       0x000000
+#define DE_SOURCE_WRAP                                  31:31
+#define DE_SOURCE_WRAP_DISABLE                          0
+#define DE_SOURCE_WRAP_ENABLE                           1
+#define DE_SOURCE_X_K1                                  29:16
+#define DE_SOURCE_Y_K2                                  15:0
+
+#define DE_DESTINATION                                  0x000004
+#define DE_DESTINATION_WRAP                             31:31
+#define DE_DESTINATION_WRAP_DISABLE                     0
+#define DE_DESTINATION_WRAP_ENABLE                      1
+#define DE_DESTINATION_X                                28:16
+#define DE_DESTINATION_Y                                15:0
+
+#define DE_DIMENSION                                    0x000008
+#define DE_DIMENSION_X                                  28:16
+#define DE_DIMENSION_Y_ET                               15:0
+
+#define DE_CONTROL                                      0x00000C
+#define DE_CONTROL_STATUS                               31:31
+#define DE_CONTROL_STATUS_STOP                          0
+#define DE_CONTROL_STATUS_START                         1
+#define DE_CONTROL_PATTERN                              30:30
+#define DE_CONTROL_PATTERN_MONO                         0
+#define DE_CONTROL_PATTERN_COLOR                        1
+#define DE_CONTROL_UPDATE_DESTINATION_X                 29:29
+#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE         0
+#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE          1
+#define DE_CONTROL_QUICK_START                          28:28
+#define DE_CONTROL_QUICK_START_DISABLE                  0
+#define DE_CONTROL_QUICK_START_ENABLE                   1
+#define DE_CONTROL_DIRECTION                            27:27
+#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT              0
+#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT              1
+#define DE_CONTROL_MAJOR                                26:26
+#define DE_CONTROL_MAJOR_X                              0
+#define DE_CONTROL_MAJOR_Y                              1
+#define DE_CONTROL_STEP_X                               25:25
+#define DE_CONTROL_STEP_X_POSITIVE                      1
+#define DE_CONTROL_STEP_X_NEGATIVE                      0
+#define DE_CONTROL_STEP_Y                               24:24
+#define DE_CONTROL_STEP_Y_POSITIVE                      1
+#define DE_CONTROL_STEP_Y_NEGATIVE                      0
+#define DE_CONTROL_STRETCH                              23:23
+#define DE_CONTROL_STRETCH_DISABLE                      0
+#define DE_CONTROL_STRETCH_ENABLE                       1
+#define DE_CONTROL_HOST                                 22:22
+#define DE_CONTROL_HOST_COLOR                           0
+#define DE_CONTROL_HOST_MONO                            1
+#define DE_CONTROL_LAST_PIXEL                           21:21
+#define DE_CONTROL_LAST_PIXEL_OFF                       0
+#define DE_CONTROL_LAST_PIXEL_ON                        1
+#define DE_CONTROL_COMMAND                              20:16
+#define DE_CONTROL_COMMAND_BITBLT                       0
+#define DE_CONTROL_COMMAND_RECTANGLE_FILL               1
+#define DE_CONTROL_COMMAND_DE_TILE                      2
+#define DE_CONTROL_COMMAND_TRAPEZOID_FILL               3
+#define DE_CONTROL_COMMAND_ALPHA_BLEND                  4
+#define DE_CONTROL_COMMAND_RLE_STRIP                    5
+#define DE_CONTROL_COMMAND_SHORT_STROKE                 6
+#define DE_CONTROL_COMMAND_LINE_DRAW                    7
+#define DE_CONTROL_COMMAND_HOST_WRITE                   8
+#define DE_CONTROL_COMMAND_HOST_READ                    9
+#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP         10
+#define DE_CONTROL_COMMAND_ROTATE                       11
+#define DE_CONTROL_COMMAND_FONT                         12
+#define DE_CONTROL_COMMAND_TEXTURE_LOAD                 15
+#define DE_CONTROL_ROP_SELECT                           15:15
+#define DE_CONTROL_ROP_SELECT_ROP3                      0
+#define DE_CONTROL_ROP_SELECT_ROP2                      1
+#define DE_CONTROL_ROP2_SOURCE                          14:14
+#define DE_CONTROL_ROP2_SOURCE_BITMAP                   0
+#define DE_CONTROL_ROP2_SOURCE_PATTERN                  1
+#define DE_CONTROL_MONO_DATA                            13:12
+#define DE_CONTROL_MONO_DATA_NOT_PACKED                 0
+#define DE_CONTROL_MONO_DATA_8_PACKED                   1
+#define DE_CONTROL_MONO_DATA_16_PACKED                  2
+#define DE_CONTROL_MONO_DATA_32_PACKED                  3
+#define DE_CONTROL_REPEAT_ROTATE                        11:11
+#define DE_CONTROL_REPEAT_ROTATE_DISABLE                0
+#define DE_CONTROL_REPEAT_ROTATE_ENABLE                 1
+#define DE_CONTROL_TRANSPARENCY_MATCH                   10:10
+#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE            0
+#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT       1
+#define DE_CONTROL_TRANSPARENCY_SELECT                  9:9
+#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE           0
+#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION      1
+#define DE_CONTROL_TRANSPARENCY                         8:8
+#define DE_CONTROL_TRANSPARENCY_DISABLE                 0
+#define DE_CONTROL_TRANSPARENCY_ENABLE                  1
+#define DE_CONTROL_ROP                                  7:0
+
+// Pseudo fields.
+
+#define DE_CONTROL_SHORT_STROKE_DIR                     27:24
+#define DE_CONTROL_SHORT_STROKE_DIR_225                 0
+#define DE_CONTROL_SHORT_STROKE_DIR_135                 1
+#define DE_CONTROL_SHORT_STROKE_DIR_315                 2
+#define DE_CONTROL_SHORT_STROKE_DIR_45                  3
+#define DE_CONTROL_SHORT_STROKE_DIR_270                 4
+#define DE_CONTROL_SHORT_STROKE_DIR_90                  5
+#define DE_CONTROL_SHORT_STROKE_DIR_180                 8
+#define DE_CONTROL_SHORT_STROKE_DIR_0                   10
+#define DE_CONTROL_ROTATION                             25:24
+#define DE_CONTROL_ROTATION_0                           0
+#define DE_CONTROL_ROTATION_270                         1
+#define DE_CONTROL_ROTATION_90                          2
+#define DE_CONTROL_ROTATION_180                         3
+
+#define DE_PITCH                                        0x000010
+#define DE_PITCH_DESTINATION                            28:16
+#define DE_PITCH_SOURCE                                 12:0
+
+#define DE_FOREGROUND                                   0x000014
+#define DE_FOREGROUND_COLOR                             31:0
+
+#define DE_BACKGROUND                                   0x000018
+#define DE_BACKGROUND_COLOR                             31:0
+
+#define DE_STRETCH_FORMAT                               0x00001C
+#define DE_STRETCH_FORMAT_PATTERN_XY                    30:30
+#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL             0
+#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE          1
+#define DE_STRETCH_FORMAT_PATTERN_Y                     29:27
+#define DE_STRETCH_FORMAT_PATTERN_X                     25:23
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT                  21:20
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8                0
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16               1
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32               2
+#define DE_STRETCH_FORMAT_ADDRESSING                    19:16
+#define DE_STRETCH_FORMAT_ADDRESSING_XY                 0
+#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR             15
+#define DE_STRETCH_FORMAT_SOURCE_HEIGHT                 11:0
+
+#define DE_COLOR_COMPARE                                0x000020
+#define DE_COLOR_COMPARE_COLOR                          23:0
+
+#define DE_COLOR_COMPARE_MASK                           0x000024
+#define DE_COLOR_COMPARE_MASK_MASKS                     23:0
+
+#define DE_MASKS                                        0x000028
+#define DE_MASKS_BYTE_MASK                              31:16
+#define DE_MASKS_BIT_MASK                               15:0
+
+#define DE_CLIP_TL                                      0x00002C
+#define DE_CLIP_TL_TOP                                  31:16
+#define DE_CLIP_TL_STATUS                               13:13
+#define DE_CLIP_TL_STATUS_DISABLE                       0
+#define DE_CLIP_TL_STATUS_ENABLE                        1
+#define DE_CLIP_TL_INHIBIT                              12:12
+#define DE_CLIP_TL_INHIBIT_OUTSIDE                      0
+#define DE_CLIP_TL_INHIBIT_INSIDE                       1
+#define DE_CLIP_TL_LEFT                                 11:0
+
+#define DE_CLIP_BR                                      0x000030
+#define DE_CLIP_BR_BOTTOM                               31:16
+#define DE_CLIP_BR_RIGHT                                12:0
+
+#define DE_MONO_PATTERN_LOW                             0x000034
+#define DE_MONO_PATTERN_LOW_PATTERN                     31:0
+
+#define DE_MONO_PATTERN_HIGH                            0x000038
+#define DE_MONO_PATTERN_HIGH_PATTERN                    31:0
+
+#define DE_WINDOW_WIDTH                                 0x00003C
+#define DE_WINDOW_WIDTH_DESTINATION                     28:16
+#define DE_WINDOW_WIDTH_SOURCE                          12:0
+
+#define DE_WINDOW_SOURCE_BASE                           0x000040
+#define DE_WINDOW_SOURCE_BASE_EXT                       27:27
+#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL                 0
+#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL              1
+#define DE_WINDOW_SOURCE_BASE_CS                        26:26
+#define DE_WINDOW_SOURCE_BASE_CS_0                      0
+#define DE_WINDOW_SOURCE_BASE_CS_1                      1
+#define DE_WINDOW_SOURCE_BASE_ADDRESS                   25:0
+
+#define DE_WINDOW_DESTINATION_BASE                      0x000044
+#define DE_WINDOW_DESTINATION_BASE_EXT                  27:27
+#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL            0
+#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL         1
+#define DE_WINDOW_DESTINATION_BASE_CS                   26:26
+#define DE_WINDOW_DESTINATION_BASE_CS_0                 0
+#define DE_WINDOW_DESTINATION_BASE_CS_1                 1
+#define DE_WINDOW_DESTINATION_BASE_ADDRESS              25:0
+
+#define DE_ALPHA                                        0x000048
+#define DE_ALPHA_VALUE                                  7:0
+
+#define DE_WRAP                                         0x00004C
+#define DE_WRAP_X                                       31:16
+#define DE_WRAP_Y                                       15:0
+
+#define DE_STATUS                                       0x000050
+#define DE_STATUS_CSC                                   1:1
+#define DE_STATUS_CSC_CLEAR                             0
+#define DE_STATUS_CSC_NOT_ACTIVE                        0
+#define DE_STATUS_CSC_ACTIVE                            1
+#define DE_STATUS_2D                                    0:0
+#define DE_STATUS_2D_CLEAR                              0
+#define DE_STATUS_2D_NOT_ACTIVE                         0
+#define DE_STATUS_2D_ACTIVE                             1
+
+// Color Space Conversion registers.
+
+#define CSC_Y_SOURCE_BASE                               0x0000C8
+#define CSC_Y_SOURCE_BASE_EXT                           27:27
+#define CSC_Y_SOURCE_BASE_EXT_LOCAL                     0
+#define CSC_Y_SOURCE_BASE_EXT_EXTERNAL                  1
+#define CSC_Y_SOURCE_BASE_CS                            26:26
+#define CSC_Y_SOURCE_BASE_CS_0                          0
+#define CSC_Y_SOURCE_BASE_CS_1                          1
+#define CSC_Y_SOURCE_BASE_ADDRESS                       25:0
+
+#define CSC_CONSTANTS                                   0x0000CC
+#define CSC_CONSTANTS_Y                                 31:24
+#define CSC_CONSTANTS_R                                 23:16
+#define CSC_CONSTANTS_G                                 15:8
+#define CSC_CONSTANTS_B                                 7:0
+
+#define CSC_Y_SOURCE_X                                  0x0000D0
+#define CSC_Y_SOURCE_X_INTEGER                          26:16
+#define CSC_Y_SOURCE_X_FRACTION                         15:3
+
+#define CSC_Y_SOURCE_Y                                  0x0000D4
+#define CSC_Y_SOURCE_Y_INTEGER                          27:16
+#define CSC_Y_SOURCE_Y_FRACTION                         15:3
+
+#define CSC_U_SOURCE_BASE                               0x0000D8
+#define CSC_U_SOURCE_BASE_EXT                           27:27
+#define CSC_U_SOURCE_BASE_EXT_LOCAL                     0
+#define CSC_U_SOURCE_BASE_EXT_EXTERNAL                  1
+#define CSC_U_SOURCE_BASE_CS                            26:26
+#define CSC_U_SOURCE_BASE_CS_0                          0
+#define CSC_U_SOURCE_BASE_CS_1                          1
+#define CSC_U_SOURCE_BASE_ADDRESS                       25:0
+
+#define CSC_V_SOURCE_BASE                               0x0000DC
+#define CSC_V_SOURCE_BASE_EXT                           27:27
+#define CSC_V_SOURCE_BASE_EXT_LOCAL                     0
+#define CSC_V_SOURCE_BASE_EXT_EXTERNAL                  1
+#define CSC_V_SOURCE_BASE_CS                            26:26
+#define CSC_V_SOURCE_BASE_CS_0                          0
+#define CSC_V_SOURCE_BASE_CS_1                          1
+#define CSC_V_SOURCE_BASE_ADDRESS                       25:0
+
+#define CSC_SOURCE_DIMENSION                            0x0000E0
+#define CSC_SOURCE_DIMENSION_X                          31:16
+#define CSC_SOURCE_DIMENSION_Y                          15:0
+
+#define CSC_SOURCE_PITCH                                0x0000E4
+#define CSC_SOURCE_PITCH_Y                              31:16
+#define CSC_SOURCE_PITCH_UV                             15:0
+
+#define CSC_DESTINATION                                 0x0000E8
+#define CSC_DESTINATION_WRAP                            31:31
+#define CSC_DESTINATION_WRAP_DISABLE                    0
+#define CSC_DESTINATION_WRAP_ENABLE                     1
+#define CSC_DESTINATION_X                               27:16
+#define CSC_DESTINATION_Y                               11:0
+
+#define CSC_DESTINATION_DIMENSION                       0x0000EC
+#define CSC_DESTINATION_DIMENSION_X                     31:16
+#define CSC_DESTINATION_DIMENSION_Y                     15:0
+
+#define CSC_DESTINATION_PITCH                           0x0000F0
+#define CSC_DESTINATION_PITCH_X                         31:16
+#define CSC_DESTINATION_PITCH_Y                         15:0
+
+#define CSC_SCALE_FACTOR                                0x0000F4
+#define CSC_SCALE_FACTOR_HORIZONTAL                     31:16
+#define CSC_SCALE_FACTOR_VERTICAL                       15:0
+
+#define CSC_DESTINATION_BASE                            0x0000F8
+#define CSC_DESTINATION_BASE_EXT                        27:27
+#define CSC_DESTINATION_BASE_EXT_LOCAL                  0
+#define CSC_DESTINATION_BASE_EXT_EXTERNAL               1
+#define CSC_DESTINATION_BASE_CS                         26:26
+#define CSC_DESTINATION_BASE_CS_0                       0
+#define CSC_DESTINATION_BASE_CS_1                       1
+#define CSC_DESTINATION_BASE_ADDRESS                    25:0
+
+#define CSC_CONTROL                                     0x0000FC
+#define CSC_CONTROL_STATUS                              31:31
+#define CSC_CONTROL_STATUS_STOP                         0
+#define CSC_CONTROL_STATUS_START                        1
+#define CSC_CONTROL_SOURCE_FORMAT                       30:28
+#define CSC_CONTROL_SOURCE_FORMAT_YUV422                0
+#define CSC_CONTROL_SOURCE_FORMAT_YUV420I               1
+#define CSC_CONTROL_SOURCE_FORMAT_YUV420                2
+#define CSC_CONTROL_SOURCE_FORMAT_YVU9                  3
+#define CSC_CONTROL_SOURCE_FORMAT_IYU1                  4
+#define CSC_CONTROL_SOURCE_FORMAT_IYU2                  5
+#define CSC_CONTROL_SOURCE_FORMAT_RGB565                6
+#define CSC_CONTROL_SOURCE_FORMAT_RGB8888               7
+#define CSC_CONTROL_DESTINATION_FORMAT                  27:26
+#define CSC_CONTROL_DESTINATION_FORMAT_RGB565           0
+#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888          1
+#define CSC_CONTROL_HORIZONTAL_FILTER                   25:25
+#define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE           0
+#define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE            1
+#define CSC_CONTROL_VERTICAL_FILTER                     24:24
+#define CSC_CONTROL_VERTICAL_FILTER_DISABLE             0
+#define CSC_CONTROL_VERTICAL_FILTER_ENABLE              1
+#define CSC_CONTROL_BYTE_ORDER                          23:23
+#define CSC_CONTROL_BYTE_ORDER_YUYV                     0
+#define CSC_CONTROL_BYTE_ORDER_UYVY                     1
+
+/*****************************************************************************\
+ *                             2D ENGINE DATA PORT                           *
+\*****************************************************************************/
+
+#define DE_BASE_ADDRESS	                                          0x100000
+#define DE_DATA_PORT                                                0x110000
+#define DE_DATA_PORT_SIZE                                           0x040000
+
+#endif /* _SM50x_H_ */
diff -uNra linux-2.6.27.6/include/linux/tty_driver.h linux-2.6.27.6.yaffs/include/linux/tty_driver.h
--- linux-2.6.27.6/include/linux/tty_driver.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/tty_driver.h	2011-05-08 18:02:37.000000000 +0800
@@ -258,7 +258,7 @@
 	 * Driver methods
 	 */
 
-	const struct tty_operations *ops;
+	struct tty_operations *ops;
 	struct list_head tty_drivers;
 };
 
diff -uNra linux-2.6.27.6/include/linux/types.h linux-2.6.27.6.yaffs/include/linux/types.h
--- linux-2.6.27.6/include/linux/types.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/types.h	2011-05-08 18:02:37.000000000 +0800
@@ -125,6 +125,10 @@
 typedef		__s64		int64_t;
 #endif
 
+#ifdef CONFIG_64BIT
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+#endif
+
 /* this is a special 64bit data type that is 8-byte aligned */
 #define aligned_u64 __u64 __attribute__((aligned(8)))
 #define aligned_be64 __be64 __attribute__((aligned(8)))
diff -uNra linux-2.6.27.6/include/linux/utsrelease.h linux-2.6.27.6.yaffs/include/linux/utsrelease.h
--- linux-2.6.27.6/include/linux/utsrelease.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/utsrelease.h	2011-05-08 18:02:37.000000000 +0800
@@ -0,0 +1 @@
+#define UTS_RELEASE "2.6.27.6-loongson-2f"
diff -uNra linux-2.6.27.6/include/linux/version.h linux-2.6.27.6.yaffs/include/linux/version.h
--- linux-2.6.27.6/include/linux/version.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/include/linux/version.h	2011-05-08 18:02:37.000000000 +0800
@@ -0,0 +1,2 @@
+#define LINUX_VERSION_CODE 132635
+#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
diff -uNra linux-2.6.27.6/init/main.c linux-2.6.27.6.yaffs/init/main.c
--- linux-2.6.27.6/init/main.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/init/main.c	2011-05-08 18:01:45.000000000 +0800
@@ -536,11 +536,14 @@
 {
 }
 
+extern int rtc_mytest();
 asmlinkage void __init start_kernel(void)
 {
 	char * command_line;
 	extern struct kernel_param __start___param[], __stop___param[];
-
+#ifdef CONFIG_CPU_LOONGSON2
+	__asm__ __volatile__ ("mtc0 %0, $22"::"r"(0x1));
+#endif
 	smp_setup_processor_id();
 
 	/*
diff -uNra linux-2.6.27.6/lib/decompress_inflate.c linux-2.6.27.6.yaffs/lib/decompress_inflate.c
--- linux-2.6.27.6/lib/decompress_inflate.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/lib/decompress_inflate.c	2011-05-16 21:57:57.000000000 +0800
@@ -0,0 +1,176 @@
+#ifdef STATIC
+/* Pre-boot environment: included */
+
+/* prevent inclusion of _LINUX_KERNEL_H in pre-boot environment: lots
+ * errors about console_printk etc... on ARM */
+#define _LINUX_KERNEL_H
+
+#include "zlib_inflate/inftrees.c"
+#include "zlib_inflate/inffast.c"
+#include "zlib_inflate/inflate.c"
+
+#else /* STATIC */
+/* initramfs et al: linked */
+
+#include <linux/zutil.h>
+
+#include "zlib_inflate/inftrees.h"
+#include "zlib_inflate/inffast.h"
+#include "zlib_inflate/inflate.h"
+
+#include "zlib_inflate/infutil.h"
+#include <linux/slab.h>
+
+#endif /* STATIC */
+
+#include <linux/decompress/mm.h>
+
+#define GZIP_IOBUF_SIZE (16*1024)
+
+static int nofill(void *buffer, unsigned int len)
+{
+	return -1;
+}
+
+/* Included from initramfs et al code */
+STATIC int INIT gunzip(unsigned char *buf, int len,
+		       int(*fill)(void*, unsigned int),
+		       int(*flush)(void*, unsigned int),
+		       unsigned char *out_buf,
+		       int *pos,
+		       void(*error_fn)(char *x)) {
+	u8 *zbuf;
+	struct z_stream_s *strm;
+	int rc;
+	size_t out_len;
+
+	set_error_fn(error_fn);
+	rc = -1;
+	if (flush) {
+		out_len = 0x8000; /* 32 K */
+		out_buf = malloc(out_len);
+	} else {
+		out_len = 0x7fffffff; /* no limit */
+	}
+	if (!out_buf) {
+		error("Out of memory while allocating output buffer");
+		goto gunzip_nomem1;
+	}
+
+	if (buf)
+		zbuf = buf;
+	else {
+		zbuf = malloc(GZIP_IOBUF_SIZE);
+		len = 0;
+	}
+	if (!zbuf) {
+		error("Out of memory while allocating input buffer");
+		goto gunzip_nomem2;
+	}
+
+	strm = malloc(sizeof(*strm));
+	if (strm == NULL) {
+		error("Out of memory while allocating z_stream");
+		goto gunzip_nomem3;
+	}
+
+	strm->workspace = malloc(flush ? zlib_inflate_workspacesize() :
+				 sizeof(struct inflate_state));
+	if (strm->workspace == NULL) {
+		error("Out of memory while allocating workspace");
+		goto gunzip_nomem4;
+	}
+
+	if (!fill)
+		fill = nofill;
+
+	if (len == 0)
+		len = fill(zbuf, GZIP_IOBUF_SIZE);
+
+	/* verify the gzip header */
+	if (len < 10 ||
+	   zbuf[0] != 0x1f || zbuf[1] != 0x8b || zbuf[2] != 0x08) {
+		if (pos)
+			*pos = 0;
+		error("Not a gzip file");
+		goto gunzip_5;
+	}
+
+	/* skip over gzip header (1f,8b,08... 10 bytes total +
+	 * possible asciz filename)
+	 */
+	strm->next_in = zbuf + 10;
+	/* skip over asciz filename */
+	if (zbuf[3] & 0x8) {
+		while (strm->next_in[0])
+			strm->next_in++;
+		strm->next_in++;
+	}
+	strm->avail_in = len - (strm->next_in - zbuf);
+
+	strm->next_out = out_buf;
+	strm->avail_out = out_len;
+
+	rc = zlib_inflateInit2(strm, -MAX_WBITS);
+
+	if (!flush) {
+		WS(strm)->inflate_state.wsize = 0;
+		WS(strm)->inflate_state.window = NULL;
+	}
+
+	while (rc == Z_OK) {
+		if (strm->avail_in == 0) {
+			/* TODO: handle case where both pos and fill are set */
+			len = fill(zbuf, GZIP_IOBUF_SIZE);
+			if (len < 0) {
+				rc = -1;
+				error("read error");
+				break;
+			}
+			strm->next_in = zbuf;
+			strm->avail_in = len;
+		}
+		rc = zlib_inflate(strm, 0);
+
+		/* Write any data generated */
+		if (flush && strm->next_out > out_buf) {
+			int l = strm->next_out - out_buf;
+			if (l != flush(out_buf, l)) {
+				rc = -1;
+				error("write error");
+				break;
+			}
+			strm->next_out = out_buf;
+			strm->avail_out = out_len;
+		}
+
+		/* after Z_FINISH, only Z_STREAM_END is "we unpacked it all" */
+		if (rc == Z_STREAM_END) {
+			rc = 0;
+			break;
+		} else if (rc != Z_OK) {
+			error("uncompression error");
+			rc = -1;
+		}
+	}
+
+	zlib_inflateEnd(strm);
+	if (pos)
+		/* add + 8 to skip over trailer */
+		*pos = strm->next_in - zbuf+8;
+
+gunzip_5:
+	free(strm->workspace);
+gunzip_nomem4:
+	free(strm);
+gunzip_nomem3:
+	if (!buf)
+		free(zbuf);
+gunzip_nomem2:
+	if (flush)
+		free(out_buf);
+gunzip_nomem1:
+	return rc; /* returns Z_OK (0) if successful */
+}
+
+#define decompress gunzip
diff -uNra linux-2.6.27.6/lib/zlib_inflate/inffast.c linux-2.6.27.6.yaffs/lib/zlib_inflate/inffast.c
--- linux-2.6.27.6/lib/zlib_inflate/inffast.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/lib/zlib_inflate/inffast.c	2011-05-16 21:48:36.000000000 +0800
@@ -21,12 +21,32 @@
    - Pentium III (Anderson)
    - M68060 (Nikl)
  */
+union uu {
+	unsigned short us;
+	unsigned char b[2];
+};
+
+/* Endian independed version */
+static inline unsigned short
+get_unaligned16(const unsigned short *p)
+{
+	union uu  mm;
+	unsigned char *b = (unsigned char *)p;
+
+	mm.b[0] = b[0];
+	mm.b[1] = b[1];
+	return mm.us;
+}
+
+
 #ifdef POSTINC
 #  define OFF 0
 #  define PUP(a) *(a)++
+#  define UP_UNALIGNED(a) get_unaligned16((a)++)
 #else
 #  define OFF 1
 #  define PUP(a) *++(a)
+#  define UP_UNALIGNED(a) get_unaligned16(++(a))
 #endif
 
 /*
@@ -239,18 +259,50 @@
                     }
                 }
                 else {
+		    unsigned short *sout;
+		    unsigned long loops;
+
                     from = out - dist;          /* copy direct from output */
-                    do {                        /* minimum length is three */
-                        PUP(out) = PUP(from);
-                        PUP(out) = PUP(from);
-                        PUP(out) = PUP(from);
-                        len -= 3;
-                    } while (len > 2);
-                    if (len) {
-                        PUP(out) = PUP(from);
-                        if (len > 1)
-                            PUP(out) = PUP(from);
-                    }
+		    /* minimum length is three */
+		    /* Align out addr */
+		    if (!((long)(out - 1 + OFF) & 1)) {
+			PUP(out) = PUP(from);
+			len--;
+		    }
+		    sout = (unsigned short *)(out - OFF);
+		    if (dist > 2) {
+			unsigned short *sfrom;
+
+			sfrom = (unsigned short *)(from - OFF);
+			loops = len >> 1;
+			do
+#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
+			    PUP(sout) = PUP(sfrom);
+#else
+			    PUP(sout) = UP_UNALIGNED(sfrom);
+#endif
+			while (--loops);
+			out = (unsigned char *)sout + OFF;
+			from = (unsigned char *)sfrom + OFF;
+		    } else { /* dist == 1 or dist == 2 */
+			unsigned short pat16;
+
+			pat16 = *(sout-1+OFF);
+			if (dist == 1) {
+				union uu mm;
+				/* copy one char pattern to both bytes */
+				mm.us = pat16;
+				mm.b[0] = mm.b[1];
+				pat16 = mm.us;
+			}
+			loops = len >> 1;
+			do
+			    PUP(sout) = pat16;
+			while (--loops);
+			out = (unsigned char *)sout + OFF;
+		    }
+		    if (len & 1)
+			PUP(out) = PUP(from);
                 }
             }
             else if ((op & 64) == 0) {          /* 2nd level distance code */
diff -uNra linux-2.6.27.6/lib/zlib_inflate/inflate.h linux-2.6.27.6.yaffs/lib/zlib_inflate/inflate.h
--- linux-2.6.27.6/lib/zlib_inflate/inflate.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/lib/zlib_inflate/inflate.h	2011-05-16 21:49:50.000000000 +0800
@@ -1,3 +1,5 @@
+#ifndef INFLATE_H
+#define INFLATE_H
 /* inflate.h -- internal inflate state definition
  * Copyright (C) 1995-2004 Mark Adler
  * For conditions of distribution and use, see copyright notice in zlib.h
@@ -105,3 +107,4 @@
     unsigned short work[288];   /* work area for code table building */
     code codes[ENOUGH];         /* space for code tables */
 };
+#endif
diff -uNra linux-2.6.27.6/lib/zlib_inflate/inftrees.h linux-2.6.27.6.yaffs/lib/zlib_inflate/inftrees.h
--- linux-2.6.27.6/lib/zlib_inflate/inftrees.h	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/lib/zlib_inflate/inftrees.h	2011-05-16 21:50:43.000000000 +0800
@@ -1,3 +1,6 @@
+
+#ifndef INFTREES_H
+#define INFTREES_H
 /* inftrees.h -- header to use inftrees.c
  * Copyright (C) 1995-2005 Mark Adler
  * For conditions of distribution and use, see copyright notice in zlib.h
@@ -53,3 +56,4 @@
 extern int zlib_inflate_table (codetype type, unsigned short *lens,
                              unsigned codes, code **table,
                              unsigned *bits, unsigned short *work);
+#endif
diff -uNra linux-2.6.27.6/Makefile linux-2.6.27.6.yaffs/Makefile
--- linux-2.6.27.6/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/Makefile	2011-05-08 18:02:54.000000000 +0800
@@ -221,8 +221,8 @@
 
 HOSTCC       = gcc
 HOSTCXX      = g++
-HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
-HOSTCXXFLAGS = -O2
+HOSTCFLAGS   = -Wall -Wstrict-prototypes -O3 -fomit-frame-pointer
+HOSTCXXFLAGS = -O3
 
 # Decide whether to build built-in, modular, or both.
 # Normally, just do built-in.
@@ -512,7 +512,7 @@
 ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS	+= -Os
 else
-KBUILD_CFLAGS	+= -O2
+KBUILD_CFLAGS	+= -O3
 endif
 
 include $(srctree)/arch/$(SRCARCH)/Makefile
diff -uNra linux-2.6.27.6/mm/vmalloc.c linux-2.6.27.6.yaffs/mm/vmalloc.c
--- linux-2.6.27.6/mm/vmalloc.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/mm/vmalloc.c	2011-05-08 18:02:40.000000000 +0800
@@ -616,6 +616,29 @@
 EXPORT_SYMBOL(vmalloc_user);
 
 /**
+ * vmalloc_user_uncached - allocate zeroed virtually contiguous memory for userspace
+ * @size: allocation size
+ *
+ * The resulting memory area is zeroed so it can be mapped to userspace
+ * without leaking data.
+ */
+void *vmalloc_user_uncached(unsigned long size)
+{
+	struct vm_struct *area;
+	void *ret;
+
+	ret = __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, pgprot_noncached(PAGE_KERNEL));
+	if (ret) {
+		write_lock(&vmlist_lock);
+		area = __find_vm_area(ret);
+		area->flags |= VM_USERMAP;
+		write_unlock(&vmlist_lock);
+	}
+	return ret;
+}
+EXPORT_SYMBOL(vmalloc_user_uncached);
+
+/**
  *	vmalloc_node  -  allocate memory on a specific node
  *	@size:		allocation size
  *	@node:		numa node
diff -uNra linux-2.6.27.6/scripts/genksyms/keywords.c linux-2.6.27.6.yaffs/scripts/genksyms/keywords.c
--- linux-2.6.27.6/scripts/genksyms/keywords.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/genksyms/keywords.c	2011-05-08 18:02:54.000000000 +0800
@@ -0,0 +1,212 @@
+/* ANSI-C code produced by gperf version 3.0.2 */
+/* Command-line: gperf -L ANSI-C -a -C -E -g -H is_reserved_hash -k '1,3,$' -N is_reserved_word -p -t scripts/genksyms/keywords.gperf  */
+
+#if !((' ' == 32) && ('!' == 33) && ('"' == 34) && ('#' == 35) \
+      && ('%' == 37) && ('&' == 38) && ('\'' == 39) && ('(' == 40) \
+      && (')' == 41) && ('*' == 42) && ('+' == 43) && (',' == 44) \
+      && ('-' == 45) && ('.' == 46) && ('/' == 47) && ('0' == 48) \
+      && ('1' == 49) && ('2' == 50) && ('3' == 51) && ('4' == 52) \
+      && ('5' == 53) && ('6' == 54) && ('7' == 55) && ('8' == 56) \
+      && ('9' == 57) && (':' == 58) && (';' == 59) && ('<' == 60) \
+      && ('=' == 61) && ('>' == 62) && ('?' == 63) && ('A' == 65) \
+      && ('B' == 66) && ('C' == 67) && ('D' == 68) && ('E' == 69) \
+      && ('F' == 70) && ('G' == 71) && ('H' == 72) && ('I' == 73) \
+      && ('J' == 74) && ('K' == 75) && ('L' == 76) && ('M' == 77) \
+      && ('N' == 78) && ('O' == 79) && ('P' == 80) && ('Q' == 81) \
+      && ('R' == 82) && ('S' == 83) && ('T' == 84) && ('U' == 85) \
+      && ('V' == 86) && ('W' == 87) && ('X' == 88) && ('Y' == 89) \
+      && ('Z' == 90) && ('[' == 91) && ('\\' == 92) && (']' == 93) \
+      && ('^' == 94) && ('_' == 95) && ('a' == 97) && ('b' == 98) \
+      && ('c' == 99) && ('d' == 100) && ('e' == 101) && ('f' == 102) \
+      && ('g' == 103) && ('h' == 104) && ('i' == 105) && ('j' == 106) \
+      && ('k' == 107) && ('l' == 108) && ('m' == 109) && ('n' == 110) \
+      && ('o' == 111) && ('p' == 112) && ('q' == 113) && ('r' == 114) \
+      && ('s' == 115) && ('t' == 116) && ('u' == 117) && ('v' == 118) \
+      && ('w' == 119) && ('x' == 120) && ('y' == 121) && ('z' == 122) \
+      && ('{' == 123) && ('|' == 124) && ('}' == 125) && ('~' == 126))
+/* The character set is not based on ISO-646.  */
+#error "gperf generated tables don't work with this execution character set. Please report a bug to <bug-gnu-gperf@gnu.org>."
+#endif
+
+#line 1 "scripts/genksyms/keywords.gperf"
+
+#line 3 "scripts/genksyms/keywords.gperf"
+struct resword { const char *name; int token; };
+/* maximum key range = 62, duplicates = 0 */
+
+#ifdef __GNUC__
+__inline
+#else
+#ifdef __cplusplus
+inline
+#endif
+#endif
+static unsigned int
+is_reserved_hash (register const char *str, register unsigned int len)
+{
+  static const unsigned char asso_values[] =
+    {
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65,  5,
+      65, 65, 65, 65, 65, 65, 35, 65, 65, 65,
+       0, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65,  0, 65,  0, 65,  5,
+      20, 15, 10, 30, 65, 15, 65, 65, 20,  0,
+      10, 35, 20, 65, 10,  5,  0, 10,  5, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+      65, 65, 65, 65, 65, 65
+    };
+  return len + asso_values[(unsigned char)str[2]] + asso_values[(unsigned char)str[0]] + asso_values[(unsigned char)str[len - 1]];
+}
+
+#ifdef __GNUC__
+__inline
+#endif
+const struct resword *
+is_reserved_word (register const char *str, register unsigned int len)
+{
+  enum
+    {
+      TOTAL_KEYWORDS = 43,
+      MIN_WORD_LENGTH = 3,
+      MAX_WORD_LENGTH = 24,
+      MIN_HASH_VALUE = 3,
+      MAX_HASH_VALUE = 64
+    };
+
+  static const struct resword wordlist[] =
+    {
+      {""}, {""}, {""},
+#line 26 "scripts/genksyms/keywords.gperf"
+      {"asm", ASM_KEYW},
+      {""},
+#line 8 "scripts/genksyms/keywords.gperf"
+      {"__asm", ASM_KEYW},
+      {""},
+#line 9 "scripts/genksyms/keywords.gperf"
+      {"__asm__", ASM_KEYW},
+      {""}, {""},
+#line 52 "scripts/genksyms/keywords.gperf"
+      {"__typeof__", TYPEOF_KEYW},
+      {""},
+#line 12 "scripts/genksyms/keywords.gperf"
+      {"__const", CONST_KEYW},
+#line 11 "scripts/genksyms/keywords.gperf"
+      {"__attribute__", ATTRIBUTE_KEYW},
+#line 13 "scripts/genksyms/keywords.gperf"
+      {"__const__", CONST_KEYW},
+#line 18 "scripts/genksyms/keywords.gperf"
+      {"__signed__", SIGNED_KEYW},
+#line 44 "scripts/genksyms/keywords.gperf"
+      {"static", STATIC_KEYW},
+#line 20 "scripts/genksyms/keywords.gperf"
+      {"__volatile__", VOLATILE_KEYW},
+#line 39 "scripts/genksyms/keywords.gperf"
+      {"int", INT_KEYW},
+#line 32 "scripts/genksyms/keywords.gperf"
+      {"char", CHAR_KEYW},
+#line 33 "scripts/genksyms/keywords.gperf"
+      {"const", CONST_KEYW},
+#line 45 "scripts/genksyms/keywords.gperf"
+      {"struct", STRUCT_KEYW},
+#line 24 "scripts/genksyms/keywords.gperf"
+      {"__restrict__", RESTRICT_KEYW},
+#line 25 "scripts/genksyms/keywords.gperf"
+      {"restrict", RESTRICT_KEYW},
+#line 23 "scripts/genksyms/keywords.gperf"
+      {"_restrict", RESTRICT_KEYW},
+#line 16 "scripts/genksyms/keywords.gperf"
+      {"__inline__", INLINE_KEYW},
+#line 10 "scripts/genksyms/keywords.gperf"
+      {"__attribute", ATTRIBUTE_KEYW},
+      {""},
+#line 14 "scripts/genksyms/keywords.gperf"
+      {"__extension__", EXTENSION_KEYW},
+#line 35 "scripts/genksyms/keywords.gperf"
+      {"enum", ENUM_KEYW},
+#line 19 "scripts/genksyms/keywords.gperf"
+      {"__volatile", VOLATILE_KEYW},
+#line 36 "scripts/genksyms/keywords.gperf"
+      {"extern", EXTERN_KEYW},
+      {""},
+#line 17 "scripts/genksyms/keywords.gperf"
+      {"__signed", SIGNED_KEYW},
+#line 7 "scripts/genksyms/keywords.gperf"
+      {"EXPORT_SYMBOL_GPL_FUTURE", EXPORT_SYMBOL_KEYW},
+      {""},
+#line 51 "scripts/genksyms/keywords.gperf"
+      {"typeof", TYPEOF_KEYW},
+#line 46 "scripts/genksyms/keywords.gperf"
+      {"typedef", TYPEDEF_KEYW},
+#line 15 "scripts/genksyms/keywords.gperf"
+      {"__inline", INLINE_KEYW},
+#line 31 "scripts/genksyms/keywords.gperf"
+      {"auto", AUTO_KEYW},
+#line 47 "scripts/genksyms/keywords.gperf"
+      {"union", UNION_KEYW},
+      {""}, {""},
+#line 48 "scripts/genksyms/keywords.gperf"
+      {"unsigned", UNSIGNED_KEYW},
+#line 49 "scripts/genksyms/keywords.gperf"
+      {"void", VOID_KEYW},
+#line 42 "scripts/genksyms/keywords.gperf"
+      {"short", SHORT_KEYW},
+      {""}, {""},
+#line 50 "scripts/genksyms/keywords.gperf"
+      {"volatile", VOLATILE_KEYW},
+      {""},
+#line 37 "scripts/genksyms/keywords.gperf"
+      {"float", FLOAT_KEYW},
+#line 34 "scripts/genksyms/keywords.gperf"
+      {"double", DOUBLE_KEYW},
+      {""},
+#line 5 "scripts/genksyms/keywords.gperf"
+      {"EXPORT_SYMBOL", EXPORT_SYMBOL_KEYW},
+      {""}, {""},
+#line 38 "scripts/genksyms/keywords.gperf"
+      {"inline", INLINE_KEYW},
+#line 6 "scripts/genksyms/keywords.gperf"
+      {"EXPORT_SYMBOL_GPL", EXPORT_SYMBOL_KEYW},
+#line 41 "scripts/genksyms/keywords.gperf"
+      {"register", REGISTER_KEYW},
+      {""},
+#line 22 "scripts/genksyms/keywords.gperf"
+      {"_Bool", BOOL_KEYW},
+#line 43 "scripts/genksyms/keywords.gperf"
+      {"signed", SIGNED_KEYW},
+      {""}, {""},
+#line 40 "scripts/genksyms/keywords.gperf"
+      {"long", LONG_KEYW}
+    };
+
+  if (len <= MAX_WORD_LENGTH && len >= MIN_WORD_LENGTH)
+    {
+      register int key = is_reserved_hash (str, len);
+
+      if (key <= MAX_HASH_VALUE && key >= 0)
+        {
+          register const char *s = wordlist[key].name;
+
+          if (*str == *s && !strcmp (str + 1, s + 1))
+            return &wordlist[key];
+        }
+    }
+  return 0;
+}
diff -uNra linux-2.6.27.6/scripts/genksyms/lex.c linux-2.6.27.6.yaffs/scripts/genksyms/lex.c
--- linux-2.6.27.6/scripts/genksyms/lex.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/genksyms/lex.c	2011-05-08 18:02:54.000000000 +0800
@@ -0,0 +1,2709 @@
+#line 2 "scripts/genksyms/lex.c"
+
+#line 4 "scripts/genksyms/lex.c"
+
+#define  YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+/* %not-for-header */
+
+/* %if-c-only */
+/* %if-not-reentrant */
+
+/* %endif */
+/* %endif */
+/* %ok-for-header */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* %if-c++-only */
+/* %endif */
+
+/* %if-c-only */
+    
+/* %endif */
+
+/* %if-c-only */
+
+/* %endif */
+
+/* First, we deal with  platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+/* %if-c-only */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+/* %endif */
+
+/* %if-tables-serialization */
+/* %endif */
+/* end standard C headers. */
+
+/* %if-c-or-c++ */
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types. 
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t; 
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN               (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN              (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN              (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX               (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX              (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX              (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX              (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX             (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX             (4294967295U)
+#endif
+
+#endif /* ! C99 */
+
+#endif /* ! FLEXINT_H */
+
+/* %endif */
+
+/* %if-c++-only */
+/* %endif */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif	/* defined (__STDC__) */
+#endif	/* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* %not-for-header */
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+/* %ok-for-header */
+
+/* %not-for-header */
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index.  If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+/* %ok-for-header */
+
+/* %if-reentrant */
+/* %endif */
+
+/* %if-not-reentrant */
+
+/* %endif */
+
+/* Enter a start condition.  This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state.  The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart(yyin  )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+/* %if-not-reentrant */
+extern int yyleng;
+/* %endif */
+
+/* %if-c-only */
+/* %if-not-reentrant */
+extern FILE *yyin, *yyout;
+/* %endif */
+/* %endif */
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+    #define YY_LESS_LINENO(n)
+    
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		*yy_cp = (yy_hold_char); \
+		YY_RESTORE_YY_MORE_OFFSET \
+		(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+		} \
+	while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr)  )
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+	{
+/* %if-c-only */
+	FILE *yy_input_file;
+/* %endif */
+
+/* %if-c++-only */
+/* %endif */
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+    int yy_bs_lineno; /**< The line count. */
+    int yy_bs_column; /**< The column count. */
+    
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+	/* When an EOF's been seen but there's still some text to process
+	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+	 * shouldn't try reading from the input source any more.  We might
+	 * still have a bunch of tokens to match, though, because of
+	 * possible backing-up.
+	 *
+	 * When we actually see the EOF, we change the status to "new"
+	 * (via yyrestart()), so that the user can continue scanning by
+	 * just pointing yyin at a new input file.
+	 */
+#define YY_BUFFER_EOF_PENDING 2
+
+	};
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* %if-c-only Standard (non-C++) definition */
+/* %not-for-header */
+
+/* %if-not-reentrant */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+/* %endif */
+/* %ok-for-header */
+
+/* %endif */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+                          : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* %if-c-only Standard (non-C++) definition */
+
+/* %if-not-reentrant */
+/* %not-for-header */
+
+/* yy_hold_char holds the character lost when yytext is formed. */
+static char yy_hold_char;
+static int yy_n_chars;		/* number of characters read into yy_ch_buf */
+int yyleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0;		/* whether we need to initialize */
+static int yy_start = 0;	/* start state number */
+
+/* Flag which is used to allow yywrap()'s to do buffer switches
+ * instead of setting up a fresh yyin.  A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+/* %ok-for-header */
+
+/* %endif */
+
+void yyrestart (FILE *input_file  );
+void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
+YY_BUFFER_STATE yy_create_buffer (FILE *file,int size  );
+void yy_delete_buffer (YY_BUFFER_STATE b  );
+void yy_flush_buffer (YY_BUFFER_STATE b  );
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer  );
+void yypop_buffer_state (void );
+
+static void yyensure_buffer_stack (void );
+static void yy_load_buffer_state (void );
+static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file  );
+
+#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size  );
+YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str  );
+YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len  );
+
+/* %endif */
+
+void *yyalloc (yy_size_t  );
+void *yyrealloc (void *,yy_size_t  );
+void yyfree (void *  );
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){ \
+        yyensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            yy_create_buffer(yyin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+	}
+
+#define yy_set_bol(at_bol) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){\
+        yyensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            yy_create_buffer(yyin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+	}
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* %% [1.0] yytext/yyin/yyout/yy_state_type/yylineno etc. def's & init go here */
+/* Begin user sect3 */
+
+#define yywrap(n) 1
+#define YY_SKIP_YYWRAP
+
+#define FLEX_DEBUG
+
+typedef unsigned char YY_CHAR;
+
+FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int yylineno;
+
+int yylineno = 1;
+
+extern char *yytext;
+#define yytext_ptr yytext
+
+/* %if-c-only Standard (non-C++) definition */
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state  );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[]  );
+
+/* %endif */
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+	(yytext_ptr) = yy_bp; \
+/* %% [2.0] code to fiddle yytext and yyleng for yymore() goes here \ */\
+	yyleng = (size_t) (yy_cp - yy_bp); \
+	(yy_hold_char) = *yy_cp; \
+	*yy_cp = '\0'; \
+/* %% [3.0] code to copy yytext_ptr to yytext[] goes here, if %array \ */\
+	(yy_c_buf_p) = yy_cp;
+
+/* %% [4.0] data tables for the DFA and the user's section 1 definitions go here */
+#define YY_NUM_RULES 13
+#define YY_END_OF_BUFFER 14
+/* This struct is not used in this scanner,
+   but its presence is necessary. */
+struct yy_trans_info
+	{
+	flex_int32_t yy_verify;
+	flex_int32_t yy_nxt;
+	};
+static yyconst flex_int16_t yy_accept[76] =
+    {   0,
+        0,    0,    0,    0,   14,   12,    4,    3,   12,    7,
+       12,   12,    7,   12,   12,   12,   12,   12,    9,    9,
+       12,   12,   12,    4,    0,    5,    0,    7,    0,    6,
+        0,    0,    0,    0,    0,    0,    2,    8,   10,   10,
+        9,    0,    0,    9,    9,    0,    9,    0,    0,   11,
+        0,    0,    0,   10,    0,   10,    9,    9,    0,    0,
+        0,    0,    0,    0,    0,   10,   10,    0,    0,    0,
+        0,    0,    0,    1,    0
+    } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
+        4,    4,    4,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    2,    1,    5,    6,    7,    8,    9,   10,    1,
+        1,    8,   11,    1,   12,   13,    8,   14,   15,   15,
+       15,   15,   15,   15,   15,   16,   16,    1,    1,   17,
+       18,   19,    1,    1,   20,   20,   20,   20,   21,   22,
+        7,    7,    7,    7,    7,   23,    7,    7,    7,    7,
+        7,    7,    7,    7,   24,    7,    7,   25,    7,    7,
+        1,   26,    1,    8,    7,    1,   20,   20,   20,   20,
+
+       21,   22,    7,    7,    7,    7,    7,   27,    7,    7,
+        7,    7,    7,    7,    7,    7,   24,    7,    7,   25,
+        7,    7,    1,   28,    1,    8,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1
+    } ;
+
+static yyconst flex_int32_t yy_meta[29] =
+    {   0,
+        1,    1,    2,    1,    1,    1,    3,    1,    1,    1,
+        4,    4,    5,    6,    6,    6,    1,    1,    1,    7,
+        8,    7,    3,    3,    3,    1,    3,    1
+    } ;
+
+static yyconst flex_int16_t yy_base[88] =
+    {   0,
+        0,  147,   21,  140,  145,  284,   39,  284,   26,    0,
+       32,  126,   40,   44,  115,   35,   36,   46,   50,   53,
+       39,   61,   54,   79,   65,  284,    0,    0,   66,  284,
+        0,  119,   79,   75,  123,  104,  284,  284,  107,    0,
+       79,   73,   76,   76,   66,    0,    0,   85,   86,  284,
+      133,   83,   91,  284,   99,  147,  284,  114,  122,   70,
+      107,  141,  172,  151,  135,  181,  284,  137,  114,  157,
+      149,   48,   45,  284,  284,  208,  214,  222,  230,  238,
+      246,  250,  255,  256,  261,  267,  275
+    } ;
+
+static yyconst flex_int16_t yy_def[88] =
+    {   0,
+       75,    1,    1,    3,   75,   75,   75,   75,   76,   77,
+       78,   75,   77,   79,   75,   75,   75,   75,   75,   19,
+       75,   75,   75,   75,   76,   75,   80,   77,   78,   75,
+       81,   75,   76,   78,   79,   79,   75,   75,   75,   39,
+       19,   82,   83,   75,   75,   84,   20,   76,   78,   75,
+       79,   51,   85,   75,   75,   75,   75,   84,   79,   51,
+       79,   79,   79,   51,   75,   75,   75,   86,   79,   63,
+       86,   87,   87,   75,    0,   75,   75,   75,   75,   75,
+       75,   75,   75,   75,   75,   75,   75
+    } ;
+
+static yyconst flex_int16_t yy_nxt[313] =
+    {   0,
+        6,    7,    8,    7,    9,    6,   10,    6,    6,   11,
+        6,    6,   12,    6,    6,    6,    6,    6,    6,   10,
+       10,   10,   13,   10,   10,    6,   10,    6,   15,   16,
+       26,   15,   17,   18,   19,   20,   20,   21,   15,   22,
+       24,   30,   24,   38,   33,   36,   37,   74,   23,   34,
+       74,   27,   38,   38,   38,   38,   38,   31,   32,   39,
+       39,   39,   40,   41,   41,   42,   47,   47,   47,   26,
+       43,   38,   44,   45,   46,   30,   44,   75,   38,   38,
+       24,   38,   24,   26,   30,   40,   55,   55,   57,   26,
+       27,   31,   57,   43,   35,   30,   64,   64,   64,   57,
+
+       31,   65,   65,   75,   27,   36,   37,   35,   59,   37,
+       27,   31,   56,   56,   56,   59,   37,   51,   52,   52,
+       39,   39,   39,   59,   37,   37,   68,   53,   54,   54,
+       69,   50,   38,   54,   59,   37,   44,   45,   32,   37,
+       44,   35,   59,   37,   75,   14,   60,   60,   66,   66,
+       66,   37,   14,   72,   75,   61,   62,   63,   59,   61,
+       56,   56,   56,   69,   64,   64,   64,   69,   67,   67,
+       75,   75,   75,   67,   37,   35,   75,   75,   75,   61,
+       62,   75,   75,   61,   75,   70,   70,   70,   75,   75,
+       75,   70,   70,   70,   66,   66,   66,   75,   75,   75,
+
+       75,   75,   54,   54,   75,   75,   75,   54,   25,   25,
+       25,   25,   25,   25,   25,   25,   28,   75,   75,   28,
+       28,   28,   29,   29,   29,   29,   29,   29,   29,   29,
+       35,   35,   35,   35,   35,   35,   35,   35,   48,   75,
+       48,   48,   48,   48,   48,   48,   49,   75,   49,   49,
+       49,   49,   49,   49,   42,   42,   75,   42,   56,   75,
+       56,   58,   58,   58,   66,   75,   66,   71,   71,   71,
+       71,   71,   71,   71,   71,   73,   73,   73,   73,   73,
+       73,   73,   73,    5,   75,   75,   75,   75,   75,   75,
+       75,   75,   75,   75,   75,   75,   75,   75,   75,   75,
+
+       75,   75,   75,   75,   75,   75,   75,   75,   75,   75,
+       75,   75
+    } ;
+
+static yyconst flex_int16_t yy_chk[313] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    3,    3,
+        9,    3,    3,    3,    3,    3,    3,    3,    3,    3,
+        7,   11,    7,   16,   13,   14,   14,   73,    3,   13,
+       72,    9,   16,   17,   17,   21,   21,   11,   18,   18,
+       18,   18,   19,   19,   19,   19,   20,   20,   20,   25,
+       19,   23,   19,   19,   19,   29,   19,   20,   22,   22,
+       24,   23,   24,   33,   34,   42,   43,   43,   45,   48,
+       25,   29,   45,   42,   60,   49,   52,   52,   52,   44,
+
+       34,   53,   53,   41,   33,   36,   36,   52,   61,   61,
+       48,   49,   55,   55,   55,   69,   69,   36,   36,   36,
+       39,   39,   39,   59,   59,   35,   59,   39,   39,   39,
+       61,   32,   15,   39,   51,   51,   58,   58,   12,   68,
+       58,   68,   62,   62,    5,    4,   51,   51,   65,   65,
+       65,   71,    2,   71,    0,   51,   51,   51,   70,   51,
+       56,   56,   56,   62,   64,   64,   64,   62,   56,   56,
+        0,    0,    0,   56,   63,   64,    0,    0,    0,   70,
+       70,    0,    0,   70,    0,   63,   63,   63,    0,    0,
+        0,   63,   63,   63,   66,   66,   66,    0,    0,    0,
+
+        0,    0,   66,   66,    0,    0,    0,   66,   76,   76,
+       76,   76,   76,   76,   76,   76,   77,    0,    0,   77,
+       77,   77,   78,   78,   78,   78,   78,   78,   78,   78,
+       79,   79,   79,   79,   79,   79,   79,   79,   80,    0,
+       80,   80,   80,   80,   80,   80,   81,    0,   81,   81,
+       81,   81,   81,   81,   82,   82,    0,   82,   83,    0,
+       83,   84,   84,   84,   85,    0,   85,   86,   86,   86,
+       86,   86,   86,   86,   86,   87,   87,   87,   87,   87,
+       87,   87,   87,   75,   75,   75,   75,   75,   75,   75,
+       75,   75,   75,   75,   75,   75,   75,   75,   75,   75,
+
+       75,   75,   75,   75,   75,   75,   75,   75,   75,   75,
+       75,   75
+    } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+extern int yy_flex_debug;
+int yy_flex_debug = 1;
+
+static yyconst flex_int16_t yy_rule_linenum[13] =
+    {   0,
+       71,   72,   73,   76,   79,   80,   81,   87,   88,   89,
+       91,   94
+    } ;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *yytext;
+#line 1 "scripts/genksyms/lex.l"
+/* Lexical analysis for genksyms.
+   Copyright 1996, 1997 Linux International.
+
+   New implementation contributed by Richard Henderson <rth@tamu.edu>
+   Based on original work by Bjorn Ekwall <bj0rn@blox.se>
+
+   Taken from Linux modutils 2.4.22.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2 of the License, or (at your
+   option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+#line 25 "scripts/genksyms/lex.l"
+
+#include <limits.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "genksyms.h"
+#include "parse.h"
+
+/* We've got a two-level lexer here.  We let flex do basic tokenization
+   and then we categorize those basic tokens in the second stage.  */
+#define YY_DECL		static int yylex1(void)
+
+/* Version 2 checksumming does proper tokenization; version 1 wasn't
+   quite so pedantic.  */
+
+/* We don't do multiple input files.  */
+#define YY_NO_INPUT 1
+#line 676 "scripts/genksyms/lex.c"
+
+#define INITIAL 0
+#define V2_TOKENS 1
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+/* %if-c-only */
+#include <unistd.h>
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+/* %if-c-only Reentrant structure and macros (non-C++). */
+/* %if-reentrant */
+/* %if-c-only */
+
+static int yy_init_globals (void );
+
+/* %endif */
+/* %if-reentrant */
+/* %endif */
+/* %endif End reentrant structures and macros. */
+
+/* Accessor methods to globals.
+   These are made visible to non-reentrant scanners for convenience. */
+
+int yylex_destroy (void );
+
+int yyget_debug (void );
+
+void yyset_debug (int debug_flag  );
+
+YY_EXTRA_TYPE yyget_extra (void );
+
+void yyset_extra (YY_EXTRA_TYPE user_defined  );
+
+FILE *yyget_in (void );
+
+void yyset_in  (FILE * in_str  );
+
+FILE *yyget_out (void );
+
+void yyset_out  (FILE * out_str  );
+
+int yyget_leng (void );
+
+char *yyget_text (void );
+
+int yyget_lineno (void );
+
+void yyset_lineno (int line_number  );
+
+/* %if-bison-bridge */
+/* %endif */
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap (void );
+#else
+extern int yywrap (void );
+#endif
+#endif
+
+/* %not-for-header */
+
+    static void yyunput (int c,char *buf_ptr  );
+    
+/* %ok-for-header */
+
+/* %endif */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+/* %if-c-only Standard (non-C++) definition */
+/* %not-for-header */
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+/* %ok-for-header */
+
+/* %endif */
+#endif
+
+/* %if-c-only */
+
+/* %endif */
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* %if-c-only Standard (non-C++) definition */
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO fwrite( yytext, yyleng, 1, yyout )
+/* %endif */
+/* %if-c++-only C++ definition */
+/* %endif */
+#endif
+
+/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+/* %% [5.0] fread()/read() definition of YY_INPUT goes here unless we're doing C++ \ */\
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+		{ \
+		int c = '*'; \
+		size_t n; \
+		for ( n = 0; n < max_size && \
+			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+			buf[n] = (char) c; \
+		if ( c == '\n' ) \
+			buf[n++] = (char) c; \
+		if ( c == EOF && ferror( yyin ) ) \
+			YY_FATAL_ERROR( "input in flex scanner failed" ); \
+		result = n; \
+		} \
+	else \
+		{ \
+		errno=0; \
+		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
+			{ \
+			if( errno != EINTR) \
+				{ \
+				YY_FATAL_ERROR( "input in flex scanner failed" ); \
+				break; \
+				} \
+			errno=0; \
+			clearerr(yyin); \
+			} \
+		}\
+\
+/* %if-c++-only C++ definition \ */\
+/* %endif */
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+/* %if-c-only */
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+#endif
+
+/* %if-tables-serialization structures and prototypes */
+/* %not-for-header */
+
+/* %ok-for-header */
+
+/* %not-for-header */
+
+/* %tables-yydmap generated elements */
+/* %endif */
+/* end tables serialization structures and prototypes */
+
+/* %ok-for-header */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+/* %if-c-only Standard (non-C++) definition */
+
+extern int yylex (void);
+
+#define YY_DECL int yylex (void)
+/* %endif */
+/* %if-c++-only C++ definition */
+/* %endif */
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+/* %% [6.0] YY_RULE_SETUP definition goes here */
+#define YY_RULE_SETUP \
+	if ( yyleng > 0 ) \
+		YY_CURRENT_BUFFER_LVALUE->yy_at_bol = \
+				(yytext[yyleng - 1] == '\n'); \
+	YY_USER_ACTION
+
+/* %not-for-header */
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp, *yy_bp;
+	register int yy_act;
+    
+/* %% [7.0] user's declarations go here */
+#line 67 "scripts/genksyms/lex.l"
+
+
+
+ /* Keep track of our location in the original source files.  */
+#line 927 "scripts/genksyms/lex.c"
+
+	if ( !(yy_init) )
+		{
+		(yy_init) = 1;
+
+#ifdef YY_USER_INIT
+		YY_USER_INIT;
+#endif
+
+		if ( ! (yy_start) )
+			(yy_start) = 1;	/* first start state */
+
+		if ( ! yyin )
+/* %if-c-only */
+			yyin = stdin;
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+
+		if ( ! yyout )
+/* %if-c-only */
+			yyout = stdout;
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+
+		if ( ! YY_CURRENT_BUFFER ) {
+			yyensure_buffer_stack ();
+			YY_CURRENT_BUFFER_LVALUE =
+				yy_create_buffer(yyin,YY_BUF_SIZE );
+		}
+
+		yy_load_buffer_state( );
+		}
+
+	while ( 1 )		/* loops until end-of-file is reached */
+		{
+/* %% [8.0] yymore()-related code goes here */
+		yy_cp = (yy_c_buf_p);
+
+		/* Support of yytext. */
+		*yy_cp = (yy_hold_char);
+
+		/* yy_bp points to the position in yy_ch_buf of the start of
+		 * the current run.
+		 */
+		yy_bp = yy_cp;
+
+/* %% [9.0] code to set up and find next match goes here */
+		yy_current_state = (yy_start);
+		yy_current_state += YY_AT_BOL();
+yy_match:
+		do
+			{
+			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+			if ( yy_accept[yy_current_state] )
+				{
+				(yy_last_accepting_state) = yy_current_state;
+				(yy_last_accepting_cpos) = yy_cp;
+				}
+			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+				{
+				yy_current_state = (int) yy_def[yy_current_state];
+				if ( yy_current_state >= 76 )
+					yy_c = yy_meta[(unsigned int) yy_c];
+				}
+			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+			++yy_cp;
+			}
+		while ( yy_base[yy_current_state] != 284 );
+
+yy_find_action:
+/* %% [10.0] code to find the action number goes here */
+		yy_act = yy_accept[yy_current_state];
+		if ( yy_act == 0 )
+			{ /* have to back up */
+			yy_cp = (yy_last_accepting_cpos);
+			yy_current_state = (yy_last_accepting_state);
+			yy_act = yy_accept[yy_current_state];
+			}
+
+		YY_DO_BEFORE_ACTION;
+
+/* %% [11.0] code for yylineno update goes here */
+
+do_action:	/* This label is used only to access EOF actions. */
+
+/* %% [12.0] debug code goes here */
+		if ( yy_flex_debug )
+			{
+			if ( yy_act == 0 )
+				fprintf( stderr, "--scanner backing up\n" );
+			else if ( yy_act < 13 )
+				fprintf( stderr, "--accepting rule at line %ld (\"%s\")\n",
+				         (long)yy_rule_linenum[yy_act], yytext );
+			else if ( yy_act == 13 )
+				fprintf( stderr, "--accepting default rule (\"%s\")\n",
+				         yytext );
+			else if ( yy_act == 14 )
+				fprintf( stderr, "--(end of buffer or a NUL)\n" );
+			else
+				fprintf( stderr, "--EOF (start condition %d)\n", YY_START );
+			}
+
+		switch ( yy_act )
+	{ /* beginning of action switch */
+/* %% [13.0] actions go here */
+			case 0: /* must back up */
+			/* undo the effects of YY_DO_BEFORE_ACTION */
+			*yy_cp = (yy_hold_char);
+			yy_cp = (yy_last_accepting_cpos);
+			yy_current_state = (yy_last_accepting_state);
+			goto yy_find_action;
+
+case 1:
+/* rule 1 can match eol */
+YY_RULE_SETUP
+#line 71 "scripts/genksyms/lex.l"
+return FILENAME;
+	YY_BREAK
+case 2:
+/* rule 2 can match eol */
+YY_RULE_SETUP
+#line 72 "scripts/genksyms/lex.l"
+cur_line++;
+	YY_BREAK
+case 3:
+/* rule 3 can match eol */
+YY_RULE_SETUP
+#line 73 "scripts/genksyms/lex.l"
+cur_line++;
+	YY_BREAK
+/* Ignore all other whitespace.  */
+case 4:
+YY_RULE_SETUP
+#line 76 "scripts/genksyms/lex.l"
+;
+	YY_BREAK
+case 5:
+/* rule 5 can match eol */
+YY_RULE_SETUP
+#line 79 "scripts/genksyms/lex.l"
+return STRING;
+	YY_BREAK
+case 6:
+/* rule 6 can match eol */
+YY_RULE_SETUP
+#line 80 "scripts/genksyms/lex.l"
+return CHAR;
+	YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 81 "scripts/genksyms/lex.l"
+return IDENT;
+	YY_BREAK
+/* The Pedant requires that the other C multi-character tokens be
+    recognized as tokens.  We don't actually use them since we don't
+    parse expressions, but we do want whitespace to be arranged
+    around them properly.  */
+case 8:
+YY_RULE_SETUP
+#line 87 "scripts/genksyms/lex.l"
+return OTHER;
+	YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 88 "scripts/genksyms/lex.l"
+return INT;
+	YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 89 "scripts/genksyms/lex.l"
+return REAL;
+	YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 91 "scripts/genksyms/lex.l"
+return DOTS;
+	YY_BREAK
+/* All other tokens are single characters.  */
+case 12:
+YY_RULE_SETUP
+#line 94 "scripts/genksyms/lex.l"
+return yytext[0];
+	YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 97 "scripts/genksyms/lex.l"
+ECHO;
+	YY_BREAK
+#line 1118 "scripts/genksyms/lex.c"
+case YY_STATE_EOF(INITIAL):
+case YY_STATE_EOF(V2_TOKENS):
+	yyterminate();
+
+	case YY_END_OF_BUFFER:
+		{
+		/* Amount of text matched not including the EOB char. */
+		int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+		/* Undo the effects of YY_DO_BEFORE_ACTION. */
+		*yy_cp = (yy_hold_char);
+		YY_RESTORE_YY_MORE_OFFSET
+
+		if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+			{
+			/* We're scanning a new file or input source.  It's
+			 * possible that this happened because the user
+			 * just pointed yyin at a new source and called
+			 * yylex().  If so, then we have to assure
+			 * consistency between YY_CURRENT_BUFFER and our
+			 * globals.  Here is the right place to do so, because
+			 * this is the first action (other than possibly a
+			 * back-up) that will match for the new input source.
+			 */
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+			YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+			}
+
+		/* Note that here we test for yy_c_buf_p "<=" to the position
+		 * of the first EOB in the buffer, since yy_c_buf_p will
+		 * already have been incremented past the NUL character
+		 * (since all states make transitions on EOB to the
+		 * end-of-buffer state).  Contrast this with the test
+		 * in input().
+		 */
+		if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			{ /* This was really a NUL. */
+			yy_state_type yy_next_state;
+
+			(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+			yy_current_state = yy_get_previous_state(  );
+
+			/* Okay, we're now positioned to make the NUL
+			 * transition.  We couldn't have
+			 * yy_get_previous_state() go ahead and do it
+			 * for us because it doesn't know how to deal
+			 * with the possibility of jamming (and we don't
+			 * want to build jamming into it because then it
+			 * will run more slowly).
+			 */
+
+			yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+			yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+			if ( yy_next_state )
+				{
+				/* Consume the NUL. */
+				yy_cp = ++(yy_c_buf_p);
+				yy_current_state = yy_next_state;
+				goto yy_match;
+				}
+
+			else
+				{
+/* %% [14.0] code to do back-up for compressed tables and set up yy_cp goes here */
+				yy_cp = (yy_c_buf_p);
+				goto yy_find_action;
+				}
+			}
+
+		else switch ( yy_get_next_buffer(  ) )
+			{
+			case EOB_ACT_END_OF_FILE:
+				{
+				(yy_did_buffer_switch_on_eof) = 0;
+
+				if ( yywrap( ) )
+					{
+					/* Note: because we've taken care in
+					 * yy_get_next_buffer() to have set up
+					 * yytext, we can now set up
+					 * yy_c_buf_p so that if some total
+					 * hoser (like flex itself) wants to
+					 * call the scanner after we return the
+					 * YY_NULL, it'll still work - another
+					 * YY_NULL will get returned.
+					 */
+					(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+					yy_act = YY_STATE_EOF(YY_START);
+					goto do_action;
+					}
+
+				else
+					{
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+					}
+				break;
+				}
+
+			case EOB_ACT_CONTINUE_SCAN:
+				(yy_c_buf_p) =
+					(yytext_ptr) + yy_amount_of_matched_text;
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_match;
+
+			case EOB_ACT_LAST_MATCH:
+				(yy_c_buf_p) =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_find_action;
+			}
+		break;
+		}
+
+	default:
+		YY_FATAL_ERROR(
+			"fatal flex scanner internal error--no action found" );
+	} /* end of action switch */
+		} /* end of scanning one token */
+} /* end of yylex */
+/* %ok-for-header */
+
+/* %if-c++-only */
+/* %not-for-header */
+
+/* %ok-for-header */
+
+/* %endif */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ *	EOB_ACT_LAST_MATCH -
+ *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ *	EOB_ACT_END_OF_FILE - end of file
+ */
+/* %if-c-only */
+static int yy_get_next_buffer (void)
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    	register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+	register char *source = (yytext_ptr);
+	register int number_to_move, i;
+	int ret_val;
+
+	if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+		YY_FATAL_ERROR(
+		"fatal flex scanner internal error--end of buffer missed" );
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+		{ /* Don't try to fill the buffer, so this is an EOF. */
+		if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+			{
+			/* We matched a single character, the EOB, so
+			 * treat this as a final EOF.
+			 */
+			return EOB_ACT_END_OF_FILE;
+			}
+
+		else
+			{
+			/* We matched some text prior to the EOB, first
+			 * process it.
+			 */
+			return EOB_ACT_LAST_MATCH;
+			}
+		}
+
+	/* Try to read more data. */
+
+	/* First move last chars to start of buffer. */
+	number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+	for ( i = 0; i < number_to_move; ++i )
+		*(dest++) = *(source++);
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+		/* don't do the read, it's not guaranteed to return an EOF,
+		 * just force an EOF
+		 */
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+	else
+		{
+			int num_to_read =
+			YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+		while ( num_to_read <= 0 )
+			{ /* Not enough room in the buffer - grow it. */
+
+			/* just a shorter name for the current buffer */
+			YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+			int yy_c_buf_p_offset =
+				(int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+			if ( b->yy_is_our_buffer )
+				{
+				int new_size = b->yy_buf_size * 2;
+
+				if ( new_size <= 0 )
+					b->yy_buf_size += b->yy_buf_size / 8;
+				else
+					b->yy_buf_size *= 2;
+
+				b->yy_ch_buf = (char *)
+					/* Include room in for 2 EOB chars. */
+					yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2  );
+				}
+			else
+				/* Can't grow it, we don't own it. */
+				b->yy_ch_buf = 0;
+
+			if ( ! b->yy_ch_buf )
+				YY_FATAL_ERROR(
+				"fatal error - scanner input buffer overflow" );
+
+			(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+			num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+						number_to_move - 1;
+
+			}
+
+		if ( num_to_read > YY_READ_BUF_SIZE )
+			num_to_read = YY_READ_BUF_SIZE;
+
+		/* Read in more data. */
+		YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+			(yy_n_chars), (size_t) num_to_read );
+
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	if ( (yy_n_chars) == 0 )
+		{
+		if ( number_to_move == YY_MORE_ADJ )
+			{
+			ret_val = EOB_ACT_END_OF_FILE;
+			yyrestart(yyin  );
+			}
+
+		else
+			{
+			ret_val = EOB_ACT_LAST_MATCH;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+				YY_BUFFER_EOF_PENDING;
+			}
+		}
+
+	else
+		ret_val = EOB_ACT_CONTINUE_SCAN;
+
+	if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+		/* Extend the array by 50%, plus the number we really need. */
+		yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+		YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size  );
+		if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+	}
+
+	(yy_n_chars) += number_to_move;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+	(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+	return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+/* %if-c-only */
+/* %not-for-header */
+
+    static yy_state_type yy_get_previous_state (void)
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp;
+    
+/* %% [15.0] code to get the start state into yy_current_state goes here */
+	yy_current_state = (yy_start);
+	yy_current_state += YY_AT_BOL();
+
+	for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+		{
+/* %% [16.0] code to find the next state goes here */
+		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+		if ( yy_accept[yy_current_state] )
+			{
+			(yy_last_accepting_state) = yy_current_state;
+			(yy_last_accepting_cpos) = yy_cp;
+			}
+		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+			{
+			yy_current_state = (int) yy_def[yy_current_state];
+			if ( yy_current_state >= 76 )
+				yy_c = yy_meta[(unsigned int) yy_c];
+			}
+		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+		}
+
+	return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ *	next_state = yy_try_NUL_trans( current_state );
+ */
+/* %if-c-only */
+    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+	register int yy_is_jam;
+    /* %% [17.0] code to find the next state, and perhaps do backing up, goes here */
+	register char *yy_cp = (yy_c_buf_p);
+
+	register YY_CHAR yy_c = 1;
+	if ( yy_accept[yy_current_state] )
+		{
+		(yy_last_accepting_state) = yy_current_state;
+		(yy_last_accepting_cpos) = yy_cp;
+		}
+	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+		{
+		yy_current_state = (int) yy_def[yy_current_state];
+		if ( yy_current_state >= 76 )
+			yy_c = yy_meta[(unsigned int) yy_c];
+		}
+	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+	yy_is_jam = (yy_current_state == 75);
+
+	return yy_is_jam ? 0 : yy_current_state;
+}
+
+/* %if-c-only */
+
+    static void yyunput (int c, register char * yy_bp )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+	register char *yy_cp;
+    
+    yy_cp = (yy_c_buf_p);
+
+	/* undo effects of setting up yytext */
+	*yy_cp = (yy_hold_char);
+
+	if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+		{ /* need to shift things up to make room */
+		/* +2 for EOB chars. */
+		register int number_to_move = (yy_n_chars) + 2;
+		register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+					YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+		register char *source =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+		while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			*--dest = *--source;
+
+		yy_cp += (int) (dest - source);
+		yy_bp += (int) (dest - source);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+		if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+			YY_FATAL_ERROR( "flex scanner push-back overflow" );
+		}
+
+	*--yy_cp = (char) c;
+
+/* %% [18.0] update yylineno here */
+
+	(yytext_ptr) = yy_bp;
+	(yy_hold_char) = *yy_cp;
+	(yy_c_buf_p) = yy_cp;
+}
+/* %if-c-only */
+
+/* %endif */
+
+/* %if-c-only */
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+    static int yyinput (void)
+#else
+    static int input  (void)
+#endif
+
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+	int c;
+    
+	*(yy_c_buf_p) = (yy_hold_char);
+
+	if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+		{
+		/* yy_c_buf_p now points to the character we want to return.
+		 * If this occurs *before* the EOB characters, then it's a
+		 * valid NUL; if not, then we've hit the end of the buffer.
+		 */
+		if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			/* This was really a NUL. */
+			*(yy_c_buf_p) = '\0';
+
+		else
+			{ /* need more input */
+			int offset = (yy_c_buf_p) - (yytext_ptr);
+			++(yy_c_buf_p);
+
+			switch ( yy_get_next_buffer(  ) )
+				{
+				case EOB_ACT_LAST_MATCH:
+					/* This happens because yy_g_n_b()
+					 * sees that we've accumulated a
+					 * token and flags that we need to
+					 * try matching the token before
+					 * proceeding.  But for input(),
+					 * there's no matching to consider.
+					 * So convert the EOB_ACT_LAST_MATCH
+					 * to EOB_ACT_END_OF_FILE.
+					 */
+
+					/* Reset buffer status. */
+					yyrestart(yyin );
+
+					/*FALLTHROUGH*/
+
+				case EOB_ACT_END_OF_FILE:
+					{
+					if ( yywrap( ) )
+						return EOF;
+
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+#ifdef __cplusplus
+					return yyinput();
+#else
+					return input();
+#endif
+					}
+
+				case EOB_ACT_CONTINUE_SCAN:
+					(yy_c_buf_p) = (yytext_ptr) + offset;
+					break;
+				}
+			}
+		}
+
+	c = *(unsigned char *) (yy_c_buf_p);	/* cast for 8-bit char's */
+	*(yy_c_buf_p) = '\0';	/* preserve yytext */
+	(yy_hold_char) = *++(yy_c_buf_p);
+
+/* %% [19.0] update BOL and yylineno */
+	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = (c == '\n');
+
+	return c;
+}
+/* %if-c-only */
+#endif	/* ifndef YY_NO_INPUT */
+/* %endif */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ * 
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+/* %if-c-only */
+    void yyrestart  (FILE * input_file )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    
+	if ( ! YY_CURRENT_BUFFER ){
+        yyensure_buffer_stack ();
+		YY_CURRENT_BUFFER_LVALUE =
+            yy_create_buffer(yyin,YY_BUF_SIZE );
+	}
+
+	yy_init_buffer(YY_CURRENT_BUFFER,input_file );
+	yy_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ * 
+ */
+/* %if-c-only */
+    void yy_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    
+	/* TODO. We should be able to replace this entire function body
+	 * with
+	 *		yypop_buffer_state();
+	 *		yypush_buffer_state(new_buffer);
+     */
+	yyensure_buffer_stack ();
+	if ( YY_CURRENT_BUFFER == new_buffer )
+		return;
+
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+	yy_load_buffer_state( );
+
+	/* We don't actually know whether we did this switch during
+	 * EOF (yywrap()) processing, but the only time this flag
+	 * is looked at is after yywrap() is called, so it's safe
+	 * to go ahead and always set it.
+	 */
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+/* %if-c-only */
+static void yy_load_buffer_state  (void)
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    	(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+	(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+	yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+	(yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ * 
+ * @return the allocated buffer state.
+ */
+/* %if-c-only */
+    YY_BUFFER_STATE yy_create_buffer  (FILE * file, int  size )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+	YY_BUFFER_STATE b;
+    
+	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_buf_size = size;
+
+	/* yy_ch_buf has to be 2 characters longer than the size given because
+	 * we need to put in 2 end-of-buffer characters.
+	 */
+	b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2  );
+	if ( ! b->yy_ch_buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_is_our_buffer = 1;
+
+	yy_init_buffer(b,file );
+
+	return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with yy_create_buffer()
+ * 
+ */
+/* %if-c-only */
+    void yy_delete_buffer (YY_BUFFER_STATE  b )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    
+	if ( ! b )
+		return;
+
+	if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+		YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+	if ( b->yy_is_our_buffer )
+		yyfree((void *) b->yy_ch_buf  );
+
+	yyfree((void *) b  );
+}
+
+/* %if-c-only */
+
+#ifndef __cplusplus
+extern int isatty (int );
+#endif /* __cplusplus */
+    
+/* %endif */
+
+/* %if-c++-only */
+/* %endif */
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+ */
+/* %if-c-only */
+    static void yy_init_buffer  (YY_BUFFER_STATE  b, FILE * file )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+
+{
+	int oerrno = errno;
+    
+	yy_flush_buffer(b );
+
+	b->yy_input_file = file;
+	b->yy_fill_buffer = 1;
+
+    /* If b is the current buffer, then yy_init_buffer was _probably_
+     * called from yyrestart() or through yy_get_next_buffer.
+     * In that case, we don't want to reset the lineno or column.
+     */
+    if (b != YY_CURRENT_BUFFER){
+        b->yy_bs_lineno = 1;
+        b->yy_bs_column = 0;
+    }
+
+/* %if-c-only */
+
+        b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+    
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+	errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ * 
+ */
+/* %if-c-only */
+    void yy_flush_buffer (YY_BUFFER_STATE  b )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    	if ( ! b )
+		return;
+
+	b->yy_n_chars = 0;
+
+	/* We always need two end-of-buffer characters.  The first causes
+	 * a transition to the end-of-buffer state.  The second causes
+	 * a jam in that state.
+	 */
+	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+	b->yy_buf_pos = &b->yy_ch_buf[0];
+
+	b->yy_at_bol = 1;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	if ( b == YY_CURRENT_BUFFER )
+		yy_load_buffer_state( );
+}
+
+/* %if-c-or-c++ */
+/** Pushes the new state onto the stack. The new state becomes
+ *  the current state. This function will allocate the stack
+ *  if necessary.
+ *  @param new_buffer The new state.
+ *  
+ */
+/* %if-c-only */
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    	if (new_buffer == NULL)
+		return;
+
+	yyensure_buffer_stack();
+
+	/* This block is copied from yy_switch_to_buffer. */
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	/* Only push if top exists. Otherwise, replace top. */
+	if (YY_CURRENT_BUFFER)
+		(yy_buffer_stack_top)++;
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+	/* copied from yy_switch_to_buffer. */
+	yy_load_buffer_state( );
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+/* %endif */
+
+/* %if-c-or-c++ */
+/** Removes and deletes the top of the stack, if present.
+ *  The next element becomes the new top.
+ *  
+ */
+/* %if-c-only */
+void yypop_buffer_state (void)
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+    	if (!YY_CURRENT_BUFFER)
+		return;
+
+	yy_delete_buffer(YY_CURRENT_BUFFER );
+	YY_CURRENT_BUFFER_LVALUE = NULL;
+	if ((yy_buffer_stack_top) > 0)
+		--(yy_buffer_stack_top);
+
+	if (YY_CURRENT_BUFFER) {
+		yy_load_buffer_state( );
+		(yy_did_buffer_switch_on_eof) = 1;
+	}
+}
+/* %endif */
+
+/* %if-c-or-c++ */
+/* Allocates the stack if it does not exist.
+ *  Guarantees space for at least one push.
+ */
+/* %if-c-only */
+static void yyensure_buffer_stack (void)
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+{
+	int num_to_alloc;
+    
+	if (!(yy_buffer_stack)) {
+
+		/* First allocation is just for 2 elements, since we don't know if this
+		 * scanner will even need a stack. We use 2 instead of 1 to avoid an
+		 * immediate realloc on the next call.
+         */
+		num_to_alloc = 1;
+		(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+								(num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+								  
+		memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+				
+		(yy_buffer_stack_max) = num_to_alloc;
+		(yy_buffer_stack_top) = 0;
+		return;
+	}
+
+	if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+		/* Increase the buffer to prepare for a possible push. */
+		int grow_size = 8 /* arbitrary grow size */;
+
+		num_to_alloc = (yy_buffer_stack_max) + grow_size;
+		(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+								((yy_buffer_stack),
+								num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+		/* zero only the new slots.*/
+		memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+		(yy_buffer_stack_max) = num_to_alloc;
+	}
+}
+/* %endif */
+
+/* %if-c-only */
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ * 
+ * @return the newly allocated buffer state object. 
+ */
+YY_BUFFER_STATE yy_scan_buffer  (char * base, yy_size_t  size )
+{
+	YY_BUFFER_STATE b;
+    
+	if ( size < 2 ||
+	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
+	     base[size-1] != YY_END_OF_BUFFER_CHAR )
+		/* They forgot to leave room for the EOB's. */
+		return 0;
+
+	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
+
+	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
+	b->yy_buf_pos = b->yy_ch_buf = base;
+	b->yy_is_our_buffer = 0;
+	b->yy_input_file = 0;
+	b->yy_n_chars = b->yy_buf_size;
+	b->yy_is_interactive = 0;
+	b->yy_at_bol = 1;
+	b->yy_fill_buffer = 0;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	yy_switch_to_buffer(b  );
+
+	return b;
+}
+/* %endif */
+
+/* %if-c-only */
+/** Setup the input buffer state to scan a string. The next call to yylex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ * 
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ *       yy_scan_bytes() instead.
+ */
+YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
+{
+    
+	return yy_scan_bytes(yystr,strlen(yystr) );
+}
+/* %endif */
+
+/* %if-c-only */
+/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ * 
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_bytes  (yyconst char * yybytes, int  _yybytes_len )
+{
+	YY_BUFFER_STATE b;
+	char *buf;
+	yy_size_t n;
+	int i;
+    
+	/* Get memory for full buffer, including space for trailing EOB's. */
+	n = _yybytes_len + 2;
+	buf = (char *) yyalloc(n  );
+	if ( ! buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
+
+	for ( i = 0; i < _yybytes_len; ++i )
+		buf[i] = yybytes[i];
+
+	buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+	b = yy_scan_buffer(buf,n );
+	if ( ! b )
+		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
+
+	/* It's okay to grow etc. this buffer, and we should throw it
+	 * away when we're done.
+	 */
+	b->yy_is_our_buffer = 1;
+
+	return b;
+}
+/* %endif */
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+/* %if-c-only */
+static void yy_fatal_error (yyconst char* msg )
+{
+    	(void) fprintf( stderr, "%s\n", msg );
+	exit( YY_EXIT_FAILURE );
+}
+/* %endif */
+/* %if-c++-only */
+/* %endif */
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		yytext[yyleng] = (yy_hold_char); \
+		(yy_c_buf_p) = yytext + yyless_macro_arg; \
+		(yy_hold_char) = *(yy_c_buf_p); \
+		*(yy_c_buf_p) = '\0'; \
+		yyleng = yyless_macro_arg; \
+		} \
+	while ( 0 )
+
+/* Accessor  methods (get/set functions) to struct members. */
+
+/* %if-c-only */
+/* %if-reentrant */
+/* %endif */
+
+/** Get the current line number.
+ * 
+ */
+int yyget_lineno  (void)
+{
+        
+    return yylineno;
+}
+
+/** Get the input stream.
+ * 
+ */
+FILE *yyget_in  (void)
+{
+        return yyin;
+}
+
+/** Get the output stream.
+ * 
+ */
+FILE *yyget_out  (void)
+{
+        return yyout;
+}
+
+/** Get the length of the current token.
+ * 
+ */
+int yyget_leng  (void)
+{
+        return yyleng;
+}
+
+/** Get the current token.
+ * 
+ */
+
+char *yyget_text  (void)
+{
+        return yytext;
+}
+
+/* %if-reentrant */
+/* %endif */
+
+/** Set the current line number.
+ * @param line_number
+ * 
+ */
+void yyset_lineno (int  line_number )
+{
+    
+    yylineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ * 
+ * @see yy_switch_to_buffer
+ */
+void yyset_in (FILE *  in_str )
+{
+        yyin = in_str ;
+}
+
+void yyset_out (FILE *  out_str )
+{
+        yyout = out_str ;
+}
+
+int yyget_debug  (void)
+{
+        return yy_flex_debug;
+}
+
+void yyset_debug (int  bdebug )
+{
+        yy_flex_debug = bdebug ;
+}
+
+/* %endif */
+
+/* %if-reentrant */
+/* %if-bison-bridge */
+/* %endif */
+/* %endif if-c-only */
+
+/* %if-c-only */
+static int yy_init_globals (void)
+{
+        /* Initialization is the same as for the non-reentrant scanner.
+     * This function is called from yylex_destroy(), so don't allocate here.
+     */
+
+    (yy_buffer_stack) = 0;
+    (yy_buffer_stack_top) = 0;
+    (yy_buffer_stack_max) = 0;
+    (yy_c_buf_p) = (char *) 0;
+    (yy_init) = 0;
+    (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+    yyin = stdin;
+    yyout = stdout;
+#else
+    yyin = (FILE *) 0;
+    yyout = (FILE *) 0;
+#endif
+
+    /* For future reference: Set errno on error, since we are called by
+     * yylex_init()
+     */
+    return 0;
+}
+/* %endif */
+
+/* %if-c-only SNIP! this currently causes conflicts with the c++ scanner */
+/* yylex_destroy is for both reentrant and non-reentrant scanners. */
+int yylex_destroy  (void)
+{
+    
+    /* Pop the buffer stack, destroying each element. */
+	while(YY_CURRENT_BUFFER){
+		yy_delete_buffer(YY_CURRENT_BUFFER  );
+		YY_CURRENT_BUFFER_LVALUE = NULL;
+		yypop_buffer_state();
+	}
+
+	/* Destroy the stack itself. */
+	yyfree((yy_buffer_stack) );
+	(yy_buffer_stack) = NULL;
+
+    /* Reset the globals. This is important in a non-reentrant scanner so the next time
+     * yylex() is called, initialization will occur. */
+    yy_init_globals( );
+
+/* %if-reentrant */
+/* %endif */
+    return 0;
+}
+/* %endif */
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+	register int i;
+	for ( i = 0; i < n; ++i )
+		s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+	register int n;
+	for ( n = 0; s[n]; ++n )
+		;
+
+	return n;
+}
+#endif
+
+void *yyalloc (yy_size_t  size )
+{
+	return (void *) malloc( size );
+}
+
+void *yyrealloc  (void * ptr, yy_size_t  size )
+{
+	/* The cast to (char *) in the following accommodates both
+	 * implementations that use char* generic pointers, and those
+	 * that use void* generic pointers.  It works with the latter
+	 * because both ANSI C and C++ allow castless assignment from
+	 * any pointer type to void*, and deal with argument conversions
+	 * as though doing an assignment.
+	 */
+	return (void *) realloc( (char *) ptr, size );
+}
+
+void yyfree (void * ptr )
+{
+	free( (char *) ptr );	/* see yyrealloc() for (char *) cast */
+}
+
+/* %if-tables-serialization definitions */
+/* %define-yytables   The name for this specific scanner's tables. */
+#define YYTABLES_NAME "yytables"
+/* %endif */
+
+/* %ok-for-header */
+
+#line 97 "scripts/genksyms/lex.l"
+
+
+
+/* Bring in the keyword recognizer.  */
+
+#include "keywords.c"
+
+
+/* Macros to append to our phrase collection list.  */
+
+#define _APP(T,L)	do {						   \
+			  cur_node = next_node;				   \
+			  next_node = xmalloc(sizeof(*next_node));	   \
+			  next_node->next = cur_node;			   \
+			  cur_node->string = memcpy(xmalloc(L+1), T, L+1); \
+			  cur_node->tag = SYM_NORMAL;			   \
+			} while (0)
+
+#define APP		_APP(yytext, yyleng)
+
+
+/* The second stage lexer.  Here we incorporate knowledge of the state
+   of the parser to tailor the tokens that are returned.  */
+
+int
+yylex(void)
+{
+  static enum {
+    ST_NOTSTARTED, ST_NORMAL, ST_ATTRIBUTE, ST_ASM, ST_BRACKET, ST_BRACE,
+    ST_EXPRESSION, ST_TABLE_1, ST_TABLE_2, ST_TABLE_3, ST_TABLE_4,
+    ST_TABLE_5, ST_TABLE_6
+  } lexstate = ST_NOTSTARTED;
+
+  static int suppress_type_lookup, dont_want_brace_phrase;
+  static struct string_list *next_node;
+
+  int token, count = 0;
+  struct string_list *cur_node;
+
+  if (lexstate == ST_NOTSTARTED)
+    {
+      BEGIN(V2_TOKENS);
+      next_node = xmalloc(sizeof(*next_node));
+      next_node->next = NULL;
+      lexstate = ST_NORMAL;
+    }
+
+repeat:
+  token = yylex1();
+
+  if (token == 0)
+    return 0;
+  else if (token == FILENAME)
+    {
+      char *file, *e;
+
+      /* Save the filename and line number for later error messages.  */
+
+      if (cur_filename)
+	free(cur_filename);
+
+      file = strchr(yytext, '\"')+1;
+      e = strchr(file, '\"');
+      *e = '\0';
+      cur_filename = memcpy(xmalloc(e-file+1), file, e-file+1);
+      cur_line = atoi(yytext+2);
+
+      goto repeat;
+    }
+
+  switch (lexstate)
+    {
+    case ST_NORMAL:
+      switch (token)
+	{
+	case IDENT:
+	  APP;
+	  {
+	    const struct resword *r = is_reserved_word(yytext, yyleng);
+	    if (r)
+	      {
+		switch (token = r->token)
+		  {
+		  case ATTRIBUTE_KEYW:
+		    lexstate = ST_ATTRIBUTE;
+		    count = 0;
+		    goto repeat;
+		  case ASM_KEYW:
+		    lexstate = ST_ASM;
+		    count = 0;
+		    goto repeat;
+
+		  case STRUCT_KEYW:
+		  case UNION_KEYW:
+		    dont_want_brace_phrase = 3;
+		  case ENUM_KEYW:
+		    suppress_type_lookup = 2;
+		    goto fini;
+
+		  case EXPORT_SYMBOL_KEYW:
+		      goto fini;
+		  }
+	      }
+	    if (!suppress_type_lookup)
+	      {
+		struct symbol *sym = find_symbol(yytext, SYM_TYPEDEF);
+		if (sym && sym->type == SYM_TYPEDEF)
+		  token = TYPE;
+	      }
+	  }
+	  break;
+
+	case '[':
+	  APP;
+	  lexstate = ST_BRACKET;
+	  count = 1;
+	  goto repeat;
+
+	case '{':
+	  APP;
+	  if (dont_want_brace_phrase)
+	    break;
+	  lexstate = ST_BRACE;
+	  count = 1;
+	  goto repeat;
+
+	case '=': case ':':
+	  APP;
+	  lexstate = ST_EXPRESSION;
+	  break;
+
+	case DOTS:
+	default:
+	  APP;
+	  break;
+	}
+      break;
+
+    case ST_ATTRIBUTE:
+      APP;
+      switch (token)
+	{
+	case '(':
+	  ++count;
+	  goto repeat;
+	case ')':
+	  if (--count == 0)
+	    {
+	      lexstate = ST_NORMAL;
+	      token = ATTRIBUTE_PHRASE;
+	      break;
+	    }
+	  goto repeat;
+	default:
+	  goto repeat;
+	}
+      break;
+
+    case ST_ASM:
+      APP;
+      switch (token)
+	{
+	case '(':
+	  ++count;
+	  goto repeat;
+	case ')':
+	  if (--count == 0)
+	    {
+	      lexstate = ST_NORMAL;
+	      token = ASM_PHRASE;
+	      break;
+	    }
+	  goto repeat;
+	default:
+	  goto repeat;
+	}
+      break;
+
+    case ST_BRACKET:
+      APP;
+      switch (token)
+	{
+	case '[':
+	  ++count;
+	  goto repeat;
+	case ']':
+	  if (--count == 0)
+	    {
+	      lexstate = ST_NORMAL;
+	      token = BRACKET_PHRASE;
+	      break;
+	    }
+	  goto repeat;
+	default:
+	  goto repeat;
+	}
+      break;
+
+    case ST_BRACE:
+      APP;
+      switch (token)
+	{
+	case '{':
+	  ++count;
+	  goto repeat;
+	case '}':
+	  if (--count == 0)
+	    {
+	      lexstate = ST_NORMAL;
+	      token = BRACE_PHRASE;
+	      break;
+	    }
+	  goto repeat;
+	default:
+	  goto repeat;
+	}
+      break;
+
+    case ST_EXPRESSION:
+      switch (token)
+	{
+	case '(': case '[': case '{':
+	  ++count;
+	  APP;
+	  goto repeat;
+	case ')': case ']': case '}':
+	  --count;
+	  APP;
+	  goto repeat;
+	case ',': case ';':
+	  if (count == 0)
+	    {
+	      /* Put back the token we just read so's we can find it again
+		 after registering the expression.  */
+	      unput(token);
+
+	      lexstate = ST_NORMAL;
+	      token = EXPRESSION_PHRASE;
+	      break;
+	    }
+	  APP;
+	  goto repeat;
+	default:
+	  APP;
+	  goto repeat;
+	}
+      break;
+
+    case ST_TABLE_1:
+      goto repeat;
+
+    case ST_TABLE_2:
+      if (token == IDENT && yyleng == 1 && yytext[0] == 'X')
+	{
+	  token = EXPORT_SYMBOL_KEYW;
+	  lexstate = ST_TABLE_5;
+	  APP;
+	  break;
+	}
+      lexstate = ST_TABLE_6;
+      /* FALLTHRU */
+
+    case ST_TABLE_6:
+      switch (token)
+	{
+	case '{': case '[': case '(':
+	  ++count;
+	  break;
+	case '}': case ']': case ')':
+	  --count;
+	  break;
+	case ',':
+	  if (count == 0)
+	    lexstate = ST_TABLE_2;
+	  break;
+	};
+      goto repeat;
+
+    case ST_TABLE_3:
+      goto repeat;
+
+    case ST_TABLE_4:
+      if (token == ';')
+	lexstate = ST_NORMAL;
+      goto repeat;
+
+    case ST_TABLE_5:
+      switch (token)
+	{
+	case ',':
+	  token = ';';
+	  lexstate = ST_TABLE_2;
+	  APP;
+	  break;
+	default:
+	  APP;
+	  break;
+	}
+      break;
+
+    default:
+      exit(1);
+    }
+fini:
+
+  if (suppress_type_lookup > 0)
+    --suppress_type_lookup;
+  if (dont_want_brace_phrase > 0)
+    --dont_want_brace_phrase;
+
+  yylval = &next_node->next;
+
+  return token;
+}
+/* A Bison parser, made by GNU Bison 2.3.  */
+
+/* Skeleton interface for Bison's Yacc-like parsers in C
+
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     ASM_KEYW = 258,
+     ATTRIBUTE_KEYW = 259,
+     AUTO_KEYW = 260,
+     BOOL_KEYW = 261,
+     CHAR_KEYW = 262,
+     CONST_KEYW = 263,
+     DOUBLE_KEYW = 264,
+     ENUM_KEYW = 265,
+     EXTERN_KEYW = 266,
+     EXTENSION_KEYW = 267,
+     FLOAT_KEYW = 268,
+     INLINE_KEYW = 269,
+     INT_KEYW = 270,
+     LONG_KEYW = 271,
+     REGISTER_KEYW = 272,
+     RESTRICT_KEYW = 273,
+     SHORT_KEYW = 274,
+     SIGNED_KEYW = 275,
+     STATIC_KEYW = 276,
+     STRUCT_KEYW = 277,
+     TYPEDEF_KEYW = 278,
+     UNION_KEYW = 279,
+     UNSIGNED_KEYW = 280,
+     VOID_KEYW = 281,
+     VOLATILE_KEYW = 282,
+     TYPEOF_KEYW = 283,
+     EXPORT_SYMBOL_KEYW = 284,
+     ASM_PHRASE = 285,
+     ATTRIBUTE_PHRASE = 286,
+     BRACE_PHRASE = 287,
+     BRACKET_PHRASE = 288,
+     EXPRESSION_PHRASE = 289,
+     CHAR = 290,
+     DOTS = 291,
+     IDENT = 292,
+     INT = 293,
+     REAL = 294,
+     STRING = 295,
+     TYPE = 296,
+     OTHER = 297,
+     FILENAME = 298
+   };
+#endif
+/* Tokens.  */
+#define ASM_KEYW 258
+#define ATTRIBUTE_KEYW 259
+#define AUTO_KEYW 260
+#define BOOL_KEYW 261
+#define CHAR_KEYW 262
+#define CONST_KEYW 263
+#define DOUBLE_KEYW 264
+#define ENUM_KEYW 265
+#define EXTERN_KEYW 266
+#define EXTENSION_KEYW 267
+#define FLOAT_KEYW 268
+#define INLINE_KEYW 269
+#define INT_KEYW 270
+#define LONG_KEYW 271
+#define REGISTER_KEYW 272
+#define RESTRICT_KEYW 273
+#define SHORT_KEYW 274
+#define SIGNED_KEYW 275
+#define STATIC_KEYW 276
+#define STRUCT_KEYW 277
+#define TYPEDEF_KEYW 278
+#define UNION_KEYW 279
+#define UNSIGNED_KEYW 280
+#define VOID_KEYW 281
+#define VOLATILE_KEYW 282
+#define TYPEOF_KEYW 283
+#define EXPORT_SYMBOL_KEYW 284
+#define ASM_PHRASE 285
+#define ATTRIBUTE_PHRASE 286
+#define BRACE_PHRASE 287
+#define BRACKET_PHRASE 288
+#define EXPRESSION_PHRASE 289
+#define CHAR 290
+#define DOTS 291
+#define IDENT 292
+#define INT 293
+#define REAL 294
+#define STRING 295
+#define TYPE 296
+#define OTHER 297
+#define FILENAME 298
+
+
+
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef int YYSTYPE;
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+extern YYSTYPE yylval;
+
+
diff -uNra linux-2.6.27.6/scripts/genksyms/parse.c linux-2.6.27.6.yaffs/scripts/genksyms/parse.c
--- linux-2.6.27.6/scripts/genksyms/parse.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/genksyms/parse.c	2011-05-08 18:02:54.000000000 +0800
@@ -0,0 +1,2353 @@
+/* A Bison parser, made by GNU Bison 2.3.  */
+
+/* Skeleton implementation for Bison's Yacc-like parsers in C
+
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+   simplifying the original so-called "semantic" parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "2.3"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Using locations.  */
+#define YYLSP_NEEDED 0
+
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     ASM_KEYW = 258,
+     ATTRIBUTE_KEYW = 259,
+     AUTO_KEYW = 260,
+     BOOL_KEYW = 261,
+     CHAR_KEYW = 262,
+     CONST_KEYW = 263,
+     DOUBLE_KEYW = 264,
+     ENUM_KEYW = 265,
+     EXTERN_KEYW = 266,
+     EXTENSION_KEYW = 267,
+     FLOAT_KEYW = 268,
+     INLINE_KEYW = 269,
+     INT_KEYW = 270,
+     LONG_KEYW = 271,
+     REGISTER_KEYW = 272,
+     RESTRICT_KEYW = 273,
+     SHORT_KEYW = 274,
+     SIGNED_KEYW = 275,
+     STATIC_KEYW = 276,
+     STRUCT_KEYW = 277,
+     TYPEDEF_KEYW = 278,
+     UNION_KEYW = 279,
+     UNSIGNED_KEYW = 280,
+     VOID_KEYW = 281,
+     VOLATILE_KEYW = 282,
+     TYPEOF_KEYW = 283,
+     EXPORT_SYMBOL_KEYW = 284,
+     ASM_PHRASE = 285,
+     ATTRIBUTE_PHRASE = 286,
+     BRACE_PHRASE = 287,
+     BRACKET_PHRASE = 288,
+     EXPRESSION_PHRASE = 289,
+     CHAR = 290,
+     DOTS = 291,
+     IDENT = 292,
+     INT = 293,
+     REAL = 294,
+     STRING = 295,
+     TYPE = 296,
+     OTHER = 297,
+     FILENAME = 298
+   };
+#endif
+/* Tokens.  */
+#define ASM_KEYW 258
+#define ATTRIBUTE_KEYW 259
+#define AUTO_KEYW 260
+#define BOOL_KEYW 261
+#define CHAR_KEYW 262
+#define CONST_KEYW 263
+#define DOUBLE_KEYW 264
+#define ENUM_KEYW 265
+#define EXTERN_KEYW 266
+#define EXTENSION_KEYW 267
+#define FLOAT_KEYW 268
+#define INLINE_KEYW 269
+#define INT_KEYW 270
+#define LONG_KEYW 271
+#define REGISTER_KEYW 272
+#define RESTRICT_KEYW 273
+#define SHORT_KEYW 274
+#define SIGNED_KEYW 275
+#define STATIC_KEYW 276
+#define STRUCT_KEYW 277
+#define TYPEDEF_KEYW 278
+#define UNION_KEYW 279
+#define UNSIGNED_KEYW 280
+#define VOID_KEYW 281
+#define VOLATILE_KEYW 282
+#define TYPEOF_KEYW 283
+#define EXPORT_SYMBOL_KEYW 284
+#define ASM_PHRASE 285
+#define ATTRIBUTE_PHRASE 286
+#define BRACE_PHRASE 287
+#define BRACKET_PHRASE 288
+#define EXPRESSION_PHRASE 289
+#define CHAR 290
+#define DOTS 291
+#define IDENT 292
+#define INT 293
+#define REAL 294
+#define STRING 295
+#define TYPE 296
+#define OTHER 297
+#define FILENAME 298
+
+
+
+
+/* Copy the first part of user declarations.  */
+#line 24 "scripts/genksyms/parse.y"
+
+
+#include <assert.h>
+#include <malloc.h>
+#include "genksyms.h"
+
+static int is_typedef;
+static int is_extern;
+static char *current_name;
+static struct string_list *decl_spec;
+
+static void yyerror(const char *);
+
+static inline void
+remove_node(struct string_list **p)
+{
+  struct string_list *node = *p;
+  *p = node->next;
+  free_node(node);
+}
+
+static inline void
+remove_list(struct string_list **pb, struct string_list **pe)
+{
+  struct string_list *b = *pb, *e = *pe;
+  *pb = e;
+  free_list(b, e);
+}
+
+
+
+/* Enabling traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 1
+#endif
+
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* Enabling the token table.  */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef int YYSTYPE;
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+
+
+/* Copy the second part of user declarations.  */
+
+
+/* Line 216 of yacc.c.  */
+#line 223 "scripts/genksyms/parse.c"
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#elif (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+typedef signed char yytype_int8;
+#else
+typedef short int yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+#  define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+#  define YYSIZE_T size_t
+# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYSIZE_T size_t
+# else
+#  define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(msgid) dgettext ("bison-runtime", msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(msgid) msgid
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E.  */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(e) ((void) (e))
+#else
+# define YYUSE(e) /* empty */
+#endif
+
+/* Identity function, used to suppress warnings about constant conditions.  */
+#ifndef lint
+# define YYID(n) (n)
+#else
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static int
+YYID (int i)
+#else
+static int
+YYID (i)
+    int i;
+#endif
+{
+  return i;
+}
+#endif
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols.  */
+
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
+#   elif defined __BUILTIN_VA_ARG_INCR
+#    include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+#   elif defined _AIX
+#    define YYSTACK_ALLOC __alloca
+#   elif defined _MSC_VER
+#    include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+#    define alloca _alloca
+#   else
+#    define YYSTACK_ALLOC alloca
+#    if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#     ifndef _STDLIB_H
+#      define _STDLIB_H 1
+#     endif
+#    endif
+#   endif
+#  endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+   /* Pacify GCC's `empty if-body' warning.  */
+#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+#  endif
+# else
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+#  endif
+#  if (defined __cplusplus && ! defined _STDLIB_H \
+       && ! ((defined YYMALLOC || defined malloc) \
+	     && (defined YYFREE || defined free)))
+#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#   ifndef _STDLIB_H
+#    define _STDLIB_H 1
+#   endif
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+     && (! defined __cplusplus \
+	 || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member.  */
+union yyalloc
+{
+  yytype_int16 yyss;
+  YYSTYPE yyvs;
+  };
+
+/* The size of the maximum gap between one aligned stack and the next.  */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+   N elements.  */
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+      + YYSTACK_GAP_MAXIMUM)
+
+/* Copy COUNT objects from FROM to TO.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined __GNUC__ && 1 < __GNUC__
+#   define YYCOPY(To, From, Count) \
+      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+#  else
+#   define YYCOPY(To, From, Count)		\
+      do					\
+	{					\
+	  YYSIZE_T yyi;				\
+	  for (yyi = 0; yyi < (Count); yyi++)	\
+	    (To)[yyi] = (From)[yyi];		\
+	}					\
+      while (YYID (0))
+#  endif
+# endif
+
+/* Relocate STACK from its old location to the new one.  The
+   local variables YYSIZE and YYSTACKSIZE give the old and new number of
+   elements in the stack, and YYPTR gives the new location of the
+   stack.  Advance YYPTR to a properly aligned location for the next
+   stack.  */
+# define YYSTACK_RELOCATE(Stack)					\
+    do									\
+      {									\
+	YYSIZE_T yynewbytes;						\
+	YYCOPY (&yyptr->Stack, Stack, yysize);				\
+	Stack = &yyptr->Stack;						\
+	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+	yyptr += yynewbytes / sizeof (*yyptr);				\
+      }									\
+    while (YYID (0))
+
+#endif
+
+/* YYFINAL -- State number of the termination state.  */
+#define YYFINAL  4
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   523
+
+/* YYNTOKENS -- Number of terminals.  */
+#define YYNTOKENS  53
+/* YYNNTS -- Number of nonterminals.  */
+#define YYNNTS  46
+/* YYNRULES -- Number of rules.  */
+#define YYNRULES  126
+/* YYNRULES -- Number of states.  */
+#define YYNSTATES  178
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   298
+
+#define YYTRANSLATE(YYX)						\
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
+static const yytype_uint8 yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+      47,    49,    48,     2,    46,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,    52,    44,
+       2,    50,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,    51,     2,    45,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,
+      25,    26,    27,    28,    29,    30,    31,    32,    33,    34,
+      35,    36,    37,    38,    39,    40,    41,    42,    43
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+   YYRHS.  */
+static const yytype_uint16 yyprhs[] =
+{
+       0,     0,     3,     5,     8,     9,    12,    13,    18,    19,
+      23,    25,    27,    29,    31,    34,    37,    41,    42,    44,
+      46,    50,    55,    56,    58,    60,    63,    65,    67,    69,
+      71,    73,    75,    77,    79,    81,    87,    92,    95,    98,
+     101,   105,   109,   113,   116,   119,   122,   124,   126,   128,
+     130,   132,   134,   136,   138,   140,   142,   144,   147,   148,
+     150,   152,   155,   157,   159,   161,   163,   166,   168,   170,
+     175,   180,   183,   187,   191,   194,   196,   198,   200,   205,
+     210,   213,   217,   221,   224,   226,   230,   231,   233,   235,
+     239,   242,   245,   247,   248,   250,   252,   257,   262,   265,
+     269,   273,   277,   278,   280,   283,   287,   291,   292,   294,
+     296,   299,   303,   306,   307,   309,   311,   315,   318,   321,
+     323,   326,   327,   330,   333,   334,   336
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS.  */
+static const yytype_int8 yyrhs[] =
+{
+      54,     0,    -1,    55,    -1,    54,    55,    -1,    -1,    56,
+      57,    -1,    -1,    12,    23,    58,    60,    -1,    -1,    23,
+      59,    60,    -1,    60,    -1,    84,    -1,    96,    -1,    98,
+      -1,     1,    44,    -1,     1,    45,    -1,    64,    61,    44,
+      -1,    -1,    62,    -1,    63,    -1,    62,    46,    63,    -1,
+      74,    97,    95,    85,    -1,    -1,    65,    -1,    66,    -1,
+      65,    66,    -1,    67,    -1,    68,    -1,     5,    -1,    17,
+      -1,    21,    -1,    11,    -1,    14,    -1,    69,    -1,    73,
+      -1,    28,    47,    65,    48,    49,    -1,    28,    47,    65,
+      49,    -1,    22,    37,    -1,    24,    37,    -1,    10,    37,
+      -1,    22,    37,    87,    -1,    24,    37,    87,    -1,    10,
+      37,    32,    -1,    10,    32,    -1,    22,    87,    -1,    24,
+      87,    -1,     7,    -1,    19,    -1,    15,    -1,    16,    -1,
+      20,    -1,    25,    -1,    13,    -1,     9,    -1,    26,    -1,
+       6,    -1,    41,    -1,    48,    71,    -1,    -1,    72,    -1,
+      73,    -1,    72,    73,    -1,     8,    -1,    27,    -1,    31,
+      -1,    18,    -1,    70,    74,    -1,    75,    -1,    37,    -1,
+      75,    47,    78,    49,    -1,    75,    47,     1,    49,    -1,
+      75,    33,    -1,    47,    74,    49,    -1,    47,     1,    49,
+      -1,    70,    76,    -1,    77,    -1,    37,    -1,    41,    -1,
+      77,    47,    78,    49,    -1,    77,    47,     1,    49,    -1,
+      77,    33,    -1,    47,    76,    49,    -1,    47,     1,    49,
+      -1,    79,    36,    -1,    79,    -1,    80,    46,    36,    -1,
+      -1,    80,    -1,    81,    -1,    80,    46,    81,    -1,    65,
+      82,    -1,    70,    82,    -1,    83,    -1,    -1,    37,    -1,
+      41,    -1,    83,    47,    78,    49,    -1,    83,    47,     1,
+      49,    -1,    83,    33,    -1,    47,    82,    49,    -1,    47,
+       1,    49,    -1,    64,    74,    32,    -1,    -1,    86,    -1,
+      50,    34,    -1,    51,    88,    45,    -1,    51,     1,    45,
+      -1,    -1,    89,    -1,    90,    -1,    89,    90,    -1,    64,
+      91,    44,    -1,     1,    44,    -1,    -1,    92,    -1,    93,
+      -1,    92,    46,    93,    -1,    76,    95,    -1,    37,    94,
+      -1,    94,    -1,    52,    34,    -1,    -1,    95,    31,    -1,
+      30,    44,    -1,    -1,    30,    -1,    29,    47,    37,    49,
+      44,    -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
+static const yytype_uint16 yyrline[] =
+{
+       0,   103,   103,   104,   108,   108,   114,   114,   116,   116,
+     118,   119,   120,   121,   122,   123,   127,   141,   142,   146,
+     154,   167,   173,   174,   178,   179,   183,   189,   193,   194,
+     195,   196,   197,   201,   202,   203,   204,   208,   210,   212,
+     216,   223,   230,   239,   240,   241,   245,   246,   247,   248,
+     249,   250,   251,   252,   253,   254,   255,   259,   264,   265,
+     269,   270,   274,   274,   274,   275,   283,   284,   288,   297,
+     299,   301,   303,   305,   312,   313,   317,   318,   319,   321,
+     323,   325,   327,   332,   333,   334,   338,   339,   343,   344,
+     349,   354,   356,   360,   361,   369,   373,   375,   377,   379,
+     381,   386,   395,   396,   401,   406,   407,   411,   412,   416,
+     417,   421,   423,   428,   429,   433,   434,   438,   439,   440,
+     444,   448,   449,   453,   457,   458,   462
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals.  */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "ASM_KEYW", "ATTRIBUTE_KEYW",
+  "AUTO_KEYW", "BOOL_KEYW", "CHAR_KEYW", "CONST_KEYW", "DOUBLE_KEYW",
+  "ENUM_KEYW", "EXTERN_KEYW", "EXTENSION_KEYW", "FLOAT_KEYW",
+  "INLINE_KEYW", "INT_KEYW", "LONG_KEYW", "REGISTER_KEYW", "RESTRICT_KEYW",
+  "SHORT_KEYW", "SIGNED_KEYW", "STATIC_KEYW", "STRUCT_KEYW",
+  "TYPEDEF_KEYW", "UNION_KEYW", "UNSIGNED_KEYW", "VOID_KEYW",
+  "VOLATILE_KEYW", "TYPEOF_KEYW", "EXPORT_SYMBOL_KEYW", "ASM_PHRASE",
+  "ATTRIBUTE_PHRASE", "BRACE_PHRASE", "BRACKET_PHRASE",
+  "EXPRESSION_PHRASE", "CHAR", "DOTS", "IDENT", "INT", "REAL", "STRING",
+  "TYPE", "OTHER", "FILENAME", "';'", "'}'", "','", "'('", "'*'", "')'",
+  "'='", "'{'", "':'", "$accept", "declaration_seq", "declaration", "@1",
+  "declaration1", "@2", "@3", "simple_declaration",
+  "init_declarator_list_opt", "init_declarator_list", "init_declarator",
+  "decl_specifier_seq_opt", "decl_specifier_seq", "decl_specifier",
+  "storage_class_specifier", "type_specifier", "simple_type_specifier",
+  "ptr_operator", "cvar_qualifier_seq_opt", "cvar_qualifier_seq",
+  "cvar_qualifier", "declarator", "direct_declarator", "nested_declarator",
+  "direct_nested_declarator", "parameter_declaration_clause",
+  "parameter_declaration_list_opt", "parameter_declaration_list",
+  "parameter_declaration", "m_abstract_declarator",
+  "direct_m_abstract_declarator", "function_definition", "initializer_opt",
+  "initializer", "class_body", "member_specification_opt",
+  "member_specification", "member_declaration",
+  "member_declarator_list_opt", "member_declarator_list",
+  "member_declarator", "member_bitfield_declarator", "attribute_opt",
+  "asm_definition", "asm_phrase_opt", "export_definition", 0
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+   token YYLEX-NUM.  */
+static const yytype_uint16 yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
+     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
+     275,   276,   277,   278,   279,   280,   281,   282,   283,   284,
+     285,   286,   287,   288,   289,   290,   291,   292,   293,   294,
+     295,   296,   297,   298,    59,   125,    44,    40,    42,    41,
+      61,   123,    58
+};
+# endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const yytype_uint8 yyr1[] =
+{
+       0,    53,    54,    54,    56,    55,    58,    57,    59,    57,
+      57,    57,    57,    57,    57,    57,    60,    61,    61,    62,
+      62,    63,    64,    64,    65,    65,    66,    66,    67,    67,
+      67,    67,    67,    68,    68,    68,    68,    68,    68,    68,
+      68,    68,    68,    68,    68,    68,    69,    69,    69,    69,
+      69,    69,    69,    69,    69,    69,    69,    70,    71,    71,
+      72,    72,    73,    73,    73,    73,    74,    74,    75,    75,
+      75,    75,    75,    75,    76,    76,    77,    77,    77,    77,
+      77,    77,    77,    78,    78,    78,    79,    79,    80,    80,
+      81,    82,    82,    83,    83,    83,    83,    83,    83,    83,
+      83,    84,    85,    85,    86,    87,    87,    88,    88,    89,
+      89,    90,    90,    91,    91,    92,    92,    93,    93,    93,
+      94,    95,    95,    96,    97,    97,    98
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
+static const yytype_uint8 yyr2[] =
+{
+       0,     2,     1,     2,     0,     2,     0,     4,     0,     3,
+       1,     1,     1,     1,     2,     2,     3,     0,     1,     1,
+       3,     4,     0,     1,     1,     2,     1,     1,     1,     1,
+       1,     1,     1,     1,     1,     5,     4,     2,     2,     2,
+       3,     3,     3,     2,     2,     2,     1,     1,     1,     1,
+       1,     1,     1,     1,     1,     1,     1,     2,     0,     1,
+       1,     2,     1,     1,     1,     1,     2,     1,     1,     4,
+       4,     2,     3,     3,     2,     1,     1,     1,     4,     4,
+       2,     3,     3,     2,     1,     3,     0,     1,     1,     3,
+       2,     2,     1,     0,     1,     1,     4,     4,     2,     3,
+       3,     3,     0,     1,     2,     3,     3,     0,     1,     1,
+       2,     3,     2,     0,     1,     1,     3,     2,     2,     1,
+       2,     0,     2,     2,     0,     1,     5
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+   means the default is an error.  */
+static const yytype_uint8 yydefact[] =
+{
+       4,     4,     2,     0,     1,     3,     0,    28,    55,    46,
+      62,    53,     0,    31,     0,    52,    32,    48,    49,    29,
+      65,    47,    50,    30,     0,     8,     0,    51,    54,    63,
+       0,     0,     0,    64,    56,     5,    10,    17,    23,    24,
+      26,    27,    33,    34,    11,    12,    13,    14,    15,    43,
+      39,     6,    37,     0,    44,    22,    38,    45,     0,     0,
+     123,    68,     0,    58,     0,    18,    19,     0,   124,    67,
+      25,    42,    22,    40,     0,   113,     0,     0,   109,     9,
+      17,    41,     0,     0,     0,     0,    57,    59,    60,    16,
+       0,    66,   125,   101,   121,    71,     0,     7,   112,   106,
+      76,    77,     0,     0,     0,   121,    75,     0,   114,   115,
+     119,   105,     0,   110,   124,     0,    36,     0,    73,    72,
+      61,    20,   102,     0,    93,     0,    84,    87,    88,   118,
+       0,    76,     0,   120,    74,   117,    80,     0,   111,     0,
+      35,   126,   122,     0,    21,   103,    70,    94,    56,     0,
+      93,    90,    92,    69,    83,     0,    82,    81,     0,     0,
+     116,   104,     0,    95,     0,    91,    98,     0,    85,    89,
+      79,    78,   100,    99,     0,     0,    97,    96
+};
+
+/* YYDEFGOTO[NTERM-NUM].  */
+static const yytype_int16 yydefgoto[] =
+{
+      -1,     1,     2,     3,    35,    72,    55,    36,    64,    65,
+      66,    75,    38,    39,    40,    41,    42,    67,    86,    87,
+      43,   114,    69,   105,   106,   125,   126,   127,   128,   151,
+     152,    44,   144,   145,    54,    76,    77,    78,   107,   108,
+     109,   110,   122,    45,    94,    46
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
+#define YYPACT_NINF -134
+static const yytype_int16 yypact[] =
+{
+    -134,    16,  -134,   312,  -134,  -134,    20,  -134,  -134,  -134,
+    -134,  -134,   -18,  -134,    -3,  -134,  -134,  -134,  -134,  -134,
+    -134,  -134,  -134,  -134,   -26,  -134,   -25,  -134,  -134,  -134,
+      -7,     5,    27,  -134,  -134,  -134,  -134,    46,   482,  -134,
+    -134,  -134,  -134,  -134,  -134,  -134,  -134,  -134,  -134,  -134,
+      -8,  -134,    30,    97,  -134,   482,    30,  -134,   482,     7,
+    -134,  -134,    12,    10,    42,    55,  -134,    46,   -15,    15,
+    -134,  -134,   482,  -134,    25,    26,    47,   145,  -134,  -134,
+      46,  -134,   356,    39,    71,    77,  -134,    10,  -134,  -134,
+      46,  -134,  -134,  -134,  -134,  -134,   193,  -134,  -134,  -134,
+      75,  -134,     6,    95,    43,  -134,    28,    86,    85,  -134,
+    -134,  -134,    88,  -134,   103,    87,  -134,    91,  -134,  -134,
+    -134,  -134,   -23,    90,   401,    94,   101,   102,  -134,  -134,
+      98,  -134,   108,  -134,  -134,   109,  -134,   230,  -134,    26,
+    -134,  -134,  -134,   134,  -134,  -134,  -134,  -134,  -134,     9,
+      48,  -134,    35,  -134,  -134,   445,  -134,  -134,   125,   126,
+    -134,  -134,   128,  -134,   129,  -134,  -134,   267,  -134,  -134,
+    -134,  -134,  -134,  -134,   130,   131,  -134,  -134
+};
+
+/* YYPGOTO[NTERM-NUM].  */
+static const yytype_int16 yypgoto[] =
+{
+    -134,  -134,   180,  -134,  -134,  -134,  -134,   -33,  -134,  -134,
+      93,     0,   -58,   -37,  -134,  -134,  -134,   -73,  -134,  -134,
+     -54,   -32,  -134,   -81,  -134,  -133,  -134,  -134,    29,   -50,
+    -134,  -134,  -134,  -134,   -20,  -134,  -134,   110,  -134,  -134,
+      49,    96,    80,  -134,  -134,  -134
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule which
+   number is the opposite.  If zero, do what YYDEFACT says.
+   If YYTABLE_NINF, syntax error.  */
+#define YYTABLE_NINF -109
+static const yytype_int16 yytable[] =
+{
+      82,    70,   104,    37,   159,    68,    57,   130,   142,    88,
+     162,    52,    56,    84,    49,    92,     4,    93,    10,    50,
+      51,   132,    79,   134,    71,    53,    53,   143,    20,   104,
+      85,   104,    73,   120,   175,    91,    81,    29,   124,    97,
+      58,    33,   -93,   131,    83,    70,   147,   101,    95,    61,
+     163,   150,    59,   102,    63,    80,   149,    63,   -93,    62,
+      63,   136,    96,   100,    47,    48,   104,   101,   166,    98,
+      99,    60,    80,   102,    63,   137,   150,   150,   103,   124,
+     131,    53,   167,    61,   101,   147,    89,    70,   117,   163,
+     102,    63,   111,    62,    63,   149,    63,   124,    74,   164,
+     165,    90,     7,     8,     9,    10,    11,    12,    13,   124,
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,
+     118,    26,    27,    28,    29,    30,   119,   103,    33,   133,
+     138,   139,    98,    92,   -22,   141,   140,   154,    34,   146,
+     142,   -22,  -107,   153,   -22,   -22,   112,   156,   155,   -22,
+       7,     8,     9,    10,    11,    12,    13,   157,    15,    16,
+      17,    18,    19,    20,    21,    22,    23,    24,   161,    26,
+      27,    28,    29,    30,   170,   171,    33,   172,   173,   176,
+     177,     5,   -22,   121,   169,   135,    34,   113,   160,   -22,
+    -108,     0,   -22,   -22,   123,     0,   129,   -22,     7,     8,
+       9,    10,    11,    12,    13,     0,    15,    16,    17,    18,
+      19,    20,    21,    22,    23,    24,     0,    26,    27,    28,
+      29,    30,     0,     0,    33,     0,     0,     0,     0,   -86,
+       0,   158,     0,     0,    34,     7,     8,     9,    10,    11,
+      12,    13,   -86,    15,    16,    17,    18,    19,    20,    21,
+      22,    23,    24,     0,    26,    27,    28,    29,    30,     0,
+       0,    33,     0,     0,     0,     0,   -86,     0,   174,     0,
+       0,    34,     7,     8,     9,    10,    11,    12,    13,   -86,
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,
+       0,    26,    27,    28,    29,    30,     0,     0,    33,     0,
+       0,     0,     0,   -86,     0,     0,     0,     0,    34,     0,
+       0,     0,     0,     6,     0,     0,   -86,     7,     8,     9,
+      10,    11,    12,    13,    14,    15,    16,    17,    18,    19,
+      20,    21,    22,    23,    24,    25,    26,    27,    28,    29,
+      30,    31,    32,    33,     0,     0,     0,     0,     0,   -22,
+       0,     0,     0,    34,     0,     0,   -22,     0,     0,   -22,
+     -22,     7,     8,     9,    10,    11,    12,    13,     0,    15,
+      16,    17,    18,    19,    20,    21,    22,    23,    24,     0,
+      26,    27,    28,    29,    30,     0,     0,    33,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,    34,     0,     0,
+       0,     0,     0,     0,   115,   116,     7,     8,     9,    10,
+      11,    12,    13,     0,    15,    16,    17,    18,    19,    20,
+      21,    22,    23,    24,     0,    26,    27,    28,    29,    30,
+       0,     0,    33,     0,     0,     0,     0,     0,   147,     0,
+       0,     0,   148,     0,     0,     0,     0,     0,   149,    63,
+       7,     8,     9,    10,    11,    12,    13,     0,    15,    16,
+      17,    18,    19,    20,    21,    22,    23,    24,     0,    26,
+      27,    28,    29,    30,     0,     0,    33,     0,     0,     0,
+       0,   168,     0,     0,     0,     0,    34,     7,     8,     9,
+      10,    11,    12,    13,     0,    15,    16,    17,    18,    19,
+      20,    21,    22,    23,    24,     0,    26,    27,    28,    29,
+      30,     0,     0,    33,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,    34
+};
+
+static const yytype_int16 yycheck[] =
+{
+      58,    38,    75,     3,   137,    37,    26,     1,    31,    63,
+       1,    37,    37,     1,    32,    30,     0,    32,     8,    37,
+      23,   102,    55,   104,    32,    51,    51,    50,    18,   102,
+      62,   104,    52,    87,   167,    67,    56,    27,    96,    72,
+      47,    31,    33,    37,    37,    82,    37,    41,    33,    37,
+      41,   124,    47,    47,    48,    55,    47,    48,    49,    47,
+      48,    33,    47,    37,    44,    45,   139,    41,    33,    44,
+      45,    44,    72,    47,    48,    47,   149,   150,    52,   137,
+      37,    51,    47,    37,    41,    37,    44,   124,    49,    41,
+      47,    48,    45,    47,    48,    47,    48,   155,     1,   149,
+     150,    46,     5,     6,     7,     8,     9,    10,    11,   167,
+      13,    14,    15,    16,    17,    18,    19,    20,    21,    22,
+      49,    24,    25,    26,    27,    28,    49,    52,    31,    34,
+      44,    46,    44,    30,    37,    44,    49,    36,    41,    49,
+      31,    44,    45,    49,    47,    48,     1,    49,    46,    52,
+       5,     6,     7,     8,     9,    10,    11,    49,    13,    14,
+      15,    16,    17,    18,    19,    20,    21,    22,    34,    24,
+      25,    26,    27,    28,    49,    49,    31,    49,    49,    49,
+      49,     1,    37,    90,   155,   105,    41,    77,   139,    44,
+      45,    -1,    47,    48,     1,    -1,   100,    52,     5,     6,
+       7,     8,     9,    10,    11,    -1,    13,    14,    15,    16,
+      17,    18,    19,    20,    21,    22,    -1,    24,    25,    26,
+      27,    28,    -1,    -1,    31,    -1,    -1,    -1,    -1,    36,
+      -1,     1,    -1,    -1,    41,     5,     6,     7,     8,     9,
+      10,    11,    49,    13,    14,    15,    16,    17,    18,    19,
+      20,    21,    22,    -1,    24,    25,    26,    27,    28,    -1,
+      -1,    31,    -1,    -1,    -1,    -1,    36,    -1,     1,    -1,
+      -1,    41,     5,     6,     7,     8,     9,    10,    11,    49,
+      13,    14,    15,    16,    17,    18,    19,    20,    21,    22,
+      -1,    24,    25,    26,    27,    28,    -1,    -1,    31,    -1,
+      -1,    -1,    -1,    36,    -1,    -1,    -1,    -1,    41,    -1,
+      -1,    -1,    -1,     1,    -1,    -1,    49,     5,     6,     7,
+       8,     9,    10,    11,    12,    13,    14,    15,    16,    17,
+      18,    19,    20,    21,    22,    23,    24,    25,    26,    27,
+      28,    29,    30,    31,    -1,    -1,    -1,    -1,    -1,    37,
+      -1,    -1,    -1,    41,    -1,    -1,    44,    -1,    -1,    47,
+      48,     5,     6,     7,     8,     9,    10,    11,    -1,    13,
+      14,    15,    16,    17,    18,    19,    20,    21,    22,    -1,
+      24,    25,    26,    27,    28,    -1,    -1,    31,    -1,    -1,
+      -1,    -1,    -1,    -1,    -1,    -1,    -1,    41,    -1,    -1,
+      -1,    -1,    -1,    -1,    48,    49,     5,     6,     7,     8,
+       9,    10,    11,    -1,    13,    14,    15,    16,    17,    18,
+      19,    20,    21,    22,    -1,    24,    25,    26,    27,    28,
+      -1,    -1,    31,    -1,    -1,    -1,    -1,    -1,    37,    -1,
+      -1,    -1,    41,    -1,    -1,    -1,    -1,    -1,    47,    48,
+       5,     6,     7,     8,     9,    10,    11,    -1,    13,    14,
+      15,    16,    17,    18,    19,    20,    21,    22,    -1,    24,
+      25,    26,    27,    28,    -1,    -1,    31,    -1,    -1,    -1,
+      -1,    36,    -1,    -1,    -1,    -1,    41,     5,     6,     7,
+       8,     9,    10,    11,    -1,    13,    14,    15,    16,    17,
+      18,    19,    20,    21,    22,    -1,    24,    25,    26,    27,
+      28,    -1,    -1,    31,    -1,    -1,    -1,    -1,    -1,    -1,
+      -1,    -1,    -1,    41
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+   symbol of state STATE-NUM.  */
+static const yytype_uint8 yystos[] =
+{
+       0,    54,    55,    56,     0,    55,     1,     5,     6,     7,
+       8,     9,    10,    11,    12,    13,    14,    15,    16,    17,
+      18,    19,    20,    21,    22,    23,    24,    25,    26,    27,
+      28,    29,    30,    31,    41,    57,    60,    64,    65,    66,
+      67,    68,    69,    73,    84,    96,    98,    44,    45,    32,
+      37,    23,    37,    51,    87,    59,    37,    87,    47,    47,
+      44,    37,    47,    48,    61,    62,    63,    70,    74,    75,
+      66,    32,    58,    87,     1,    64,    88,    89,    90,    60,
+      64,    87,    65,    37,     1,    74,    71,    72,    73,    44,
+      46,    74,    30,    32,    97,    33,    47,    60,    44,    45,
+      37,    41,    47,    52,    70,    76,    77,    91,    92,    93,
+      94,    45,     1,    90,    74,    48,    49,    49,    49,    49,
+      73,    63,    95,     1,    65,    78,    79,    80,    81,    94,
+       1,    37,    76,    34,    76,    95,    33,    47,    44,    46,
+      49,    44,    31,    50,    85,    86,    49,    37,    41,    47,
+      70,    82,    83,    49,    36,    46,    49,    49,     1,    78,
+      93,    34,     1,    41,    82,    82,    33,    47,    36,    81,
+      49,    49,    49,    49,     1,    78,    49,    49
+};
+
+#define yyerrok		(yyerrstatus = 0)
+#define yyclearin	(yychar = YYEMPTY)
+#define YYEMPTY		(-2)
+#define YYEOF		0
+
+#define YYACCEPT	goto yyacceptlab
+#define YYABORT		goto yyabortlab
+#define YYERROR		goto yyerrorlab
+
+
+/* Like YYERROR except do call yyerror.  This remains here temporarily
+   to ease the transition to the new meaning of YYERROR, for GCC.
+   Once GCC version 2 has supplanted version 1, this can go.  */
+
+#define YYFAIL		goto yyerrlab
+
+#define YYRECOVERING()  (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value)					\
+do								\
+  if (yychar == YYEMPTY && yylen == 1)				\
+    {								\
+      yychar = (Token);						\
+      yylval = (Value);						\
+      yytoken = YYTRANSLATE (yychar);				\
+      YYPOPSTACK (1);						\
+      goto yybackup;						\
+    }								\
+  else								\
+    {								\
+      yyerror (YY_("syntax error: cannot back up")); \
+      YYERROR;							\
+    }								\
+while (YYID (0))
+
+
+#define YYTERROR	1
+#define YYERRCODE	256
+
+
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+   If N is 0, then set CURRENT to the empty location which ends
+   the previous symbol: RHS[0] (always defined).  */
+
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+#ifndef YYLLOC_DEFAULT
+# define YYLLOC_DEFAULT(Current, Rhs, N)				\
+    do									\
+      if (YYID (N))                                                    \
+	{								\
+	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
+	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
+	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
+	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
+	}								\
+      else								\
+	{								\
+	  (Current).first_line   = (Current).last_line   =		\
+	    YYRHSLOC (Rhs, 0).last_line;				\
+	  (Current).first_column = (Current).last_column =		\
+	    YYRHSLOC (Rhs, 0).last_column;				\
+	}								\
+    while (YYID (0))
+#endif
+
+
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+   This macro was not mandated originally: define only if we know
+   we won't break user code: when these are the locations we know.  */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+#  define YY_LOCATION_PRINT(File, Loc)			\
+     fprintf (File, "%d.%d-%d.%d",			\
+	      (Loc).first_line, (Loc).first_column,	\
+	      (Loc).last_line,  (Loc).last_column)
+# else
+#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
+
+
+/* YYLEX -- calling `yylex' with the right arguments.  */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
+
+/* Enable debugging if requested.  */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args)			\
+do {						\
+  if (yydebug)					\
+    YYFPRINTF Args;				\
+} while (YYID (0))
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)			  \
+do {									  \
+  if (yydebug)								  \
+    {									  \
+      YYFPRINTF (stderr, "%s ", Title);					  \
+      yy_symbol_print (stderr,						  \
+		  Type, Value); \
+      YYFPRINTF (stderr, "\n");						  \
+    }									  \
+} while (YYID (0))
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_value_print (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE const * const yyvaluep;
+#endif
+{
+  if (!yyvaluep)
+    return;
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# else
+  YYUSE (yyoutput);
+# endif
+  switch (yytype)
+    {
+      default:
+	break;
+    }
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_print (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE const * const yyvaluep;
+#endif
+{
+  if (yytype < YYNTOKENS)
+    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+  else
+    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+  yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+  YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_stack_print (yytype_int16 *bottom, yytype_int16 *top)
+#else
+static void
+yy_stack_print (bottom, top)
+    yytype_int16 *bottom;
+    yytype_int16 *top;
+#endif
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (; bottom <= top; ++bottom)
+    YYFPRINTF (stderr, " %d", *bottom);
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)				\
+do {								\
+  if (yydebug)							\
+    yy_stack_print ((Bottom), (Top));				\
+} while (YYID (0))
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
+#else
+static void
+yy_reduce_print (yyvsp, yyrule)
+    YYSTYPE *yyvsp;
+    int yyrule;
+#endif
+{
+  int yynrhs = yyr2[yyrule];
+  int yyi;
+  unsigned long int yylno = yyrline[yyrule];
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+	     yyrule - 1, yylno);
+  /* The symbols being reduced.  */
+  for (yyi = 0; yyi < yynrhs; yyi++)
+    {
+      fprintf (stderr, "   $%d = ", yyi + 1);
+      yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
+		       &(yyvsp[(yyi + 1) - (yynrhs)])
+		       		       );
+      fprintf (stderr, "\n");
+    }
+}
+
+# define YY_REDUCE_PRINT(Rule)		\
+do {					\
+  if (yydebug)				\
+    yy_reduce_print (yyvsp, Rule); \
+} while (YYID (0))
+
+/* Nonzero means print parse trace.  It is left uninitialized so that
+   multiple parsers can coexist.  */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks.  */
+#ifndef	YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+   if the built-in stack extension method is used).
+
+   Do not make this value too large; the results are undefined if
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+   evaluated with infinite-precision integer arithmetic.  */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+#  if defined __GLIBC__ && defined _STRING_H
+#   define yystrlen strlen
+#  else
+/* Return the length of YYSTR.  */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static YYSIZE_T
+yystrlen (const char *yystr)
+#else
+static YYSIZE_T
+yystrlen (yystr)
+    const char *yystr;
+#endif
+{
+  YYSIZE_T yylen;
+  for (yylen = 0; yystr[yylen]; yylen++)
+    continue;
+  return yylen;
+}
+#  endif
+# endif
+
+# ifndef yystpcpy
+#  if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+#   define yystpcpy stpcpy
+#  else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+   YYDEST.  */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+#else
+static char *
+yystpcpy (yydest, yysrc)
+    char *yydest;
+    const char *yysrc;
+#endif
+{
+  char *yyd = yydest;
+  const char *yys = yysrc;
+
+  while ((*yyd++ = *yys++) != '\0')
+    continue;
+
+  return yyd - 1;
+}
+#  endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      YYSIZE_T yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+	switch (*++yyp)
+	  {
+	  case '\'':
+	  case ',':
+	    goto do_not_strip_quotes;
+
+	  case '\\':
+	    if (*++yyp != '\\')
+	      goto do_not_strip_quotes;
+	    /* Fall through.  */
+	  default:
+	    if (yyres)
+	      yyres[yyn] = *yyp;
+	    yyn++;
+	    break;
+
+	  case '"':
+	    if (yyres)
+	      yyres[yyn] = '\0';
+	    return yyn;
+	  }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into YYRESULT an error message about the unexpected token
+   YYCHAR while in state YYSTATE.  Return the number of bytes copied,
+   including the terminating null byte.  If YYRESULT is null, do not
+   copy anything; just return the number of bytes that would be
+   copied.  As a special case, return 0 if an ordinary "syntax error"
+   message will do.  Return YYSIZE_MAXIMUM if overflow occurs during
+   size calculation.  */
+static YYSIZE_T
+yysyntax_error (char *yyresult, int yystate, int yychar)
+{
+  int yyn = yypact[yystate];
+
+  if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
+    return 0;
+  else
+    {
+      int yytype = YYTRANSLATE (yychar);
+      YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+      YYSIZE_T yysize = yysize0;
+      YYSIZE_T yysize1;
+      int yysize_overflow = 0;
+      enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+      char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+      int yyx;
+
+# if 0
+      /* This is so xgettext sees the translatable formats that are
+	 constructed on the fly.  */
+      YY_("syntax error, unexpected %s");
+      YY_("syntax error, unexpected %s, expecting %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+# endif
+      char *yyfmt;
+      char const *yyf;
+      static char const yyunexpected[] = "syntax error, unexpected %s";
+      static char const yyexpecting[] = ", expecting %s";
+      static char const yyor[] = " or %s";
+      char yyformat[sizeof yyunexpected
+		    + sizeof yyexpecting - 1
+		    + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+		       * (sizeof yyor - 1))];
+      char const *yyprefix = yyexpecting;
+
+      /* Start YYX at -YYN if negative to avoid negative indexes in
+	 YYCHECK.  */
+      int yyxbegin = yyn < 0 ? -yyn : 0;
+
+      /* Stay within bounds of both yycheck and yytname.  */
+      int yychecklim = YYLAST - yyn + 1;
+      int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+      int yycount = 1;
+
+      yyarg[0] = yytname[yytype];
+      yyfmt = yystpcpy (yyformat, yyunexpected);
+
+      for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+	if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+	  {
+	    if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+	      {
+		yycount = 1;
+		yysize = yysize0;
+		yyformat[sizeof yyunexpected - 1] = '\0';
+		break;
+	      }
+	    yyarg[yycount++] = yytname[yyx];
+	    yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+	    yysize_overflow |= (yysize1 < yysize);
+	    yysize = yysize1;
+	    yyfmt = yystpcpy (yyfmt, yyprefix);
+	    yyprefix = yyor;
+	  }
+
+      yyf = YY_(yyformat);
+      yysize1 = yysize + yystrlen (yyf);
+      yysize_overflow |= (yysize1 < yysize);
+      yysize = yysize1;
+
+      if (yysize_overflow)
+	return YYSIZE_MAXIMUM;
+
+      if (yyresult)
+	{
+	  /* Avoid sprintf, as that infringes on the user's name space.
+	     Don't have undefined behavior even if the translation
+	     produced a string with the wrong number of "%s"s.  */
+	  char *yyp = yyresult;
+	  int yyi = 0;
+	  while ((*yyp = *yyf) != '\0')
+	    {
+	      if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+		{
+		  yyp += yytnamerr (yyp, yyarg[yyi++]);
+		  yyf += 2;
+		}
+	      else
+		{
+		  yyp++;
+		  yyf++;
+		}
+	    }
+	}
+      return yysize;
+    }
+}
+#endif /* YYERROR_VERBOSE */
+
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+    const char *yymsg;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  YYUSE (yyvaluep);
+
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  switch (yytype)
+    {
+
+      default:
+	break;
+    }
+}
+
+
+/* Prevent warnings from -Wmissing-prototypes.  */
+
+#ifdef YYPARSE_PARAM
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void *YYPARSE_PARAM);
+#else
+int yyparse ();
+#endif
+#else /* ! YYPARSE_PARAM */
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void);
+#else
+int yyparse ();
+#endif
+#endif /* ! YYPARSE_PARAM */
+
+
+
+/* The look-ahead symbol.  */
+int yychar;
+
+/* The semantic value of the look-ahead symbol.  */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far.  */
+int yynerrs;
+
+
+
+/*----------.
+| yyparse.  |
+`----------*/
+
+#ifdef YYPARSE_PARAM
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void *YYPARSE_PARAM)
+#else
+int
+yyparse (YYPARSE_PARAM)
+    void *YYPARSE_PARAM;
+#endif
+#else /* ! YYPARSE_PARAM */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void)
+#else
+int
+yyparse ()
+
+#endif
+#endif
+{
+  
+  int yystate;
+  int yyn;
+  int yyresult;
+  /* Number of tokens to shift before error messages enabled.  */
+  int yyerrstatus;
+  /* Look-ahead token as an internal (translated) token number.  */
+  int yytoken = 0;
+#if YYERROR_VERBOSE
+  /* Buffer for error messages, and its allocated size.  */
+  char yymsgbuf[128];
+  char *yymsg = yymsgbuf;
+  YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+  /* Three stacks and their tools:
+     `yyss': related to states,
+     `yyvs': related to semantic values,
+     `yyls': related to locations.
+
+     Refer to the stacks thru separate pointers, to allow yyoverflow
+     to reallocate them elsewhere.  */
+
+  /* The state stack.  */
+  yytype_int16 yyssa[YYINITDEPTH];
+  yytype_int16 *yyss = yyssa;
+  yytype_int16 *yyssp;
+
+  /* The semantic value stack.  */
+  YYSTYPE yyvsa[YYINITDEPTH];
+  YYSTYPE *yyvs = yyvsa;
+  YYSTYPE *yyvsp;
+
+
+
+#define YYPOPSTACK(N)   (yyvsp -= (N), yyssp -= (N))
+
+  YYSIZE_T yystacksize = YYINITDEPTH;
+
+  /* The variables used to return semantic value and location from the
+     action routines.  */
+  YYSTYPE yyval;
+
+
+  /* The number of symbols on the RHS of the reduced rule.
+     Keep to zero when no symbol should be popped.  */
+  int yylen = 0;
+
+  YYDPRINTF ((stderr, "Starting parse\n"));
+
+  yystate = 0;
+  yyerrstatus = 0;
+  yynerrs = 0;
+  yychar = YYEMPTY;		/* Cause a token to be read.  */
+
+  /* Initialize stack pointers.
+     Waste one element of value and location stack
+     so that they stay on the same level as the state stack.
+     The wasted elements are never initialized.  */
+
+  yyssp = yyss;
+  yyvsp = yyvs;
+
+  goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate.  |
+`------------------------------------------------------------*/
+ yynewstate:
+  /* In all cases, when you get here, the value and location stacks
+     have just been pushed.  So pushing a state here evens the stacks.  */
+  yyssp++;
+
+ yysetstate:
+  *yyssp = yystate;
+
+  if (yyss + yystacksize - 1 <= yyssp)
+    {
+      /* Get the current used size of the three stacks, in elements.  */
+      YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+      {
+	/* Give user a chance to reallocate the stack.  Use copies of
+	   these so that the &'s don't force the real ones into
+	   memory.  */
+	YYSTYPE *yyvs1 = yyvs;
+	yytype_int16 *yyss1 = yyss;
+
+
+	/* Each stack pointer address is followed by the size of the
+	   data in use in that stack, in bytes.  This used to be a
+	   conditional around just the two extra args, but that might
+	   be undefined if yyoverflow is a macro.  */
+	yyoverflow (YY_("memory exhausted"),
+		    &yyss1, yysize * sizeof (*yyssp),
+		    &yyvs1, yysize * sizeof (*yyvsp),
+
+		    &yystacksize);
+
+	yyss = yyss1;
+	yyvs = yyvs1;
+      }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+      goto yyexhaustedlab;
+# else
+      /* Extend the stack our own way.  */
+      if (YYMAXDEPTH <= yystacksize)
+	goto yyexhaustedlab;
+      yystacksize *= 2;
+      if (YYMAXDEPTH < yystacksize)
+	yystacksize = YYMAXDEPTH;
+
+      {
+	yytype_int16 *yyss1 = yyss;
+	union yyalloc *yyptr =
+	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+	if (! yyptr)
+	  goto yyexhaustedlab;
+	YYSTACK_RELOCATE (yyss);
+	YYSTACK_RELOCATE (yyvs);
+
+#  undef YYSTACK_RELOCATE
+	if (yyss1 != yyssa)
+	  YYSTACK_FREE (yyss1);
+      }
+# endif
+#endif /* no yyoverflow */
+
+      yyssp = yyss + yysize - 1;
+      yyvsp = yyvs + yysize - 1;
+
+
+      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+		  (unsigned long int) yystacksize));
+
+      if (yyss + yystacksize - 1 <= yyssp)
+	YYABORT;
+    }
+
+  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+  goto yybackup;
+
+/*-----------.
+| yybackup.  |
+`-----------*/
+yybackup:
+
+  /* Do appropriate processing given the current state.  Read a
+     look-ahead token if we need one and don't already have one.  */
+
+  /* First try to decide what to do without reference to look-ahead token.  */
+  yyn = yypact[yystate];
+  if (yyn == YYPACT_NINF)
+    goto yydefault;
+
+  /* Not known => get a look-ahead token if don't already have one.  */
+
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
+  if (yychar == YYEMPTY)
+    {
+      YYDPRINTF ((stderr, "Reading a token: "));
+      yychar = YYLEX;
+    }
+
+  if (yychar <= YYEOF)
+    {
+      yychar = yytoken = YYEOF;
+      YYDPRINTF ((stderr, "Now at end of input.\n"));
+    }
+  else
+    {
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+    }
+
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+    goto yydefault;
+  yyn = yytable[yyn];
+  if (yyn <= 0)
+    {
+      if (yyn == 0 || yyn == YYTABLE_NINF)
+	goto yyerrlab;
+      yyn = -yyn;
+      goto yyreduce;
+    }
+
+  if (yyn == YYFINAL)
+    YYACCEPT;
+
+  /* Count tokens shifted since error; after three, turn off error
+     status.  */
+  if (yyerrstatus)
+    yyerrstatus--;
+
+  /* Shift the look-ahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+  /* Discard the shifted token unless it is eof.  */
+  if (yychar != YYEOF)
+    yychar = YYEMPTY;
+
+  yystate = yyn;
+  *++yyvsp = yylval;
+
+  goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state.  |
+`-----------------------------------------------------------*/
+yydefault:
+  yyn = yydefact[yystate];
+  if (yyn == 0)
+    goto yyerrlab;
+  goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction.  |
+`-----------------------------*/
+yyreduce:
+  /* yyn is the number of a rule to reduce with.  */
+  yylen = yyr2[yyn];
+
+  /* If YYLEN is nonzero, implement the default value of the action:
+     `$$ = $1'.
+
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
+     users should not rely upon it.  Assigning to YYVAL
+     unconditionally makes the parser a bit smaller, and it avoids a
+     GCC warning that YYVAL may be used uninitialized.  */
+  yyval = yyvsp[1-yylen];
+
+
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 4:
+#line 108 "scripts/genksyms/parse.y"
+    { is_typedef = 0; is_extern = 0; current_name = NULL; decl_spec = NULL; ;}
+    break;
+
+  case 5:
+#line 110 "scripts/genksyms/parse.y"
+    { free_list(*(yyvsp[(2) - (2)]), NULL); *(yyvsp[(2) - (2)]) = NULL; ;}
+    break;
+
+  case 6:
+#line 114 "scripts/genksyms/parse.y"
+    { is_typedef = 1; ;}
+    break;
+
+  case 7:
+#line 115 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 8:
+#line 116 "scripts/genksyms/parse.y"
+    { is_typedef = 1; ;}
+    break;
+
+  case 9:
+#line 117 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 14:
+#line 122 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 15:
+#line 123 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 16:
+#line 128 "scripts/genksyms/parse.y"
+    { if (current_name) {
+		    struct string_list *decl = (*(yyvsp[(3) - (3)]))->next;
+		    (*(yyvsp[(3) - (3)]))->next = NULL;
+		    add_symbol(current_name,
+			       is_typedef ? SYM_TYPEDEF : SYM_NORMAL,
+			       decl, is_extern);
+		    current_name = NULL;
+		  }
+		  (yyval) = (yyvsp[(3) - (3)]);
+		;}
+    break;
+
+  case 17:
+#line 141 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 19:
+#line 147 "scripts/genksyms/parse.y"
+    { struct string_list *decl = *(yyvsp[(1) - (1)]);
+		  *(yyvsp[(1) - (1)]) = NULL;
+		  add_symbol(current_name,
+			     is_typedef ? SYM_TYPEDEF : SYM_NORMAL, decl, is_extern);
+		  current_name = NULL;
+		  (yyval) = (yyvsp[(1) - (1)]);
+		;}
+    break;
+
+  case 20:
+#line 155 "scripts/genksyms/parse.y"
+    { struct string_list *decl = *(yyvsp[(3) - (3)]);
+		  *(yyvsp[(3) - (3)]) = NULL;
+		  free_list(*(yyvsp[(2) - (3)]), NULL);
+		  *(yyvsp[(2) - (3)]) = decl_spec;
+		  add_symbol(current_name,
+			     is_typedef ? SYM_TYPEDEF : SYM_NORMAL, decl, is_extern);
+		  current_name = NULL;
+		  (yyval) = (yyvsp[(3) - (3)]);
+		;}
+    break;
+
+  case 21:
+#line 168 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]) ? (yyvsp[(4) - (4)]) : (yyvsp[(3) - (4)]) ? (yyvsp[(3) - (4)]) : (yyvsp[(2) - (4)]) ? (yyvsp[(2) - (4)]) : (yyvsp[(1) - (4)]); ;}
+    break;
+
+  case 22:
+#line 173 "scripts/genksyms/parse.y"
+    { decl_spec = NULL; ;}
+    break;
+
+  case 24:
+#line 178 "scripts/genksyms/parse.y"
+    { decl_spec = *(yyvsp[(1) - (1)]); ;}
+    break;
+
+  case 25:
+#line 179 "scripts/genksyms/parse.y"
+    { decl_spec = *(yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 26:
+#line 184 "scripts/genksyms/parse.y"
+    { /* Version 2 checksumming ignores storage class, as that
+		     is really irrelevant to the linkage.  */
+		  remove_node((yyvsp[(1) - (1)]));
+		  (yyval) = (yyvsp[(1) - (1)]);
+		;}
+    break;
+
+  case 31:
+#line 196 "scripts/genksyms/parse.y"
+    { is_extern = 1; (yyval) = (yyvsp[(1) - (1)]); ;}
+    break;
+
+  case 32:
+#line 197 "scripts/genksyms/parse.y"
+    { is_extern = 0; (yyval) = (yyvsp[(1) - (1)]); ;}
+    break;
+
+  case 37:
+#line 209 "scripts/genksyms/parse.y"
+    { remove_node((yyvsp[(1) - (2)])); (*(yyvsp[(2) - (2)]))->tag = SYM_STRUCT; (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 38:
+#line 211 "scripts/genksyms/parse.y"
+    { remove_node((yyvsp[(1) - (2)])); (*(yyvsp[(2) - (2)]))->tag = SYM_UNION; (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 39:
+#line 213 "scripts/genksyms/parse.y"
+    { remove_node((yyvsp[(1) - (2)])); (*(yyvsp[(2) - (2)]))->tag = SYM_ENUM; (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 40:
+#line 217 "scripts/genksyms/parse.y"
+    { struct string_list *s = *(yyvsp[(3) - (3)]), *i = *(yyvsp[(2) - (3)]), *r;
+		  r = copy_node(i); r->tag = SYM_STRUCT;
+		  r->next = (*(yyvsp[(1) - (3)]))->next; *(yyvsp[(3) - (3)]) = r; (*(yyvsp[(1) - (3)]))->next = NULL;
+		  add_symbol(i->string, SYM_STRUCT, s, is_extern);
+		  (yyval) = (yyvsp[(3) - (3)]);
+		;}
+    break;
+
+  case 41:
+#line 224 "scripts/genksyms/parse.y"
+    { struct string_list *s = *(yyvsp[(3) - (3)]), *i = *(yyvsp[(2) - (3)]), *r;
+		  r = copy_node(i); r->tag = SYM_UNION;
+		  r->next = (*(yyvsp[(1) - (3)]))->next; *(yyvsp[(3) - (3)]) = r; (*(yyvsp[(1) - (3)]))->next = NULL;
+		  add_symbol(i->string, SYM_UNION, s, is_extern);
+		  (yyval) = (yyvsp[(3) - (3)]);
+		;}
+    break;
+
+  case 42:
+#line 231 "scripts/genksyms/parse.y"
+    { struct string_list *s = *(yyvsp[(3) - (3)]), *i = *(yyvsp[(2) - (3)]), *r;
+		  r = copy_node(i); r->tag = SYM_ENUM;
+		  r->next = (*(yyvsp[(1) - (3)]))->next; *(yyvsp[(3) - (3)]) = r; (*(yyvsp[(1) - (3)]))->next = NULL;
+		  add_symbol(i->string, SYM_ENUM, s, is_extern);
+		  (yyval) = (yyvsp[(3) - (3)]);
+		;}
+    break;
+
+  case 43:
+#line 239 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 44:
+#line 240 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 45:
+#line 241 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 56:
+#line 255 "scripts/genksyms/parse.y"
+    { (*(yyvsp[(1) - (1)]))->tag = SYM_TYPEDEF; (yyval) = (yyvsp[(1) - (1)]); ;}
+    break;
+
+  case 57:
+#line 260 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]) ? (yyvsp[(2) - (2)]) : (yyvsp[(1) - (2)]); ;}
+    break;
+
+  case 58:
+#line 264 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 61:
+#line 270 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 65:
+#line 276 "scripts/genksyms/parse.y"
+    { /* restrict has no effect in prototypes so ignore it */
+		  remove_node((yyvsp[(1) - (1)]));
+		  (yyval) = (yyvsp[(1) - (1)]);
+		;}
+    break;
+
+  case 66:
+#line 283 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 68:
+#line 289 "scripts/genksyms/parse.y"
+    { if (current_name != NULL) {
+		    error_with_pos("unexpected second declaration name");
+		    YYERROR;
+		  } else {
+		    current_name = (*(yyvsp[(1) - (1)]))->string;
+		    (yyval) = (yyvsp[(1) - (1)]);
+		  }
+		;}
+    break;
+
+  case 69:
+#line 298 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 70:
+#line 300 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 71:
+#line 302 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 72:
+#line 304 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 73:
+#line 306 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 74:
+#line 312 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 78:
+#line 320 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 79:
+#line 322 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 80:
+#line 324 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 81:
+#line 326 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 82:
+#line 328 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 83:
+#line 332 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 85:
+#line 334 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 86:
+#line 338 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 89:
+#line 345 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 90:
+#line 350 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]) ? (yyvsp[(2) - (2)]) : (yyvsp[(1) - (2)]); ;}
+    break;
+
+  case 91:
+#line 355 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]) ? (yyvsp[(2) - (2)]) : (yyvsp[(1) - (2)]); ;}
+    break;
+
+  case 93:
+#line 360 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 94:
+#line 362 "scripts/genksyms/parse.y"
+    { /* For version 2 checksums, we don't want to remember
+		     private parameter names.  */
+		  remove_node((yyvsp[(1) - (1)]));
+		  (yyval) = (yyvsp[(1) - (1)]);
+		;}
+    break;
+
+  case 95:
+#line 370 "scripts/genksyms/parse.y"
+    { remove_node((yyvsp[(1) - (1)]));
+		  (yyval) = (yyvsp[(1) - (1)]);
+		;}
+    break;
+
+  case 96:
+#line 374 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 97:
+#line 376 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(4) - (4)]); ;}
+    break;
+
+  case 98:
+#line 378 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 99:
+#line 380 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 100:
+#line 382 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 101:
+#line 387 "scripts/genksyms/parse.y"
+    { struct string_list *decl = *(yyvsp[(2) - (3)]);
+		  *(yyvsp[(2) - (3)]) = NULL;
+		  add_symbol(current_name, SYM_NORMAL, decl, is_extern);
+		  (yyval) = (yyvsp[(3) - (3)]);
+		;}
+    break;
+
+  case 102:
+#line 395 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 104:
+#line 402 "scripts/genksyms/parse.y"
+    { remove_list((yyvsp[(2) - (2)]), &(*(yyvsp[(1) - (2)]))->next); (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 105:
+#line 406 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 106:
+#line 407 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 107:
+#line 411 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 110:
+#line 417 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 111:
+#line 422 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 112:
+#line 424 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 113:
+#line 428 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 116:
+#line 434 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(3) - (3)]); ;}
+    break;
+
+  case 117:
+#line 438 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]) ? (yyvsp[(2) - (2)]) : (yyvsp[(1) - (2)]); ;}
+    break;
+
+  case 118:
+#line 439 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 120:
+#line 444 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 121:
+#line 448 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 123:
+#line 453 "scripts/genksyms/parse.y"
+    { (yyval) = (yyvsp[(2) - (2)]); ;}
+    break;
+
+  case 124:
+#line 457 "scripts/genksyms/parse.y"
+    { (yyval) = NULL; ;}
+    break;
+
+  case 126:
+#line 463 "scripts/genksyms/parse.y"
+    { export_symbol((*(yyvsp[(3) - (5)]))->string); (yyval) = (yyvsp[(5) - (5)]); ;}
+    break;
+
+
+/* Line 1267 of yacc.c.  */
+#line 2132 "scripts/genksyms/parse.c"
+      default: break;
+    }
+  YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+
+  *++yyvsp = yyval;
+
+
+  /* Now `shift' the result of the reduction.  Determine what state
+     that goes to, based on the state we popped back to and the rule
+     number reduced by.  */
+
+  yyn = yyr1[yyn];
+
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+    yystate = yytable[yystate];
+  else
+    yystate = yydefgoto[yyn - YYNTOKENS];
+
+  goto yynewstate;
+
+
+/*------------------------------------.
+| yyerrlab -- here on detecting error |
+`------------------------------------*/
+yyerrlab:
+  /* If not already recovering from an error, report this error.  */
+  if (!yyerrstatus)
+    {
+      ++yynerrs;
+#if ! YYERROR_VERBOSE
+      yyerror (YY_("syntax error"));
+#else
+      {
+	YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
+	if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
+	  {
+	    YYSIZE_T yyalloc = 2 * yysize;
+	    if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
+	      yyalloc = YYSTACK_ALLOC_MAXIMUM;
+	    if (yymsg != yymsgbuf)
+	      YYSTACK_FREE (yymsg);
+	    yymsg = (char *) YYSTACK_ALLOC (yyalloc);
+	    if (yymsg)
+	      yymsg_alloc = yyalloc;
+	    else
+	      {
+		yymsg = yymsgbuf;
+		yymsg_alloc = sizeof yymsgbuf;
+	      }
+	  }
+
+	if (0 < yysize && yysize <= yymsg_alloc)
+	  {
+	    (void) yysyntax_error (yymsg, yystate, yychar);
+	    yyerror (yymsg);
+	  }
+	else
+	  {
+	    yyerror (YY_("syntax error"));
+	    if (yysize != 0)
+	      goto yyexhaustedlab;
+	  }
+      }
+#endif
+    }
+
+
+
+  if (yyerrstatus == 3)
+    {
+      /* If just tried and failed to reuse look-ahead token after an
+	 error, discard it.  */
+
+      if (yychar <= YYEOF)
+	{
+	  /* Return failure if at end of input.  */
+	  if (yychar == YYEOF)
+	    YYABORT;
+	}
+      else
+	{
+	  yydestruct ("Error: discarding",
+		      yytoken, &yylval);
+	  yychar = YYEMPTY;
+	}
+    }
+
+  /* Else will try to reuse look-ahead token after shifting the error
+     token.  */
+  goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
+
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (/*CONSTCOND*/ 0)
+     goto yyerrorlab;
+
+  /* Do not reclaim the symbols of the rule which action triggered
+     this YYERROR.  */
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+  yystate = *yyssp;
+  goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
+
+  for (;;)
+    {
+      yyn = yypact[yystate];
+      if (yyn != YYPACT_NINF)
+	{
+	  yyn += YYTERROR;
+	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+	    {
+	      yyn = yytable[yyn];
+	      if (0 < yyn)
+		break;
+	    }
+	}
+
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+	YYABORT;
+
+
+      yydestruct ("Error: popping",
+		  yystos[yystate], yyvsp);
+      YYPOPSTACK (1);
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
+    }
+
+  if (yyn == YYFINAL)
+    YYACCEPT;
+
+  *++yyvsp = yylval;
+
+
+  /* Shift the error token.  */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+  yystate = yyn;
+  goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here.  |
+`-------------------------------------*/
+yyacceptlab:
+  yyresult = 0;
+  goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here.  |
+`-----------------------------------*/
+yyabortlab:
+  yyresult = 1;
+  goto yyreturn;
+
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
+  yyresult = 2;
+  /* Fall through.  */
+#endif
+
+yyreturn:
+  if (yychar != YYEOF && yychar != YYEMPTY)
+     yydestruct ("Cleanup: discarding lookahead",
+		 yytoken, &yylval);
+  /* Do not reclaim the symbols of the rule which action triggered
+     this YYABORT or YYACCEPT.  */
+  YYPOPSTACK (yylen);
+  YY_STACK_PRINT (yyss, yyssp);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+		  yystos[*yyssp], yyvsp);
+      YYPOPSTACK (1);
+    }
+#ifndef yyoverflow
+  if (yyss != yyssa)
+    YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+  if (yymsg != yymsgbuf)
+    YYSTACK_FREE (yymsg);
+#endif
+  /* Make sure YYID is used.  */
+  return YYID (yyresult);
+}
+
+
+#line 467 "scripts/genksyms/parse.y"
+
+
+static void
+yyerror(const char *e)
+{
+  error_with_pos("%s", e);
+}
+
diff -uNra linux-2.6.27.6/scripts/genksyms/parse.h linux-2.6.27.6.yaffs/scripts/genksyms/parse.h
--- linux-2.6.27.6/scripts/genksyms/parse.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/genksyms/parse.h	2011-05-08 18:02:54.000000000 +0800
@@ -0,0 +1,139 @@
+/* A Bison parser, made by GNU Bison 2.3.  */
+
+/* Skeleton interface for Bison's Yacc-like parsers in C
+
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     ASM_KEYW = 258,
+     ATTRIBUTE_KEYW = 259,
+     AUTO_KEYW = 260,
+     BOOL_KEYW = 261,
+     CHAR_KEYW = 262,
+     CONST_KEYW = 263,
+     DOUBLE_KEYW = 264,
+     ENUM_KEYW = 265,
+     EXTERN_KEYW = 266,
+     EXTENSION_KEYW = 267,
+     FLOAT_KEYW = 268,
+     INLINE_KEYW = 269,
+     INT_KEYW = 270,
+     LONG_KEYW = 271,
+     REGISTER_KEYW = 272,
+     RESTRICT_KEYW = 273,
+     SHORT_KEYW = 274,
+     SIGNED_KEYW = 275,
+     STATIC_KEYW = 276,
+     STRUCT_KEYW = 277,
+     TYPEDEF_KEYW = 278,
+     UNION_KEYW = 279,
+     UNSIGNED_KEYW = 280,
+     VOID_KEYW = 281,
+     VOLATILE_KEYW = 282,
+     TYPEOF_KEYW = 283,
+     EXPORT_SYMBOL_KEYW = 284,
+     ASM_PHRASE = 285,
+     ATTRIBUTE_PHRASE = 286,
+     BRACE_PHRASE = 287,
+     BRACKET_PHRASE = 288,
+     EXPRESSION_PHRASE = 289,
+     CHAR = 290,
+     DOTS = 291,
+     IDENT = 292,
+     INT = 293,
+     REAL = 294,
+     STRING = 295,
+     TYPE = 296,
+     OTHER = 297,
+     FILENAME = 298
+   };
+#endif
+/* Tokens.  */
+#define ASM_KEYW 258
+#define ATTRIBUTE_KEYW 259
+#define AUTO_KEYW 260
+#define BOOL_KEYW 261
+#define CHAR_KEYW 262
+#define CONST_KEYW 263
+#define DOUBLE_KEYW 264
+#define ENUM_KEYW 265
+#define EXTERN_KEYW 266
+#define EXTENSION_KEYW 267
+#define FLOAT_KEYW 268
+#define INLINE_KEYW 269
+#define INT_KEYW 270
+#define LONG_KEYW 271
+#define REGISTER_KEYW 272
+#define RESTRICT_KEYW 273
+#define SHORT_KEYW 274
+#define SIGNED_KEYW 275
+#define STATIC_KEYW 276
+#define STRUCT_KEYW 277
+#define TYPEDEF_KEYW 278
+#define UNION_KEYW 279
+#define UNSIGNED_KEYW 280
+#define VOID_KEYW 281
+#define VOLATILE_KEYW 282
+#define TYPEOF_KEYW 283
+#define EXPORT_SYMBOL_KEYW 284
+#define ASM_PHRASE 285
+#define ATTRIBUTE_PHRASE 286
+#define BRACE_PHRASE 287
+#define BRACKET_PHRASE 288
+#define EXPRESSION_PHRASE 289
+#define CHAR 290
+#define DOTS 291
+#define IDENT 292
+#define INT 293
+#define REAL 294
+#define STRING 295
+#define TYPE 296
+#define OTHER 297
+#define FILENAME 298
+
+
+
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef int YYSTYPE;
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+extern YYSTYPE yylval;
+
diff -uNra linux-2.6.27.6/scripts/kallsyms linux-2.6.27.6.yaffs/scripts/kallsyms
\ 文件尾没有 newline 字符
diff -uNra linux-2.6.27.6/scripts/kconfig/conf linux-2.6.27.6.yaffs/scripts/kconfig/conf
\ 文件尾没有 newline 字符
diff -uNra linux-2.6.27.6/scripts/kconfig/lex.zconf.c linux-2.6.27.6.yaffs/scripts/kconfig/lex.zconf.c
--- linux-2.6.27.6/scripts/kconfig/lex.zconf.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/kconfig/lex.zconf.c	2011-05-08 18:02:54.000000000 +0800
@@ -0,0 +1,2413 @@
+
+#line 3 "scripts/kconfig/lex.zconf.c"
+
+#define  YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define yy_create_buffer zconf_create_buffer
+#define yy_delete_buffer zconf_delete_buffer
+#define yy_flex_debug zconf_flex_debug
+#define yy_init_buffer zconf_init_buffer
+#define yy_flush_buffer zconf_flush_buffer
+#define yy_load_buffer_state zconf_load_buffer_state
+#define yy_switch_to_buffer zconf_switch_to_buffer
+#define yyin zconfin
+#define yyleng zconfleng
+#define yylex zconflex
+#define yylineno zconflineno
+#define yyout zconfout
+#define yyrestart zconfrestart
+#define yytext zconftext
+#define yywrap zconfwrap
+#define yyalloc zconfalloc
+#define yyrealloc zconfrealloc
+#define yyfree zconffree
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with  platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types. 
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t; 
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN               (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN              (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN              (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX               (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX              (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX              (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX              (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX             (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX             (4294967295U)
+#endif
+
+#endif /* ! C99 */
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif	/* defined (__STDC__) */
+#endif	/* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index.  If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition.  This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state.  The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE zconfrestart(zconfin  )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+extern int zconfleng;
+
+extern FILE *zconfin, *zconfout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+    #define YY_LESS_LINENO(n)
+    
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up zconftext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		*yy_cp = (yy_hold_char); \
+		YY_RESTORE_YY_MORE_OFFSET \
+		(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+		YY_DO_BEFORE_ACTION; /* set up zconftext again */ \
+		} \
+	while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr)  )
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+	{
+	FILE *yy_input_file;
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+    int yy_bs_lineno; /**< The line count. */
+    int yy_bs_column; /**< The column count. */
+    
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+	/* When an EOF's been seen but there's still some text to process
+	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+	 * shouldn't try reading from the input source any more.  We might
+	 * still have a bunch of tokens to match, though, because of
+	 * possible backing-up.
+	 *
+	 * When we actually see the EOF, we change the status to "new"
+	 * (via zconfrestart()), so that the user can continue scanning by
+	 * just pointing zconfin at a new input file.
+	 */
+#define YY_BUFFER_EOF_PENDING 2
+
+	};
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+                          : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when zconftext is formed. */
+static char yy_hold_char;
+static int yy_n_chars;		/* number of characters read into yy_ch_buf */
+int zconfleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0;		/* whether we need to initialize */
+static int yy_start = 0;	/* start state number */
+
+/* Flag which is used to allow zconfwrap()'s to do buffer switches
+ * instead of setting up a fresh zconfin.  A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void zconfrestart (FILE *input_file  );
+void zconf_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
+YY_BUFFER_STATE zconf_create_buffer (FILE *file,int size  );
+void zconf_delete_buffer (YY_BUFFER_STATE b  );
+void zconf_flush_buffer (YY_BUFFER_STATE b  );
+void zconfpush_buffer_state (YY_BUFFER_STATE new_buffer  );
+void zconfpop_buffer_state (void );
+
+static void zconfensure_buffer_stack (void );
+static void zconf_load_buffer_state (void );
+static void zconf_init_buffer (YY_BUFFER_STATE b,FILE *file  );
+
+#define YY_FLUSH_BUFFER zconf_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE zconf_scan_buffer (char *base,yy_size_t size  );
+YY_BUFFER_STATE zconf_scan_string (yyconst char *yy_str  );
+YY_BUFFER_STATE zconf_scan_bytes (yyconst char *bytes,int len  );
+
+void *zconfalloc (yy_size_t  );
+void *zconfrealloc (void *,yy_size_t  );
+void zconffree (void *  );
+
+#define yy_new_buffer zconf_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){ \
+        zconfensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            zconf_create_buffer(zconfin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+	}
+
+#define yy_set_bol(at_bol) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){\
+        zconfensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            zconf_create_buffer(zconfin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+	}
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+#define zconfwrap(n) 1
+#define YY_SKIP_YYWRAP
+
+typedef unsigned char YY_CHAR;
+
+FILE *zconfin = (FILE *) 0, *zconfout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int zconflineno;
+
+int zconflineno = 1;
+
+extern char *zconftext;
+#define yytext_ptr zconftext
+static yyconst flex_int16_t yy_nxt[][17] =
+    {
+    {
+        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,
+        0,    0,    0,    0,    0,    0,    0
+    },
+
+    {
+       11,   12,   13,   14,   12,   12,   15,   12,   12,   12,
+       12,   12,   12,   12,   12,   12,   12
+    },
+
+    {
+       11,   12,   13,   14,   12,   12,   15,   12,   12,   12,
+       12,   12,   12,   12,   12,   12,   12
+    },
+
+    {
+       11,   16,   16,   17,   16,   16,   16,   16,   16,   16,
+       16,   16,   16,   18,   16,   16,   16
+    },
+
+    {
+       11,   16,   16,   17,   16,   16,   16,   16,   16,   16,
+       16,   16,   16,   18,   16,   16,   16
+
+    },
+
+    {
+       11,   19,   20,   21,   19,   19,   19,   19,   19,   19,
+       19,   19,   19,   19,   19,   19,   19
+    },
+
+    {
+       11,   19,   20,   21,   19,   19,   19,   19,   19,   19,
+       19,   19,   19,   19,   19,   19,   19
+    },
+
+    {
+       11,   22,   22,   23,   22,   24,   22,   22,   24,   22,
+       22,   22,   22,   22,   22,   25,   22
+    },
+
+    {
+       11,   22,   22,   23,   22,   24,   22,   22,   24,   22,
+       22,   22,   22,   22,   22,   25,   22
+    },
+
+    {
+       11,   26,   26,   27,   28,   29,   30,   31,   29,   32,
+       33,   34,   35,   35,   36,   37,   38
+
+    },
+
+    {
+       11,   26,   26,   27,   28,   29,   30,   31,   29,   32,
+       33,   34,   35,   35,   36,   37,   38
+    },
+
+    {
+      -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,
+      -11,  -11,  -11,  -11,  -11,  -11,  -11
+    },
+
+    {
+       11,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,
+      -12,  -12,  -12,  -12,  -12,  -12,  -12
+    },
+
+    {
+       11,  -13,   39,   40,  -13,  -13,   41,  -13,  -13,  -13,
+      -13,  -13,  -13,  -13,  -13,  -13,  -13
+    },
+
+    {
+       11,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,
+      -14,  -14,  -14,  -14,  -14,  -14,  -14
+
+    },
+
+    {
+       11,   42,   42,   43,   42,   42,   42,   42,   42,   42,
+       42,   42,   42,   42,   42,   42,   42
+    },
+
+    {
+       11,  -16,  -16,  -16,  -16,  -16,  -16,  -16,  -16,  -16,
+      -16,  -16,  -16,  -16,  -16,  -16,  -16
+    },
+
+    {
+       11,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,
+      -17,  -17,  -17,  -17,  -17,  -17,  -17
+    },
+
+    {
+       11,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,
+      -18,  -18,  -18,   44,  -18,  -18,  -18
+    },
+
+    {
+       11,   45,   45,  -19,   45,   45,   45,   45,   45,   45,
+       45,   45,   45,   45,   45,   45,   45
+
+    },
+
+    {
+       11,  -20,   46,   47,  -20,  -20,  -20,  -20,  -20,  -20,
+      -20,  -20,  -20,  -20,  -20,  -20,  -20
+    },
+
+    {
+       11,   48,  -21,  -21,   48,   48,   48,   48,   48,   48,
+       48,   48,   48,   48,   48,   48,   48
+    },
+
+    {
+       11,   49,   49,   50,   49,  -22,   49,   49,  -22,   49,
+       49,   49,   49,   49,   49,  -22,   49
+    },
+
+    {
+       11,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,
+      -23,  -23,  -23,  -23,  -23,  -23,  -23
+    },
+
+    {
+       11,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,
+      -24,  -24,  -24,  -24,  -24,  -24,  -24
+
+    },
+
+    {
+       11,   51,   51,   52,   51,   51,   51,   51,   51,   51,
+       51,   51,   51,   51,   51,   51,   51
+    },
+
+    {
+       11,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,
+      -26,  -26,  -26,  -26,  -26,  -26,  -26
+    },
+
+    {
+       11,  -27,  -27,  -27,  -27,  -27,  -27,  -27,  -27,  -27,
+      -27,  -27,  -27,  -27,  -27,  -27,  -27
+    },
+
+    {
+       11,  -28,  -28,  -28,  -28,  -28,  -28,  -28,  -28,  -28,
+      -28,  -28,  -28,  -28,   53,  -28,  -28
+    },
+
+    {
+       11,  -29,  -29,  -29,  -29,  -29,  -29,  -29,  -29,  -29,
+      -29,  -29,  -29,  -29,  -29,  -29,  -29
+
+    },
+
+    {
+       11,   54,   54,  -30,   54,   54,   54,   54,   54,   54,
+       54,   54,   54,   54,   54,   54,   54
+    },
+
+    {
+       11,  -31,  -31,  -31,  -31,  -31,  -31,   55,  -31,  -31,
+      -31,  -31,  -31,  -31,  -31,  -31,  -31
+    },
+
+    {
+       11,  -32,  -32,  -32,  -32,  -32,  -32,  -32,  -32,  -32,
+      -32,  -32,  -32,  -32,  -32,  -32,  -32
+    },
+
+    {
+       11,  -33,  -33,  -33,  -33,  -33,  -33,  -33,  -33,  -33,
+      -33,  -33,  -33,  -33,  -33,  -33,  -33
+    },
+
+    {
+       11,  -34,  -34,  -34,  -34,  -34,  -34,  -34,  -34,  -34,
+      -34,   56,   57,   57,  -34,  -34,  -34
+
+    },
+
+    {
+       11,  -35,  -35,  -35,  -35,  -35,  -35,  -35,  -35,  -35,
+      -35,   57,   57,   57,  -35,  -35,  -35
+    },
+
+    {
+       11,  -36,  -36,  -36,  -36,  -36,  -36,  -36,  -36,  -36,
+      -36,  -36,  -36,  -36,  -36,  -36,  -36
+    },
+
+    {
+       11,  -37,  -37,   58,  -37,  -37,  -37,  -37,  -37,  -37,
+      -37,  -37,  -37,  -37,  -37,  -37,  -37
+    },
+
+    {
+       11,  -38,  -38,  -38,  -38,  -38,  -38,  -38,  -38,  -38,
+      -38,  -38,  -38,  -38,  -38,  -38,   59
+    },
+
+    {
+       11,  -39,   39,   40,  -39,  -39,   41,  -39,  -39,  -39,
+      -39,  -39,  -39,  -39,  -39,  -39,  -39
+
+    },
+
+    {
+       11,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,
+      -40,  -40,  -40,  -40,  -40,  -40,  -40
+    },
+
+    {
+       11,   42,   42,   43,   42,   42,   42,   42,   42,   42,
+       42,   42,   42,   42,   42,   42,   42
+    },
+
+    {
+       11,   42,   42,   43,   42,   42,   42,   42,   42,   42,
+       42,   42,   42,   42,   42,   42,   42
+    },
+
+    {
+       11,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,
+      -43,  -43,  -43,  -43,  -43,  -43,  -43
+    },
+
+    {
+       11,  -44,  -44,  -44,  -44,  -44,  -44,  -44,  -44,  -44,
+      -44,  -44,  -44,   44,  -44,  -44,  -44
+
+    },
+
+    {
+       11,   45,   45,  -45,   45,   45,   45,   45,   45,   45,
+       45,   45,   45,   45,   45,   45,   45
+    },
+
+    {
+       11,  -46,   46,   47,  -46,  -46,  -46,  -46,  -46,  -46,
+      -46,  -46,  -46,  -46,  -46,  -46,  -46
+    },
+
+    {
+       11,   48,  -47,  -47,   48,   48,   48,   48,   48,   48,
+       48,   48,   48,   48,   48,   48,   48
+    },
+
+    {
+       11,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,
+      -48,  -48,  -48,  -48,  -48,  -48,  -48
+    },
+
+    {
+       11,   49,   49,   50,   49,  -49,   49,   49,  -49,   49,
+       49,   49,   49,   49,   49,  -49,   49
+
+    },
+
+    {
+       11,  -50,  -50,  -50,  -50,  -50,  -50,  -50,  -50,  -50,
+      -50,  -50,  -50,  -50,  -50,  -50,  -50
+    },
+
+    {
+       11,  -51,  -51,   52,  -51,  -51,  -51,  -51,  -51,  -51,
+      -51,  -51,  -51,  -51,  -51,  -51,  -51
+    },
+
+    {
+       11,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,
+      -52,  -52,  -52,  -52,  -52,  -52,  -52
+    },
+
+    {
+       11,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,
+      -53,  -53,  -53,  -53,  -53,  -53,  -53
+    },
+
+    {
+       11,   54,   54,  -54,   54,   54,   54,   54,   54,   54,
+       54,   54,   54,   54,   54,   54,   54
+
+    },
+
+    {
+       11,  -55,  -55,  -55,  -55,  -55,  -55,  -55,  -55,  -55,
+      -55,  -55,  -55,  -55,  -55,  -55,  -55
+    },
+
+    {
+       11,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,
+      -56,   60,   57,   57,  -56,  -56,  -56
+    },
+
+    {
+       11,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,
+      -57,   57,   57,   57,  -57,  -57,  -57
+    },
+
+    {
+       11,  -58,  -58,  -58,  -58,  -58,  -58,  -58,  -58,  -58,
+      -58,  -58,  -58,  -58,  -58,  -58,  -58
+    },
+
+    {
+       11,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,
+      -59,  -59,  -59,  -59,  -59,  -59,  -59
+
+    },
+
+    {
+       11,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,
+      -60,   57,   57,   57,  -60,  -60,  -60
+    },
+
+    } ;
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state  );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[]  );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up zconftext.
+ */
+#define YY_DO_BEFORE_ACTION \
+	(yytext_ptr) = yy_bp; \
+	zconfleng = (size_t) (yy_cp - yy_bp); \
+	(yy_hold_char) = *yy_cp; \
+	*yy_cp = '\0'; \
+	(yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 33
+#define YY_END_OF_BUFFER 34
+/* This struct is not used in this scanner,
+   but its presence is necessary. */
+struct yy_trans_info
+	{
+	flex_int32_t yy_verify;
+	flex_int32_t yy_nxt;
+	};
+static yyconst flex_int16_t yy_accept[61] =
+    {   0,
+        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,
+       34,    5,    4,    2,    3,    7,    8,    6,   32,   29,
+       31,   24,   28,   27,   26,   22,   17,   13,   16,   20,
+       22,   11,   12,   19,   19,   14,   22,   22,    4,    2,
+        3,    3,    1,    6,   32,   29,   31,   30,   24,   23,
+       26,   25,   15,   20,    9,   19,   19,   21,   10,   18
+    } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    2,    4,    5,    6,    1,    1,    7,    8,    9,
+       10,    1,    1,    1,   11,   12,   12,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,    1,    1,    1,
+       14,    1,    1,    1,   13,   13,   13,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+        1,   15,    1,    1,   13,    1,   13,   13,   13,   13,
+
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+       13,   13,    1,   16,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1
+    } ;
+
+extern int zconf_flex_debug;
+int zconf_flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *zconftext;
+#define YY_NO_INPUT 1
+
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+#define START_STRSIZE	16
+
+static struct {
+	struct file *file;
+	int lineno;
+} current_pos;
+
+static char *text;
+static int text_size, text_asize;
+
+struct buffer {
+        struct buffer *parent;
+        YY_BUFFER_STATE state;
+};
+
+struct buffer *current_buf;
+
+static int last_ts, first_ts;
+
+static void zconf_endhelp(void);
+static void zconf_endfile(void);
+
+void new_string(void)
+{
+	text = malloc(START_STRSIZE);
+	text_asize = START_STRSIZE;
+	text_size = 0;
+	*text = 0;
+}
+
+void append_string(const char *str, int size)
+{
+	int new_size = text_size + size + 1;
+	if (new_size > text_asize) {
+		new_size += START_STRSIZE - 1;
+		new_size &= -START_STRSIZE;
+		text = realloc(text, new_size);
+		text_asize = new_size;
+	}
+	memcpy(text + text_size, str, size);
+	text_size += size;
+	text[text_size] = 0;
+}
+
+void alloc_string(const char *str, int size)
+{
+	text = malloc(size + 1);
+	memcpy(text, str, size);
+	text[size] = 0;
+}
+
+#define INITIAL 0
+#define COMMAND 1
+#define HELP 2
+#define STRING 3
+#define PARAM 4
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Accessor methods to globals.
+   These are made visible to non-reentrant scanners for convenience. */
+
+int zconflex_destroy (void );
+
+int zconfget_debug (void );
+
+void zconfset_debug (int debug_flag  );
+
+YY_EXTRA_TYPE zconfget_extra (void );
+
+void zconfset_extra (YY_EXTRA_TYPE user_defined  );
+
+FILE *zconfget_in (void );
+
+void zconfset_in  (FILE * in_str  );
+
+FILE *zconfget_out (void );
+
+void zconfset_out  (FILE * out_str  );
+
+int zconfget_leng (void );
+
+char *zconfget_text (void );
+
+int zconfget_lineno (void );
+
+void zconfset_lineno (int line_number  );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int zconfwrap (void );
+#else
+extern int zconfwrap (void );
+#endif
+#endif
+
+    static void yyunput (int c,char *buf_ptr  );
+    
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO fwrite( zconftext, zconfleng, 1, zconfout )
+#endif
+
+/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+	errno=0; \
+	while ( (result = read( fileno(zconfin), (char *) buf, max_size )) < 0 ) \
+	{ \
+		if( errno != EINTR) \
+		{ \
+			YY_FATAL_ERROR( "input in flex scanner failed" ); \
+			break; \
+		} \
+		errno=0; \
+		clearerr(zconfin); \
+	}\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int zconflex (void);
+
+#define YY_DECL int zconflex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after zconftext and zconfleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+	YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp, *yy_bp;
+	register int yy_act;
+    
+	int str = 0;
+	int ts, i;
+
+	if ( !(yy_init) )
+		{
+		(yy_init) = 1;
+
+#ifdef YY_USER_INIT
+		YY_USER_INIT;
+#endif
+
+		if ( ! (yy_start) )
+			(yy_start) = 1;	/* first start state */
+
+		if ( ! zconfin )
+			zconfin = stdin;
+
+		if ( ! zconfout )
+			zconfout = stdout;
+
+		if ( ! YY_CURRENT_BUFFER ) {
+			zconfensure_buffer_stack ();
+			YY_CURRENT_BUFFER_LVALUE =
+				zconf_create_buffer(zconfin,YY_BUF_SIZE );
+		}
+
+		zconf_load_buffer_state( );
+		}
+
+	while ( 1 )		/* loops until end-of-file is reached */
+		{
+		yy_cp = (yy_c_buf_p);
+
+		/* Support of zconftext. */
+		*yy_cp = (yy_hold_char);
+
+		/* yy_bp points to the position in yy_ch_buf of the start of
+		 * the current run.
+		 */
+		yy_bp = yy_cp;
+
+		yy_current_state = (yy_start);
+yy_match:
+		while ( (yy_current_state = yy_nxt[yy_current_state][ yy_ec[YY_SC_TO_UI(*yy_cp)]  ]) > 0 )
+			++yy_cp;
+
+		yy_current_state = -yy_current_state;
+
+yy_find_action:
+		yy_act = yy_accept[yy_current_state];
+
+		YY_DO_BEFORE_ACTION;
+
+do_action:	/* This label is used only to access EOF actions. */
+
+		switch ( yy_act )
+	{ /* beginning of action switch */
+case 1:
+/* rule 1 can match eol */
+case 2:
+/* rule 2 can match eol */
+YY_RULE_SETUP
+{
+	current_file->lineno++;
+	return T_EOL;
+}
+	YY_BREAK
+case 3:
+YY_RULE_SETUP
+
+	YY_BREAK
+case 4:
+YY_RULE_SETUP
+{
+	BEGIN(COMMAND);
+}
+	YY_BREAK
+case 5:
+YY_RULE_SETUP
+{
+	unput(zconftext[0]);
+	BEGIN(COMMAND);
+}
+	YY_BREAK
+
+case 6:
+YY_RULE_SETUP
+{
+		struct kconf_id *id = kconf_id_lookup(zconftext, zconfleng);
+		BEGIN(PARAM);
+		current_pos.file = current_file;
+		current_pos.lineno = current_file->lineno;
+		if (id && id->flags & TF_COMMAND) {
+			zconflval.id = id;
+			return id->token;
+		}
+		alloc_string(zconftext, zconfleng);
+		zconflval.string = text;
+		return T_WORD;
+	}
+	YY_BREAK
+case 7:
+YY_RULE_SETUP
+
+	YY_BREAK
+case 8:
+/* rule 8 can match eol */
+YY_RULE_SETUP
+{
+		BEGIN(INITIAL);
+		current_file->lineno++;
+		return T_EOL;
+	}
+	YY_BREAK
+
+case 9:
+YY_RULE_SETUP
+return T_AND;
+	YY_BREAK
+case 10:
+YY_RULE_SETUP
+return T_OR;
+	YY_BREAK
+case 11:
+YY_RULE_SETUP
+return T_OPEN_PAREN;
+	YY_BREAK
+case 12:
+YY_RULE_SETUP
+return T_CLOSE_PAREN;
+	YY_BREAK
+case 13:
+YY_RULE_SETUP
+return T_NOT;
+	YY_BREAK
+case 14:
+YY_RULE_SETUP
+return T_EQUAL;
+	YY_BREAK
+case 15:
+YY_RULE_SETUP
+return T_UNEQUAL;
+	YY_BREAK
+case 16:
+YY_RULE_SETUP
+{
+		str = zconftext[0];
+		new_string();
+		BEGIN(STRING);
+	}
+	YY_BREAK
+case 17:
+/* rule 17 can match eol */
+YY_RULE_SETUP
+BEGIN(INITIAL); current_file->lineno++; return T_EOL;
+	YY_BREAK
+case 18:
+YY_RULE_SETUP
+/* ignore */
+	YY_BREAK
+case 19:
+YY_RULE_SETUP
+{
+		struct kconf_id *id = kconf_id_lookup(zconftext, zconfleng);
+		if (id && id->flags & TF_PARAM) {
+			zconflval.id = id;
+			return id->token;
+		}
+		alloc_string(zconftext, zconfleng);
+		zconflval.string = text;
+		return T_WORD;
+	}
+	YY_BREAK
+case 20:
+YY_RULE_SETUP
+/* comment */
+	YY_BREAK
+case 21:
+/* rule 21 can match eol */
+YY_RULE_SETUP
+current_file->lineno++;
+	YY_BREAK
+case 22:
+YY_RULE_SETUP
+
+	YY_BREAK
+case YY_STATE_EOF(PARAM):
+{
+		BEGIN(INITIAL);
+	}
+	YY_BREAK
+
+case 23:
+/* rule 23 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up zconftext again */
+YY_RULE_SETUP
+{
+		append_string(zconftext, zconfleng);
+		zconflval.string = text;
+		return T_WORD_QUOTE;
+	}
+	YY_BREAK
+case 24:
+YY_RULE_SETUP
+{
+		append_string(zconftext, zconfleng);
+	}
+	YY_BREAK
+case 25:
+/* rule 25 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up zconftext again */
+YY_RULE_SETUP
+{
+		append_string(zconftext + 1, zconfleng - 1);
+		zconflval.string = text;
+		return T_WORD_QUOTE;
+	}
+	YY_BREAK
+case 26:
+YY_RULE_SETUP
+{
+		append_string(zconftext + 1, zconfleng - 1);
+	}
+	YY_BREAK
+case 27:
+YY_RULE_SETUP
+{
+		if (str == zconftext[0]) {
+			BEGIN(PARAM);
+			zconflval.string = text;
+			return T_WORD_QUOTE;
+		} else
+			append_string(zconftext, 1);
+	}
+	YY_BREAK
+case 28:
+/* rule 28 can match eol */
+YY_RULE_SETUP
+{
+		printf("%s:%d:warning: multi-line strings not supported\n", zconf_curname(), zconf_lineno());
+		current_file->lineno++;
+		BEGIN(INITIAL);
+		return T_EOL;
+	}
+	YY_BREAK
+case YY_STATE_EOF(STRING):
+{
+		BEGIN(INITIAL);
+	}
+	YY_BREAK
+
+case 29:
+YY_RULE_SETUP
+{
+		ts = 0;
+		for (i = 0; i < zconfleng; i++) {
+			if (zconftext[i] == '\t')
+				ts = (ts & ~7) + 8;
+			else
+				ts++;
+		}
+		last_ts = ts;
+		if (first_ts) {
+			if (ts < first_ts) {
+				zconf_endhelp();
+				return T_HELPTEXT;
+			}
+			ts -= first_ts;
+			while (ts > 8) {
+				append_string("        ", 8);
+				ts -= 8;
+			}
+			append_string("        ", ts);
+		}
+	}
+	YY_BREAK
+case 30:
+/* rule 30 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up zconftext again */
+YY_RULE_SETUP
+{
+		current_file->lineno++;
+		zconf_endhelp();
+		return T_HELPTEXT;
+	}
+	YY_BREAK
+case 31:
+/* rule 31 can match eol */
+YY_RULE_SETUP
+{
+		current_file->lineno++;
+		append_string("\n", 1);
+	}
+	YY_BREAK
+case 32:
+YY_RULE_SETUP
+{
+		while (zconfleng) {
+			if ((zconftext[zconfleng-1] != ' ') && (zconftext[zconfleng-1] != '\t'))
+				break;
+			zconfleng--;
+		}
+		append_string(zconftext, zconfleng);
+		if (!first_ts)
+			first_ts = last_ts;
+	}
+	YY_BREAK
+case YY_STATE_EOF(HELP):
+{
+		zconf_endhelp();
+		return T_HELPTEXT;
+	}
+	YY_BREAK
+
+case YY_STATE_EOF(INITIAL):
+case YY_STATE_EOF(COMMAND):
+{
+	if (current_file) {
+		zconf_endfile();
+		return T_EOL;
+	}
+	fclose(zconfin);
+	yyterminate();
+}
+	YY_BREAK
+case 33:
+YY_RULE_SETUP
+YY_FATAL_ERROR( "flex scanner jammed" );
+	YY_BREAK
+
+	case YY_END_OF_BUFFER:
+		{
+		/* Amount of text matched not including the EOB char. */
+		int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+		/* Undo the effects of YY_DO_BEFORE_ACTION. */
+		*yy_cp = (yy_hold_char);
+		YY_RESTORE_YY_MORE_OFFSET
+
+		if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+			{
+			/* We're scanning a new file or input source.  It's
+			 * possible that this happened because the user
+			 * just pointed zconfin at a new source and called
+			 * zconflex().  If so, then we have to assure
+			 * consistency between YY_CURRENT_BUFFER and our
+			 * globals.  Here is the right place to do so, because
+			 * this is the first action (other than possibly a
+			 * back-up) that will match for the new input source.
+			 */
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+			YY_CURRENT_BUFFER_LVALUE->yy_input_file = zconfin;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+			}
+
+		/* Note that here we test for yy_c_buf_p "<=" to the position
+		 * of the first EOB in the buffer, since yy_c_buf_p will
+		 * already have been incremented past the NUL character
+		 * (since all states make transitions on EOB to the
+		 * end-of-buffer state).  Contrast this with the test
+		 * in input().
+		 */
+		if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			{ /* This was really a NUL. */
+			yy_state_type yy_next_state;
+
+			(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+			yy_current_state = yy_get_previous_state(  );
+
+			/* Okay, we're now positioned to make the NUL
+			 * transition.  We couldn't have
+			 * yy_get_previous_state() go ahead and do it
+			 * for us because it doesn't know how to deal
+			 * with the possibility of jamming (and we don't
+			 * want to build jamming into it because then it
+			 * will run more slowly).
+			 */
+
+			yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+			yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+			if ( yy_next_state )
+				{
+				/* Consume the NUL. */
+				yy_cp = ++(yy_c_buf_p);
+				yy_current_state = yy_next_state;
+				goto yy_match;
+				}
+
+			else
+				{
+				yy_cp = (yy_c_buf_p);
+				goto yy_find_action;
+				}
+			}
+
+		else switch ( yy_get_next_buffer(  ) )
+			{
+			case EOB_ACT_END_OF_FILE:
+				{
+				(yy_did_buffer_switch_on_eof) = 0;
+
+				if ( zconfwrap( ) )
+					{
+					/* Note: because we've taken care in
+					 * yy_get_next_buffer() to have set up
+					 * zconftext, we can now set up
+					 * yy_c_buf_p so that if some total
+					 * hoser (like flex itself) wants to
+					 * call the scanner after we return the
+					 * YY_NULL, it'll still work - another
+					 * YY_NULL will get returned.
+					 */
+					(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+					yy_act = YY_STATE_EOF(YY_START);
+					goto do_action;
+					}
+
+				else
+					{
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+					}
+				break;
+				}
+
+			case EOB_ACT_CONTINUE_SCAN:
+				(yy_c_buf_p) =
+					(yytext_ptr) + yy_amount_of_matched_text;
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_match;
+
+			case EOB_ACT_LAST_MATCH:
+				(yy_c_buf_p) =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_find_action;
+			}
+		break;
+		}
+
+	default:
+		YY_FATAL_ERROR(
+			"fatal flex scanner internal error--no action found" );
+	} /* end of action switch */
+		} /* end of scanning one token */
+} /* end of zconflex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ *	EOB_ACT_LAST_MATCH -
+ *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ *	EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+    	register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+	register char *source = (yytext_ptr);
+	register int number_to_move, i;
+	int ret_val;
+
+	if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+		YY_FATAL_ERROR(
+		"fatal flex scanner internal error--end of buffer missed" );
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+		{ /* Don't try to fill the buffer, so this is an EOF. */
+		if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+			{
+			/* We matched a single character, the EOB, so
+			 * treat this as a final EOF.
+			 */
+			return EOB_ACT_END_OF_FILE;
+			}
+
+		else
+			{
+			/* We matched some text prior to the EOB, first
+			 * process it.
+			 */
+			return EOB_ACT_LAST_MATCH;
+			}
+		}
+
+	/* Try to read more data. */
+
+	/* First move last chars to start of buffer. */
+	number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+	for ( i = 0; i < number_to_move; ++i )
+		*(dest++) = *(source++);
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+		/* don't do the read, it's not guaranteed to return an EOF,
+		 * just force an EOF
+		 */
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+	else
+		{
+			int num_to_read =
+			YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+		while ( num_to_read <= 0 )
+			{ /* Not enough room in the buffer - grow it. */
+
+			/* just a shorter name for the current buffer */
+			YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+			int yy_c_buf_p_offset =
+				(int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+			if ( b->yy_is_our_buffer )
+				{
+				int new_size = b->yy_buf_size * 2;
+
+				if ( new_size <= 0 )
+					b->yy_buf_size += b->yy_buf_size / 8;
+				else
+					b->yy_buf_size *= 2;
+
+				b->yy_ch_buf = (char *)
+					/* Include room in for 2 EOB chars. */
+					zconfrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2  );
+				}
+			else
+				/* Can't grow it, we don't own it. */
+				b->yy_ch_buf = 0;
+
+			if ( ! b->yy_ch_buf )
+				YY_FATAL_ERROR(
+				"fatal error - scanner input buffer overflow" );
+
+			(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+			num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+						number_to_move - 1;
+
+			}
+
+		if ( num_to_read > YY_READ_BUF_SIZE )
+			num_to_read = YY_READ_BUF_SIZE;
+
+		/* Read in more data. */
+		YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+			(yy_n_chars), (size_t) num_to_read );
+
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	if ( (yy_n_chars) == 0 )
+		{
+		if ( number_to_move == YY_MORE_ADJ )
+			{
+			ret_val = EOB_ACT_END_OF_FILE;
+			zconfrestart(zconfin  );
+			}
+
+		else
+			{
+			ret_val = EOB_ACT_LAST_MATCH;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+				YY_BUFFER_EOF_PENDING;
+			}
+		}
+
+	else
+		ret_val = EOB_ACT_CONTINUE_SCAN;
+
+	if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+		/* Extend the array by 50%, plus the number we really need. */
+		yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+		YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) zconfrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size  );
+		if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+	}
+
+	(yy_n_chars) += number_to_move;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+	(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+	return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+    static yy_state_type yy_get_previous_state (void)
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp;
+    
+	yy_current_state = (yy_start);
+
+	for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+		{
+		yy_current_state = yy_nxt[yy_current_state][(*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1)];
+		}
+
+	return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ *	next_state = yy_try_NUL_trans( current_state );
+ */
+    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )
+{
+	register int yy_is_jam;
+    
+	yy_current_state = yy_nxt[yy_current_state][1];
+	yy_is_jam = (yy_current_state <= 0);
+
+	return yy_is_jam ? 0 : yy_current_state;
+}
+
+    static void yyunput (int c, register char * yy_bp )
+{
+	register char *yy_cp;
+    
+    yy_cp = (yy_c_buf_p);
+
+	/* undo effects of setting up zconftext */
+	*yy_cp = (yy_hold_char);
+
+	if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+		{ /* need to shift things up to make room */
+		/* +2 for EOB chars. */
+		register int number_to_move = (yy_n_chars) + 2;
+		register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+					YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+		register char *source =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+		while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			*--dest = *--source;
+
+		yy_cp += (int) (dest - source);
+		yy_bp += (int) (dest - source);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+		if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+			YY_FATAL_ERROR( "flex scanner push-back overflow" );
+		}
+
+	*--yy_cp = (char) c;
+
+	(yytext_ptr) = yy_bp;
+	(yy_hold_char) = *yy_cp;
+	(yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+    static int yyinput (void)
+#else
+    static int input  (void)
+#endif
+
+{
+	int c;
+    
+	*(yy_c_buf_p) = (yy_hold_char);
+
+	if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+		{
+		/* yy_c_buf_p now points to the character we want to return.
+		 * If this occurs *before* the EOB characters, then it's a
+		 * valid NUL; if not, then we've hit the end of the buffer.
+		 */
+		if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			/* This was really a NUL. */
+			*(yy_c_buf_p) = '\0';
+
+		else
+			{ /* need more input */
+			int offset = (yy_c_buf_p) - (yytext_ptr);
+			++(yy_c_buf_p);
+
+			switch ( yy_get_next_buffer(  ) )
+				{
+				case EOB_ACT_LAST_MATCH:
+					/* This happens because yy_g_n_b()
+					 * sees that we've accumulated a
+					 * token and flags that we need to
+					 * try matching the token before
+					 * proceeding.  But for input(),
+					 * there's no matching to consider.
+					 * So convert the EOB_ACT_LAST_MATCH
+					 * to EOB_ACT_END_OF_FILE.
+					 */
+
+					/* Reset buffer status. */
+					zconfrestart(zconfin );
+
+					/*FALLTHROUGH*/
+
+				case EOB_ACT_END_OF_FILE:
+					{
+					if ( zconfwrap( ) )
+						return EOF;
+
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+#ifdef __cplusplus
+					return yyinput();
+#else
+					return input();
+#endif
+					}
+
+				case EOB_ACT_CONTINUE_SCAN:
+					(yy_c_buf_p) = (yytext_ptr) + offset;
+					break;
+				}
+			}
+		}
+
+	c = *(unsigned char *) (yy_c_buf_p);	/* cast for 8-bit char's */
+	*(yy_c_buf_p) = '\0';	/* preserve zconftext */
+	(yy_hold_char) = *++(yy_c_buf_p);
+
+	return c;
+}
+#endif	/* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ * 
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+    void zconfrestart  (FILE * input_file )
+{
+    
+	if ( ! YY_CURRENT_BUFFER ){
+        zconfensure_buffer_stack ();
+		YY_CURRENT_BUFFER_LVALUE =
+            zconf_create_buffer(zconfin,YY_BUF_SIZE );
+	}
+
+	zconf_init_buffer(YY_CURRENT_BUFFER,input_file );
+	zconf_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ * 
+ */
+    void zconf_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )
+{
+    
+	/* TODO. We should be able to replace this entire function body
+	 * with
+	 *		zconfpop_buffer_state();
+	 *		zconfpush_buffer_state(new_buffer);
+     */
+	zconfensure_buffer_stack ();
+	if ( YY_CURRENT_BUFFER == new_buffer )
+		return;
+
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+	zconf_load_buffer_state( );
+
+	/* We don't actually know whether we did this switch during
+	 * EOF (zconfwrap()) processing, but the only time this flag
+	 * is looked at is after zconfwrap() is called, so it's safe
+	 * to go ahead and always set it.
+	 */
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void zconf_load_buffer_state  (void)
+{
+    	(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+	(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+	zconfin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+	(yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ * 
+ * @return the allocated buffer state.
+ */
+    YY_BUFFER_STATE zconf_create_buffer  (FILE * file, int  size )
+{
+	YY_BUFFER_STATE b;
+    
+	b = (YY_BUFFER_STATE) zconfalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_create_buffer()" );
+
+	b->yy_buf_size = size;
+
+	/* yy_ch_buf has to be 2 characters longer than the size given because
+	 * we need to put in 2 end-of-buffer characters.
+	 */
+	b->yy_ch_buf = (char *) zconfalloc(b->yy_buf_size + 2  );
+	if ( ! b->yy_ch_buf )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_create_buffer()" );
+
+	b->yy_is_our_buffer = 1;
+
+	zconf_init_buffer(b,file );
+
+	return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with zconf_create_buffer()
+ * 
+ */
+    void zconf_delete_buffer (YY_BUFFER_STATE  b )
+{
+    
+	if ( ! b )
+		return;
+
+	if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+		YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+	if ( b->yy_is_our_buffer )
+		zconffree((void *) b->yy_ch_buf  );
+
+	zconffree((void *) b  );
+}
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a zconfrestart() or at EOF.
+ */
+    static void zconf_init_buffer  (YY_BUFFER_STATE  b, FILE * file )
+
+{
+	int oerrno = errno;
+    
+	zconf_flush_buffer(b );
+
+	b->yy_input_file = file;
+	b->yy_fill_buffer = 1;
+
+    /* If b is the current buffer, then zconf_init_buffer was _probably_
+     * called from zconfrestart() or through yy_get_next_buffer.
+     * In that case, we don't want to reset the lineno or column.
+     */
+    if (b != YY_CURRENT_BUFFER){
+        b->yy_bs_lineno = 1;
+        b->yy_bs_column = 0;
+    }
+
+        b->yy_is_interactive = 0;
+    
+	errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ * 
+ */
+    void zconf_flush_buffer (YY_BUFFER_STATE  b )
+{
+    	if ( ! b )
+		return;
+
+	b->yy_n_chars = 0;
+
+	/* We always need two end-of-buffer characters.  The first causes
+	 * a transition to the end-of-buffer state.  The second causes
+	 * a jam in that state.
+	 */
+	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+	b->yy_buf_pos = &b->yy_ch_buf[0];
+
+	b->yy_at_bol = 1;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	if ( b == YY_CURRENT_BUFFER )
+		zconf_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ *  the current state. This function will allocate the stack
+ *  if necessary.
+ *  @param new_buffer The new state.
+ *  
+ */
+void zconfpush_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+    	if (new_buffer == NULL)
+		return;
+
+	zconfensure_buffer_stack();
+
+	/* This block is copied from zconf_switch_to_buffer. */
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	/* Only push if top exists. Otherwise, replace top. */
+	if (YY_CURRENT_BUFFER)
+		(yy_buffer_stack_top)++;
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+	/* copied from zconf_switch_to_buffer. */
+	zconf_load_buffer_state( );
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ *  The next element becomes the new top.
+ *  
+ */
+void zconfpop_buffer_state (void)
+{
+    	if (!YY_CURRENT_BUFFER)
+		return;
+
+	zconf_delete_buffer(YY_CURRENT_BUFFER );
+	YY_CURRENT_BUFFER_LVALUE = NULL;
+	if ((yy_buffer_stack_top) > 0)
+		--(yy_buffer_stack_top);
+
+	if (YY_CURRENT_BUFFER) {
+		zconf_load_buffer_state( );
+		(yy_did_buffer_switch_on_eof) = 1;
+	}
+}
+
+/* Allocates the stack if it does not exist.
+ *  Guarantees space for at least one push.
+ */
+static void zconfensure_buffer_stack (void)
+{
+	int num_to_alloc;
+    
+	if (!(yy_buffer_stack)) {
+
+		/* First allocation is just for 2 elements, since we don't know if this
+		 * scanner will even need a stack. We use 2 instead of 1 to avoid an
+		 * immediate realloc on the next call.
+         */
+		num_to_alloc = 1;
+		(yy_buffer_stack) = (struct yy_buffer_state**)zconfalloc
+								(num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in zconfensure_buffer_stack()" );
+								  
+		memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+				
+		(yy_buffer_stack_max) = num_to_alloc;
+		(yy_buffer_stack_top) = 0;
+		return;
+	}
+
+	if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+		/* Increase the buffer to prepare for a possible push. */
+		int grow_size = 8 /* arbitrary grow size */;
+
+		num_to_alloc = (yy_buffer_stack_max) + grow_size;
+		(yy_buffer_stack) = (struct yy_buffer_state**)zconfrealloc
+								((yy_buffer_stack),
+								num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in zconfensure_buffer_stack()" );
+
+		/* zero only the new slots.*/
+		memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+		(yy_buffer_stack_max) = num_to_alloc;
+	}
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ * 
+ * @return the newly allocated buffer state object. 
+ */
+YY_BUFFER_STATE zconf_scan_buffer  (char * base, yy_size_t  size )
+{
+	YY_BUFFER_STATE b;
+    
+	if ( size < 2 ||
+	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
+	     base[size-1] != YY_END_OF_BUFFER_CHAR )
+		/* They forgot to leave room for the EOB's. */
+		return 0;
+
+	b = (YY_BUFFER_STATE) zconfalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_scan_buffer()" );
+
+	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
+	b->yy_buf_pos = b->yy_ch_buf = base;
+	b->yy_is_our_buffer = 0;
+	b->yy_input_file = 0;
+	b->yy_n_chars = b->yy_buf_size;
+	b->yy_is_interactive = 0;
+	b->yy_at_bol = 1;
+	b->yy_fill_buffer = 0;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	zconf_switch_to_buffer(b  );
+
+	return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to zconflex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ * 
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ *       zconf_scan_bytes() instead.
+ */
+YY_BUFFER_STATE zconf_scan_string (yyconst char * yystr )
+{
+    
+	return zconf_scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to zconflex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ * 
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE zconf_scan_bytes  (yyconst char * yybytes, int  _yybytes_len )
+{
+	YY_BUFFER_STATE b;
+	char *buf;
+	yy_size_t n;
+	int i;
+    
+	/* Get memory for full buffer, including space for trailing EOB's. */
+	n = _yybytes_len + 2;
+	buf = (char *) zconfalloc(n  );
+	if ( ! buf )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_scan_bytes()" );
+
+	for ( i = 0; i < _yybytes_len; ++i )
+		buf[i] = yybytes[i];
+
+	buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+	b = zconf_scan_buffer(buf,n );
+	if ( ! b )
+		YY_FATAL_ERROR( "bad buffer in zconf_scan_bytes()" );
+
+	/* It's okay to grow etc. this buffer, and we should throw it
+	 * away when we're done.
+	 */
+	b->yy_is_our_buffer = 1;
+
+	return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+    	(void) fprintf( stderr, "%s\n", msg );
+	exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up zconftext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		zconftext[zconfleng] = (yy_hold_char); \
+		(yy_c_buf_p) = zconftext + yyless_macro_arg; \
+		(yy_hold_char) = *(yy_c_buf_p); \
+		*(yy_c_buf_p) = '\0'; \
+		zconfleng = yyless_macro_arg; \
+		} \
+	while ( 0 )
+
+/* Accessor  methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ * 
+ */
+int zconfget_lineno  (void)
+{
+        
+    return zconflineno;
+}
+
+/** Get the input stream.
+ * 
+ */
+FILE *zconfget_in  (void)
+{
+        return zconfin;
+}
+
+/** Get the output stream.
+ * 
+ */
+FILE *zconfget_out  (void)
+{
+        return zconfout;
+}
+
+/** Get the length of the current token.
+ * 
+ */
+int zconfget_leng  (void)
+{
+        return zconfleng;
+}
+
+/** Get the current token.
+ * 
+ */
+
+char *zconfget_text  (void)
+{
+        return zconftext;
+}
+
+/** Set the current line number.
+ * @param line_number
+ * 
+ */
+void zconfset_lineno (int  line_number )
+{
+    
+    zconflineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ * 
+ * @see zconf_switch_to_buffer
+ */
+void zconfset_in (FILE *  in_str )
+{
+        zconfin = in_str ;
+}
+
+void zconfset_out (FILE *  out_str )
+{
+        zconfout = out_str ;
+}
+
+int zconfget_debug  (void)
+{
+        return zconf_flex_debug;
+}
+
+void zconfset_debug (int  bdebug )
+{
+        zconf_flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+        /* Initialization is the same as for the non-reentrant scanner.
+     * This function is called from zconflex_destroy(), so don't allocate here.
+     */
+
+    (yy_buffer_stack) = 0;
+    (yy_buffer_stack_top) = 0;
+    (yy_buffer_stack_max) = 0;
+    (yy_c_buf_p) = (char *) 0;
+    (yy_init) = 0;
+    (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+    zconfin = stdin;
+    zconfout = stdout;
+#else
+    zconfin = (FILE *) 0;
+    zconfout = (FILE *) 0;
+#endif
+
+    /* For future reference: Set errno on error, since we are called by
+     * zconflex_init()
+     */
+    return 0;
+}
+
+/* zconflex_destroy is for both reentrant and non-reentrant scanners. */
+int zconflex_destroy  (void)
+{
+    
+    /* Pop the buffer stack, destroying each element. */
+	while(YY_CURRENT_BUFFER){
+		zconf_delete_buffer(YY_CURRENT_BUFFER  );
+		YY_CURRENT_BUFFER_LVALUE = NULL;
+		zconfpop_buffer_state();
+	}
+
+	/* Destroy the stack itself. */
+	zconffree((yy_buffer_stack) );
+	(yy_buffer_stack) = NULL;
+
+    /* Reset the globals. This is important in a non-reentrant scanner so the next time
+     * zconflex() is called, initialization will occur. */
+    yy_init_globals( );
+
+    return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+	register int i;
+	for ( i = 0; i < n; ++i )
+		s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+	register int n;
+	for ( n = 0; s[n]; ++n )
+		;
+
+	return n;
+}
+#endif
+
+void *zconfalloc (yy_size_t  size )
+{
+	return (void *) malloc( size );
+}
+
+void *zconfrealloc  (void * ptr, yy_size_t  size )
+{
+	/* The cast to (char *) in the following accommodates both
+	 * implementations that use char* generic pointers, and those
+	 * that use void* generic pointers.  It works with the latter
+	 * because both ANSI C and C++ allow castless assignment from
+	 * any pointer type to void*, and deal with argument conversions
+	 * as though doing an assignment.
+	 */
+	return (void *) realloc( (char *) ptr, size );
+}
+
+void zconffree (void * ptr )
+{
+	free( (char *) ptr );	/* see zconfrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+void zconf_starthelp(void)
+{
+	new_string();
+	last_ts = first_ts = 0;
+	BEGIN(HELP);
+}
+
+static void zconf_endhelp(void)
+{
+	zconflval.string = text;
+	BEGIN(INITIAL);
+}
+
+/*
+ * Try to open specified file with following names:
+ * ./name
+ * $(srctree)/name
+ * The latter is used when srctree is separate from objtree
+ * when compiling the kernel.
+ * Return NULL if file is not found.
+ */
+FILE *zconf_fopen(const char *name)
+{
+	char *env, fullname[PATH_MAX+1];
+	FILE *f;
+
+	f = fopen(name, "r");
+	if (!f && name != NULL && name[0] != '/') {
+		env = getenv(SRCTREE);
+		if (env) {
+			sprintf(fullname, "%s/%s", env, name);
+			f = fopen(fullname, "r");
+		}
+	}
+	return f;
+}
+
+void zconf_initscan(const char *name)
+{
+	zconfin = zconf_fopen(name);
+	if (!zconfin) {
+		printf("can't find file %s\n", name);
+		exit(1);
+	}
+
+	current_buf = malloc(sizeof(*current_buf));
+	memset(current_buf, 0, sizeof(*current_buf));
+
+	current_file = file_lookup(name);
+	current_file->lineno = 1;
+	current_file->flags = FILE_BUSY;
+}
+
+void zconf_nextfile(const char *name)
+{
+	struct file *file = file_lookup(name);
+	struct buffer *buf = malloc(sizeof(*buf));
+	memset(buf, 0, sizeof(*buf));
+
+	current_buf->state = YY_CURRENT_BUFFER;
+	zconfin = zconf_fopen(name);
+	if (!zconfin) {
+		printf("%s:%d: can't open file \"%s\"\n", zconf_curname(), zconf_lineno(), name);
+		exit(1);
+	}
+	zconf_switch_to_buffer(zconf_create_buffer(zconfin,YY_BUF_SIZE));
+	buf->parent = current_buf;
+	current_buf = buf;
+
+	if (file->flags & FILE_BUSY) {
+		printf("recursive scan (%s)?\n", name);
+		exit(1);
+	}
+	if (file->flags & FILE_SCANNED) {
+		printf("file %s already scanned?\n", name);
+		exit(1);
+	}
+	file->flags |= FILE_BUSY;
+	file->lineno = 1;
+	file->parent = current_file;
+	current_file = file;
+}
+
+static void zconf_endfile(void)
+{
+	struct buffer *parent;
+
+	current_file->flags |= FILE_SCANNED;
+	current_file->flags &= ~FILE_BUSY;
+	current_file = current_file->parent;
+
+	parent = current_buf->parent;
+	if (parent) {
+		fclose(zconfin);
+		zconf_delete_buffer(YY_CURRENT_BUFFER);
+		zconf_switch_to_buffer(parent->state);
+	}
+	free(current_buf);
+	current_buf = parent;
+}
+
+int zconf_lineno(void)
+{
+	return current_pos.lineno;
+}
+
+char *zconf_curname(void)
+{
+	return current_pos.file ? current_pos.file->name : "<none>";
+}
+
diff -uNra linux-2.6.27.6/scripts/kconfig/mconf linux-2.6.27.6.yaffs/scripts/kconfig/mconf
\ 文件尾没有 newline 字符
diff -uNra linux-2.6.27.6/scripts/kconfig/zconf.hash.c linux-2.6.27.6.yaffs/scripts/kconfig/zconf.hash.c
--- linux-2.6.27.6/scripts/kconfig/zconf.hash.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/kconfig/zconf.hash.c	2011-05-08 18:02:54.000000000 +0800
@@ -0,0 +1,237 @@
+/* ANSI-C code produced by gperf version 3.0.3 */
+/* Command-line: gperf  */
+/* Computed positions: -k'1,3' */
+
+#if !((' ' == 32) && ('!' == 33) && ('"' == 34) && ('#' == 35) \
+      && ('%' == 37) && ('&' == 38) && ('\'' == 39) && ('(' == 40) \
+      && (')' == 41) && ('*' == 42) && ('+' == 43) && (',' == 44) \
+      && ('-' == 45) && ('.' == 46) && ('/' == 47) && ('0' == 48) \
+      && ('1' == 49) && ('2' == 50) && ('3' == 51) && ('4' == 52) \
+      && ('5' == 53) && ('6' == 54) && ('7' == 55) && ('8' == 56) \
+      && ('9' == 57) && (':' == 58) && (';' == 59) && ('<' == 60) \
+      && ('=' == 61) && ('>' == 62) && ('?' == 63) && ('A' == 65) \
+      && ('B' == 66) && ('C' == 67) && ('D' == 68) && ('E' == 69) \
+      && ('F' == 70) && ('G' == 71) && ('H' == 72) && ('I' == 73) \
+      && ('J' == 74) && ('K' == 75) && ('L' == 76) && ('M' == 77) \
+      && ('N' == 78) && ('O' == 79) && ('P' == 80) && ('Q' == 81) \
+      && ('R' == 82) && ('S' == 83) && ('T' == 84) && ('U' == 85) \
+      && ('V' == 86) && ('W' == 87) && ('X' == 88) && ('Y' == 89) \
+      && ('Z' == 90) && ('[' == 91) && ('\\' == 92) && (']' == 93) \
+      && ('^' == 94) && ('_' == 95) && ('a' == 97) && ('b' == 98) \
+      && ('c' == 99) && ('d' == 100) && ('e' == 101) && ('f' == 102) \
+      && ('g' == 103) && ('h' == 104) && ('i' == 105) && ('j' == 106) \
+      && ('k' == 107) && ('l' == 108) && ('m' == 109) && ('n' == 110) \
+      && ('o' == 111) && ('p' == 112) && ('q' == 113) && ('r' == 114) \
+      && ('s' == 115) && ('t' == 116) && ('u' == 117) && ('v' == 118) \
+      && ('w' == 119) && ('x' == 120) && ('y' == 121) && ('z' == 122) \
+      && ('{' == 123) && ('|' == 124) && ('}' == 125) && ('~' == 126))
+/* The character set is not based on ISO-646.  */
+#error "gperf generated tables don't work with this execution character set. Please report a bug to <bug-gnu-gperf@gnu.org>."
+#endif
+
+struct kconf_id;
+/* maximum key range = 47, duplicates = 0 */
+
+#ifdef __GNUC__
+__inline
+#else
+#ifdef __cplusplus
+inline
+#endif
+#endif
+static unsigned int
+kconf_id_hash (register const char *str, register unsigned int len)
+{
+  static unsigned char asso_values[] =
+    {
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 11,  5,
+       0,  0,  5, 49,  5, 20, 49, 49,  5, 20,
+       5,  0, 30, 49,  0, 15,  0, 10,  0, 49,
+      25, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
+      49, 49, 49, 49, 49, 49
+    };
+  register int hval = len;
+
+  switch (hval)
+    {
+      default:
+        hval += asso_values[(unsigned char)str[2]];
+      /*FALLTHROUGH*/
+      case 2:
+      case 1:
+        hval += asso_values[(unsigned char)str[0]];
+        break;
+    }
+  return hval;
+}
+
+struct kconf_id_strings_t
+  {
+    char kconf_id_strings_str2[sizeof("on")];
+    char kconf_id_strings_str3[sizeof("env")];
+    char kconf_id_strings_str5[sizeof("endif")];
+    char kconf_id_strings_str6[sizeof("option")];
+    char kconf_id_strings_str7[sizeof("endmenu")];
+    char kconf_id_strings_str8[sizeof("optional")];
+    char kconf_id_strings_str9[sizeof("endchoice")];
+    char kconf_id_strings_str10[sizeof("range")];
+    char kconf_id_strings_str11[sizeof("choice")];
+    char kconf_id_strings_str12[sizeof("default")];
+    char kconf_id_strings_str13[sizeof("def_bool")];
+    char kconf_id_strings_str14[sizeof("help")];
+    char kconf_id_strings_str15[sizeof("bool")];
+    char kconf_id_strings_str16[sizeof("config")];
+    char kconf_id_strings_str17[sizeof("def_tristate")];
+    char kconf_id_strings_str18[sizeof("boolean")];
+    char kconf_id_strings_str19[sizeof("defconfig_list")];
+    char kconf_id_strings_str21[sizeof("string")];
+    char kconf_id_strings_str22[sizeof("if")];
+    char kconf_id_strings_str23[sizeof("int")];
+    char kconf_id_strings_str26[sizeof("select")];
+    char kconf_id_strings_str27[sizeof("modules")];
+    char kconf_id_strings_str28[sizeof("tristate")];
+    char kconf_id_strings_str29[sizeof("menu")];
+    char kconf_id_strings_str31[sizeof("source")];
+    char kconf_id_strings_str32[sizeof("comment")];
+    char kconf_id_strings_str33[sizeof("hex")];
+    char kconf_id_strings_str35[sizeof("menuconfig")];
+    char kconf_id_strings_str36[sizeof("prompt")];
+    char kconf_id_strings_str37[sizeof("depends")];
+    char kconf_id_strings_str48[sizeof("mainmenu")];
+  };
+static struct kconf_id_strings_t kconf_id_strings_contents =
+  {
+    "on",
+    "env",
+    "endif",
+    "option",
+    "endmenu",
+    "optional",
+    "endchoice",
+    "range",
+    "choice",
+    "default",
+    "def_bool",
+    "help",
+    "bool",
+    "config",
+    "def_tristate",
+    "boolean",
+    "defconfig_list",
+    "string",
+    "if",
+    "int",
+    "select",
+    "modules",
+    "tristate",
+    "menu",
+    "source",
+    "comment",
+    "hex",
+    "menuconfig",
+    "prompt",
+    "depends",
+    "mainmenu"
+  };
+#define kconf_id_strings ((const char *) &kconf_id_strings_contents)
+#ifdef __GNUC__
+__inline
+#ifdef __GNUC_STDC_INLINE__
+__attribute__ ((__gnu_inline__))
+#endif
+#endif
+struct kconf_id *
+kconf_id_lookup (register const char *str, register unsigned int len)
+{
+  enum
+    {
+      TOTAL_KEYWORDS = 31,
+      MIN_WORD_LENGTH = 2,
+      MAX_WORD_LENGTH = 14,
+      MIN_HASH_VALUE = 2,
+      MAX_HASH_VALUE = 48
+    };
+
+  static struct kconf_id wordlist[] =
+    {
+      {-1}, {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str2,		T_ON,		TF_PARAM},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str3,		T_OPT_ENV,	TF_OPTION},
+      {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str5,		T_ENDIF,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str6,		T_OPTION,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str7,	T_ENDMENU,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str8,	T_OPTIONAL,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str9,	T_ENDCHOICE,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str10,		T_RANGE,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str11,		T_CHOICE,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str12,	T_DEFAULT,	TF_COMMAND, S_UNKNOWN},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str13,	T_DEFAULT,	TF_COMMAND, S_BOOLEAN},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str14,		T_HELP,		TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str15,		T_TYPE,		TF_COMMAND, S_BOOLEAN},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str16,		T_CONFIG,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str17,	T_DEFAULT,	TF_COMMAND, S_TRISTATE},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str18,	T_TYPE,		TF_COMMAND, S_BOOLEAN},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str19,	T_OPT_DEFCONFIG_LIST,TF_OPTION},
+      {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str21,		T_TYPE,		TF_COMMAND, S_STRING},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str22,		T_IF,		TF_COMMAND|TF_PARAM},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str23,		T_TYPE,		TF_COMMAND, S_INT},
+      {-1}, {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str26,		T_SELECT,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str27,	T_OPT_MODULES,	TF_OPTION},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str28,	T_TYPE,		TF_COMMAND, S_TRISTATE},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str29,		T_MENU,		TF_COMMAND},
+      {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str31,		T_SOURCE,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str32,	T_COMMENT,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str33,		T_TYPE,		TF_COMMAND, S_HEX},
+      {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str35,	T_MENUCONFIG,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str36,		T_PROMPT,	TF_COMMAND},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str37,	T_DEPENDS,	TF_COMMAND},
+      {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, {-1},
+      {-1},
+      {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str48,	T_MAINMENU,	TF_COMMAND}
+    };
+
+  if (len <= MAX_WORD_LENGTH && len >= MIN_WORD_LENGTH)
+    {
+      register int key = kconf_id_hash (str, len);
+
+      if (key <= MAX_HASH_VALUE && key >= 0)
+        {
+          register int o = wordlist[key].name;
+          if (o >= 0)
+            {
+              register const char *s = o + kconf_id_strings;
+
+              if (*str == *s && !strncmp (str + 1, s + 1, len - 1) && s[len] == '\0')
+                return &wordlist[key];
+            }
+        }
+    }
+  return 0;
+}
+
diff -uNra linux-2.6.27.6/scripts/kconfig/zconf.tab.c linux-2.6.27.6.yaffs/scripts/kconfig/zconf.tab.c
--- linux-2.6.27.6/scripts/kconfig/zconf.tab.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/kconfig/zconf.tab.c	2011-05-08 18:10:01.000000000 +0800
@@ -0,0 +1,2490 @@
+/* A Bison parser, made by GNU Bison 2.3.  */
+
+/* Skeleton implementation for Bison's Yacc-like parsers in C
+
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+   simplifying the original so-called "semantic" parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "2.3"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Using locations.  */
+#define YYLSP_NEEDED 0
+
+/* Substitute the variable and function names.  */
+#define yyparse zconfparse
+#define yylex   zconflex
+#define yyerror zconferror
+#define yylval  zconflval
+#define yychar  zconfchar
+#define yydebug zconfdebug
+#define yynerrs zconfnerrs
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     T_MAINMENU = 258,
+     T_MENU = 259,
+     T_ENDMENU = 260,
+     T_SOURCE = 261,
+     T_CHOICE = 262,
+     T_ENDCHOICE = 263,
+     T_COMMENT = 264,
+     T_CONFIG = 265,
+     T_MENUCONFIG = 266,
+     T_HELP = 267,
+     T_HELPTEXT = 268,
+     T_IF = 269,
+     T_ENDIF = 270,
+     T_DEPENDS = 271,
+     T_OPTIONAL = 272,
+     T_PROMPT = 273,
+     T_TYPE = 274,
+     T_DEFAULT = 275,
+     T_SELECT = 276,
+     T_RANGE = 277,
+     T_OPTION = 278,
+     T_ON = 279,
+     T_WORD = 280,
+     T_WORD_QUOTE = 281,
+     T_UNEQUAL = 282,
+     T_CLOSE_PAREN = 283,
+     T_OPEN_PAREN = 284,
+     T_EOL = 285,
+     T_OR = 286,
+     T_AND = 287,
+     T_EQUAL = 288,
+     T_NOT = 289
+   };
+#endif
+/* Tokens.  */
+#define T_MAINMENU 258
+#define T_MENU 259
+#define T_ENDMENU 260
+#define T_SOURCE 261
+#define T_CHOICE 262
+#define T_ENDCHOICE 263
+#define T_COMMENT 264
+#define T_CONFIG 265
+#define T_MENUCONFIG 266
+#define T_HELP 267
+#define T_HELPTEXT 268
+#define T_IF 269
+#define T_ENDIF 270
+#define T_DEPENDS 271
+#define T_OPTIONAL 272
+#define T_PROMPT 273
+#define T_TYPE 274
+#define T_DEFAULT 275
+#define T_SELECT 276
+#define T_RANGE 277
+#define T_OPTION 278
+#define T_ON 279
+#define T_WORD 280
+#define T_WORD_QUOTE 281
+#define T_UNEQUAL 282
+#define T_CLOSE_PAREN 283
+#define T_OPEN_PAREN 284
+#define T_EOL 285
+#define T_OR 286
+#define T_AND 287
+#define T_EQUAL 288
+#define T_NOT 289
+
+
+
+
+/* Copy the first part of user declarations.  */
+
+
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <ctype.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdbool.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+#include "zconf.hash.c"
+
+#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt)
+
+#define PRINTD		0x0001
+#define DEBUG_PARSE	0x0002
+
+int cdebug = PRINTD;
+
+extern int zconflex(void);
+static void zconfprint(const char *err, ...);
+static void zconf_error(const char *err, ...);
+static void zconferror(const char *err);
+static bool zconf_endtoken(struct kconf_id *id, int starttoken, int endtoken);
+
+struct symbol *symbol_hash[257];
+
+static struct menu *current_menu, *current_entry;
+
+#define YYDEBUG 0
+#if YYDEBUG
+#define YYERROR_VERBOSE
+#endif
+
+
+/* Enabling traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* Enabling the token table.  */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE
+
+{
+	char *string;
+	struct file *file;
+	struct symbol *symbol;
+	struct expr *expr;
+	struct menu *menu;
+	struct kconf_id *id;
+}
+/* Line 187 of yacc.c.  */
+
+	YYSTYPE;
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+
+
+/* Copy the second part of user declarations.  */
+
+
+/* Line 216 of yacc.c.  */
+
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#elif (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+typedef signed char yytype_int8;
+#else
+typedef short int yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+#  define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+#  define YYSIZE_T size_t
+# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYSIZE_T size_t
+# else
+#  define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(msgid) dgettext ("bison-runtime", msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(msgid) msgid
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E.  */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(e) ((void) (e))
+#else
+# define YYUSE(e) /* empty */
+#endif
+
+/* Identity function, used to suppress warnings about constant conditions.  */
+#ifndef lint
+# define YYID(n) (n)
+#else
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static int
+YYID (int i)
+#else
+static int
+YYID (i)
+    int i;
+#endif
+{
+  return i;
+}
+#endif
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols.  */
+
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
+#   elif defined __BUILTIN_VA_ARG_INCR
+#    include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+#   elif defined _AIX
+#    define YYSTACK_ALLOC __alloca
+#   elif defined _MSC_VER
+#    include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+#    define alloca _alloca
+#   else
+#    define YYSTACK_ALLOC alloca
+#    if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#     ifndef _STDLIB_H
+#      define _STDLIB_H 1
+#     endif
+#    endif
+#   endif
+#  endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+   /* Pacify GCC's `empty if-body' warning.  */
+#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+#  endif
+# else
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+#  endif
+#  if (defined __cplusplus && ! defined _STDLIB_H \
+       && ! ((defined YYMALLOC || defined malloc) \
+	     && (defined YYFREE || defined free)))
+#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#   ifndef _STDLIB_H
+#    define _STDLIB_H 1
+#   endif
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+     && (! defined __cplusplus \
+	 || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member.  */
+union yyalloc
+{
+  yytype_int16 yyss;
+  YYSTYPE yyvs;
+  };
+
+/* The size of the maximum gap between one aligned stack and the next.  */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+   N elements.  */
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+      + YYSTACK_GAP_MAXIMUM)
+
+/* Copy COUNT objects from FROM to TO.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined __GNUC__ && 1 < __GNUC__
+#   define YYCOPY(To, From, Count) \
+      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+#  else
+#   define YYCOPY(To, From, Count)		\
+      do					\
+	{					\
+	  YYSIZE_T yyi;				\
+	  for (yyi = 0; yyi < (Count); yyi++)	\
+	    (To)[yyi] = (From)[yyi];		\
+	}					\
+      while (YYID (0))
+#  endif
+# endif
+
+/* Relocate STACK from its old location to the new one.  The
+   local variables YYSIZE and YYSTACKSIZE give the old and new number of
+   elements in the stack, and YYPTR gives the new location of the
+   stack.  Advance YYPTR to a properly aligned location for the next
+   stack.  */
+# define YYSTACK_RELOCATE(Stack)					\
+    do									\
+      {									\
+	YYSIZE_T yynewbytes;						\
+	YYCOPY (&yyptr->Stack, Stack, yysize);				\
+	Stack = &yyptr->Stack;						\
+	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+	yyptr += yynewbytes / sizeof (*yyptr);				\
+      }									\
+    while (YYID (0))
+
+#endif
+
+/* YYFINAL -- State number of the termination state.  */
+#define YYFINAL  3
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   259
+
+/* YYNTOKENS -- Number of terminals.  */
+#define YYNTOKENS  35
+/* YYNNTS -- Number of nonterminals.  */
+#define YYNNTS  46
+/* YYNRULES -- Number of rules.  */
+#define YYNRULES  110
+/* YYNRULES -- Number of states.  */
+#define YYNSTATES  180
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   289
+
+#define YYTRANSLATE(YYX)						\
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
+static const yytype_uint8 yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,
+      25,    26,    27,    28,    29,    30,    31,    32,    33,    34
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+   YYRHS.  */
+static const yytype_uint16 yyprhs[] =
+{
+       0,     0,     3,     5,     6,     9,    12,    15,    20,    23,
+      28,    33,    37,    39,    41,    43,    45,    47,    49,    51,
+      53,    55,    57,    59,    61,    63,    67,    70,    74,    77,
+      81,    84,    85,    88,    91,    94,    97,   100,   103,   107,
+     112,   117,   122,   128,   132,   133,   137,   138,   141,   145,
+     148,   150,   154,   155,   158,   161,   164,   167,   170,   175,
+     179,   182,   187,   188,   191,   195,   197,   201,   202,   205,
+     208,   211,   215,   218,   220,   224,   225,   228,   231,   234,
+     238,   242,   245,   248,   251,   252,   255,   258,   261,   266,
+     267,   270,   272,   274,   277,   280,   283,   285,   288,   289,
+     292,   294,   298,   302,   306,   309,   313,   317,   319,   321,
+     322
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS.  */
+static const yytype_int8 yyrhs[] =
+{
+      36,     0,    -1,    37,    -1,    -1,    37,    39,    -1,    37,
+      53,    -1,    37,    64,    -1,    37,     3,    74,    76,    -1,
+      37,    75,    -1,    37,    25,     1,    30,    -1,    37,    38,
+       1,    30,    -1,    37,     1,    30,    -1,    16,    -1,    18,
+      -1,    19,    -1,    21,    -1,    17,    -1,    22,    -1,    20,
+      -1,    30,    -1,    59,    -1,    68,    -1,    42,    -1,    44,
+      -1,    66,    -1,    25,     1,    30,    -1,     1,    30,    -1,
+      10,    25,    30,    -1,    41,    45,    -1,    11,    25,    30,
+      -1,    43,    45,    -1,    -1,    45,    46,    -1,    45,    47,
+      -1,    45,    72,    -1,    45,    70,    -1,    45,    40,    -1,
+      45,    30,    -1,    19,    73,    30,    -1,    18,    74,    77,
+      30,    -1,    20,    78,    77,    30,    -1,    21,    25,    77,
+      30,    -1,    22,    79,    79,    77,    30,    -1,    23,    48,
+      30,    -1,    -1,    48,    25,    49,    -1,    -1,    33,    74,
+      -1,     7,    80,    30,    -1,    50,    54,    -1,    75,    -1,
+      51,    56,    52,    -1,    -1,    54,    55,    -1,    54,    72,
+      -1,    54,    70,    -1,    54,    30,    -1,    54,    40,    -1,
+      18,    74,    77,    30,    -1,    19,    73,    30,    -1,    17,
+      30,    -1,    20,    25,    77,    30,    -1,    -1,    56,    39,
+      -1,    14,    78,    76,    -1,    75,    -1,    57,    60,    58,
+      -1,    -1,    60,    39,    -1,    60,    64,    -1,    60,    53,
+      -1,     4,    74,    30,    -1,    61,    71,    -1,    75,    -1,
+      62,    65,    63,    -1,    -1,    65,    39,    -1,    65,    64,
+      -1,    65,    53,    -1,     6,    74,    30,    -1,     9,    74,
+      30,    -1,    67,    71,    -1,    12,    30,    -1,    69,    13,
+      -1,    -1,    71,    72,    -1,    71,    30,    -1,    71,    40,
+      -1,    16,    24,    78,    30,    -1,    -1,    74,    77,    -1,
+      25,    -1,    26,    -1,     5,    30,    -1,     8,    30,    -1,
+      15,    30,    -1,    30,    -1,    76,    30,    -1,    -1,    14,
+      78,    -1,    79,    -1,    79,    33,    79,    -1,    79,    27,
+      79,    -1,    29,    78,    28,    -1,    34,    78,    -1,    78,
+      31,    78,    -1,    78,    32,    78,    -1,    25,    -1,    26,
+      -1,    -1,    25,    -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
+static const yytype_uint16 yyrline[] =
+{
+       0,   104,   104,   106,   108,   109,   110,   111,   112,   113,
+     114,   118,   122,   122,   122,   122,   122,   122,   122,   126,
+     127,   128,   129,   130,   131,   135,   136,   142,   150,   156,
+     164,   174,   176,   177,   178,   179,   180,   181,   184,   192,
+     198,   208,   214,   220,   223,   225,   236,   237,   242,   251,
+     256,   264,   267,   269,   270,   271,   272,   273,   276,   282,
+     293,   299,   309,   311,   316,   324,   332,   335,   337,   338,
+     339,   344,   351,   356,   364,   367,   369,   370,   371,   374,
+     382,   389,   396,   402,   409,   411,   412,   413,   416,   424,
+     426,   431,   432,   435,   436,   437,   441,   442,   445,   446,
+     449,   450,   451,   452,   453,   454,   455,   458,   459,   462,
+     463
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals.  */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "T_MAINMENU", "T_MENU", "T_ENDMENU",
+  "T_SOURCE", "T_CHOICE", "T_ENDCHOICE", "T_COMMENT", "T_CONFIG",
+  "T_MENUCONFIG", "T_HELP", "T_HELPTEXT", "T_IF", "T_ENDIF", "T_DEPENDS",
+  "T_OPTIONAL", "T_PROMPT", "T_TYPE", "T_DEFAULT", "T_SELECT", "T_RANGE",
+  "T_OPTION", "T_ON", "T_WORD", "T_WORD_QUOTE", "T_UNEQUAL",
+  "T_CLOSE_PAREN", "T_OPEN_PAREN", "T_EOL", "T_OR", "T_AND", "T_EQUAL",
+  "T_NOT", "$accept", "input", "stmt_list", "option_name", "common_stmt",
+  "option_error", "config_entry_start", "config_stmt",
+  "menuconfig_entry_start", "menuconfig_stmt", "config_option_list",
+  "config_option", "symbol_option", "symbol_option_list",
+  "symbol_option_arg", "choice", "choice_entry", "choice_end",
+  "choice_stmt", "choice_option_list", "choice_option", "choice_block",
+  "if_entry", "if_end", "if_stmt", "if_block", "menu", "menu_entry",
+  "menu_end", "menu_stmt", "menu_block", "source_stmt", "comment",
+  "comment_stmt", "help_start", "help", "depends_list", "depends",
+  "prompt_stmt_opt", "prompt", "end", "nl", "if_expr", "expr", "symbol",
+  "word_opt", 0
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+   token YYLEX-NUM.  */
+static const yytype_uint16 yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
+     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
+     275,   276,   277,   278,   279,   280,   281,   282,   283,   284,
+     285,   286,   287,   288,   289
+};
+# endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const yytype_uint8 yyr1[] =
+{
+       0,    35,    36,    37,    37,    37,    37,    37,    37,    37,
+      37,    37,    38,    38,    38,    38,    38,    38,    38,    39,
+      39,    39,    39,    39,    39,    40,    40,    41,    42,    43,
+      44,    45,    45,    45,    45,    45,    45,    45,    46,    46,
+      46,    46,    46,    47,    48,    48,    49,    49,    50,    51,
+      52,    53,    54,    54,    54,    54,    54,    54,    55,    55,
+      55,    55,    56,    56,    57,    58,    59,    60,    60,    60,
+      60,    61,    62,    63,    64,    65,    65,    65,    65,    66,
+      67,    68,    69,    70,    71,    71,    71,    71,    72,    73,
+      73,    74,    74,    75,    75,    75,    76,    76,    77,    77,
+      78,    78,    78,    78,    78,    78,    78,    79,    79,    80,
+      80
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
+static const yytype_uint8 yyr2[] =
+{
+       0,     2,     1,     0,     2,     2,     2,     4,     2,     4,
+       4,     3,     1,     1,     1,     1,     1,     1,     1,     1,
+       1,     1,     1,     1,     1,     3,     2,     3,     2,     3,
+       2,     0,     2,     2,     2,     2,     2,     2,     3,     4,
+       4,     4,     5,     3,     0,     3,     0,     2,     3,     2,
+       1,     3,     0,     2,     2,     2,     2,     2,     4,     3,
+       2,     4,     0,     2,     3,     1,     3,     0,     2,     2,
+       2,     3,     2,     1,     3,     0,     2,     2,     2,     3,
+       3,     2,     2,     2,     0,     2,     2,     2,     4,     0,
+       2,     1,     1,     2,     2,     2,     1,     2,     0,     2,
+       1,     3,     3,     3,     2,     3,     3,     1,     1,     0,
+       1
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+   means the default is an error.  */
+static const yytype_uint8 yydefact[] =
+{
+       3,     0,     0,     1,     0,     0,     0,     0,     0,   109,
+       0,     0,     0,     0,     0,     0,    12,    16,    13,    14,
+      18,    15,    17,     0,    19,     0,     4,    31,    22,    31,
+      23,    52,    62,     5,    67,    20,    84,    75,     6,    24,
+      84,    21,     8,    11,    91,    92,     0,     0,    93,     0,
+     110,     0,    94,     0,     0,     0,   107,   108,     0,     0,
+       0,   100,    95,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,    96,     7,    71,    79,    48,    80,    27,
+      29,     0,   104,     0,     0,    64,     0,     0,     9,    10,
+       0,     0,     0,     0,    89,     0,     0,     0,    44,     0,
+      37,    36,    32,    33,     0,    35,    34,     0,     0,    89,
+       0,    56,    57,    53,    55,    54,    63,    51,    50,    68,
+      70,    66,    69,    65,    86,    87,    85,    76,    78,    74,
+      77,    73,    97,   103,   105,   106,   102,   101,    26,    82,
+       0,    98,     0,    98,    98,    98,     0,     0,     0,    83,
+      60,    98,     0,    98,     0,     0,     0,    38,    90,     0,
+       0,    98,    46,    43,    25,     0,    59,     0,    88,    99,
+      39,    40,    41,     0,     0,    45,    58,    61,    42,    47
+};
+
+/* YYDEFGOTO[NTERM-NUM].  */
+static const yytype_int16 yydefgoto[] =
+{
+      -1,     1,     2,    25,    26,   101,    27,    28,    29,    30,
+      65,   102,   103,   147,   175,    31,    32,   117,    33,    67,
+     113,    68,    34,   121,    35,    69,    36,    37,   129,    38,
+      71,    39,    40,    41,   104,   105,    70,   106,   142,   143,
+      42,    74,   156,    60,    61,    51
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
+#define YYPACT_NINF -80
+static const yytype_int16 yypact[] =
+{
+     -80,     2,   132,   -80,   -13,    -1,    -1,    -2,    -1,     9,
+      33,    -1,    27,    40,    -3,    38,   -80,   -80,   -80,   -80,
+     -80,   -80,   -80,    71,   -80,    77,   -80,   -80,   -80,   -80,
+     -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,
+     -80,   -80,   -80,   -80,   -80,   -80,    57,    61,   -80,    63,
+     -80,    76,   -80,    87,   101,   133,   -80,   -80,    -3,    -3,
+     195,    -6,   -80,   136,   149,    39,   104,    65,   150,     5,
+     194,     5,   167,   -80,   176,   -80,   -80,   -80,   -80,   -80,
+     -80,    68,   -80,    -3,    -3,   176,    72,    72,   -80,   -80,
+     177,   187,    78,    -1,    -1,    -3,   196,    72,   -80,   222,
+     -80,   -80,   -80,   -80,   221,   -80,   -80,   205,    -1,    -1,
+     211,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,
+     -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,
+     -80,   -80,   -80,   -80,   206,   -80,   -80,   -80,   -80,   -80,
+      -3,   223,   209,   223,   197,   223,    72,     7,   210,   -80,
+     -80,   223,   212,   223,   201,    -3,   213,   -80,   -80,   214,
+     215,   223,   208,   -80,   -80,   216,   -80,   217,   -80,   113,
+     -80,   -80,   -80,   218,    -1,   -80,   -80,   -80,   -80,   -80
+};
+
+/* YYPGOTO[NTERM-NUM].  */
+static const yytype_int16 yypgoto[] =
+{
+     -80,   -80,   -80,   -80,   122,   -34,   -80,   -80,   -80,   -80,
+     220,   -80,   -80,   -80,   -80,   -80,   -80,   -80,    59,   -80,
+     -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   -80,   125,
+     -80,   -80,   -80,   -80,   -80,   183,   219,    22,   142,    -5,
+     147,   192,    69,   -54,   -79,   -80
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule which
+   number is the opposite.  If zero, do what YYDEFACT says.
+   If YYTABLE_NINF, syntax error.  */
+#define YYTABLE_NINF -82
+static const yytype_int16 yytable[] =
+{
+      46,    47,     3,    49,    81,    82,    53,   136,   137,     6,
+       7,     8,     9,    10,    11,    12,    13,    43,   146,    14,
+      15,    86,    56,    57,    44,    45,    58,    87,    48,   134,
+     135,    59,   162,   112,    50,    24,   125,   163,   125,   -28,
+      90,   144,   -28,   -28,   -28,   -28,   -28,   -28,   -28,   -28,
+     -28,    91,    54,   -28,   -28,    92,   -28,    93,    94,    95,
+      96,    97,    98,    52,    99,    55,    90,   161,    62,   100,
+     -49,   -49,    63,   -49,   -49,   -49,   -49,    91,    64,   -49,
+     -49,    92,   107,   108,   109,   110,   154,    73,   141,   115,
+      99,    75,   126,    76,   126,   111,   133,    56,    57,    83,
+      84,   169,   140,   151,   -30,    90,    77,   -30,   -30,   -30,
+     -30,   -30,   -30,   -30,   -30,   -30,    91,    78,   -30,   -30,
+      92,   -30,    93,    94,    95,    96,    97,    98,   120,    99,
+     128,    79,    -2,     4,   100,     5,     6,     7,     8,     9,
+      10,    11,    12,    13,    83,    84,    14,    15,    16,    17,
+      18,    19,    20,    21,    22,     7,     8,    23,    10,    11,
+      12,    13,    24,    80,    14,    15,    88,   -81,    90,   179,
+     -81,   -81,   -81,   -81,   -81,   -81,   -81,   -81,   -81,    89,
+      24,   -81,   -81,    92,   -81,   -81,   -81,   -81,   -81,   -81,
+     116,   119,    99,   127,   122,    90,   130,   124,   -72,   -72,
+     -72,   -72,   -72,   -72,   -72,   -72,   132,   138,   -72,   -72,
+      92,   155,   158,   159,   160,   118,   123,   139,   131,    99,
+     165,   145,   167,   148,   124,    73,    83,    84,    83,    84,
+     173,   168,    83,    84,   149,   150,   153,   155,    84,   157,
+     164,   174,   166,   170,   171,   172,   176,   177,   178,    66,
+     114,   152,    85,     0,     0,     0,     0,     0,     0,    72
+};
+
+static const yytype_int16 yycheck[] =
+{
+       5,     6,     0,     8,    58,    59,    11,    86,    87,     4,
+       5,     6,     7,     8,     9,    10,    11,    30,    97,    14,
+      15,    27,    25,    26,    25,    26,    29,    33,    30,    83,
+      84,    34,    25,    67,    25,    30,    70,    30,    72,     0,
+       1,    95,     3,     4,     5,     6,     7,     8,     9,    10,
+      11,    12,    25,    14,    15,    16,    17,    18,    19,    20,
+      21,    22,    23,    30,    25,    25,     1,   146,    30,    30,
+       5,     6,     1,     8,     9,    10,    11,    12,     1,    14,
+      15,    16,    17,    18,    19,    20,   140,    30,    93,    67,
+      25,    30,    70,    30,    72,    30,    28,    25,    26,    31,
+      32,   155,    24,   108,     0,     1,    30,     3,     4,     5,
+       6,     7,     8,     9,    10,    11,    12,    30,    14,    15,
+      16,    17,    18,    19,    20,    21,    22,    23,    69,    25,
+      71,    30,     0,     1,    30,     3,     4,     5,     6,     7,
+       8,     9,    10,    11,    31,    32,    14,    15,    16,    17,
+      18,    19,    20,    21,    22,     5,     6,    25,     8,     9,
+      10,    11,    30,    30,    14,    15,    30,     0,     1,   174,
+       3,     4,     5,     6,     7,     8,     9,    10,    11,    30,
+      30,    14,    15,    16,    17,    18,    19,    20,    21,    22,
+      68,    69,    25,    71,    69,     1,    71,    30,     4,     5,
+       6,     7,     8,     9,    10,    11,    30,    30,    14,    15,
+      16,    14,   143,   144,   145,    68,    69,    30,    71,    25,
+     151,    25,   153,     1,    30,    30,    31,    32,    31,    32,
+     161,    30,    31,    32,    13,    30,    25,    14,    32,    30,
+      30,    33,    30,    30,    30,    30,    30,    30,    30,    29,
+      67,   109,    60,    -1,    -1,    -1,    -1,    -1,    -1,    40
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+   symbol of state STATE-NUM.  */
+static const yytype_uint8 yystos[] =
+{
+       0,    36,    37,     0,     1,     3,     4,     5,     6,     7,
+       8,     9,    10,    11,    14,    15,    16,    17,    18,    19,
+      20,    21,    22,    25,    30,    38,    39,    41,    42,    43,
+      44,    50,    51,    53,    57,    59,    61,    62,    64,    66,
+      67,    68,    75,    30,    25,    26,    74,    74,    30,    74,
+      25,    80,    30,    74,    25,    25,    25,    26,    29,    34,
+      78,    79,    30,     1,     1,    45,    45,    54,    56,    60,
+      71,    65,    71,    30,    76,    30,    30,    30,    30,    30,
+      30,    78,    78,    31,    32,    76,    27,    33,    30,    30,
+       1,    12,    16,    18,    19,    20,    21,    22,    23,    25,
+      30,    40,    46,    47,    69,    70,    72,    17,    18,    19,
+      20,    30,    40,    55,    70,    72,    39,    52,    75,    39,
+      53,    58,    64,    75,    30,    40,    72,    39,    53,    63,
+      64,    75,    30,    28,    78,    78,    79,    79,    30,    30,
+      24,    74,    73,    74,    78,    25,    79,    48,     1,    13,
+      30,    74,    73,    25,    78,    14,    77,    30,    77,    77,
+      77,    79,    25,    30,    30,    77,    30,    77,    30,    78,
+      30,    30,    30,    77,    33,    49,    30,    30,    30,    74
+};
+
+#define yyerrok		(yyerrstatus = 0)
+#define yyclearin	(yychar = YYEMPTY)
+#define YYEMPTY		(-2)
+#define YYEOF		0
+
+#define YYACCEPT	goto yyacceptlab
+#define YYABORT		goto yyabortlab
+#define YYERROR		goto yyerrorlab
+
+
+/* Like YYERROR except do call yyerror.  This remains here temporarily
+   to ease the transition to the new meaning of YYERROR, for GCC.
+   Once GCC version 2 has supplanted version 1, this can go.  */
+
+#define YYFAIL		goto yyerrlab
+
+#define YYRECOVERING()  (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value)					\
+do								\
+  if (yychar == YYEMPTY && yylen == 1)				\
+    {								\
+      yychar = (Token);						\
+      yylval = (Value);						\
+      yytoken = YYTRANSLATE (yychar);				\
+      YYPOPSTACK (1);						\
+      goto yybackup;						\
+    }								\
+  else								\
+    {								\
+      yyerror (YY_("syntax error: cannot back up")); \
+      YYERROR;							\
+    }								\
+while (YYID (0))
+
+
+#define YYTERROR	1
+#define YYERRCODE	256
+
+
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+   If N is 0, then set CURRENT to the empty location which ends
+   the previous symbol: RHS[0] (always defined).  */
+
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+#ifndef YYLLOC_DEFAULT
+# define YYLLOC_DEFAULT(Current, Rhs, N)				\
+    do									\
+      if (YYID (N))                                                    \
+	{								\
+	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
+	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
+	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
+	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
+	}								\
+      else								\
+	{								\
+	  (Current).first_line   = (Current).last_line   =		\
+	    YYRHSLOC (Rhs, 0).last_line;				\
+	  (Current).first_column = (Current).last_column =		\
+	    YYRHSLOC (Rhs, 0).last_column;				\
+	}								\
+    while (YYID (0))
+#endif
+
+
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+   This macro was not mandated originally: define only if we know
+   we won't break user code: when these are the locations we know.  */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+#  define YY_LOCATION_PRINT(File, Loc)			\
+     fprintf (File, "%d.%d-%d.%d",			\
+	      (Loc).first_line, (Loc).first_column,	\
+	      (Loc).last_line,  (Loc).last_column)
+# else
+#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
+
+
+/* YYLEX -- calling `yylex' with the right arguments.  */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
+
+/* Enable debugging if requested.  */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args)			\
+do {						\
+  if (yydebug)					\
+    YYFPRINTF Args;				\
+} while (YYID (0))
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)			  \
+do {									  \
+  if (yydebug)								  \
+    {									  \
+      YYFPRINTF (stderr, "%s ", Title);					  \
+      yy_symbol_print (stderr,						  \
+		  Type, Value); \
+      YYFPRINTF (stderr, "\n");						  \
+    }									  \
+} while (YYID (0))
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_value_print (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE const * const yyvaluep;
+#endif
+{
+  if (!yyvaluep)
+    return;
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# else
+  YYUSE (yyoutput);
+# endif
+  switch (yytype)
+    {
+      default:
+	break;
+    }
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_print (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE const * const yyvaluep;
+#endif
+{
+  if (yytype < YYNTOKENS)
+    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+  else
+    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+  yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+  YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_stack_print (yytype_int16 *bottom, yytype_int16 *top)
+#else
+static void
+yy_stack_print (bottom, top)
+    yytype_int16 *bottom;
+    yytype_int16 *top;
+#endif
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (; bottom <= top; ++bottom)
+    YYFPRINTF (stderr, " %d", *bottom);
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)				\
+do {								\
+  if (yydebug)							\
+    yy_stack_print ((Bottom), (Top));				\
+} while (YYID (0))
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
+#else
+static void
+yy_reduce_print (yyvsp, yyrule)
+    YYSTYPE *yyvsp;
+    int yyrule;
+#endif
+{
+  int yynrhs = yyr2[yyrule];
+  int yyi;
+  unsigned long int yylno = yyrline[yyrule];
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+	     yyrule - 1, yylno);
+  /* The symbols being reduced.  */
+  for (yyi = 0; yyi < yynrhs; yyi++)
+    {
+      fprintf (stderr, "   $%d = ", yyi + 1);
+      yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
+		       &(yyvsp[(yyi + 1) - (yynrhs)])
+		       		       );
+      fprintf (stderr, "\n");
+    }
+}
+
+# define YY_REDUCE_PRINT(Rule)		\
+do {					\
+  if (yydebug)				\
+    yy_reduce_print (yyvsp, Rule); \
+} while (YYID (0))
+
+/* Nonzero means print parse trace.  It is left uninitialized so that
+   multiple parsers can coexist.  */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks.  */
+#ifndef	YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+   if the built-in stack extension method is used).
+
+   Do not make this value too large; the results are undefined if
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+   evaluated with infinite-precision integer arithmetic.  */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+#  if defined __GLIBC__ && defined _STRING_H
+#   define yystrlen strlen
+#  else
+/* Return the length of YYSTR.  */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static YYSIZE_T
+yystrlen (const char *yystr)
+#else
+static YYSIZE_T
+yystrlen (yystr)
+    const char *yystr;
+#endif
+{
+  YYSIZE_T yylen;
+  for (yylen = 0; yystr[yylen]; yylen++)
+    continue;
+  return yylen;
+}
+#  endif
+# endif
+
+# ifndef yystpcpy
+#  if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+#   define yystpcpy stpcpy
+#  else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+   YYDEST.  */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+#else
+static char *
+yystpcpy (yydest, yysrc)
+    char *yydest;
+    const char *yysrc;
+#endif
+{
+  char *yyd = yydest;
+  const char *yys = yysrc;
+
+  while ((*yyd++ = *yys++) != '\0')
+    continue;
+
+  return yyd - 1;
+}
+#  endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      YYSIZE_T yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+	switch (*++yyp)
+	  {
+	  case '\'':
+	  case ',':
+	    goto do_not_strip_quotes;
+
+	  case '\\':
+	    if (*++yyp != '\\')
+	      goto do_not_strip_quotes;
+	    /* Fall through.  */
+	  default:
+	    if (yyres)
+	      yyres[yyn] = *yyp;
+	    yyn++;
+	    break;
+
+	  case '"':
+	    if (yyres)
+	      yyres[yyn] = '\0';
+	    return yyn;
+	  }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into YYRESULT an error message about the unexpected token
+   YYCHAR while in state YYSTATE.  Return the number of bytes copied,
+   including the terminating null byte.  If YYRESULT is null, do not
+   copy anything; just return the number of bytes that would be
+   copied.  As a special case, return 0 if an ordinary "syntax error"
+   message will do.  Return YYSIZE_MAXIMUM if overflow occurs during
+   size calculation.  */
+static YYSIZE_T
+yysyntax_error (char *yyresult, int yystate, int yychar)
+{
+  int yyn = yypact[yystate];
+
+  if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
+    return 0;
+  else
+    {
+      int yytype = YYTRANSLATE (yychar);
+      YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+      YYSIZE_T yysize = yysize0;
+      YYSIZE_T yysize1;
+      int yysize_overflow = 0;
+      enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+      char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+      int yyx;
+
+# if 0
+      /* This is so xgettext sees the translatable formats that are
+	 constructed on the fly.  */
+      YY_("syntax error, unexpected %s");
+      YY_("syntax error, unexpected %s, expecting %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+# endif
+      char *yyfmt;
+      char const *yyf;
+      static char const yyunexpected[] = "syntax error, unexpected %s";
+      static char const yyexpecting[] = ", expecting %s";
+      static char const yyor[] = " or %s";
+      char yyformat[sizeof yyunexpected
+		    + sizeof yyexpecting - 1
+		    + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+		       * (sizeof yyor - 1))];
+      char const *yyprefix = yyexpecting;
+
+      /* Start YYX at -YYN if negative to avoid negative indexes in
+	 YYCHECK.  */
+      int yyxbegin = yyn < 0 ? -yyn : 0;
+
+      /* Stay within bounds of both yycheck and yytname.  */
+      int yychecklim = YYLAST - yyn + 1;
+      int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+      int yycount = 1;
+
+      yyarg[0] = yytname[yytype];
+      yyfmt = yystpcpy (yyformat, yyunexpected);
+
+      for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+	if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+	  {
+	    if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+	      {
+		yycount = 1;
+		yysize = yysize0;
+		yyformat[sizeof yyunexpected - 1] = '\0';
+		break;
+	      }
+	    yyarg[yycount++] = yytname[yyx];
+	    yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+	    yysize_overflow |= (yysize1 < yysize);
+	    yysize = yysize1;
+	    yyfmt = yystpcpy (yyfmt, yyprefix);
+	    yyprefix = yyor;
+	  }
+
+      yyf = YY_(yyformat);
+      yysize1 = yysize + yystrlen (yyf);
+      yysize_overflow |= (yysize1 < yysize);
+      yysize = yysize1;
+
+      if (yysize_overflow)
+	return YYSIZE_MAXIMUM;
+
+      if (yyresult)
+	{
+	  /* Avoid sprintf, as that infringes on the user's name space.
+	     Don't have undefined behavior even if the translation
+	     produced a string with the wrong number of "%s"s.  */
+	  char *yyp = yyresult;
+	  int yyi = 0;
+	  while ((*yyp = *yyf) != '\0')
+	    {
+	      if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+		{
+		  yyp += yytnamerr (yyp, yyarg[yyi++]);
+		  yyf += 2;
+		}
+	      else
+		{
+		  yyp++;
+		  yyf++;
+		}
+	    }
+	}
+      return yysize;
+    }
+}
+#endif /* YYERROR_VERBOSE */
+
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+    const char *yymsg;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  YYUSE (yyvaluep);
+
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  switch (yytype)
+    {
+      case 51: /* "choice_entry" */
+
+	{
+	fprintf(stderr, "%s:%d: missing end statement for this entry\n",
+		(yyvaluep->menu)->file->name, (yyvaluep->menu)->lineno);
+	if (current_menu == (yyvaluep->menu))
+		menu_end_menu();
+};
+
+	break;
+      case 57: /* "if_entry" */
+
+	{
+	fprintf(stderr, "%s:%d: missing end statement for this entry\n",
+		(yyvaluep->menu)->file->name, (yyvaluep->menu)->lineno);
+	if (current_menu == (yyvaluep->menu))
+		menu_end_menu();
+};
+
+	break;
+      case 62: /* "menu_entry" */
+
+	{
+	fprintf(stderr, "%s:%d: missing end statement for this entry\n",
+		(yyvaluep->menu)->file->name, (yyvaluep->menu)->lineno);
+	if (current_menu == (yyvaluep->menu))
+		menu_end_menu();
+};
+
+	break;
+
+      default:
+	break;
+    }
+}
+
+
+/* Prevent warnings from -Wmissing-prototypes.  */
+
+#ifdef YYPARSE_PARAM
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void *YYPARSE_PARAM);
+#else
+int yyparse ();
+#endif
+#else /* ! YYPARSE_PARAM */
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void);
+#else
+int yyparse ();
+#endif
+#endif /* ! YYPARSE_PARAM */
+
+
+
+/* The look-ahead symbol.  */
+int yychar;
+
+/* The semantic value of the look-ahead symbol.  */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far.  */
+int yynerrs;
+
+
+
+/*----------.
+| yyparse.  |
+`----------*/
+
+#ifdef YYPARSE_PARAM
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void *YYPARSE_PARAM)
+#else
+int
+yyparse (YYPARSE_PARAM)
+    void *YYPARSE_PARAM;
+#endif
+#else /* ! YYPARSE_PARAM */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void)
+#else
+int
+yyparse ()
+
+#endif
+#endif
+{
+  
+  int yystate;
+  int yyn;
+  int yyresult;
+  /* Number of tokens to shift before error messages enabled.  */
+  int yyerrstatus;
+  /* Look-ahead token as an internal (translated) token number.  */
+  int yytoken = 0;
+#if YYERROR_VERBOSE
+  /* Buffer for error messages, and its allocated size.  */
+  char yymsgbuf[128];
+  char *yymsg = yymsgbuf;
+  YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+  /* Three stacks and their tools:
+     `yyss': related to states,
+     `yyvs': related to semantic values,
+     `yyls': related to locations.
+
+     Refer to the stacks thru separate pointers, to allow yyoverflow
+     to reallocate them elsewhere.  */
+
+  /* The state stack.  */
+  yytype_int16 yyssa[YYINITDEPTH];
+  yytype_int16 *yyss = yyssa;
+  yytype_int16 *yyssp;
+
+  /* The semantic value stack.  */
+  YYSTYPE yyvsa[YYINITDEPTH];
+  YYSTYPE *yyvs = yyvsa;
+  YYSTYPE *yyvsp;
+
+
+
+#define YYPOPSTACK(N)   (yyvsp -= (N), yyssp -= (N))
+
+  YYSIZE_T yystacksize = YYINITDEPTH;
+
+  /* The variables used to return semantic value and location from the
+     action routines.  */
+  YYSTYPE yyval;
+
+
+  /* The number of symbols on the RHS of the reduced rule.
+     Keep to zero when no symbol should be popped.  */
+  int yylen = 0;
+
+  YYDPRINTF ((stderr, "Starting parse\n"));
+
+  yystate = 0;
+  yyerrstatus = 0;
+  yynerrs = 0;
+  yychar = YYEMPTY;		/* Cause a token to be read.  */
+
+  /* Initialize stack pointers.
+     Waste one element of value and location stack
+     so that they stay on the same level as the state stack.
+     The wasted elements are never initialized.  */
+
+  yyssp = yyss;
+  yyvsp = yyvs;
+
+  goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate.  |
+`------------------------------------------------------------*/
+ yynewstate:
+  /* In all cases, when you get here, the value and location stacks
+     have just been pushed.  So pushing a state here evens the stacks.  */
+  yyssp++;
+
+ yysetstate:
+  *yyssp = yystate;
+
+  if (yyss + yystacksize - 1 <= yyssp)
+    {
+      /* Get the current used size of the three stacks, in elements.  */
+      YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+      {
+	/* Give user a chance to reallocate the stack.  Use copies of
+	   these so that the &'s don't force the real ones into
+	   memory.  */
+	YYSTYPE *yyvs1 = yyvs;
+	yytype_int16 *yyss1 = yyss;
+
+
+	/* Each stack pointer address is followed by the size of the
+	   data in use in that stack, in bytes.  This used to be a
+	   conditional around just the two extra args, but that might
+	   be undefined if yyoverflow is a macro.  */
+	yyoverflow (YY_("memory exhausted"),
+		    &yyss1, yysize * sizeof (*yyssp),
+		    &yyvs1, yysize * sizeof (*yyvsp),
+
+		    &yystacksize);
+
+	yyss = yyss1;
+	yyvs = yyvs1;
+      }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+      goto yyexhaustedlab;
+# else
+      /* Extend the stack our own way.  */
+      if (YYMAXDEPTH <= yystacksize)
+	goto yyexhaustedlab;
+      yystacksize *= 2;
+      if (YYMAXDEPTH < yystacksize)
+	yystacksize = YYMAXDEPTH;
+
+      {
+	yytype_int16 *yyss1 = yyss;
+	union yyalloc *yyptr =
+	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+	if (! yyptr)
+	  goto yyexhaustedlab;
+	YYSTACK_RELOCATE (yyss);
+	YYSTACK_RELOCATE (yyvs);
+
+#  undef YYSTACK_RELOCATE
+	if (yyss1 != yyssa)
+	  YYSTACK_FREE (yyss1);
+      }
+# endif
+#endif /* no yyoverflow */
+
+      yyssp = yyss + yysize - 1;
+      yyvsp = yyvs + yysize - 1;
+
+
+      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+		  (unsigned long int) yystacksize));
+
+      if (yyss + yystacksize - 1 <= yyssp)
+	YYABORT;
+    }
+
+  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+  goto yybackup;
+
+/*-----------.
+| yybackup.  |
+`-----------*/
+yybackup:
+
+  /* Do appropriate processing given the current state.  Read a
+     look-ahead token if we need one and don't already have one.  */
+
+  /* First try to decide what to do without reference to look-ahead token.  */
+  yyn = yypact[yystate];
+  if (yyn == YYPACT_NINF)
+    goto yydefault;
+
+  /* Not known => get a look-ahead token if don't already have one.  */
+
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
+  if (yychar == YYEMPTY)
+    {
+      YYDPRINTF ((stderr, "Reading a token: "));
+      yychar = YYLEX;
+    }
+
+  if (yychar <= YYEOF)
+    {
+      yychar = yytoken = YYEOF;
+      YYDPRINTF ((stderr, "Now at end of input.\n"));
+    }
+  else
+    {
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+    }
+
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+    goto yydefault;
+  yyn = yytable[yyn];
+  if (yyn <= 0)
+    {
+      if (yyn == 0 || yyn == YYTABLE_NINF)
+	goto yyerrlab;
+      yyn = -yyn;
+      goto yyreduce;
+    }
+
+  if (yyn == YYFINAL)
+    YYACCEPT;
+
+  /* Count tokens shifted since error; after three, turn off error
+     status.  */
+  if (yyerrstatus)
+    yyerrstatus--;
+
+  /* Shift the look-ahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+  /* Discard the shifted token unless it is eof.  */
+  if (yychar != YYEOF)
+    yychar = YYEMPTY;
+
+  yystate = yyn;
+  *++yyvsp = yylval;
+
+  goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state.  |
+`-----------------------------------------------------------*/
+yydefault:
+  yyn = yydefact[yystate];
+  if (yyn == 0)
+    goto yyerrlab;
+  goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction.  |
+`-----------------------------*/
+yyreduce:
+  /* yyn is the number of a rule to reduce with.  */
+  yylen = yyr2[yyn];
+
+  /* If YYLEN is nonzero, implement the default value of the action:
+     `$$ = $1'.
+
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
+     users should not rely upon it.  Assigning to YYVAL
+     unconditionally makes the parser a bit smaller, and it avoids a
+     GCC warning that YYVAL may be used uninitialized.  */
+  yyval = yyvsp[1-yylen];
+
+
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 8:
+
+    { zconf_error("unexpected end statement"); ;}
+    break;
+
+  case 9:
+
+    { zconf_error("unknown statement \"%s\"", (yyvsp[(2) - (4)].string)); ;}
+    break;
+
+  case 10:
+
+    {
+	zconf_error("unexpected option \"%s\"", kconf_id_strings + (yyvsp[(2) - (4)].id)->name);
+;}
+    break;
+
+  case 11:
+
+    { zconf_error("invalid statement"); ;}
+    break;
+
+  case 25:
+
+    { zconf_error("unknown option \"%s\"", (yyvsp[(1) - (3)].string)); ;}
+    break;
+
+  case 26:
+
+    { zconf_error("invalid option"); ;}
+    break;
+
+  case 27:
+
+    {
+	struct symbol *sym = sym_lookup((yyvsp[(2) - (3)].string), 0);
+	sym->flags |= SYMBOL_OPTIONAL;
+	menu_add_entry(sym);
+	printd(DEBUG_PARSE, "%s:%d:config %s\n", zconf_curname(), zconf_lineno(), (yyvsp[(2) - (3)].string));
+;}
+    break;
+
+  case 28:
+
+    {
+	menu_end_entry();
+	printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 29:
+
+    {
+	struct symbol *sym = sym_lookup((yyvsp[(2) - (3)].string), 0);
+	sym->flags |= SYMBOL_OPTIONAL;
+	menu_add_entry(sym);
+	printd(DEBUG_PARSE, "%s:%d:menuconfig %s\n", zconf_curname(), zconf_lineno(), (yyvsp[(2) - (3)].string));
+;}
+    break;
+
+  case 30:
+
+    {
+	if (current_entry->prompt)
+		current_entry->prompt->type = P_MENU;
+	else
+		zconfprint("warning: menuconfig statement without prompt");
+	menu_end_entry();
+	printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 38:
+
+    {
+	menu_set_type((yyvsp[(1) - (3)].id)->stype);
+	printd(DEBUG_PARSE, "%s:%d:type(%u)\n",
+		zconf_curname(), zconf_lineno(),
+		(yyvsp[(1) - (3)].id)->stype);
+;}
+    break;
+
+  case 39:
+
+    {
+	menu_add_prompt(P_PROMPT, (yyvsp[(2) - (4)].string), (yyvsp[(3) - (4)].expr));
+	printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 40:
+
+    {
+	menu_add_expr(P_DEFAULT, (yyvsp[(2) - (4)].expr), (yyvsp[(3) - (4)].expr));
+	if ((yyvsp[(1) - (4)].id)->stype != S_UNKNOWN)
+		menu_set_type((yyvsp[(1) - (4)].id)->stype);
+	printd(DEBUG_PARSE, "%s:%d:default(%u)\n",
+		zconf_curname(), zconf_lineno(),
+		(yyvsp[(1) - (4)].id)->stype);
+;}
+    break;
+
+  case 41:
+
+    {
+	menu_add_symbol(P_SELECT, sym_lookup((yyvsp[(2) - (4)].string), 0), (yyvsp[(3) - (4)].expr));
+	printd(DEBUG_PARSE, "%s:%d:select\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 42:
+
+    {
+	menu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,(yyvsp[(2) - (5)].symbol), (yyvsp[(3) - (5)].symbol)), (yyvsp[(4) - (5)].expr));
+	printd(DEBUG_PARSE, "%s:%d:range\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 45:
+
+    {
+	struct kconf_id *id = kconf_id_lookup((yyvsp[(2) - (3)].string), strlen((yyvsp[(2) - (3)].string)));
+	if (id && id->flags & TF_OPTION)
+		menu_add_option(id->token, (yyvsp[(3) - (3)].string));
+	else
+		zconfprint("warning: ignoring unknown option %s", (yyvsp[(2) - (3)].string));
+	free((yyvsp[(2) - (3)].string));
+;}
+    break;
+
+  case 46:
+
+    { (yyval.string) = NULL; ;}
+    break;
+
+  case 47:
+
+    { (yyval.string) = (yyvsp[(2) - (2)].string); ;}
+    break;
+
+  case 48:
+
+    {
+	struct symbol *sym = sym_lookup((yyvsp[(2) - (3)].string), SYMBOL_CHOICE);
+	sym->flags |= SYMBOL_AUTO;
+	menu_add_entry(sym);
+	menu_add_expr(P_CHOICE, NULL, NULL);
+	printd(DEBUG_PARSE, "%s:%d:choice\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 49:
+
+    {
+	(yyval.menu) = menu_add_menu();
+;}
+    break;
+
+  case 50:
+
+    {
+	if (zconf_endtoken((yyvsp[(1) - (1)].id), T_CHOICE, T_ENDCHOICE)) {
+		menu_end_menu();
+		printd(DEBUG_PARSE, "%s:%d:endchoice\n", zconf_curname(), zconf_lineno());
+	}
+;}
+    break;
+
+  case 58:
+
+    {
+	menu_add_prompt(P_PROMPT, (yyvsp[(2) - (4)].string), (yyvsp[(3) - (4)].expr));
+	printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 59:
+
+    {
+	if ((yyvsp[(1) - (3)].id)->stype == S_BOOLEAN || (yyvsp[(1) - (3)].id)->stype == S_TRISTATE) {
+		menu_set_type((yyvsp[(1) - (3)].id)->stype);
+		printd(DEBUG_PARSE, "%s:%d:type(%u)\n",
+			zconf_curname(), zconf_lineno(),
+			(yyvsp[(1) - (3)].id)->stype);
+	} else
+		YYERROR;
+;}
+    break;
+
+  case 60:
+
+    {
+	current_entry->sym->flags |= SYMBOL_OPTIONAL;
+	printd(DEBUG_PARSE, "%s:%d:optional\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 61:
+
+    {
+	if ((yyvsp[(1) - (4)].id)->stype == S_UNKNOWN) {
+		menu_add_symbol(P_DEFAULT, sym_lookup((yyvsp[(2) - (4)].string), 0), (yyvsp[(3) - (4)].expr));
+		printd(DEBUG_PARSE, "%s:%d:default\n",
+			zconf_curname(), zconf_lineno());
+	} else
+		YYERROR;
+;}
+    break;
+
+  case 64:
+
+    {
+	printd(DEBUG_PARSE, "%s:%d:if\n", zconf_curname(), zconf_lineno());
+	menu_add_entry(NULL);
+	menu_add_dep((yyvsp[(2) - (3)].expr));
+	(yyval.menu) = menu_add_menu();
+;}
+    break;
+
+  case 65:
+
+    {
+	if (zconf_endtoken((yyvsp[(1) - (1)].id), T_IF, T_ENDIF)) {
+		menu_end_menu();
+		printd(DEBUG_PARSE, "%s:%d:endif\n", zconf_curname(), zconf_lineno());
+	}
+;}
+    break;
+
+  case 71:
+
+    {
+	menu_add_entry(NULL);
+	menu_add_prompt(P_MENU, (yyvsp[(2) - (3)].string), NULL);
+	printd(DEBUG_PARSE, "%s:%d:menu\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 72:
+
+    {
+	(yyval.menu) = menu_add_menu();
+;}
+    break;
+
+  case 73:
+
+    {
+	if (zconf_endtoken((yyvsp[(1) - (1)].id), T_MENU, T_ENDMENU)) {
+		menu_end_menu();
+		printd(DEBUG_PARSE, "%s:%d:endmenu\n", zconf_curname(), zconf_lineno());
+	}
+;}
+    break;
+
+  case 79:
+
+    {
+	printd(DEBUG_PARSE, "%s:%d:source %s\n", zconf_curname(), zconf_lineno(), (yyvsp[(2) - (3)].string));
+	zconf_nextfile((yyvsp[(2) - (3)].string));
+;}
+    break;
+
+  case 80:
+
+    {
+	menu_add_entry(NULL);
+	menu_add_prompt(P_COMMENT, (yyvsp[(2) - (3)].string), NULL);
+	printd(DEBUG_PARSE, "%s:%d:comment\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 81:
+
+    {
+	menu_end_entry();
+;}
+    break;
+
+  case 82:
+
+    {
+	printd(DEBUG_PARSE, "%s:%d:help\n", zconf_curname(), zconf_lineno());
+	zconf_starthelp();
+;}
+    break;
+
+  case 83:
+
+    {
+	current_entry->help = (yyvsp[(2) - (2)].string);
+;}
+    break;
+
+  case 88:
+
+    {
+	menu_add_dep((yyvsp[(3) - (4)].expr));
+	printd(DEBUG_PARSE, "%s:%d:depends on\n", zconf_curname(), zconf_lineno());
+;}
+    break;
+
+  case 90:
+
+    {
+	menu_add_prompt(P_PROMPT, (yyvsp[(1) - (2)].string), (yyvsp[(2) - (2)].expr));
+;}
+    break;
+
+  case 93:
+
+    { (yyval.id) = (yyvsp[(1) - (2)].id); ;}
+    break;
+
+  case 94:
+
+    { (yyval.id) = (yyvsp[(1) - (2)].id); ;}
+    break;
+
+  case 95:
+
+    { (yyval.id) = (yyvsp[(1) - (2)].id); ;}
+    break;
+
+  case 98:
+
+    { (yyval.expr) = NULL; ;}
+    break;
+
+  case 99:
+
+    { (yyval.expr) = (yyvsp[(2) - (2)].expr); ;}
+    break;
+
+  case 100:
+
+    { (yyval.expr) = expr_alloc_symbol((yyvsp[(1) - (1)].symbol)); ;}
+    break;
+
+  case 101:
+
+    { (yyval.expr) = expr_alloc_comp(E_EQUAL, (yyvsp[(1) - (3)].symbol), (yyvsp[(3) - (3)].symbol)); ;}
+    break;
+
+  case 102:
+
+    { (yyval.expr) = expr_alloc_comp(E_UNEQUAL, (yyvsp[(1) - (3)].symbol), (yyvsp[(3) - (3)].symbol)); ;}
+    break;
+
+  case 103:
+
+    { (yyval.expr) = (yyvsp[(2) - (3)].expr); ;}
+    break;
+
+  case 104:
+
+    { (yyval.expr) = expr_alloc_one(E_NOT, (yyvsp[(2) - (2)].expr)); ;}
+    break;
+
+  case 105:
+
+    { (yyval.expr) = expr_alloc_two(E_OR, (yyvsp[(1) - (3)].expr), (yyvsp[(3) - (3)].expr)); ;}
+    break;
+
+  case 106:
+
+    { (yyval.expr) = expr_alloc_two(E_AND, (yyvsp[(1) - (3)].expr), (yyvsp[(3) - (3)].expr)); ;}
+    break;
+
+  case 107:
+
+    { (yyval.symbol) = sym_lookup((yyvsp[(1) - (1)].string), 0); free((yyvsp[(1) - (1)].string)); ;}
+    break;
+
+  case 108:
+
+    { (yyval.symbol) = sym_lookup((yyvsp[(1) - (1)].string), SYMBOL_CONST); free((yyvsp[(1) - (1)].string)); ;}
+    break;
+
+  case 109:
+
+    { (yyval.string) = NULL; ;}
+    break;
+
+
+/* Line 1267 of yacc.c.  */
+
+      default: break;
+    }
+  YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+
+  *++yyvsp = yyval;
+
+
+  /* Now `shift' the result of the reduction.  Determine what state
+     that goes to, based on the state we popped back to and the rule
+     number reduced by.  */
+
+  yyn = yyr1[yyn];
+
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+    yystate = yytable[yystate];
+  else
+    yystate = yydefgoto[yyn - YYNTOKENS];
+
+  goto yynewstate;
+
+
+/*------------------------------------.
+| yyerrlab -- here on detecting error |
+`------------------------------------*/
+yyerrlab:
+  /* If not already recovering from an error, report this error.  */
+  if (!yyerrstatus)
+    {
+      ++yynerrs;
+#if ! YYERROR_VERBOSE
+      yyerror (YY_("syntax error"));
+#else
+      {
+	YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
+	if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
+	  {
+	    YYSIZE_T yyalloc = 2 * yysize;
+	    if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
+	      yyalloc = YYSTACK_ALLOC_MAXIMUM;
+	    if (yymsg != yymsgbuf)
+	      YYSTACK_FREE (yymsg);
+	    yymsg = (char *) YYSTACK_ALLOC (yyalloc);
+	    if (yymsg)
+	      yymsg_alloc = yyalloc;
+	    else
+	      {
+		yymsg = yymsgbuf;
+		yymsg_alloc = sizeof yymsgbuf;
+	      }
+	  }
+
+	if (0 < yysize && yysize <= yymsg_alloc)
+	  {
+	    (void) yysyntax_error (yymsg, yystate, yychar);
+	    yyerror (yymsg);
+	  }
+	else
+	  {
+	    yyerror (YY_("syntax error"));
+	    if (yysize != 0)
+	      goto yyexhaustedlab;
+	  }
+      }
+#endif
+    }
+
+
+
+  if (yyerrstatus == 3)
+    {
+      /* If just tried and failed to reuse look-ahead token after an
+	 error, discard it.  */
+
+      if (yychar <= YYEOF)
+	{
+	  /* Return failure if at end of input.  */
+	  if (yychar == YYEOF)
+	    YYABORT;
+	}
+      else
+	{
+	  yydestruct ("Error: discarding",
+		      yytoken, &yylval);
+	  yychar = YYEMPTY;
+	}
+    }
+
+  /* Else will try to reuse look-ahead token after shifting the error
+     token.  */
+  goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
+
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (/*CONSTCOND*/ 0)
+     goto yyerrorlab;
+
+  /* Do not reclaim the symbols of the rule which action triggered
+     this YYERROR.  */
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+  yystate = *yyssp;
+  goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
+
+  for (;;)
+    {
+      yyn = yypact[yystate];
+      if (yyn != YYPACT_NINF)
+	{
+	  yyn += YYTERROR;
+	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+	    {
+	      yyn = yytable[yyn];
+	      if (0 < yyn)
+		break;
+	    }
+	}
+
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+	YYABORT;
+
+
+      yydestruct ("Error: popping",
+		  yystos[yystate], yyvsp);
+      YYPOPSTACK (1);
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
+    }
+
+  if (yyn == YYFINAL)
+    YYACCEPT;
+
+  *++yyvsp = yylval;
+
+
+  /* Shift the error token.  */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+  yystate = yyn;
+  goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here.  |
+`-------------------------------------*/
+yyacceptlab:
+  yyresult = 0;
+  goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here.  |
+`-----------------------------------*/
+yyabortlab:
+  yyresult = 1;
+  goto yyreturn;
+
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
+  yyresult = 2;
+  /* Fall through.  */
+#endif
+
+yyreturn:
+  if (yychar != YYEOF && yychar != YYEMPTY)
+     yydestruct ("Cleanup: discarding lookahead",
+		 yytoken, &yylval);
+  /* Do not reclaim the symbols of the rule which action triggered
+     this YYABORT or YYACCEPT.  */
+  YYPOPSTACK (yylen);
+  YY_STACK_PRINT (yyss, yyssp);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+		  yystos[*yyssp], yyvsp);
+      YYPOPSTACK (1);
+    }
+#ifndef yyoverflow
+  if (yyss != yyssa)
+    YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+  if (yymsg != yymsgbuf)
+    YYSTACK_FREE (yymsg);
+#endif
+  /* Make sure YYID is used.  */
+  return YYID (yyresult);
+}
+
+
+
+
+
+void conf_parse(const char *name)
+{
+	struct symbol *sym;
+	int i;
+
+	zconf_initscan(name);
+
+	sym_init();
+	menu_init();
+	modules_sym = sym_lookup(NULL, 0);
+	modules_sym->type = S_BOOLEAN;
+	modules_sym->flags |= SYMBOL_AUTO;
+	rootmenu.prompt = menu_add_prompt(P_MENU, "Linux Kernel Configuration", NULL);
+
+#if YYDEBUG
+	if (getenv("ZCONF_DEBUG"))
+		zconfdebug = 1;
+#endif
+	zconfparse();
+	if (zconfnerrs)
+		exit(1);
+	if (!modules_sym->prop) {
+		struct property *prop;
+
+		prop = prop_alloc(P_DEFAULT, modules_sym);
+		prop->expr = expr_alloc_symbol(sym_lookup("MODULES", 0));
+	}
+	menu_finalize(&rootmenu);
+	for_all_symbols(i, sym) {
+		if (sym_check_deps(sym))
+			zconfnerrs++;
+        }
+	if (zconfnerrs)
+		exit(1);
+	sym_set_change_count(1);
+}
+
+const char *zconf_tokenname(int token)
+{
+	switch (token) {
+	case T_MENU:		return "menu";
+	case T_ENDMENU:		return "endmenu";
+	case T_CHOICE:		return "choice";
+	case T_ENDCHOICE:	return "endchoice";
+	case T_IF:		return "if";
+	case T_ENDIF:		return "endif";
+	case T_DEPENDS:		return "depends";
+	}
+	return "<token>";
+}
+
+static bool zconf_endtoken(struct kconf_id *id, int starttoken, int endtoken)
+{
+	if (id->token != endtoken) {
+		zconf_error("unexpected '%s' within %s block",
+			kconf_id_strings + id->name, zconf_tokenname(starttoken));
+		zconfnerrs++;
+		return false;
+	}
+	if (current_menu->file != current_file) {
+		zconf_error("'%s' in different file than '%s'",
+			kconf_id_strings + id->name, zconf_tokenname(starttoken));
+		fprintf(stderr, "%s:%d: location of the '%s'\n",
+			current_menu->file->name, current_menu->lineno,
+			zconf_tokenname(starttoken));
+		zconfnerrs++;
+		return false;
+	}
+	return true;
+}
+
+static void zconfprint(const char *err, ...)
+{
+	va_list ap;
+
+	fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno());
+	va_start(ap, err);
+	vfprintf(stderr, err, ap);
+	va_end(ap);
+	fprintf(stderr, "\n");
+}
+
+static void zconf_error(const char *err, ...)
+{
+	va_list ap;
+
+	zconfnerrs++;
+	fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno());
+	va_start(ap, err);
+	vfprintf(stderr, err, ap);
+	va_end(ap);
+	fprintf(stderr, "\n");
+}
+
+static void zconferror(const char *err)
+{
+#if YYDEBUG
+	fprintf(stderr, "%s:%d: %s\n", zconf_curname(), zconf_lineno() + 1, err);
+#endif
+}
+
+void print_quoted_string(FILE *out, const char *str)
+{
+	const char *p;
+	int len;
+
+	putc('"', out);
+	while ((p = strchr(str, '"'))) {
+		len = p - str;
+		if (len)
+			fprintf(out, "%.*s", len, str);
+		fputs("\\\"", out);
+		str = p + 1;
+	}
+	fputs(str, out);
+	putc('"', out);
+}
+
+void print_symbol(FILE *out, struct menu *menu)
+{
+	struct symbol *sym = menu->sym;
+	struct property *prop;
+
+	if (sym_is_choice(sym))
+		fprintf(out, "choice\n");
+	else
+		fprintf(out, "config %s\n", sym->name);
+	switch (sym->type) {
+	case S_BOOLEAN:
+		fputs("  boolean\n", out);
+		break;
+	case S_TRISTATE:
+		fputs("  tristate\n", out);
+		break;
+	case S_STRING:
+		fputs("  string\n", out);
+		break;
+	case S_INT:
+		fputs("  integer\n", out);
+		break;
+	case S_HEX:
+		fputs("  hex\n", out);
+		break;
+	default:
+		fputs("  ???\n", out);
+		break;
+	}
+	for (prop = sym->prop; prop; prop = prop->next) {
+		if (prop->menu != menu)
+			continue;
+		switch (prop->type) {
+		case P_PROMPT:
+			fputs("  prompt ", out);
+			print_quoted_string(out, prop->text);
+			if (!expr_is_yes(prop->visible.expr)) {
+				fputs(" if ", out);
+				expr_fprint(prop->visible.expr, out);
+			}
+			fputc('\n', out);
+			break;
+		case P_DEFAULT:
+			fputs( "  default ", out);
+			expr_fprint(prop->expr, out);
+			if (!expr_is_yes(prop->visible.expr)) {
+				fputs(" if ", out);
+				expr_fprint(prop->visible.expr, out);
+			}
+			fputc('\n', out);
+			break;
+		case P_CHOICE:
+			fputs("  #choice value\n", out);
+			break;
+		default:
+			fprintf(out, "  unknown prop %d!\n", prop->type);
+			break;
+		}
+	}
+	if (menu->help) {
+		int len = strlen(menu->help);
+		while (menu->help[--len] == '\n')
+			menu->help[len] = 0;
+		fprintf(out, "  help\n%s\n", menu->help);
+	}
+	fputc('\n', out);
+}
+
+void zconfdump(FILE *out)
+{
+	struct property *prop;
+	struct symbol *sym;
+	struct menu *menu;
+
+	menu = rootmenu.list;
+	while (menu) {
+		if ((sym = menu->sym))
+			print_symbol(out, menu);
+		else if ((prop = menu->prompt)) {
+			switch (prop->type) {
+			case P_COMMENT:
+				fputs("\ncomment ", out);
+				print_quoted_string(out, prop->text);
+				fputs("\n", out);
+				break;
+			case P_MENU:
+				fputs("\nmenu ", out);
+				print_quoted_string(out, prop->text);
+				fputs("\n", out);
+				break;
+			default:
+				;
+			}
+			if (!expr_is_yes(prop->visible.expr)) {
+				fputs("  depends ", out);
+				expr_fprint(prop->visible.expr, out);
+				fputc('\n', out);
+			}
+			fputs("\n", out);
+		}
+
+		if (menu->list)
+			menu = menu->list;
+		else if (menu->next)
+			menu = menu->next;
+		else while ((menu = menu->parent)) {
+			if (menu->prompt && menu->prompt->type == P_MENU)
+				fputs("\nendmenu\n", out);
+			if (menu->next) {
+				menu = menu->next;
+				break;
+			}
+		}
+	}
+}
+
+#include "lex.zconf.c"
+#include "util.c"
+#include "confdata.c"
+#include "expr.c"
+#include "symbol.c"
+#include "menu.c"
+
diff -uNra linux-2.6.27.6/scripts/Makefile.modpost linux-2.6.27.6.yaffs/scripts/Makefile.modpost
--- linux-2.6.27.6/scripts/Makefile.modpost	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/Makefile.modpost	2011-05-08 18:02:53.000000000 +0800
@@ -100,9 +100,9 @@
 quiet_cmd_kernel-mod = MODPOST $@
       cmd_kernel-mod = $(modpost) $@
 
-vmlinux.o: FORCE
-	@rm -fr $(kernelmarkersfile)
-	$(call cmd,kernel-mod)
+#vmlinux.o: FORCE
+#	@rm -fr $(kernelmarkersfile)
+#	$(call cmd,kernel-mod)
 
 # Declare generated files as targets for modpost
 $(symverfile):         __modpost ;
diff -uNra linux-2.6.27.6/scripts/mod/elfconfig.h linux-2.6.27.6.yaffs/scripts/mod/elfconfig.h
--- linux-2.6.27.6/scripts/mod/elfconfig.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/scripts/mod/elfconfig.h	2012-03-14 10:53:32.000000000 +0800
@@ -0,0 +1,5 @@
+#define KERNEL_ELFCLASS ELFCLASS64
+#define KERNEL_ELFDATA ELFDATA2LSB
+#define HOST_ELFCLASS ELFCLASS32
+#define HOST_ELFDATA ELFDATA2LSB
+#define MODULE_SYMBOL_PREFIX ""
diff -uNra linux-2.6.27.6/scripts/mod/mk_elfconfig linux-2.6.27.6.yaffs/scripts/mod/mk_elfconfig
\ 文件尾没有 newline 字符
diff -uNra linux-2.6.27.6/scripts/mod/modpost linux-2.6.27.6.yaffs/scripts/mod/modpost
\ 文件尾没有 newline 字符
diff -uNra linux-2.6.27.6/scripts/pnmtologo linux-2.6.27.6.yaffs/scripts/pnmtologo
\ 文件尾没有 newline 字符
diff -uNra linux-2.6.27.6/sound/core/pcm_native.c linux-2.6.27.6.yaffs/sound/core/pcm_native.c
--- linux-2.6.27.6/sound/core/pcm_native.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/core/pcm_native.c	2011-05-08 18:06:17.000000000 +0800
@@ -3107,7 +3107,12 @@
 			return VM_FAULT_SIGBUS;
 	} else {
 		vaddr = runtime->dma_area + offset;
+//#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+#if 0 //mj change
+		page = virt_to_page(CAC_ADDR(vaddr));
+#else
 		page = virt_to_page(vaddr);
+#endif
 	}
 	get_page(page);
 	vmf->page = page;
@@ -3222,6 +3227,13 @@
 	substream = pcm_file->substream;
 	snd_assert(substream != NULL, return -ENXIO);
 
+//#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)	
+#if 0
+	/* all mmap using uncached mode */
+	area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
+	area->vm_flags |= ( VM_RESERVED | VM_IO);
+#endif
+
 	offset = area->vm_pgoff << PAGE_SHIFT;
 	switch (offset) {
 	case SNDRV_PCM_MMAP_OFFSET_STATUS:
diff -uNra linux-2.6.27.6/sound/core/sgbuf.c linux-2.6.27.6.yaffs/sound/core/sgbuf.c
--- linux-2.6.27.6/sound/core/sgbuf.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/core/sgbuf.c	2011-05-08 18:06:17.000000000 +0800
@@ -91,12 +91,22 @@
 		}
 		sgbuf->table[i].buf = tmpb.area;
 		sgbuf->table[i].addr = tmpb.addr;
+//#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+#if 0 //mj change
+		sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area));
+#else
 		sgbuf->page_table[i] = virt_to_page(tmpb.area);
+#endif
 		sgbuf->pages++;
 	}
 
 	sgbuf->size = size;
+//#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+#if 0 //mj change
+	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL));
+#else
 	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL);
+#endif
 	if (! dmab->area)
 		goto _failed;
 	return dmab->area;
diff -uNra linux-2.6.27.6/sound/oss/Kconfig linux-2.6.27.6.yaffs/sound/oss/Kconfig
--- linux-2.6.27.6/sound/oss/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/oss/Kconfig	2011-05-08 18:06:17.000000000 +0800
@@ -602,3 +602,15 @@
 	int "DAC channel"
 	default "1"
 	depends on SOUND_SH_DAC_AUDIO
+
+config SOUND_SM501 
+	tristate "Silicon Motion VoyagerGX (SM501)"
+	depends on SOUND_PRIME && PCI
+
+config  SOUND_SM501_VBR
+    bool "Enable Variable Bit Rate" 	
+	depends on SOUND_SM501
+
+config  SOUND_SM501_DEBUG
+    bool "Enable Debugging"
+    depends on SOUND_SM501
diff -uNra linux-2.6.27.6/sound/oss/Makefile linux-2.6.27.6.yaffs/sound/oss/Makefile
--- linux-2.6.27.6/sound/oss/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/oss/Makefile	2011-05-08 18:06:18.000000000 +0800
@@ -32,6 +32,7 @@
 obj-$(CONFIG_SOUND_BCM_CS4297A)	+= swarm_cs4297a.o
 
 obj-$(CONFIG_DMASOUND)		+= dmasound/
+obj-$(CONFIG_SOUND_SM501)	+= sm501/ ac97_codec.o
 
 # Declare multi-part drivers.
 
diff -uNra linux-2.6.27.6/sound/oss/sm501/Makefile linux-2.6.27.6.yaffs/sound/oss/sm501/Makefile
--- linux-2.6.27.6/sound/oss/sm501/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/oss/sm501/Makefile	2011-05-08 18:06:17.000000000 +0800
@@ -0,0 +1,5 @@
+# Makefile for Cirrus Logic-Crystal CS4281 
+#
+
+obj-$(CONFIG_SOUND_SM501) += sm501_oss.o
+
diff -uNra linux-2.6.27.6/sound/oss/sm501/sm501fw.h linux-2.6.27.6.yaffs/sound/oss/sm501/sm501fw.h
--- linux-2.6.27.6/sound/oss/sm501/sm501fw.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/oss/sm501/sm501fw.h	2011-05-08 18:06:17.000000000 +0800
@@ -0,0 +1,450 @@
+/******************************************************************************\
+ *
+ * $Workfile:   sm501fw.h  $
+ *
+ * Silicon Motion VoyagerGX SM501 audio driver firmware for 8051 controller.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 675 Mass
+ * Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright (c) 2004, Himalaya Software
+ * All Rights Reserved
+ *
+ * $Log:   V:/Himalaya/archives/VoyagerGX Linux/drivers/sound/sm501fw.h-arc  $
+ * 
+ *    Rev 1.5   Feb 25 2004 23:15:10   frido
+ * Grr...
+ * 
+ *    Rev 1.4   Feb 25 2004 23:08:20   frido
+ * Changed firmware from string to bytes.
+ * 
+ *    Rev 1.3   Feb 22 2004 12:09:02   frido
+ * Unix EOL.
+ * 
+ *    Rev 1.2   Feb 12 2004 22:25:44   frido
+ * Changed UCHAR and USHORT to unsigned char and unsigned short.
+ * 
+ *    Rev 1.1   Feb 11 2004 22:38:36   frido
+ * Changed comments to C style.
+ * 
+ *    Rev 1.0   Feb 11 2004 22:26:54   frido
+ * Initial Revision
+ *
+\******************************************************************************/
+
+#ifndef _SM501FW_H_
+#define _SM501FW_H_
+
+#define SET_TX_SLOT_0                    0
+#define SET_TX_SLOT_1                    1
+#define SET_TX_SLOT_2                    2
+#define SET_PLAYBACK_BUFFER_ADDRESS      3
+#define SET_PLAYBACK_BUFFER_SIZE         4
+#define SET_PLAYBACK_BUFFER_READY        5
+#define GET_BUFFER_STATUS                6
+#define START_STOP_AUDIO_PLAYBACK        7
+#define GET_RX_SLOT0                     8
+#define GET_RX_SLOT1                     9
+#define GET_RX_SLOT2                    10
+#define SET_CAPTURE_BUFFER_ADDRESS      11
+#define SET_CAPTURE_BUFFER_SIZE         12
+#define SET_CAPTIRE_BUFFER_EMPTY        13
+#define START_STOP_AUDIO_CAPTURE        14
+#define SET_GET_AC97_REGISTER           15
+
+
+
+/* Initial volume */
+//#define VGX_INITIALVOLUME	0x0A0A
+#define VGX_INITIALVOLUME	0x3F3F
+
+// Known AC97 codec vendors
+#define AC97_VENDOR_CRYSTAL      0x43525900  // Crystal Semicondutor "CRY"
+#define AC97_VENDOR_TRITECH      0x54524100  // TriTech "TRA"
+#define AC97_VENDOR_AKM          0x414B4D00  // Asahi Kasei "AKM"
+#define AC97_VENDOR_SIGMATEL     0x83847600  // SigmaTel
+#define AC97_VENDOR_VIA1613     0x0  // SigmaTel
+#define AC97_VENDOR_ALC203     0x0  // SigmaTel
+#define AC97_VENDOR_ALC655     0x0  // SigmaTel
+
+#if  0
+
+typedef struct
+{
+    unsigned char firmware[0x3000];                     /* 0x0000 */
+    union
+    {
+        struct 
+        {
+            unsigned char playback_buffer_0[0x0600];    /* 0x3000 */
+            unsigned char playback_buffer_1[0x0600];    /* 0x3600 */
+        }B;
+        struct
+        {
+            unsigned char filler[0x0600];               /* 0x3000 */
+            unsigned char capture_buffer_0[0x0300];     /* 0x3600 */
+            unsigned char capture_buffer_1[0x0300];     /* 0x3900 */
+        }C;
+    }A;
+    unsigned char filler1[0x0200];                      /* 0x3C00 */
+    unsigned short ac97_regs[64];                       /* 0x3E00 */
+    unsigned char filler2[0x0170];                      /* 0x3E80 */
+    unsigned char command_byte;                         /* 0x3FF0 */
+    unsigned char status_byte;                          /* 0x3FF1 */
+    unsigned char data_byte[8];                         /* 0x3FF2 */
+    unsigned char filler3[2];                           /* 0x3FFA */
+    unsigned char buffer_status;                        /* 0x3FFC */
+    unsigned char command_busy;                         /* 0x3FFD */
+    unsigned char filler4;                              /* 0x3FFE */
+    unsigned char init_count;                           /* 0x3FFF */
+}
+FIRMWARE_SRAM;
+
+
+
+
+                 
+#else
+
+typedef struct
+{
+    unsigned char firmware[0x3000];                     /* 0x0000 */
+    union
+    {
+        struct 
+        {
+            unsigned char playback_buffer_0[0x0300];    /* 0x3000 */
+            unsigned char playback_buffer_1[0x0300];    /* 0x3300 */
+        }B;
+        struct
+        {
+            unsigned char filler[0x0600];               /* 0x3000 */
+            unsigned char capture_buffer_0[0x0300];     /* 0x3600 */
+            unsigned char capture_buffer_1[0x0300];     /* 0x3900 */
+        }C;
+    }A;
+    unsigned char filler1[0x0200];                      /* 0x3C00 */
+    unsigned short ac97_regs[64];                       /* 0x3E00 */
+    unsigned char filler2[0x0170];                      /* 0x3E80 */
+    unsigned char command_byte;                    /* 0x3FF0 */
+    unsigned char status_byte;                          /* 0x3FF1 */
+    unsigned char data_byte[8];                         /* 0x3FF2 */
+    unsigned char filler3[2];                               /* 0x3FFA */
+    unsigned char buffer_status;                        /* 0x3FFC */
+    unsigned char command_busy;                    /* 0x3FFD */
+    unsigned char filler4;                                  /* 0x3FFE */
+    unsigned char init_count;                            /* 0x3FFF */
+}
+FIRMWARE_SRAM;
+
+//Using 8051 AC97 Controller firmware version 1.4
+#define FIRMWARE \
+":03000000020100FA" \
+":03003B00020EEEC4" \
+":030043000206DCD6" \
+":10010000758129750C03750D11750EFF750F2FC2C2" \
+":10011000D3C2D4120D49120DB5120D2B120D0D12B2" \
+":0A0120000CAB1210E112012A0100DD" \
+":10012A0090110485820A85830B7497F582F5087409" \
+":10013A000CF583F5097A14E493A38582088583096B" \
+":10014A00850A82850B83F0A385830B85820A85093C" \
+":10015A0083850882DAE1901118E4F0A3F090111A6D" \
+":10016A00E4F0A3F090111CE4F0A3F090111EE4F067" \
+":10017A00A3F0903FFFE004F0781876007819760033" \
+":10018A009091807403F09011047A047808E0F6A341" \
+":10019A0008DAFA9091007A047808E6F0A308DAFA05" \
+":1001AA009011087A047808E0F6A308DAFA90910424" \
+":1001BA007A047808E6F0A308DAFA90110C7A04783F" \
+":1001CA0008E0F6A308DAFA9091087A047808E6F0CB" \
+":1001DA00A308DAFA9011107A047808E0F6A308DA8C" \
+":1001EA00FA90910C7A047808E6F0A308DAFA9011EA" \
+":1001FA00147A047808E0F6A308DAFA9091107A04DF" \
+":10020A007808E6F0A308DAFA909140E4F0A3F0A3A4" \
+":10021A00F0A3F0909144E4F0A3F0A3F0A3F090913E" \
+":10022A0048E4F0A3F0A3F0A3F0901120E4F0A3F0C7" \
+":10023A00120046901118E4F0A3F0901118C3E0944C" \
+":10024A00E8A3E0940330D204B2E7D2E030E7389072" \
+":10025A00111AE4F0A3F090111AC3E094C8A3E09431" \
+":10026A000030D204B2E7D2E030E70E90111AE0244F" \
+":10027A0001F0A3E03400F080DD901118E02401F0D1" \
+":10028A00A3E03400F080B39091807401F0901120C3" \
+":10029A0074FFF0A3E4F0120046901118E4F0A3F002" \
+":1002AA00901118C3E094E8A3E0940330D204B2E7B3" \
+":1002BA00D2E030E73890111AE4F0A3F090111AC393" \
+":1002CA00E09464A3E0940030D204B2E7D2E030E7CD" \
+":1002DA000E90111AE02401F0A3E03400F080DD90C2" \
+":1002EA001118E02401F0A3E03400F080B3909140AB" \
+":1002FA00E05400F508A3E05480F509A3E05400F5A2" \
+":10030A000AA3E05400F50B78087A04E6700308DAC9" \
+":10031A00FA6002800280D690112074FFF0A3E4F004" \
+":10032A00120046909140E05400F508A3E05480F58D" \
+":10033A0009A3E05400F50AA3E05400F50B78087A03" \
+":10034A0004E6700308DAFA6002800280D6903FF071" \
+":10035A00740FF0903FF2E4F0A37460F0A3740AF013" \
+":10036A00A3E4F0903FF6E4F0A3F0A3F0A3F0120E9A" \
+":10037A0079903FF6E054F0F5087A037808A308E08C" \
+":10038A005400F6DAF878087A04E6700308DAFA60B4" \
+":10039A0002800280B8903FF0740FF0903FF2E4F0D0" \
+":1003AA00A37460F0A3740AF0A3E4F0903FF6E4F0BB" \
+":1003BA00A3F0A3F0A3F0120E79903FF6E054F0F503" \
+":1003CA00087A037808A308E05400F6DAF878087A7D" \
+":1003DA0004E6700308DAFA6002800280B890111A03" \
+":1003EA00E4F0A3F0901118E4F0A3F0903FFFE004CA" \
+":1003FA00F07819E670567818E67051901118C3E033" \
+":10040A0094E87004A3E09403702C901118E4F0A30C" \
+":10041A00F090111AE02401F0A3E03400F090111AD0" \
+":10042A00C3E094907004A3E09401700A90111AE456" \
+":10043A00F0A3F01208FE901118E02401F0A3E034B2" \
+":10044A0000F0781BE66003120E7980A5901118E47B" \
+":10045A00F0A3F07819E670057818E6600A781BE6CA" \
+":10046A006003120E7980EC0203FB909180E4F02283" \
+":10047A00901120E04400F508A3E04400F509A3E048" \
+":10048A004408F50AA3E04400F50B90112A7A04788F" \
+":10049A0008E6F0A308DAFA9011267400F0A3743E75" \
+":1004AA00F09011207A047808E0F6A308DAFA7A0DB7" \
+":1004BA00E50BA2E713F50BE50A13F50AE50913F5AF" \
+":1004CA0009E50813F508DAE8E508C333F508E5098C" \
+":1004DA0033F509901126E02508F0A3E03509F090DC" \
+":1004EA0011287400F0A3743FF09011207A04780860" \
+":1004FA00E0F6A308DAFA7A0DE50BA2E713F50BE5A5" \
+":10050A000A13F50AE50913F509E50813F508DAE807" \
+":10051A00E508C333F508E50933F509901128E02504" \
+":10052A0008F0A3E03509F0909108E4F0A3F0A3F0F5" \
+":10053A00A3F090112A7A047808E0F6A308DAFA9070" \
+":10054A0091047A047808E6F0A308DAFA9091007523" \
+":10055A0008007509E0750A00750B007A047808E04E" \
+":10056A0046F0A308DAF9901124E4F0A3F0901124DC" \
+":10057A00C3E09480A3E0943830D204B2E7D2E020FA" \
+":10058A00E70302066F909140E05400F508A3E05497" \
+":10059A0060F509A3E05400F50AA3E05400F50B78CE" \
+":1005AA00087A04E6700308DAFA700302066090918A" \
+":1005BA0000750800750998750A00750B007A0478A9" \
+":1005CA0008E056F0A308DAF99091487A047808E02E" \
+":1005DA00F6A308DAFA903FF67A047808E6F0A30858" \
+":1005EA00DAFA9091487A047808E0F6A308DAFA7AF7" \
+":1005FA0004E50BA2E713F50BE50A13F50AE509135F" \
+":10060A00F509E50813F508DAE8901126E0FAA3E0FF" \
+":10061A008A82F583E508F0A3E509F09091487A0407" \
+":10062A007808E0F6A308DAFA7A04E50BA2E713F5EC" \
+":10063A000BE50A13F50AE50913F509E50813F508A8" \
+":10064A00DAE8901128E0FAA3E08A82F583E508F057" \
+":10065A00A3E509F0800F901124E02401F0A3E0340F" \
+":10066A0000F0020577901124E4F0A3F0901124C35E" \
+":10067A00E09480A3E0943830D204B2E7D2E030E7C5" \
+":10068A0036909140E05400F508A3E05460F509A3C0" \
+":10069A00E05400F50AA3E05400F50B78087A04E662" \
+":1006AA00700308DAFA7002800E901124E02401F037" \
+":1006BA00A3E03400F080B5909100750800750998A0" \
+":1006CA00750A00750B007A047808E056F0A308DA78" \
+":0206DA00F92203" \
+":1006DC00C0E0C082C083C0D0C008C009C00AC00B33" \
+":1006EC00C2D3D2D4C2AF53E8F97818E6700302072C" \
+":1006FC00DF909140E05400F508A3E05418F509A3ED" \
+":10070C00E05400F50AA3E05400F50B78087A04E6EF" \
+":10071C00700308DAFA70030207DF90914C7A0478C0" \
+":10072C0008E0F6A308DAFA9010F1E0FAA3E08A8266" \
+":10073C00F5837A047808E6F0A308DAFA9010F1E071" \
+":10074C002404F0A3E03400F09091507A047808E08F" \
+":10075C00F6A308DAFA9010F1E0FAA3E08A82F583A6" \
+":10076C007A047808E6F0A308DAFA9010F1E0240491" \
+":10077C00F0A3E03400F09010F1C3E094007004A3F7" \
+":10078C00E09439701B903FFCE054CFF0903FFCE0BC" \
+":10079C004410F09090087401F0A3E4F0A3F0A3F0DF" \
+":1007AC009010F1C3E094007004A3E0943C7024908A" \
+":1007BC003FFCE054CFF0903FFCE04420F09010F16F" \
+":1007CC00E4F0A37436F09090087401F0A3E4F0A365" \
+":1007DC00F0A3F07819E670030208D3909144E0542A" \
+":1007EC0000F508A3E0540CF509A3E05400F50AA3A6" \
+":1007FC00E05400F50B78087A04E6700308DAFA7016" \
+":10080C00028019900034E0F508E4F509F50AF50BBF" \
+":10081C0078087A04E6700308DAFA70030208479045" \
+":10082C0091007508FF7509E77A027808E056F0A385" \
+":10083C0008DAF9900034E4F00208D39091017509BC" \
+":10084C00987809E046F09010EFE0FAA3E08A82F580" \
+":10085C00837A077808E0F6A308DAFA90910C7A0606" \
+":10086C007808E6F0A308DAFAE6F09010EFE0240836" \
+":10087C00F0A3E03400F09010EFC3E094007015A3E7" \
+":10088C00E09433700F903FFCE054FC4401F09090E6" \
+":10089C00087401F09010EFC3E094007024A3E0946E" \
+":1008AC0036701E903FFCE054FC4402F09010EFE4D4" \
+":1008BC00F0A37430F09090087401F090003474013F" \
+":1008CC00F09000347401F0909181E054FC6004E0ED" \
+":1008DC005403F0781DE660011643E80643F804D291" \
+":1008EC00AFD00BD00AD009D008D0D0D083D082D0D2" \
+":0208FC00E032E8" \
+":1008FE009011247400F0A3743EF0901126E4F0A33E" \
+":10090E00F0A37408F0A3E4F0909108E4F0A3F0A330" \
+":10091E00F0A3F0901120E4F0A3F0901120C3E09426" \
+":10092E0040A3E0940030D204B2E7D2E020E7030205" \
+":10093E000AB89011267A047808E0F6A308DAFA903D" \
+":10094E0091047A047808E6F0A308DAFA909100751B" \
+":10095E0008007509C0750A00750B007A047808E066" \
+":10096E0046F0A308DAF9901122E4F0A3F0901122D8" \
+":10097E00C3E09440A3E0941F30D204B2E7D2E0204B" \
+":10098E00E703020A1D909140E05400F508A3E054DD" \
+":10099E0060F509A3E05400F50AA3E05400F50B78C6" \
+":1009AE00087A04E6700308DAFA605590910075082B" \
+":1009BE0000750998750A00750B007A047808E056E0" \
+":1009CE00F0A308DAF99091487A047808E0F6A308C3" \
+":1009DE00DAFA7A04E50BA2E713F50BE50A13F50A2A" \
+":1009EE00E50913F509E50813F508DAE8901124E096" \
+":1009FE00FAA3E08A82F583E508F0A3E509F0800FFB" \
+":100A0E00901122E02401F0A3E03400F002097B9063" \
+":100A1E001124E02402F0A3E03400F0901126E0242B" \
+":100A2E0000F508A3E03420F509A3E03400F50AA38D" \
+":100A3E00E03400F50B9011267A047808E6F0A3084E" \
+":100A4E00DAFA901122E4F0A3F0901122C3E0944060" \
+":100A5E00A3E0941F30D204B2E7D2E030E736909193" \
+":100A6E0040E05400F508A3E05460F509A3E05400FB" \
+":100A7E00F50AA3E05400F50B78087A04E670030833" \
+":100A8E00DAFA7002800E901122E02401F0A3E03415" \
+":100A9E0000F080B5781BE66002800F901120E024F4" \
+":100AAE0001F0A3E03400F0020928909100750800CF" \
+":100ABE00750998750A00750B007A047808E056F0EF" \
+":050ACE00A308DAF92283" \
+":100AD300903FF27A047808E0F6A308DAFA909104DA" \
+":100AE3007A047808E6F0A308DAFA903FF67A0478F5" \
+":100AF30008E0F6A308DAFA9091087A047808E6F099" \
+":100B0300A308DAFA903FF67A047808E0F6A308DA45" \
+":100B1300FA9011307A047808E6F0A308DAFA903FE5" \
+":100B2300F17401F0909104E05400F508A3E054003F" \
+":100B3300F509A3E05408F50AA3E05400F50B78087F" \
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+":100B9300A3F080F2909100750800750998750A001A" \
+":100BA300750B007A047808E056F0A308DAF9781D8B" \
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+":100BC30090112EE4F0A3F090112EC3E09480A3E0E3" \
+":100BD300943830D204B2E7D2E030E736909140E067" \
+":100BE3005400F508A3E05460F509A3E05400F50AA6" \
+":100BF300A3E05400F50B78087A04E6700308DAFAE8" \
+":100C03007002800E90112EE02401F0A3E03400F076" \
+":100C130080B590112EC3E09480A3E0943830D204C1" \
+":100C2300B2E7D2E030E74C903FF27A047808E0F67E" \
+":100C3300A308DAFA90112078087A04E6F0A308DA18" \
+":100C4300FA12047A903FF67A047808E0F6A308DAF9" \
+":100C5300FA901130C3E095087010A3E09509700A6B" \
+":100C6300A3E0950A7004A3E0950B6006903FF1742E" \
+":100C7300FFF022909100750800750998750A0075B8" \
+":100C83000B007A047808E056F0A308DAF9903FF1F4" \
+":040C930074FFF022D8" \
+":100C970000800000000000000000000000000800C5" \
+":100CA70000000800741470047400601E9010BDA842" \
+":100CB70083A9829010EFAA83AB82901103AC83AD16" \
+":100CC70082C3ED9B7028EC9A702474017004740041" \
+":100CD700601B900035AC83AD82900034C3ED9582E4" \
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+":100D070083AB82020CC87400600D9000007900FA72" \
+":100D1700E493F7A309DAF9741160087818FAE4F68E" \
+":100D270008DAFC227400600D9000007900FAE49361" \
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+":100D4700FC2274006035FB900000740075F0088485" \
+":100D57002420F87A08E5F06007E6031AD5F0FBF6D9" \
+":100D6700EB600D1BE493A3A2E0E613F6DAF280052D" \
+":100D7700E603DAFDF6087A08EB70E57400602EFBEF" \
+":100D8700740075F008842420F87A08E5F06007E617" \
+":100D9700031AD5F0FBF6EB60091BC3E613F6DAF688" \
+":100DA7008005E603DAFDF6087A08EB70E92274009D" \
+":100DB700600D9000007900FAE493F7A309DAF9745B" \
+":0C0DC7000060087800FAE4F608DAFC226C" \
+":10004600901124E4F0A37430F0901122E4F0A3F0B0" \
+":10005600901122C3E094F0A3E0940F30D204B2E7EB" \
+":10006600D2E030E72E901120E0901124C0E0E0FAB3" \
+":10007600A3E08A82F583D0E0F0901124E02401F019" \
+":10008600A3E03400F0901122E02401F0A3E0340054" \
+":10009600F080BD901124E4F0A3743CF0901122E4AA" \
+":1000A600F0A3F0901122C3E09400A3E0940130D2B3" \
+":1000B60004B2E7D2E030E72E901122E0901124C07E" \
+":1000C600E0E0FAA3E08A82F583D0E0F0901124E024" \
+":1000D6002401F0A3E03400F0901122E02401F0A303" \
+":0700E600E03400F080BD22B0" \
+":100DD3009010FBE0FAA3E08A82F583E060109010A4" \
+":100DE300F1E4F0A37436F078187601020E727818E5" \
+":100DF30076009010F1E0F508A3E0F509901120E5E5" \
+":100E030008F0A3E509F0901120C3E09400F508A3CE" \
+":100E1300E09436F509901120E508F0A3E509F09078" \
+":100E23001120C3E094007A0060010AA3E094034A0E" \
+":100E330030D204B2E7D2E020E7027002801F7825A7" \
+":100E43007600087603901120C3E09400F508A3E030" \
+":100E53009403F5097827A60808A60980127827764F" \
+":100E6300000876039011207825E0F608A3E0F690B9" \
+":060E73003FF1740EF022B5" \
+":100E7900903FFD7401F0903FF1E4F0903FF0E0FA0B" \
+":100E8900333354FC2A781EF6900E96E673120FBF80" \
+":100E99008049120FE18044121002803F1200ED8058" \
+":100EA9003A120003803512108680301210A2802B6E" \
+":100EB900120F9780261210238021121044801C12D1" \
+":100EC900106580171210D18012120F41800D120F78" \
+":100ED9006E8008120DD38003120AD3781B76009016" \
+":050EE9003FFDE4F022D2" \
+":100EEE00C0E0C082C083C0D0C008C009C00AC00B19" \
+":100EFE00C2D3D2D4C2AF53E8F9781B7601903FFD2E" \
+":100F0E007401F090900C7A047808E0F6A308DAFAEF" \
+":100F1E009000307A047808E6F0A308DAFA43E8067F" \
+":100F2E00D2AFD00BD00AD009D008D0D0D083D08287" \
+":030F3E00D0E032CE" \
+":100003009010F7E0FAA3E08A82F5837821E0F608FE" \
+":10001300A3E0F69010F9E0FAA3E08A82F58378234F" \
+":0D002300E0F608A3E0F6903FF17401F02232" \
+":100F410078259010F7E0FAA3E08A82F583E6F0A312" \
+":100F510008E6F078279010F9E0FAA3E08A82F58399" \
+":0D0F6100E6F0A308E6F0903FF17401F022E5" \
+":100F6E009010FBE0FAA3E08A82F583E044CFF09084" \
+":100F7E0010FBE0FAA3E08A82F583E0903FFCFAE0F2" \
+":090F8E005AF0903FF17401F022C9" \
+":100F97009010FBE0FAA3E08A82F583E0600F9010DF" \
+":100FA700EFE4F0A37430F0781976018004781976AD" \
+":080FB70000903FF17401F022EB" \
+":100FBF00903FF27A047808E0F6A308DAFA909100ED" \
+":100FCF007A047808E046F0A308DAF9903FF174014B" \
+":020FDF00F022FE" \
+":100FE100903FF27A047808E0F6A308DAFA909104C7" \
+":100FF1007A047808E6F0A308DAFA903FF17401F078" \
+":0110010022CC" \
+":10100200903FF27A047808E0F6A308DAFA909108A1" \
+":101012007A047808E6F0A308DAFA903FF17401F056" \
+":0110220022AB" \
+":101023009091407A047808E0F6A308DAFA903FF248" \
+":101033007A047808E6F0A308DAFA903FF17401F035" \
+":01104300228A" \
+":101044009091447A047808E0F6A308DAFA903FF223" \
+":101054007A047808E6F0A308DAFA903FF17401F014" \
+":011064002269" \
+":101065009091487A047808E0F6A308DAFA903FF2FE" \
+":101075007A047808E6F0A308DAFA903FF17401F0F3" \
+":011085002248" \
+":101086009010FBE0FAA3E08A82F583E05403903FD8" \
+":0C109600FCFAE04AF0903FF17401F022F7" \
+":1010A200903FFCE09010FBC0E0E0FAA3E08A82F5FA" \
+":0B10B20083D0E0F0903FF17401F022C9" \
+":1010BD000030003641914591F23FF43FF23FF33F4E" \
+":0410CD00F43FF53FB8" \
+":1000ED009010EFE4F0A37430F0903FF17401F02222" \
+":1010D1009010F1E4F0A37436F0903FF17401F02226" \
+":0E10E10075E80675F804D2AF900034E4F022F2" \
+":00000001FF"
+
+
+
+
+
+#endif
+
+
+#endif /* _SM501FW_H_ */
+
diff -uNra linux-2.6.27.6/sound/oss/sm501/sm501_oss.c linux-2.6.27.6.yaffs/sound/oss/sm501/sm501_oss.c
--- linux-2.6.27.6/sound/oss/sm501/sm501_oss.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/oss/sm501/sm501_oss.c	2011-05-08 18:06:17.000000000 +0800
@@ -0,0 +1,2700 @@
+/******************************************************************************\
+ *
+ * $Workfile:   sm501.c  $
+ *
+ * Silicon Motion VoyagerGX SM501 audio driver.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 675 Mass
+ * Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright (c) 2004, Himalaya Software
+ * Copyright (c) 2008, Siliconmotion corp.
+ *
+  *
+ *    Rev 1.7   Jun 03 2008 14:22:00   boyod
+ *	Add recorde function.
+ *
+ *    Rev 1.6   Apr 31 2008 15:00:00   boyod
+ *	upgrate to 2.6.21, Base SM501 core interface module.
+ *
+ *    Rev 1.5   Apr 13 2004 18:35:40   alexei
+ * Created a wrapper for read_codec and write_codec to be used when called
+ * from the outside, so that the functions could be called from the inside
+ * without having to grab the semaphore, which could be already grabbed by
+ * the caller function, which would lead to the driver waiting infinitely
+ * and causing the whole system to hang. The lock situation has been noticed
+ * during the init, when wait_codec is called by the ac97 engine and
+ * wait_codec in turn calls read_codec.
+ *
+ *    Rev 1.4   Mar 17 2004 11:59:44   frido
+ * Added DEBUG flag.
+ * 
+ *    Rev 1.3   Mar 17 2004 11:56:38   frido
+ * Added version number 1.0.1.
+ * Changed some KERROR into KWARNING.
+ * Added VBR flag.
+ * 
+ *    Rev 1.2   Mar 16 2004 23:41:48   frido
+ * First working driver on 44.1kHz.
+ * 
+ *    Rev 1.1   Mar 04 2004 23:12:02   frido
+ * Tired of bug hunting outside my driver.
+ * 
+ *    Rev 1.0   Feb 22 2004 12:09:40   frido
+ * Initial Revision
+ *
+\******************************************************************************/
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+//#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/sound.h>
+#include <linux/slab.h>
+#include <linux/soundcard.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/bitops.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/smp_lock.h>
+#include <linux/ac97_codec.h>
+#include <linux/platform_device.h>
+//#include <linux/wrapper.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+#include <asm/uaccess.h>
+#include <asm/hardirq.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+#include "sm501fw.h"
+
+
+/* -------------------------------------------------------------------------- */
+
+#undef OSS_DOCUMENTED_MIXER_SEMANTICS
+
+#define KERROR(msg, args...) printk(KERN_ERR PFX msg, ##args)
+#define KWARNING(msg, args...) printk(KERN_WARNING PFX msg, ##args)
+//#define KDEBUG(msg, args...)                       printk(KERN_INFO PFX msg, ##args)
+#ifdef CONFIG_SOUND_SM501_DEBUG
+#   define KDEBUG(msg, args...) printk(KERN_DEBUG PFX msg, ##args)
+#else
+#   define KDEBUG(msg, args...) do {} while(0)
+#endif
+
+/* -------------------------------------------------------------------------- */
+
+#ifndef PCI_VENDOR_ID_SILICONMOTION
+#define PCI_VENDOR_ID_SILICONMOTION         0x126F
+#endif
+
+#ifndef PCI_DEVICE_ID_SILICONMOTION_SM501
+#define PCI_DEVICE_ID_SILICONMOTION_SM501   0x0501
+#endif
+
+#define SM501_MAGIC     ((PCI_VENDOR_ID_SILICONMOTION << 16) | \
+                         PCI_DEVICE_ID_SILICONMOTION_SM501)
+
+#define SM501_EXTENT    (2 * 1024 * 1024)
+
+#define SM501_MODULE_NAME   "sm501"
+#define PFX                 SM501_MODULE_NAME ": "
+
+/* -------------------------------------------------------------------------- */
+
+typedef struct
+{
+    /* Buffer stuff. */
+    unsigned hw_buffer;
+    unsigned hw_buffer_size;
+    unsigned char* sw_buffer;
+    unsigned sw_buffer_size;
+    unsigned hw_ptr, sw_ptr;
+    unsigned total_bytes;
+    int count;
+    unsigned error;
+    int threshold;
+    /* Kernel suff. */
+    wait_queue_head_t wait;
+    /* Format suff. */
+    int bits;
+    int channels;
+    int rate;
+    unsigned int enabled : 1;
+    unsigned int ready : 1;
+    unsigned int endcleared : 1;
+    unsigned int running : 1;
+    unsigned int vbr : 1;
+}
+sm501BufferRec, *sm501BufferPtr;
+
+typedef struct
+{
+    /* Magic. */
+    unsigned int magic;
+
+    /* The corresponding pci_dev structure. */
+    struct device * dev;
+    unsigned int device;
+    unsigned int revision;
+
+    /* Soundcore stuff. */
+    int dev_audio;
+    struct ac97_codec* codec;
+    sm501BufferRec playing;
+    sm501BufferRec recording;
+
+    /* Hardware resources. */
+    unsigned int phys_io;
+    unsigned char* io;
+    unsigned int irq;
+
+#ifdef CONFIG_SOUND_SM501_DEBUG
+    /* debug /proc entry */
+    struct proc_dir_entry* ps;
+    struct proc_dir_entry* ac97ps;
+    unsigned int* samples;
+    unsigned int sample_index;
+    unsigned int sample_size;
+    unsigned char* data;
+    unsigned int data_index;
+    unsigned int data_size;
+    struct proc_dir_entry* sample_ps;
+#endif
+
+    spinlock_t lock;
+    struct semaphore open_sem;
+    mode_t open_mode;
+    wait_queue_head_t open_wait;
+    struct semaphore sem;
+}
+sm501Rec, *sm501Ptr;
+
+static sm501Ptr host_data;
+static ulong CodecPowerState;
+
+/* -------------------------------------------------------------------------- */
+
+static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
+static int i_flag = 15;
+	
+#define VALIDATE_STATE(s) \
+    do \
+    { \
+		if ((s) == NULL) \
+		{ \
+		    printk(invalid_magic); \
+		    return(-ENXIO); \
+		} \
+    } \
+    while (0)
+
+	/* -------------------------------------------------------------------------- */
+
+	#define LOWORD(x) ((unsigned short) (x))
+	#define HIWORD(x) ((unsigned short) ((x) >> 16))
+	#define LOBYTE(x) ((unsigned char) (x))
+	#define HIBYTE(x) ((unsigned char) ((x) >> 8))
+
+	#define MAKEWORD(l,h)  (((unsigned short) (unsigned char) (l)) | \
+			       (((unsigned short) (unsigned char) (h)) << 8))
+	#define MAKEDWORD(l,h) (((unsigned int) (unsigned short) (l)) | \
+			       (((unsigned int) (unsigned short) (h)) << 16))
+
+	#define SRAM(x)      (U8051_SRAM + offsetof(FIRMWARE_SRAM, x))
+	#define SRAM_SIZE(x) (sizeof(((FIRMWARE_SRAM*) 0)->x))
+
+
+static int write_command(sm501Ptr s, unsigned char command, unsigned int data0,
+				 unsigned int data1)
+{
+	    int i;
+	    /* Reset status. */
+	    SmWrite8(SRAM(status_byte), 0);
+
+	    /* Fill command and data bytes. */
+	    KDEBUG("write_command: %u %08x %08x\n", command, data0, data1);
+	    SmWrite8(SRAM(command_byte), command);
+#if 1
+		SmWrite32(SRAM(data_byte[0]), data0);
+	       	SmWrite32(SRAM(data_byte[4]), data1);
+#else
+	    SmWrite8(SRAM(data_byte[0]), LOBYTE(LOWORD(data0)));
+	    SmWrite8(SRAM(data_byte[1]), HIBYTE(LOWORD(data0)));
+	    SmWrite8(SRAM(data_byte[2]), LOBYTE(HIWORD(data0)));
+	    SmWrite8(SRAM(data_byte[3]), HIBYTE(HIWORD(data0)));
+	    SmWrite8(SRAM(data_byte[4]), LOBYTE(LOWORD(data1)));
+	    SmWrite8(SRAM(data_byte[5]), HIBYTE(LOWORD(data1)));
+	    SmWrite8(SRAM(data_byte[6]), LOBYTE(HIWORD(data1)));
+	    SmWrite8(SRAM(data_byte[7]), HIBYTE(HIWORD(data1)));
+#endif
+	    /* Interrupt 8051. */
+	    SmWrite32(U8051_CPU_PROTOCOL_INTERRUPT, 1);
+
+	    /* Wait for command to start. */
+	    i = 10000;
+	    while (SmRead8(SRAM(command_busy)) == 0)
+	    {
+		if (i-- <= 0)
+		{
+//		    KWARNING("firmware did not accept command %u\n", command);
+		    break;
+		}
+		udelay(1);
+	    }
+
+	    /* Wait for command to finish. */
+	    while (SmRead8(SRAM(command_busy)) == 1)
+		udelay(1);
+
+	    /* Return status byte. */
+		
+/*		tmp = SmRead8(SRAM(status_byte));
+		KDEBUG("s %08x\n",  tmp);*/
+
+	    return(SmRead8(SRAM(status_byte)) == 0x1);
+	}
+
+	/* -------------------------------------------------------------------------- */
+
+	static void write_codec(struct ac97_codec* codec, u8 addr, u16 data)
+	{
+	    sm501Ptr s = (sm501Ptr) codec->private_data;
+
+	    KDEBUG("write_codec: addr=%02x data=%04x\n", addr, data);
+
+	    /* Write Codec register. */
+	    if (!write_command(s, SET_GET_AC97_REGISTER, (unsigned int) addr << 12,
+			       (unsigned int) data << 4) && (addr != AC97_RESET))
+	    {
+			unsigned int read_back;
+			read_back = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+						       SmRead8(SRAM(data_byte[5]))),
+					      MAKEWORD(SmRead8(SRAM(data_byte[6])),
+						       SmRead8(SRAM(data_byte[7])))) >> 4;
+			KDEBUG("write_codec failed: addr=%02x data=%04x read_back=%04x\n",
+				 addr, data, read_back);
+	    }
+	}
+
+	static void write_codec_wrapper(struct ac97_codec* codec, u8 addr, u16 data)
+	{
+	    sm501Ptr s = (sm501Ptr) codec->private_data;
+	    unsigned long flags;
+	    int i;
+#if 0
+           int regv[]={1,2,4,6,0xa,0xc,0xe,0x10,0x12,0x14,0x16,0x1c};
+/*
+		for  (i=0;i<12;i++)
+			if (regv[i]==addr)
+			return;
+*/
+			
+	    if (i_flag)	{
+		for  (i=0;i<12;i++)
+			if (regv[i]==addr)
+			{
+			i_flag--;
+			return;
+			}
+		}
+	    else{
+		for  (i=0;i<12;i++)
+			if (regv[i]==addr)
+			i_flag=15;
+	    }
+	    
+#endif
+
+	    KDEBUG("write_codec_wrapper: addr=%02x data=%04x\n", addr, data);
+	    spin_lock_irqsave(&s->lock, flags);
+
+	    write_codec(codec, addr, data);
+
+	    spin_unlock_irqrestore(&s->lock, flags);
+		
+	}
+
+	static u16 read_codec(struct ac97_codec* codec, u8 addr)
+	{
+	    sm501Ptr s = (sm501Ptr) codec->private_data;
+	    unsigned int data;
+	    int i;
+
+	    KDEBUG("read_codec: addr=%02x\n", addr);
+
+ 
+	    /* Read Codec register. */
+	    if (write_command(s, SET_GET_AC97_REGISTER,
+			      (unsigned int) (addr << 12) | (1 << 19), 0))
+	    {
+		data = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+					  SmRead8(SRAM(data_byte[5]))),
+				 MAKEWORD(SmRead8(SRAM(data_byte[6])),
+					  SmRead8(SRAM(data_byte[7])))) >> 4;
+	    }
+	    else
+	    {
+		/* Read register from SRAM in case link failes. */
+		for (i = 1000; i > 0; i--)
+		{
+		    data = SmRead16(SRAM(ac97_regs[addr >> 1]));
+		    if (data != 0xFFFF)
+			break;
+
+		    mdelay(1);
+		}
+
+		KDEBUG("read_codec failed: addr=%02x sram=%04x\n", addr, data);
+	    }
+
+	    KDEBUG("--read_codec: data=%04x\n", data);
+	    return((unsigned short) data);
+	}
+
+	static u16 read_codec_wrapper(struct ac97_codec* codec, u8 addr)
+		{
+		    sm501Ptr s = (sm501Ptr) codec->private_data;
+		    unsigned long flags;
+		    unsigned int data;
+
+		    if (addr== AC97_RECORD_SELECT)
+			return 0;
+			 
+		    KDEBUG("read_codec_wrapper: addr=%02x\n", addr);
+		    spin_lock_irqsave(&s->lock, flags);
+
+		    data = read_codec(codec, addr);
+
+		    spin_unlock_irqrestore(&s->lock, flags);
+		    return((unsigned short) data);
+		}
+
+		static void wait_codec(struct ac97_codec* codec)
+		{
+		    sm501Ptr s = (sm501Ptr) codec->private_data;
+		    unsigned long flags;
+		    int i;
+		    unsigned int data;
+
+		    KDEBUG("wait_codec\n");
+		    spin_lock_irqsave(&s->lock, flags);
+
+		    /* Wait for AC97 active. */
+		    for (i = 1000; i > 0; i--)
+		    {
+			data = read_codec(codec, AC97_POWER_CONTROL);
+			if (data & AC97_PWR_DAC)
+			{
+			    KDEBUG("AC97_POWER_CONTROL: %04x\n", data);
+			    break;
+			}
+		    }
+		    if (i <= 0)
+			KWARNING("AC97 codec did not respond to reset: %04x\n", data);
+
+		    spin_unlock_irqrestore(&s->lock, flags);
+		}
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+/**
+	This routine is provided by linux 2.6.21 but not with 2.6.28
+	
+ *	ac97_set_adc_rate	-	set codec rate adaption
+ *	@codec: ac97 code
+ *	@rate: rate in hertz
+ *
+ *	Set the ADC rate. Assumes the codec supports VRA. The caller is
+ *	expected to have checked this little detail.
+ */
+
+unsigned int ac97_set_adc_rate(struct ac97_codec *codec, unsigned int rate)
+{
+	unsigned int new_rate = rate;
+	u32 dacp;
+
+	if(rate != codec->codec_read(codec, AC97_PCM_LR_ADC_RATE))
+	{
+		/* Power down the ADC */
+		dacp=codec->codec_read(codec, AC97_POWER_CONTROL);
+		codec->codec_write(codec, AC97_POWER_CONTROL, dacp|0x0100);
+		/* Load the rate and read the effective rate */
+		codec->codec_write(codec, AC97_PCM_LR_ADC_RATE, rate);
+		new_rate=codec->codec_read(codec, AC97_PCM_LR_ADC_RATE);
+		/* Power it back up */
+		codec->codec_write(codec, AC97_POWER_CONTROL, dacp);
+	}
+	return new_rate;
+}
+
+/**
+	This routine is provided by linux 2.6.21 but not with 2.6.28
+	
+ *	ac97_set_dac_rate	-	set codec rate adaption
+ *	@codec: ac97 code
+ *	@rate: rate in hertz
+ *
+ *	Set the DAC rate. Assumes the codec supports VRA. The caller is
+ *	expected to have checked this little detail.
+ */
+ 
+unsigned int ac97_set_dac_rate(struct ac97_codec *codec, unsigned int rate)
+{
+	unsigned int new_rate = rate;
+	u32 dacp;
+	u32 mast_vol, phone_vol, mono_vol, pcm_vol;
+	u32 mute_vol = 0x8000;	/* The mute volume? */
+
+	if(rate != codec->codec_read(codec, AC97_PCM_FRONT_DAC_RATE))
+	{
+		/* Mute several registers */
+		mast_vol = codec->codec_read(codec, AC97_MASTER_VOL_STEREO);
+		mono_vol = codec->codec_read(codec, AC97_MASTER_VOL_MONO);
+		phone_vol = codec->codec_read(codec, AC97_HEADPHONE_VOL);
+		pcm_vol = codec->codec_read(codec, AC97_PCMOUT_VOL);
+		codec->codec_write(codec, AC97_MASTER_VOL_STEREO, mute_vol);
+		codec->codec_write(codec, AC97_MASTER_VOL_MONO, mute_vol);
+		codec->codec_write(codec, AC97_HEADPHONE_VOL, mute_vol);
+		codec->codec_write(codec, AC97_PCMOUT_VOL, mute_vol);
+		
+		/* Power down the DAC */
+		dacp=codec->codec_read(codec, AC97_POWER_CONTROL);
+		codec->codec_write(codec, AC97_POWER_CONTROL, dacp|0x0200);
+		/* Load the rate and read the effective rate */
+		codec->codec_write(codec, AC97_PCM_FRONT_DAC_RATE, rate);
+		new_rate=codec->codec_read(codec, AC97_PCM_FRONT_DAC_RATE);
+		/* Power it back up */
+		codec->codec_write(codec, AC97_POWER_CONTROL, dacp);
+
+		/* Restore volumes */
+		codec->codec_write(codec, AC97_MASTER_VOL_STEREO, mast_vol);
+		codec->codec_write(codec, AC97_MASTER_VOL_MONO, mono_vol);
+		codec->codec_write(codec, AC97_HEADPHONE_VOL, phone_vol);
+		codec->codec_write(codec, AC97_PCMOUT_VOL, pcm_vol);
+	}
+	return new_rate;
+}
+#endif
+static void set_recording_rate(sm501Ptr s, unsigned rate)
+{
+
+		   if (!s->recording.vbr)
+			s->recording.rate = 48000;
+		    else
+		    {
+			if (rate > 48000)
+			    rate = 48000;
+			else if (rate < 11500)
+			    rate = 11500;
+
+			KDEBUG("Set recording rate to %d\n", rate);
+			s->recording.rate = ac97_set_adc_rate(s->codec, rate);
+			KDEBUG("-> %d\n", s->recording.rate);
+		    }
+}
+
+static void set_playing_rate(sm501Ptr s, unsigned rate)
+{
+		    if (!s->playing.vbr)
+			s->playing.rate = 48000;
+		    else
+		    {
+			if (rate > 48000)
+			    rate = 48000;
+			if (rate < 4000)
+			    rate = 4000;
+
+			KDEBUG("Set playing rate to %d\n", rate);
+			s->playing.rate = ac97_set_dac_rate(s->codec, rate);
+			KDEBUG("-> %d\n", s->playing.rate);
+		    }
+}
+
+
+/* -------------------------------------------------------------------------- */
+
+		static void select_buffer(sm501Ptr s, unsigned char status)
+		{
+			if (status & 1)
+			{
+			    s->playing.hw_buffer = SRAM(A.B.playback_buffer_0);
+			    s->playing.hw_buffer_size = SRAM_SIZE(A.B.playback_buffer_0);
+			}
+			else  if (status & 2)
+			{
+			    s->playing.hw_buffer = SRAM(A.B.playback_buffer_1);
+			    s->playing.hw_buffer_size = SRAM_SIZE(A.B.playback_buffer_1);
+			}
+			else if (status & 0x10)
+			{
+			    s->recording.hw_buffer = SRAM(A.C.capture_buffer_0);
+			    s->recording.hw_buffer_size = SRAM_SIZE(A.C.capture_buffer_0);
+			}
+			else if (status & 0x20)
+			{
+			    s->recording.hw_buffer = SRAM(A.C.capture_buffer_1);
+			    s->recording.hw_buffer_size = SRAM_SIZE(A.C.capture_buffer_1);
+			}
+		}
+
+		#define U8_TO_S16(v)    MAKEWORD(0, v)  //(v) - 0x80)
+
+		static void fill_playing(sm501Ptr s)
+		{
+		    unsigned int sample;
+		    unsigned hw_buffer;
+		    int hw_buffer_count, count;
+		    unsigned hw_ptr, sw_buffer_size, total_bytes;
+
+		    /* Load parameters. */
+		    hw_buffer = s->playing.hw_buffer;
+		    hw_buffer_count = s->playing.hw_buffer_size;
+		    count = s->playing.count;
+
+		    KDEBUG("sample count:%d\n",count);
+
+		    /* Test for buffer underrun. */
+		    if (count <= 0)
+		    {
+			/* Buffer underrun. */
+			s->playing.error++;
+			KDEBUG("Buffer underrun count:%d\n",count );
+		    }
+		    else
+		    {
+			sw_buffer_size = s->playing.sw_buffer_size;
+			hw_ptr = s->playing.hw_ptr;
+			total_bytes = s->playing.total_bytes;
+
+			/* Loop while hardware buffer has room. */
+			while (hw_buffer_count > 0)
+			{
+			    /* Determine sample bit size. */
+			    if (s->playing.bits == 8)
+			    {
+				/* Make sure software buffer has sample. */
+				if (count < 1)
+				    break;
+
+				/* Convert sample into 24-bit. */
+				sample = U8_TO_S16(s->playing.sw_buffer[hw_ptr]);
+
+				/* Update software buffer. */
+				hw_ptr += 1;
+				count -= 1;
+				total_bytes += 1;
+			    }
+			    else
+			    {
+				/* Make sure software buffer has sample. */
+				if (count < 2)
+				    break;
+
+				/* Convert sample into 24-bit. */
+				sample = MAKEWORD(s->playing.sw_buffer[hw_ptr + 0],
+						  s->playing.sw_buffer[hw_ptr + 1]);
+
+				/* Update software buffer. */
+				hw_ptr += 2;
+				count -= 2;
+				total_bytes += 2;
+			    }
+
+			    hw_ptr %= sw_buffer_size;
+
+			    /* Store sample in hardware buffer. */
+			    SmWrite32(hw_buffer, sample << 4);
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			    if (s->sample_index < s->sample_size)
+				s->samples[s->sample_index++] = sample << 4;
+		#endif
+			    hw_buffer += 4;
+			    hw_buffer_count -= 4;
+
+			    /* Test if sample is stereo. */
+			    if (s->playing.channels == 2)
+			    {
+
+				
+				/* Determine sample bit size. */
+				if (s->playing.bits == 8)
+				{
+				    /* Make sure software buffer has sample. */
+				    if (count < 1)
+				    {
+					/* Stereo data missing - error. */
+					s->playing.error++;
+					KDEBUG("Stereo data missing 1\n");
+
+					break;
+				    }
+
+				    /* Convert sample into 24-bit. */
+				    sample = U8_TO_S16(s->playing.sw_buffer[hw_ptr]);
+
+				    /* Update software buffer. */
+				    hw_ptr += 1;
+				    count -= 1;
+				    total_bytes += 1;
+				}
+				else
+				{
+				    /* Make sure software buffer has sample. */
+				    if (count < 2)
+				    {
+					/* Stereo data missing - error. */
+					s->playing.error++;
+					KDEBUG("Stereo data missing 2\n");
+					break;
+				    }
+
+				    /* Convert sample into 24-bit. */
+				    sample = MAKEWORD(s->playing.sw_buffer[hw_ptr + 0],
+						      s->playing.sw_buffer[hw_ptr + 1]);
+
+				    /* Update software buffer. */
+				    hw_ptr += 2;
+				    count -= 2;
+				    total_bytes += 2;
+				}
+
+
+				hw_ptr %= sw_buffer_size;
+			    }
+
+			    /* Store sample in hardware buffer. */
+			    SmWrite32(hw_buffer, sample << 4);
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			    if (s->sample_index < s->sample_size)
+				s->samples[s->sample_index++] = sample << 4;
+		#endif
+			    hw_buffer += 4;
+			    hw_buffer_count -= 4;
+			}
+
+			/* Store software buffer parameters. */
+			s->playing.hw_ptr = hw_ptr % sw_buffer_size;
+			s->playing.count = count;
+			s->playing.total_bytes = total_bytes;
+		    }
+
+		    /* See if hardware buffer needs to be cleared. */
+		    if (hw_buffer_count > 0)
+		    {
+			/* Mark clear flag. */
+			s->playing.endcleared = 1;
+
+			/* Fill hardware buffer with samples. */
+			KDEBUG("clearing %d samples\n", hw_buffer_count / 4);
+			while (hw_buffer_count > 0)
+			{
+			    SmWrite32(hw_buffer, 0);
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			    if (s->sample_index < s->sample_size)
+				s->samples[s->sample_index++] = 0;
+		#endif
+			    hw_buffer += 4;
+			    hw_buffer_count -= 4;
+			}
+		    }
+		}
+
+		#define S16_TO_U8(v) ((unsigned char) (HIBYTE(v) + 0x80))
+
+		static void get_recording(sm501Ptr s)
+		{
+
+/*				hw_ptr:  hwbuffer   pos
+				count:    copy  count
+				total_bytes:   bytes in sw buffer
+*/
+		    unsigned int sample;
+		    unsigned hw_buffer;
+		    int hw_buffer_size, count;
+		    unsigned hw_ptr, sw_buffer_size, total_bytes;
+		    static int cc;
+		
+		    /* Get parameters. */
+		    hw_buffer = s->recording.hw_buffer;
+		    hw_buffer_size = s->recording.hw_buffer_size;
+		    sw_buffer_size = s->recording.sw_buffer_size;
+		    count = s->recording.count;
+
+		    KDEBUG("get_recording NO. %d \n", cc++);
+			
+		    /* Test for buffer overrun. */
+		    if (count >= sw_buffer_size)
+		    {
+			KDEBUG(" Buffer overrun 1. \n");
+			s->recording.error++;
+		    }
+		    else
+		    {
+			hw_ptr = s->recording.hw_ptr;
+			total_bytes = s->recording.total_bytes;
+
+			/* Loop while hardware buffer has samples. */
+			while (hw_buffer_size > 0)
+			{
+			    /* Read sample from hardware buffer. */
+			    sample = SmRead32(hw_buffer);
+			    hw_buffer += 4;
+			    hw_buffer_size -= 4;
+
+				
+			// first channel
+                         {
+			    /* Test for buffer overrun. */
+			    if (count >= sw_buffer_size)
+			    {
+				KDEBUG(" Buffer overrun 2\n ");
+				s->recording.error++;
+				break;
+			    }
+
+			    KDEBUG("sample:%08x\n ", (sample) );
+				
+			    /* Determine sample bit size. */
+			    if (s->recording.bits == 8)
+			    {
+				/* Convert sample into 8-bit. */
+				s->recording.sw_buffer[hw_ptr] = 
+						(unsigned char) (sample >> 12);
+			    KDEBUG("%8x\n ",s->recording.sw_buffer[hw_ptr]  );
+
+
+				/* Update hardware buffer. */
+				hw_ptr += 1;        //hwbuffer   pos
+				count += 1;          // copy  count
+				total_bytes += 1;    //bytes in sw buffer
+			    }
+			    else
+			    {
+				/* Convert sample into 16-bit. */
+				s->recording.sw_buffer[hw_ptr + 0] = (unsigned char)
+								     (sample >> 4);
+				s->recording.sw_buffer[hw_ptr + 1] = (unsigned char)
+								     (sample >> 12);
+
+				/* Update hardware buffer. */
+				hw_ptr += 2;
+				count += 2;
+				total_bytes += 2;
+			    }
+
+			    hw_ptr %= sw_buffer_size;
+
+			    /* Read sample from hardware buffer. */
+			    sample = SmRead32(hw_buffer);
+			    hw_buffer += 4;
+			    hw_buffer_size -= 4;
+	  		   }
+
+
+			
+			    /* second channel. */
+			    if (s->recording.channels == 2)
+			   {
+				/* Test for buffer overrun. */
+				if (count >= sw_buffer_size)
+				{
+				KDEBUG(" Buffer overrun 3. \n");
+				    s->recording.error++;
+				    break;
+				}
+
+				/* Determine sample bit size. */
+				if (s->recording.bits == 8)
+				{
+				    /* Convert sample into 8-bit. */
+				    s->recording.sw_buffer[hw_ptr] = 
+						    (unsigned char) (sample >> 12);
+
+				    /* Update hardware buffer. */
+				    hw_ptr += 1;
+				    count += 1;
+				    total_bytes += 1;
+				}
+				else
+				{
+				    /* Convert sample into 16-bit. */
+				    s->recording.sw_buffer[hw_ptr + 0] = (unsigned char)
+									 (sample >> 4);
+				    s->recording.sw_buffer[hw_ptr + 1] = (unsigned char)
+									 (sample >> 12);
+
+				    /* Update hardware buffer. */
+				    hw_ptr += 2;
+				    count += 2;
+				    total_bytes += 2;
+				}
+				hw_ptr %= sw_buffer_size;
+			    } 
+
+
+				
+			}
+
+			/* Store hardware buffer parameters. */
+			s->recording.hw_ptr = hw_ptr % sw_buffer_size;
+			s->recording.count = count;
+			s->recording.total_bytes = total_bytes;
+		    }
+		}
+
+		/* -------------------------------------------------------------------------- */
+
+		static void start_playing(sm501Ptr s, unsigned short SampleRate )
+		{
+		    unsigned long flags;
+			
+		    if (SampleRate)	
+                  write_codec_wrapper(s->codec, AC97_PCM_FRONT_DAC_RATE, SampleRate);
+				  
+		    spin_lock_irqsave(&s->lock, flags);
+		    if (!s->playing.running && s->playing.ready && s->playing.count > 0)
+		    {
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			KDEBUG("start playing: %d bits, %d channels\n", s->playing.bits,
+			       s->playing.channels);
+			s->sample_index = 0;
+		#endif
+			fill_playing(s);
+			write_command(s, START_STOP_AUDIO_PLAYBACK, s->playing.running = 1, 0);
+		    }
+		    spin_unlock_irqrestore(&s->lock, flags);
+		}
+
+		static inline void stop_playing(sm501Ptr s)
+		{
+		    unsigned long flags;
+		    unsigned char status;
+
+		    spin_lock_irqsave(&s->lock, flags);
+		    write_command(s, START_STOP_AUDIO_PLAYBACK, s->playing.running = 0, 0);
+		    spin_unlock_irqrestore(&s->lock, flags);
+		    status = SmRead8(SRAM(buffer_status));
+		    SmWrite8(SRAM(buffer_status), status&0xF0);
+		}
+
+		static void start_recording(sm501Ptr s, unsigned short SampleRate )
+		{
+		    unsigned long flags;
+
+		    if (SampleRate)	{
+			write_codec_wrapper(s->codec, AC97_PCM_LR_ADC_RATE, SampleRate);  //in case of line-in 
+			write_codec_wrapper(s->codec, AC97_PCM_MIC_ADC_RATE, SampleRate);				  
+		    }
+		    spin_lock_irqsave(&s->lock, flags);
+		    if (!s->recording.running && s->recording.ready &&
+			s->recording.count < s->recording.sw_buffer_size)
+		    {
+			KDEBUG("start recording: %d bits, %d channels\n", s->recording.bits,
+			       s->recording.channels);
+			write_command(s, START_STOP_AUDIO_CAPTURE, s->recording.running = 1, 0);
+		    }
+		    spin_unlock_irqrestore(&s->lock, flags);
+		    mdelay(2);
+
+		}
+
+		static inline void stop_recording(sm501Ptr s)
+		{
+		    unsigned long flags;
+		    unsigned char status;
+
+		    spin_lock_irqsave(&s->lock, flags);
+		    write_command(s, START_STOP_AUDIO_CAPTURE, s->recording.running = 0, 0);
+		    spin_unlock_irqrestore(&s->lock, flags);
+		    status = SmRead8(SRAM(buffer_status));
+		    SmWrite8(SRAM(buffer_status), status&0x0F);			
+		}
+
+		/* -------------------------------------------------------------------------- */
+
+		static void dealloc_buffer(sm501Ptr s, sm501BufferPtr buffer)
+		{
+		    /* Free allocated software buffer. */
+		    if (buffer->sw_buffer != NULL)
+			kfree(buffer->sw_buffer);
+
+		    /* Disable buffer. */
+		    buffer->sw_buffer = NULL;
+		    buffer->enabled = buffer->ready = 0;
+		}
+
+		static int program_buffer(sm501Ptr s, sm501BufferPtr buffer, unsigned hw_buffer,
+					  unsigned hw_buffer_size)
+		{
+		    /* Zero offsets, counters, and flags. */
+		    buffer->hw_ptr = buffer->sw_ptr = 0;
+		    buffer->total_bytes = buffer->count = buffer->error = 0;
+		    buffer->endcleared = 0;
+
+		    if (buffer->sw_buffer == NULL)
+		    {
+			/* Allocate software buffer. */
+			buffer->sw_buffer = kmalloc(buffer->sw_buffer_size = 0x4000, GFP_KERNEL);
+			if (buffer->sw_buffer == NULL){
+			    KDEBUG("Not enough memory.");
+			    return(-ENOMEM);
+			}
+		    }
+
+		    /* Set hardware buffer. */
+		    buffer->hw_buffer = hw_buffer;
+		    buffer->hw_buffer_size = hw_buffer_size;
+
+		    /* Calculate threshold(count of int size). */
+		    buffer->threshold = hw_buffer_size / 4 * (buffer->bits >> 3);
+
+		    /* Enable buffer. */
+		    buffer->enabled = buffer->ready = 1;
+		    return(0);
+		}
+
+		static inline int program_recording(sm501Ptr s)
+		{
+		    stop_recording(s);
+		    return(program_buffer(s, &s->recording, SRAM(A.C.capture_buffer_0),
+					  SRAM_SIZE(A.C.capture_buffer_0)));
+		}
+
+		static inline int program_playing(sm501Ptr s)
+		{
+		    stop_playing(s);
+		    return(program_buffer(s, &s->playing, SRAM(A.B.playback_buffer_0),
+					  SRAM_SIZE(A.B.playback_buffer_0)));
+		}
+
+		static irqreturn_t sm501_interrupt(int irq, void* dev_id, struct pt_regs* regs)
+		{
+		    sm501Ptr s = (sm501Ptr) dev_id;
+		    unsigned int status, mask;
+                  unsigned long flags;
+
+		    /* Read interrupt status. */
+		    status = SmRead32(INTERRUPT_STATUS);
+		    if (TEST_FIELD(status, INTERRUPT_STATUS_8051, NOT_ACTIVE))
+			return IRQ_NONE; 
+
+//		    KDEBUG("interrupt status: %08x\n", status);
+
+		    /* Reset 8051 interrupt status. */
+			
+		    mask = SmRead32(INTERRUPT_MASK);
+		    SmWrite32(INTERRUPT_MASK, SET_FIELD(mask, INTERRUPT_MASK_8051, DISABLE));	
+			
+		    spin_lock_irqsave(&s->lock, flags);
+		    SmRead32(U8051_8051_PROTOCOL_INTERRUPT);
+		    /* Check 8051 buffer status. */
+		    status = SmRead8(SRAM(buffer_status));
+//		    KDEBUG("interrupt status: %08x\n", status);
+		    if (status != 0)
+		    {
+			select_buffer(s, status);
+			if (status & 0x0F)
+			{
+				// Playback buffer empty.
+			    fill_playing(s);
+			    if (s->playing.error)
+			    {
+				KDEBUG("playing underflow.\n");
+				write_command(s, START_STOP_AUDIO_PLAYBACK,
+					      s->playing.running = 0, 0);
+				s->playing.error = 0;
+			    }
+			    else if (s->playing.sw_buffer_size - s->playing.count >= s->playing.threshold)
+			    {
+				wake_up(&s->playing.wait);
+			    }
+			}
+			if (status & 0xF0)
+			{
+				// Recording buffer full.
+			    get_recording(s);
+			    if (s->recording.error)
+			    {
+				KDEBUG("recording overflow.\n");
+				write_command(s, START_STOP_AUDIO_CAPTURE,
+					      s->recording.running = 0, 0);
+				s->recording.error = 0;
+			    }
+			    else if (s->recording.count >= s->recording.threshold)
+			    {
+				wake_up(&s->recording.wait);
+			    }
+			}
+			
+		    }
+		    spin_unlock_irqrestore(&s->lock, flags);
+			
+		    SmWrite32(INTERRUPT_MASK, SET_FIELD(mask, INTERRUPT_MASK_8051, ENABLE));	
+
+		    return IRQ_HANDLED;
+		}
+
+		/* -------------------------------------------------------------------------- */
+
+		static int sm501_open_mixdev(struct inode* inode, struct file* file)
+		{
+		    int minor;
+		    sm501Ptr s;
+		    KDEBUG("sm501 open mixdev\n");
+
+		    minor = MINOR(inode->i_rdev);
+		    //minor = iminor(inode);
+		    s = host_data;
+		    VALIDATE_STATE(s);
+
+		    if (s->codec->dev_mixer != minor)
+			return(-ENODEV);
+
+		    file->private_data = s;
+		    return(0);
+		}
+
+		static int sm501_release_mixdev(struct inode* inode, struct file* file)
+		{
+		    host_data = (sm501Ptr) file->private_data;
+		    VALIDATE_STATE(host_data);
+
+		    return(0);
+		}
+
+		static int sm501_ioctl_mixdev(struct inode* inode, struct file* file,
+					      unsigned int cmd, unsigned long arg)
+		{
+		    sm501Ptr s = (sm501Ptr) file->private_data;
+		    VALIDATE_STATE(s);
+
+		    return(s->codec->mixer_ioctl(s->codec, cmd, arg));
+		}
+
+		static struct file_operations sm501_mixer_fops =
+		{
+		    .owner=      THIS_MODULE,
+		    .llseek=     no_llseek,
+		    .ioctl=      sm501_ioctl_mixdev,
+		    .open=       sm501_open_mixdev,
+		    .release=    sm501_release_mixdev,
+		};
+
+		/* -------------------------------------------------------------------------- */
+
+		static int drain_playing(sm501Ptr s, int nonblock)
+		{
+		    DECLARE_WAITQUEUE(wait, current);
+		    unsigned long flags;
+		    int count;
+
+		    add_wait_queue(&s->playing.wait, &wait);
+
+		    while (1)
+		    {
+			__set_current_state(TASK_UNINTERRUPTIBLE);
+			spin_lock_irqsave(&s->lock, flags);
+			count = s->playing.count;
+			spin_unlock_irqrestore(&s->lock, flags);
+			if (count <= 0)
+			    break;
+
+			if (signal_pending(current))
+			    break;
+
+			if (nonblock)
+			{
+			    remove_wait_queue(&s->playing.wait, &wait);
+			    set_current_state(TASK_RUNNING);
+			    return(-EBUSY);
+			}
+
+			if (!schedule_timeout(count * HZ / s->playing.rate))
+			    KDEBUG("drain_playing: can not schedule a timeout\n");
+		    }
+
+		    remove_wait_queue(&s->playing.wait, &wait);
+		    set_current_state(TASK_RUNNING);
+		    if (signal_pending(current))
+			return(-ERESTARTSYS);
+
+		    return(0);
+		}
+
+/* -------------------------------------------------------------------------- */
+
+static ssize_t sm501_oss_read(struct file* file, char* buffer, size_t count,  loff_t* ppos)
+		{
+		    sm501Ptr s;
+		    ssize_t ret;
+		    unsigned long flags;
+		    unsigned sw_ptr;
+		    int byte_count;
+		    char* pbuf=buffer;
+
+		    KDEBUG("sm501_read: count=%d, ppos=%ld, file->f_pos=%ld\n", count, ppos, &file->f_pos);
+
+		    s = (sm501Ptr) file->private_data;
+		    DECLARE_WAITQUEUE(wait, current);
+		    ret = 0;
+
+		    VALIDATE_STATE(s);
+
+		    /* Verify file position and file buffer. */
+/*			
+		   if (ppos != &file->f_pos)
+				return(-ESPIPE);
+*/		   
+		    if (!access_ok(VERIFY_WRITE, buffer, count))
+			return(-EFAULT);
+
+		    /* Down semaphore. */
+		    down(&s->sem);
+		    if (!s->recording.ready)
+		    {
+			/* Program recording buffer. */
+			ret = program_recording(s);
+			if (ret != 0)
+			    goto out_set_state;
+		    }
+		    add_wait_queue(&s->recording.wait, &wait);
+
+		    /* Loop while there are bytes to be read. */
+		    while (count > 0)
+		    {
+			/* Get number of bytes left in software buffer. */
+			spin_lock_irqsave(&s->lock, flags);
+			
+		       /*sw_ptr   current position in buffer*/
+			sw_ptr = s->recording.sw_ptr;        
+			byte_count = s->recording.sw_buffer_size - sw_ptr;
+			
+			/*error check*/
+			if (byte_count > s->recording.count)
+			    byte_count = s->recording.count;
+			if (byte_count <= 0)
+			    __set_current_state(TASK_INTERRUPTIBLE);
+			spin_unlock_irqrestore(&s->lock, flags);
+
+		    KDEBUG("sw_ptr=%d, sw_buffer_size=%d, s->recording.count=%d s->recording.threshold=%d \n", sw_ptr, s->recording.sw_buffer_size, s->recording.count, s->recording.threshold);
+			/* Don't overflow file buffer. */
+			if (byte_count > count)
+			    byte_count = count;
+			if (byte_count <= 0)
+			{
+			    /* Start recording. */
+			    if (s->recording.enabled)
+				start_recording(s,0);
+
+			/* For non-blocking I/O, return now. */
+			    if (file->f_flags & O_NONBLOCK)
+			    {
+				if (ret != 0)
+				    ret = -EAGAIN;
+				goto out_up;
+			    }
+
+		    KDEBUG("sm501_read: 5\n");
+			/* Up semaphore and reschedule. */
+			    up(&s->sem);
+			    schedule();
+			    if (signal_pending(current))
+			    {
+				if (ret != 0)
+				    ret = -ERESTARTSYS;
+				goto out_remove_queue;
+			    }
+
+			    /* Down semaphore again. */
+			    down(&s->sem);
+			}
+			else
+			{
+		    KDEBUG("sm501_read: 5.1\n");
+			
+			    /* Copy bytes from software buffer to file buffer. */
+			    //if (copy_to_user(buffer, s->recording.sw_buffer + sw_ptr,
+			    if (copy_to_user(pbuf, s->recording.sw_buffer + sw_ptr,
+					     byte_count))
+			    {
+				if (ret != 0)
+				    ret = -EFAULT;
+				goto out_up;
+			    }
+
+		    KDEBUG("sm501_read: 6\n");
+			    /* Update software buffer. */
+			    sw_ptr = (sw_ptr + byte_count) % s->recording.sw_buffer_size;
+			    spin_lock_irqsave(&s->lock, flags);
+			    s->recording.sw_ptr = sw_ptr;
+			    s->recording.count -= byte_count;
+			    spin_unlock_irqrestore(&s->lock, flags);
+
+			    /* Update file buffer. */
+			    count -= byte_count;
+			    //buffer += byte_count;
+			    pbuf += byte_count;
+			    ret += byte_count;
+
+			    /* Start recording if it was stopped. */
+			    if (s->recording.enabled)
+				start_recording(s,0);
+			}
+		    }
+
+		out_up:
+		    /* Up semaphore. */
+		    up(&s->sem);
+		out_remove_queue:
+		    remove_wait_queue(&s->recording.wait, &wait);
+		out_set_state:
+		    set_current_state(TASK_RUNNING);
+
+		    KDEBUG("sm501_read: 7\n");
+		    /* Return error or number of bytes read. */
+		    return(ret);
+		    //return(nonseekable_open(inode, file));
+		}
+
+static ssize_t sm501_oss_write(struct file* file, const char* buffer, size_t count, loff_t* ppos)
+		{
+		    sm501Ptr s = (sm501Ptr) file->private_data;
+		    wait_queue_t wait = __WAITQUEUE_INITIALIZER(wait, current);
+		    //DECLARE_WAITQUEUE(wait, current);
+		    ssize_t ret = 0;
+		    unsigned long flags;
+		    unsigned sw_ptr;
+		    int byte_count;
+
+		    VALIDATE_STATE(s);
+
+//		    KDEBUG("sm501_write: buffer=%d, count=%d\n", buffer, count);
+		    /* Verify file position and file buffer. */
+		    //if (ppos != &file->f_pos)
+		    //	return(-ESPIPE);
+		
+		    if (!access_ok(VERIFY_READ, buffer, count))
+			return(-EFAULT);
+
+		    /* Down semaphore. */
+		    down(&s->sem);
+		    if (!s->playing.ready)
+		    {
+			/* Program playing buffer. */
+			ret = program_playing(s);
+			if (ret != 0)
+			    goto out_set_state;
+		    }
+		    add_wait_queue(&s->playing.wait, &wait);
+
+		    /* Loop while bytes in file buffer. */
+		    while (count > 0)
+		    {
+			/* Get number of bytes left in software buffer. */
+			spin_lock_irqsave(&s->lock, flags);
+			if (s->playing.count < 0)
+			{
+			    /* Reset in case of error. */
+			    s->playing.count = 0;
+			    s->playing.sw_ptr = s->playing.hw_ptr;
+			}
+			sw_ptr = s->playing.sw_ptr;
+			byte_count = s->playing.sw_buffer_size - sw_ptr;
+			if (s->playing.count + byte_count > s->playing.sw_buffer_size)
+			    byte_count = s->playing.sw_buffer_size - s->playing.count;
+			if (byte_count <= 0)
+			    __set_current_state(TASK_INTERRUPTIBLE);
+			spin_unlock_irqrestore(&s->lock, flags);
+
+			/* Don't overflow file buffer. */
+			if (byte_count > count)
+			    byte_count = count;
+
+			if (byte_count <= 0)
+			{
+			    /* Start playing. */
+			    if (s->playing.enabled)
+				start_playing(s,0);
+
+			    /* For non-blocking I/O, return now. */
+			    if (file->f_flags & O_NONBLOCK)
+			    {
+				if (ret != 0)
+				    ret = -EAGAIN;
+				goto out_up;
+			    }
+
+			    /* Up semaphore and reschedule. */
+			    up(&s->sem);
+			    schedule();
+			    if (signal_pending(current))
+			    {
+				if (ret != 0)
+				    ret = -ERESTARTSYS;
+				goto out_remove_queue;
+			    }
+
+			    /* Down semaphore again. */
+			    down(&s->sem);
+			}
+			else
+			{
+			    /* Copy bytes from file buffer to software buffer. */
+			    if (copy_from_user(s->playing.sw_buffer + sw_ptr, buffer,
+					       byte_count))
+			    {
+				if (ret != 0)
+				    ret = -EFAULT;
+				goto out_up;
+			    }
+
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+		{
+			    int n = byte_count;
+			    if (n >= s->data_size - s->data_index)
+				n = s->data_size - s->data_index;
+			    copy_from_user(s->data + s->data_index, buffer, n);
+			    s->data_index += n;
+		}
+		#endif
+
+			    /* Update software buffer. */
+			    sw_ptr = (sw_ptr + byte_count) % s->playing.sw_buffer_size;
+			    spin_lock_irqsave(&s->lock, flags);
+			    s->playing.sw_ptr = sw_ptr;
+			    s->playing.count += byte_count;
+			    s->playing.endcleared = 0;
+			    spin_unlock_irqrestore(&s->lock, flags);
+
+			    /* Update file buffer. */
+			    count -= byte_count;
+			    buffer += byte_count;
+			    ret += byte_count;
+
+			    /* Start playing if it was stopped. */
+			    if (s->playing.enabled)
+				start_playing(s,0);
+			}
+		    }
+
+		out_up:
+		    /* Up semaphore. */
+		    up(&s->sem);
+		out_remove_queue:
+		    remove_wait_queue(&s->playing.wait, &wait);
+		out_set_state:
+		    set_current_state(TASK_RUNNING);
+
+		    /* Return error or number of bytes written. */
+		    return(ret);
+		}
+
+		static unsigned int sm501_oss_poll(struct file* file,
+					       struct poll_table_struct* wait)
+		{
+		    sm501Ptr s = (sm501Ptr) file->private_data;
+		    unsigned long flags;
+		    unsigned int mask = 0;
+
+		    VALIDATE_STATE(s);
+
+		    if (file->f_mode & FMODE_WRITE)
+		    {
+			if (!s->playing.ready && program_playing(s))
+			    return(0);
+			poll_wait(file, &s->playing.wait, wait);
+		    }
+		    if (file->f_mode & FMODE_READ)
+		    {
+			if (!s->recording.ready && program_recording(s))
+			    return(0);
+			poll_wait(file, &s->recording.wait, wait);
+		    }
+
+		    spin_lock_irqsave(&s->lock, flags);
+		    if (file->f_mode & FMODE_READ)
+		    {
+			if (s->recording.count >= s->recording.threshold)
+			    mask |= POLLIN | POLLRDNORM;
+		    }
+		    if (file->f_mode & FMODE_WRITE)
+		    {
+			if (s->playing.sw_buffer_size - s->playing.count >=  s->playing.threshold)
+			    mask |= POLLOUT | POLLWRNORM;
+		    }
+		    spin_unlock_irqrestore(&s->lock, flags);
+		    return(mask);
+		}
+
+		static int sm501_oss_ioctl(struct inode* inode, struct file* file, unsigned int cmd,
+				       unsigned long arg)
+		{
+		    sm501Ptr s = (sm501Ptr) file->private_data;
+		    unsigned long flags;
+		    audio_buf_info abinfo;
+		    count_info cinfo;
+		    int count, val, ret;
+
+		    VALIDATE_STATE(s);
+
+		    KDEBUG("sm501_ioctl:  -> %d\n", cmd);
+
+		    switch (cmd)
+		    {
+		    case OSS_GETVERSION:
+			return(put_user(SOUND_VERSION, (int*) arg));
+
+		    case SNDCTL_DSP_SYNC:
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_SYNC\n");
+			if (file->f_mode & FMODE_WRITE)
+			    return(drain_playing(s, 0));
+			return(0);
+
+		    case SNDCTL_DSP_SETDUPLEX:
+//			return 0;
+			return(-EINVAL);
+
+		    case SNDCTL_DSP_GETCAPS:
+			return(put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER, (int*) arg));
+
+		    case SNDCTL_DSP_RESET:
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_RESET\n");
+			if (file->f_mode & FMODE_WRITE)
+			{
+			    stop_playing(s);
+			    synchronize_irq(s->irq);
+			    s->playing.sw_ptr = s->playing.hw_ptr = 0;
+			    s->playing.count = s->playing.total_bytes = 0;
+			}
+			if (file->f_mode & FMODE_READ)
+			{
+			    stop_recording(s);
+			    synchronize_irq(s->irq);
+			    s->recording.sw_ptr = s->recording.hw_ptr = 0;
+			    s->recording.count = s->recording.total_bytes = 0;
+			}
+
+			return(0);
+
+		    case SNDCTL_DSP_SPEED:
+			if (get_user(val, (int*) arg))
+			    return(-EFAULT);
+			
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_SPEED %d\n", val);
+			if (val >= 0)
+			{
+			    if (file->f_mode & FMODE_READ)
+			    {
+				stop_recording(s);
+				s->recording.ready = 0;
+		#ifdef CONFIG_SOUND_SM501_VBR
+				set_recording_rate(s, val);
+		#endif
+			    }
+			    if (file->f_mode & FMODE_WRITE)
+			    {
+				stop_playing(s);
+				s->playing.ready = 0;
+		#ifdef CONFIG_SOUND_SM501_VBR
+				set_playing_rate(s, val);
+		#endif
+			    }
+			}
+
+			return(put_user((file->f_mode & FMODE_READ) ? s->recording.rate :
+					s->playing.rate, (int*) arg));
+
+		    case SNDCTL_DSP_STEREO:
+			if (get_user(val, (int*) arg))
+			    return(-EFAULT);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_STEREO %d\n", val);
+			if (file->f_mode & FMODE_READ)
+			{
+			    stop_recording(s);
+			    s->recording.ready = 0;
+			    spin_lock_irqsave(&s->lock, flags);
+			    s->recording.channels = (val != 0) ? 2 : 1;
+			    spin_unlock_irqrestore(&s->lock, flags);
+			}
+			if (file->f_mode & FMODE_WRITE)
+			{
+			    stop_playing(s);
+			    s->playing.ready = 0;
+			    spin_lock_irqsave(&s->lock, flags);
+			    s->playing.channels = (val != 0) ? 2 : 1;
+			    spin_unlock_irqrestore(&s->lock, flags);
+			}
+
+			return(0);
+
+		    case SNDCTL_DSP_CHANNELS:
+			if (get_user(val, (int*) arg))
+			    return(-EFAULT);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_CHANNELS %d\n", val);
+			if (val != 0)
+			{
+			    if (file->f_mode & FMODE_READ)
+			    {
+				stop_recording(s);
+				s->recording.ready = 0;
+				spin_lock_irqsave(&s->lock, flags);
+				s->recording.channels = (val >= 2) ? 2 : 1;
+				spin_unlock_irqrestore(&s->lock, flags);
+			    }
+			    if (file->f_mode & FMODE_WRITE)
+			    {
+				stop_playing(s);
+				s->playing.ready = 0;
+				spin_lock_irqsave(&s->lock, flags);
+				s->playing.channels = (val >= 2) ? 2 : 1;
+				spin_unlock_irqrestore(&s->lock, flags);
+			    }
+			}
+
+			return(put_user((file->f_mode & FMODE_READ) ? s->recording.channels :
+					s->playing.channels, (int*) arg));
+
+		    case SNDCTL_DSP_GETFMTS:
+			return(put_user(AFMT_S16_LE | AFMT_U8, (int*) arg));
+
+		    case SNDCTL_DSP_SETFMT:
+			if (get_user(val, (int*) arg))
+			    return(-EFAULT);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_SETFMT %d\n", val);
+			if (val != AFMT_QUERY)
+			{
+			    if (file->f_mode & FMODE_READ)
+			    {
+				stop_recording(s);
+				s->recording.ready = 0;
+				spin_lock_irqsave(&s->lock, flags);
+				s->recording.bits = (val == AFMT_S16_LE) ? 16 : 8;
+				spin_unlock_irqrestore(&s->lock, flags);
+			    }
+			    if (file->f_mode & FMODE_WRITE)
+			    {
+				stop_playing(s);
+				s->playing.ready = 0;
+				spin_lock_irqsave(&s->lock, flags);
+				s->playing.bits = (val == AFMT_S16_LE) ? 16 : 8;
+				spin_unlock_irqrestore(&s->lock, flags);
+			    }
+			}
+
+			return(put_user((((file->f_mode & FMODE_READ) ? s->recording.bits :
+					s->playing.bits) == 16) ? AFMT_S16_LE : AFMT_U8,
+					(int*) arg));
+
+		    case SNDCTL_DSP_POST:
+			return(0);
+
+		    case SNDCTL_DSP_GETTRIGGER:
+			val = 0;
+			if ((file->f_mode & FMODE_READ) && s->recording.running)
+			    val |= PCM_ENABLE_INPUT;
+			if ((file->f_mode & FMODE_WRITE) && s->playing.running)
+			    val |= PCM_ENABLE_OUTPUT;
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETTRIGGER -> 0x%x\n", val);
+			return(put_user(val, (int*) arg));
+
+		    case SNDCTL_DSP_SETTRIGGER:
+			if (get_user(val, (int*) arg))
+			    return(-EFAULT);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
+			if (file->f_mode & FMODE_READ)
+			{
+			    if (val & PCM_ENABLE_INPUT)
+			    {
+				if (!s->recording.ready)
+				{
+				    ret = program_recording(s);
+				    if (ret != 0)
+					return(ret);
+				}
+
+				s->recording.enabled = 1;
+				start_recording(s,0);
+			    }
+			    else
+			    {
+				s->recording.enabled = 0;
+				stop_recording(s);
+			    }
+			}
+			if (file->f_mode & FMODE_WRITE)
+			{
+			    if (val & PCM_ENABLE_OUTPUT)
+			    {
+				if (!s->playing.ready)
+				{
+				    ret = program_playing(s);
+				    if (ret != 0)
+					return(ret);
+				}
+
+				s->playing.enabled = 1;
+				start_playing(s,0);
+			    }
+			    else
+			    {
+				s->playing.enabled = 0;
+				stop_playing(s);
+			    }
+			}
+
+			return(0);
+
+		    case SNDCTL_DSP_GETOSPACE:
+			if (!(file->f_mode & FMODE_WRITE))
+			    return(-EINVAL);
+
+			if (!s->playing.ready)
+			{
+			    ret = program_playing(s);
+			    if (ret != 0)
+				return(ret);
+			}
+
+			spin_lock_irqsave(&s->lock, flags);
+			abinfo.fragsize = s->playing.threshold;
+			count = s->playing.count;
+			if (count < 0)
+			    count = 0;
+			abinfo.bytes = s->playing.sw_buffer_size - count;
+			abinfo.fragstotal = s->playing.sw_buffer_size / abinfo.fragsize;
+			abinfo.fragments = abinfo.bytes / abinfo.fragsize;
+			spin_unlock_irqrestore(&s->lock, flags);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETOSPACE -> fragsize=%d,bytes=%d\n",
+			       abinfo.fragsize, abinfo.bytes);
+			if (copy_to_user((void*) arg, &abinfo, sizeof(abinfo)))
+			    return(-EFAULT);
+			return(0);
+
+		    case SNDCTL_DSP_GETISPACE:
+			if (!(file->f_mode & FMODE_READ))
+			    return(-EINVAL);
+
+			if (!s->recording.ready)
+			{
+			    ret = program_recording(s);
+			    if (ret != 0)
+				return(ret);
+			}
+
+			spin_lock_irqsave(&s->lock, flags);
+			abinfo.fragsize = s->recording.threshold;
+			count = s->recording.count;
+			if (count < 0)
+			    count = 0;
+			abinfo.bytes = count;
+			abinfo.fragstotal = s->recording.sw_buffer_size / abinfo.fragsize;
+			abinfo.fragments = abinfo.bytes / abinfo.fragsize;
+			spin_unlock_irqrestore(&s->lock, flags);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETISPACE -> fragsize=%d,bytes=%d\n",
+			       abinfo.fragsize, abinfo.bytes);
+			if (copy_to_user((void*) arg, &abinfo, sizeof(abinfo)))
+			    return(-EFAULT);
+			return(0);
+
+		    case SNDCTL_DSP_NONBLOCK:
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_NONBLOCK\n");
+			file->f_flags |= O_NONBLOCK;
+			return(0);
+
+		    case SNDCTL_DSP_GETODELAY:
+			if (!(file->f_mode & FMODE_WRITE))
+			    return(-EINVAL);
+
+			if (!s->playing.ready)
+			{
+			    ret = program_playing(s);
+			    if (ret != 0)
+				return(ret);
+			}
+
+			spin_lock_irqsave(&s->lock, flags);
+			count = s->playing.count;
+			spin_unlock_irqrestore(&s->lock, flags);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETODELAY -> %d\n", count);
+			return(put_user(count, (int*) arg));
+
+		    case SNDCTL_DSP_GETIPTR:
+			if (!(file->f_mode & FMODE_READ))
+			    return(-EINVAL);
+
+			if (!s->recording.ready)
+			{
+			    ret = program_recording(s);
+			    if (ret != 0)
+				return(ret);
+			}
+
+			spin_lock_irqsave(&s->lock, flags);
+			cinfo.bytes = s->recording.total_bytes;
+			count = s->recording.count;
+			if (count < 0)
+			    count = 0;
+			cinfo.blocks = count / s->recording.threshold;
+			cinfo.ptr = s->recording.hw_ptr;
+			spin_unlock_irqrestore(&s->lock, flags);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETIPTR -> bytes=%d,block=%d,ptr=%u\n",
+			       cinfo.bytes, cinfo.blocks, cinfo.ptr);
+			if (copy_to_user((void*) arg, &cinfo, sizeof(cinfo)))
+			    return(-EFAULT);
+			return(0);
+
+		    case SNDCTL_DSP_GETOPTR:
+			if (!(file->f_mode & FMODE_WRITE))
+			    return(-EINVAL);
+
+			if (!s->playing.ready)
+			{
+			    ret = program_playing(s);
+			    if (ret != 0)
+				return(ret);
+			}
+
+			spin_lock_irqsave(&s->lock, flags);
+			cinfo.bytes = s->playing.total_bytes;
+			count = s->playing.count;
+			if (count < 0)
+			    count = 0;
+			cinfo.blocks = count / s->playing.threshold;
+			cinfo.ptr = s->playing.hw_ptr;
+			spin_unlock_irqrestore(&s->lock, flags);
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETOPTR -> bytes=%d,block=%d,ptr=%u\n",
+			       cinfo.bytes, cinfo.blocks, cinfo.ptr);
+			if (copy_to_user((void*) arg, &cinfo, sizeof(cinfo)))
+			    return(-EFAULT);
+			return(0);
+
+		    case SNDCTL_DSP_GETBLKSIZE:
+			val = 0;
+
+			if (file->f_mode & FMODE_WRITE)
+			{
+			    ret = program_playing(s);
+			    if (ret != 0)
+				return(ret);
+
+			    val = s->playing.threshold;
+			}
+
+			if (file->f_mode & FMODE_READ)
+			{
+			    ret = program_recording(s);
+			    if (ret != 0)
+				return(ret);
+
+			    val = s->recording.threshold;
+			}
+
+			KDEBUG("sm501_ioctl: SNDCTL_DSP_GETBLKSIZE -> %d\n", val);
+			return(put_user(val, (int*) arg));
+
+		    case SNDCTL_DSP_SETFRAGMENT:
+//			return 0;				
+		    case SNDCTL_DSP_SUBDIVIDE:
+		    case SNDCTL_DSP_SETSYNCRO:
+			return(-EINVAL);
+
+		    case SOUND_PCM_READ_RATE:
+			return(put_user((file->f_mode & FMODE_READ) ? s->recording.rate :
+					s->playing.rate, (int*) arg));
+
+		    case SOUND_PCM_READ_CHANNELS:
+			return(put_user((file->f_mode & FMODE_READ) ? s->recording.channels :
+					s->playing.channels, (int*) arg));
+
+		    case SOUND_PCM_READ_BITS:
+			return(put_user((file->f_mode & FMODE_READ) ? s->recording.bits :
+					s->playing.bits, (int*) arg));
+
+		    case SOUND_PCM_WRITE_FILTER:
+		    case SOUND_PCM_READ_FILTER:
+			return(-EINVAL);
+		    }
+
+		    return(s->codec->mixer_ioctl(s->codec, cmd, arg));
+		}
+
+static int sm501_oss_open(struct inode* inode, struct file* file)
+		{
+		    int minor = MINOR(inode->i_rdev);
+		    //int minor = iminor(inode);
+		    DECLARE_WAITQUEUE(wait, current);
+		    unsigned long flags;
+		    sm501Ptr s = host_data;
+		    unsigned int value;
+
+		    VALIDATE_STATE(s);
+
+		    if (((s->dev_audio ^ minor) & ~0xF))
+			return(-ENODEV);
+
+		    file->private_data = s;
+
+		    down(&s->open_sem);
+		    while (s->open_mode & file->f_mode)
+		    {
+			KDEBUG("device already in use, waiting...\n");
+
+			if (file->f_flags & O_NONBLOCK)
+			{
+			    up(&s->open_sem);
+			    return(-EBUSY);
+			}
+			add_wait_queue(&s->open_wait, &wait);
+			__set_current_state(TASK_INTERRUPTIBLE);
+			up(&s->open_sem);
+			schedule();
+			remove_wait_queue(&s->open_wait, &wait);
+			set_current_state(TASK_RUNNING);
+			if (signal_pending(current))
+			    return(-ERESTARTSYS);
+			down(&s->open_sem);
+		    }
+		    if (file->f_mode & FMODE_READ)
+		    {
+		    //AC97_RECMUX_MIC
+//		    	value = read_codec_wrapper(s->codec, AC97_AUX_VOL );    //06h
+//			KDEBUG("sm501 aux vol: %d \n", value);
+//			write_codec_wrapper(s->codec, AC97_AUX_VOL , 0x8000 );
+
+//		    	value = read_codec_wrapper(s->codec, AC97_LINEIN_VOL );    //06h
+//			KDEBUG("sm501 linein vol: %d \n", value);
+//			write_codec_wrapper(s->codec, AC97_LINEIN_VOL , 0x8000 );
+
+//		    	value = read_codec_wrapper(s->codec, AC97_MASTER_VOL_MONO );    //06h
+//			KDEBUG("sm501 mono vol: %d \n", value);
+//			write_codec_wrapper(s->codec,AC97_MASTER_VOL_MONO , 0x0020 );
+
+		//	value = read_codec_wrapper(s->codec, AC97_PCBEEP_VOL );    //0ah
+		//	KDEBUG("sm501 pc beep: %d \n", value);
+		//	write_codec_wrapper(s->codec, AC97_PCBEEP_VOL, value | 0x8000 );
+
+	// Write the stereo analog lines volume.
+		//	write_codec_wrapper(s->codec, AC97_LINEIN_VOL, 0x0808);
+
+			// Set up the record mux for line input.
+		//	write_codec_wrapper(s->codec, AC97_RECORD_SELECT, AC97_RECMUX_MIC);
+
+			// Enable variable rate control.
+		//	write_codec_wrapper(s->codec, AC97_HEADPHONE_VOL, 0x3F3F);
+
+
+		//	value = read_codec_wrapper(s->codec, AC97_RECORD_GAIN_MIC);    //1eh
+		//	KDEBUG("sm501 pcm mic adc rate: %d \n", value);
+		//	value = 0x0808;
+		//	write_codec_wrapper(s->codec, AC97_RECORD_GAIN_MIC, value);
+
+//		   	value = read_codec_wrapper(s->codec, AC97_PCM_LR_ADC_RATE);    //32h
+//			KDEBUG("sm501 pcm L/R adc rate: %d \n", value);
+//			value = 44100;
+//			write_codec_wrapper(s->codec, AC97_PCM_LR_ADC_RATE, value);
+
+//		   	value = read_codec_wrapper(s->codec, AC97_PCM_MIC_ADC_RATE);    //34h
+//			KDEBUG("sm501 pcm mic adc rate: %d \n", value);
+//			value = 44100;
+//			write_codec_wrapper(s->codec, AC97_PCM_MIC_ADC_RATE, value);
+
+		    	value = read_codec_wrapper(s->codec, AC97_RECORD_SELECT  );          // 1eh
+			KDEBUG("sm501 record select: %d \n", value);
+			write_codec_wrapper(s->codec, AC97_RECORD_SELECT , AC97_RECMUX_MIC );
+
+			// Set up a default record gain.
+   		       write_codec_wrapper(s->codec, AC97_RECORD_GAIN, 0x0);
+
+		    	value = read_codec_wrapper(s->codec, AC97_GENERAL_PURPOSE);    //20h
+			KDEBUG("sm501 general purpose: %d \n", value);
+			write_codec_wrapper(s->codec, AC97_GENERAL_PURPOSE, value&~0x0100);
+
+		   	value = read_codec_wrapper(s->codec, AC97_EXTENDED_STATUS);        // 2ah
+			KDEBUG("sm501 extened status: %d \n", value);
+			write_codec_wrapper(s->codec, AC97_EXTENDED_STATUS,
+			                 value | AC97_EXTSTAT_VRA | AC97_EXTSTAT_VRM);
+
+			s->recording.enabled = 1;
+			set_recording_rate(s, 48000);//11025);                                  //32h
+
+		    }
+		    if (file->f_mode & FMODE_WRITE)
+		    {
+			KDEBUG("sm501 open play: \n");
+			//hxp add
+			s->playing.enabled = 1;
+			set_playing_rate(s, 48000);
+		    }
+
+		    spin_lock_irqsave(&s->lock, flags);
+		    if (file->f_mode & FMODE_READ)
+		    {
+			KDEBUG("sm501 open record: 1\n");
+			//hxp add
+			s->recording.bits = ((minor & 0xF) == SND_DEV_DSP16) ? 16 : 8;
+			s->recording.channels = 1;
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			s->data_index = 0;
+		#endif			
+		    }
+			
+		    if (file->f_mode & FMODE_WRITE)
+		    {
+			KDEBUG("sm501 open play: 1 \n");
+			//hxp add
+			s->playing.bits = ((minor & 0xF) == SND_DEV_DSP16) ? 16 : 8;
+			s->playing.channels = 1;
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			s->data_index = 0;
+		#endif
+		    }
+		    spin_unlock_irqrestore(&s->lock, flags);
+
+		    s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
+		    up(&s->open_sem);
+		    init_MUTEX(&s->sem);
+			KDEBUG("sm501 open success!\n");
+			//hxp add
+		    return(nonseekable_open(inode, file));
+		    //return(0);
+		}
+
+		static int sm501_oss_release(struct inode* inode, struct file* file)
+		{
+		    sm501Ptr s = (sm501Ptr) file->private_data;
+		    VALIDATE_STATE(s);
+
+		    KDEBUG("release: file=%p\n", file);
+
+		    lock_kernel();
+		    if (file->f_mode & FMODE_WRITE)
+			drain_playing(s, file->f_flags & O_NONBLOCK);
+
+		    down(&s->open_sem);
+		    if (file->f_mode & FMODE_WRITE)
+		    {
+			stop_playing(s);
+			dealloc_buffer(s, &s->playing);
+		    KDEBUG("release play\n");
+		    }
+		    if (file->f_mode & FMODE_READ)
+		    {
+			stop_recording(s);
+			dealloc_buffer(s, &s->recording);
+		    KDEBUG("release record\n");
+		    }
+		    s->open_mode &= ~(file->f_mode & (FMODE_READ | FMODE_WRITE));
+		    up(&s->open_sem);
+
+		    wake_up(&s->open_wait);
+		    unlock_kernel();
+		    return(0);
+		}
+
+		static struct file_operations sm501_audio_fops =
+		{
+		    .owner=      THIS_MODULE,
+		    .llseek=     no_llseek,
+		    .read=       sm501_oss_read,
+		    .write=      sm501_oss_write,
+		    .poll=       sm501_oss_poll,
+		    .ioctl=      sm501_oss_ioctl,
+		    .open=       sm501_oss_open,
+		    .release=    sm501_oss_release,
+		};
+
+		/* --------------------------------------------------------------------- */
+
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+		#define DUMP(msg, args...) \
+		do { \
+		    len += sprintf(buf + len, msg, ##args); \
+		    if (len >= limit) \
+		    { \
+			*start = buf; \
+			return(len); \
+		    } \
+		} while (0)
+
+		static int proc_sm501_dump(char* buf, char** start, off_t fpos, int length,
+					   int* eof, void* data)
+		{
+		    sm501Ptr s;
+		    int i, len = 0;
+		    int limit = length - 80;
+
+		    s = data;
+		    if (s == NULL)
+		    {
+			*eof = 1;
+			return(0);
+		    }
+
+		    /* Print out header. */
+		    DUMP("Silicon Motion SM501 Debug Dump-o-matic\n");
+		    DUMP("=======================================\n");
+
+		    /* Print out PCI config space. */
+/*
+		    if (s->dev != NULL)
+		    {
+			DUMP("  PCI Configuration space:\n");
+			for (i = 0; i < 64; i += 4)
+			{
+			    unsigned int value;
+			    pci_read_config_dword(s->dev, i, &value);
+			    if ((i & 15) == 0)
+				DUMP("    %02x:", i);
+			    DUMP(" %08x", value);
+			    if ((i & 15) == 12)
+				DUMP("\n");
+			}
+		    }
+*/
+		    /* Print out some registers. */
+		    DUMP("  Register dump:\n");
+		    DUMP("    SYSTEM_CONTROL:        %08x\n", SmRead32(SYSTEM_CTRL));
+		    DUMP("    MISCELLANEOUS_CONTROL: %08x\n", SmRead32(MISC_CTRL));
+		    DUMP("    GPIO_CONTROL_LOW:      %08x\n", SmRead32(GPIO_CONTROL_LOW));
+		    DUMP("    INTERRUPT_STATUS:      %08x\n", SmRead32(INTERRUPT_STATUS));
+		    DUMP("    INTERRUPT_MASK:        %08x\n", SmRead32(INTERRUPT_MASK));
+		    DUMP("    CURRENT_GATE:          %08x\n", SmRead32(CURRENT_GATE));
+		    DUMP("    CURRENT_CLOCK:         %08x\n", SmRead32(CURRENT_POWER_CLOCK));
+		    DUMP("    MISCELLANEOUS_TIMING:  %08x\n", SmRead32(MISCELLANEOUS_TIMING));
+		    DUMP("    U8051_RESET:           %08x\n", SmRead32(U8051_RESET));
+		    DUMP("    U8051_MODE_SELECT:     %08x\n", SmRead32(U8051_MODE_SELECT));
+
+		    /* Print out some SRAM. */
+/*
+		    DUMP("  SRAM dump:\n");
+		    for (i = 0; i < 64; i++)
+		    {
+			if ((i & 7) == 0)
+			    DUMP("    %05x:", SRAM(ac97_regs[i]));
+			if ((i & 7) == 4)
+			    DUMP(" ");
+			DUMP(" %04x", SmRead16(SRAM(ac97_regs[i])));
+			if ((i & 7) == 7)
+			    DUMP("\n");
+		    }
+
+		    for (i = SRAM(command_byte); i <= SRAM(init_count); i++)
+		    {
+			if ((i & 15) == 0)
+			    DUMP("    %05x:", i);
+			if ((i & 15) == 8)
+			    DUMP(" ");
+			DUMP(" %02x", SmRead8(i));
+			if ((i & 15) == 15)
+			    DUMP("\n");
+		    }
+			DUMP("\n");
+*/
+		    /* Print out the codec state. */
+/*			
+		    DUMP("  AC97 CODEC state:\n");
+		    for (i = 0; i < 0x80; i += 2)
+		    {
+			if ((i & 15) == 0)
+			    DUMP("    %02x:", i);
+			if ((i & 15) == 8)
+			    DUMP(" ");
+			DUMP(" %04x", read_codec_wrapper(s->codec, i));
+			if ((i & 15) == 14)
+			    DUMP("\n");
+		    }
+*/
+		    *eof = 1;
+		    return(len);
+
+		}
+		static int proc_AC97_dump(char* buf, char** start, off_t fpos, int length,
+					   int* eof, void* data)
+		{
+		    sm501Ptr s;
+		    int i, len = 0;
+		    int limit = length - 80;
+
+		    s = data;
+		    if (s == NULL)
+		    {
+			*eof = 1;
+			return(0);
+		    }
+
+		    /* Print out header. */
+		
+		    DUMP("  AC97 CODEC state:\n");
+		    for (i = 0; i < 0x70; i += 2)
+		    {
+			if ((i & 15) == 0)
+			    DUMP("    %02x:", i);
+			if ((i & 15) == 8)
+			    DUMP(" ");
+			DUMP(" %04x", read_codec_wrapper(s->codec, i));
+			if ((i & 15) == 14)
+			    DUMP("\n");
+		    }
+
+		    *eof = 1;
+		    return(len);
+			
+		}
+		static int proc_sm501_sample(char* buf, char** start, off_t fpos, int length,
+					     int* eof, void* data)
+		{
+		    sm501Ptr s;
+		    int len = 0;
+		    int limit = length - 80;
+		    static int i, j;
+
+		    s = data;
+		    if (s == NULL)
+		    {
+			*eof = 1;
+			return(0);
+		    }
+
+		    /* Print out header. */
+		    if (fpos == 0)
+		    {
+			DUMP("Silicon Motion SM501 Sample Debug Dump-o-matic\n");
+			DUMP("==============================================\n");
+			i = j = 0;
+		    }
+
+		    if (j == 0)
+		    {
+			/* Print out the sample buffer. */
+			if (i == 0)
+			    DUMP("  Sample buffer: %d samples.\n", s->sample_index);
+
+			for (i &= ~3; i < s->sample_index; i++)
+			{
+			    if ((i & 3) == 0) DUMP("\r%9d:", i);
+			    DUMP(" %08x", s->samples[i]);
+			    if ((i & 3) == 3) DUMP("\n");
+			}
+
+			/* Print out the data buffer. */
+			i = 0;
+			j = 1;
+			DUMP("\n  Data buffer: %d bytes.\n", s->data_index);
+		    }
+
+		    for (i &= ~15; i < s->data_index; i++)
+		    {
+			if ((i & 15) == 0) DUMP("\r%9d:", i);
+			if ((i & 15) == 8) DUMP(" ");
+			DUMP(" %02x", s->data[i]);
+			if ((i & 15) == 15) DUMP("\n");
+		    }
+
+		    *eof = 1;
+		    return(len);
+		}
+		#endif
+
+		static struct initvol
+		{
+		    int mixch;
+		    int vol;
+		}
+		initvol[] __initdata =
+		{
+		    { SOUND_MIXER_WRITE_LINE, 0x4040 },
+		    { SOUND_MIXER_WRITE_CD, 0x4040 },
+		    { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
+		    { SOUND_MIXER_WRITE_LINE1, 0x4040 },
+		    { SOUND_MIXER_WRITE_PCM, 0x4040 },
+		    { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
+		    { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
+		    { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
+		    { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
+		    { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
+		    { SOUND_MIXER_WRITE_MIC, 0x4040 },
+		    { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
+		    { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
+		};
+
+		static unsigned int __devinit ascii_hex(const char* text, int* index, int count)
+		{
+		    /* Initialize result. */
+		    unsigned int result = 0;
+
+		    /* Convert nibbles. */
+		    while (count-- > 0)
+		    {
+			/* Get Ascii nibble. */
+			char c = text[*index];
+
+			/* Convert from Ascii into hex. */
+			if (c >= '0' && c <= '9')
+			    c -= '0';
+			else if (c >= 'A' && c <= 'F')
+			    c -= 'A' - 10;
+			else if (c >= 'a' && c <= 'f')
+			    c -= 'a' - 10;
+			else
+			    /* Invalid digits, return 0. */
+			    return 0;
+
+			/* Add nibble to result. */
+			result = (result << 4) | c;
+
+			/* Increment string index. */
+			(*index)++;
+		    }
+
+		    /* Return result. */
+		    return result;
+		}
+
+static int __devinit load_firmware(sm501Ptr s, const char* firmware)
+{
+	unsigned int value;
+	int i, errors, retry=1;
+
+	/* Put 8051 in reset state. */
+	value = SET_FIELD(0, U8051_RESET_CONTROL, RESET);
+	SmWrite32( U8051_RESET, value);
+
+	/* Retry loop for loading firmware. */
+	for (retry = 1; retry <= 1; retry++)
+	{
+		KDEBUG("loading firmware: retry %d\n", retry);
+
+		/* Reset error count. */
+		errors = 0;
+
+		/* !!BUGBUG!! Settle down 8051 or SRAM, seems to be required. */
+		mdelay(250);
+
+		/* Zero SRAM. */
+		SmMemset(U8051_SRAM, 0, U8051_SRAM_SIZE);
+
+		/* Walk entire firmware. */
+		for (i = 0; i < strlen(firmware);)
+		{
+			unsigned int bytes, address, finish;
+
+			/* Skip colon (start of line). */
+			if (firmware[i] != ':')
+			{
+				KERROR("invalid firmware character '%c'\n",
+				       firmware[i]);
+				break;
+			}
+			i++;
+
+			/* Get number of bytes (first byte). */
+			bytes = ascii_hex(firmware, &i, 2);
+
+			/* Get address (second and third byte). */
+			address = ascii_hex(firmware, &i, 4);
+
+			/* Get finish flag (fourth byte). */
+			finish = ascii_hex(firmware, &i, 2);
+
+			/* Loop through all bytes. */
+			while (bytes-- > 0)
+			{
+				/* Get byte. */
+				unsigned int value = ascii_hex(firmware,
+						&i, 2);
+
+				/* Write byte into SRAM address. */
+				SmWrite8( U8051_SRAM + address,
+						value);
+				if (SmRead8( U8051_SRAM + address)
+								!= value)
+				{
+					if (errors++ < 10)
+					{
+						KWARNING("%04x: mismatch: "
+								"code(%02x) "
+								"sram(%02x)\n",
+						address, value,
+						SmRead8( U8051_SRAM + address));
+					}
+				}
+
+				/* Increment address. */
+				address++;
+			}
+
+			/* Skip checksum. */
+			i += 2;
+
+			/* Finish when end of data. */
+			if (finish != 0)
+				break;
+		}
+
+		if (errors == 0)
+			break;
+	}
+
+	if (errors > 0)
+		return(-EFAULT);
+
+	/* Enable 8051. */
+	value = SET_FIELD(0, U8051_RESET_CONTROL, ENABLE);
+	SmWrite32( U8051_RESET, value);
+
+	/* Wait until the init is complete. During its initialization the
+	firmware will increment the "init counter" twice, so that when the
+	counter becomes 2, we know that the initialization is complete. */
+	
+	i = 5000;
+	while (SmRead8( SRAM(init_count)) != 2)
+	{
+		if (i-- <= 0)
+		{
+			KERROR("firmware timed out during reset\n");
+			return(-ETIME);
+		}
+		mdelay(1);
+	}
+
+	KDEBUG("firmware loaded and running\n");
+	return 0;
+}
+
+static int sm501_oss_remove(struct platform_device * pdev)
+		{
+		    unsigned int value;
+		    sm501Ptr s = NULL;
+
+		    s = platform_get_drvdata(pdev);
+		    platform_set_drvdata(pdev, s->dev);
+		
+		    KDEBUG("cleanup: s=%p\n", s);
+		    if (s == NULL)
+			return;
+
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+		    if (s->ps != NULL)
+			remove_proc_entry("driver/sm501_audio", NULL);
+		    if (s->ac97ps != NULL)
+			remove_proc_entry("driver/sm501_ac97", NULL);			
+		#endif
+
+		    if (s->irq)
+		    {
+			/* Remove interrupt service handler. */
+		       synchronize_irq(s->irq);
+			free_irq(s->irq, s);
+		    }
+
+		    if (s->dev_audio != 0)
+		    {
+			/* Unregister device. */
+			unregister_sound_dsp(s->dev_audio);
+		    }
+
+		    if (s->codec != NULL)
+		    {
+			/* Unregister mixer device. */
+			if (s->codec->dev_mixer != -1)
+			    unregister_sound_mixer(s->codec->dev_mixer);
+
+			/* Release codec. */
+			ac97_release_codec(s->codec);
+		    }
+
+		    if (s->io != NULL)
+		    {
+			/* Disable 8051 interrupt mask. */
+			value = SmRead32(INTERRUPT_MASK);
+			value = SET_FIELD(value, INTERRUPT_MASK_8051, DISABLE);
+			SmWrite32(INTERRUPT_MASK, value);
+
+			/* Put 8051 in reset state. */
+			value = SmRead32(U8051_RESET);
+			value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+			SmWrite32(U8051_RESET, value);
+
+			/* Disable SRAM. */
+			value = SmRead32(U8051_MODE_SELECT);
+			value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, DISABLED);
+			SmWrite32(U8051_MODE_SELECT, value);
+
+			/* Reset GPIO lines. */
+			value = SmRead32(GPIO_CONTROL_LOW);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+			SmWrite32(GPIO_CONTROL_LOW, value);
+
+			/* Disable 8051 and AC97. */
+			value = SmRead32(CURRENT_GATE);
+			value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, DISABLE);
+			value = SET_FIELD(value, CURRENT_GATE_8051, DISABLE);
+			sm501_set_gate( value);
+
+		    }
+
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+		    if (s->sample_ps != NULL)
+			remove_proc_entry("driver/sm501sample", NULL);
+		    if (s->samples != NULL)
+			kfree(s->samples);
+		    if (s->data != NULL)
+			kfree(s->data);
+		#endif
+
+		    /* Free state structure. */
+		    kfree(s);
+		    KDEBUG("cleanup: done\n");
+}
+
+
+static int sm501_oss_probe(struct platform_device *pdev)
+{
+		    mm_segment_t fs;
+		    unsigned int value, clock;
+		    int res = -1, i=0,ret=0;
+		    struct device  *pcidev = NULL;
+		    sm501Ptr s = NULL;
+
+		    KDEBUG("SM501 audio -- probe:\n");
+
+			s = kmalloc(sizeof(sm501Rec),GFP_KERNEL);
+
+	   	      if (s == NULL)
+	 	      {
+			  KERROR("out of memory\n");
+			  return(-ENOMEM);
+			}
+	             memset(s, 0, sizeof(sm501Rec));
+
+			s->dev = pcidev = platform_get_drvdata(pdev);
+			platform_set_drvdata(pdev, s);
+
+		    /* Store state structure pointer. */
+			host_data = s;
+
+			/* Allocate codec. */
+			s->codec = ac97_alloc_codec();
+			if (s->codec == NULL)
+			    goto failed;
+			KDEBUG("codec mixer: %d\n", s->codec->dev_mixer);
+			s->codec->dev_mixer = -1;
+
+			/* Initialize some queues and stuff. */
+			init_waitqueue_head(&s->playing.wait);
+			init_waitqueue_head(&s->recording.wait);
+			init_waitqueue_head(&s->open_wait);
+			init_MUTEX(&s->open_sem);
+			spin_lock_init(&s->lock);
+
+			s->irq = platform_get_irq(pdev, 0);
+			if (s->irq < 0) {
+				/* we currently do not use the IRQ */
+				KERROR( "no irq for device\n");
+				return s->irq;
+			}
+
+			/* Initial audio chip interrupt     */
+			ret = request_irq(s->irq, &sm501_interrupt, IRQF_SHARED,"sm501_audio", s);
+			if (ret < 0) {
+				KERROR( "inital sm501_audio: unable to get irq %d\n",s->irq);
+				return ret;
+			}
+		
+			/* Initialize codec stuff. */
+			s->codec->private_data = s;
+			s->codec->id = 0;
+			s->codec->codec_read = read_codec_wrapper;
+			s->codec->codec_write = write_codec_wrapper;
+			s->codec->codec_wait = wait_codec;
+
+			/* Register device. */
+			res = s->dev_audio = register_sound_dsp(&sm501_audio_fops, -1);
+			if (res < 0)
+				goto failed;
+				res = s->codec->dev_mixer = register_sound_mixer(&sm501_mixer_fops, -1);
+			if (res < 0)
+				goto failed;
+				KDEBUG("registered mixer %d\n", s->codec->dev_mixer);
+
+		#ifdef CONFIG_SOUND_SM501_DEBUG
+			/* Intialize the debug proc device. */
+			s->ps = create_proc_read_entry("driver/sm501_audio", 0, NULL, proc_sm501_dump, s);
+
+			s->ac97ps = create_proc_read_entry("driver/sm501_ac97", 0, NULL, proc_AC97_dump, s);
+
+			s->sample_size = 32768;
+			s->samples = kmalloc(s->sample_size * sizeof(int), GFP_KERNEL);
+			if (s->samples == NULL)
+			{
+			    KWARNING("unable to allocate %d-entry sample buffer\n",
+				     s->sample_size);
+			    s->sample_size = 0;
+			}
+			else
+			{
+			    s->data_size = 16384;
+			    s->data = kmalloc(s->data_size, GFP_KERNEL);
+			    if (s->data == NULL)
+			    {
+				KWARNING("unable to allocate %d-byte data buffer\n",	 s->data_size);
+				s->data_size = 0;
+			    }
+
+			    s->sample_ps = create_proc_read_entry("driver/sm501sample", 0, NULL,
+								  proc_sm501_sample, s);
+			}
+		#endif
+
+
+			value = SmRead32(GPIO_CONTROL_LOW);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_28, AC97_RX_I2S);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_27, AC97_TX_I2S);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_26, AC97_CLOCK_I2S);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_25, AC97_SYNC_I2S);
+			value = SET_FIELD(value, GPIO_CONTROL_LOW_24, AC97_RESET);
+			SmWrite32(GPIO_CONTROL_LOW, value);
+
+	
+			// Set arbitartion control.
+			value = SmRead32(ARBITRATION_CONTROL);
+			value = SET_FIELD(value, ARBITRATION_CONTROL_DMA, PRIORITY_1);
+			SmWrite32(ARBITRATION_CONTROL, value);
+	
+			value = SmRead32(INTERRUPT_MASK);
+			value = SET_FIELD(value, INTERRUPT_MASK_8051, ENABLE);
+			value = SET_FIELD(value, INTERRUPT_MASK_DMA, ENABLE);
+			SmWrite32(INTERRUPT_MASK, value);
+
+			/* Initialize chip. */
+			value = SmRead32(CURRENT_GATE);
+			value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, ENABLE);
+			value = SET_FIELD(value, CURRENT_GATE_8051, ENABLE);
+			value = SET_FIELD(value, CURRENT_GATE_HOST_COMMAND_LIST_DMA, ENABLE);
+			value = SET_FIELD(value, CURRENT_GATE_GPIO_PWM_I2C, ENABLE);
+			sm501_set_gate(value);
+			
+			value = SmRead32(U8051_MODE_SELECT);
+			value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, ENABLED);
+			value = SET_FIELD(value, U8051_MODE_SELECT_TEST_MODE, NORMAL);
+			value = SET_FIELD(value, U8051_MODE_SELECT_CODEC_SELECT, AC97);
+			value = SET_FIELD(value, U8051_MODE_SELECT_DIVIDER, 2);
+			SmWrite32(U8051_MODE_SELECT, value);
+
+			/* Initialize firmware. */
+			res = load_firmware(s, FIRMWARE);
+			if (res < 0)
+			    goto failed;
+			
+			/* Codec init. */
+			if (!ac97_probe_codec(s->codec))
+			{
+			    KERROR("ac97_probe_codec failed\n");
+			    res = -ENODEV;
+			    goto failed;
+			}
+
+//			InitCodec(s);
+			/* Determine variable bit rate support. */
+	//		value = AC97_EA_VRM | AC97_EA_VRA;
+	//		write_codec_wrapper(s->codec, AC97_EXTENDED_STATUS, value);
+			value = read_codec_wrapper(s->codec, AC97_EXTENDED_ID);
+
+			s->playing.vbr = (value & AC97_EA_VRA) ? 1 : 0;
+			s->recording.vbr = (value & AC97_EA_VRM) ? 1 : 0;
+
+			/* Enable variable bit rate. */
+			value &= AC97_EA_VRA | AC97_EA_VRM;
+			write_codec_wrapper(s->codec, AC97_EXTENDED_STATUS, value);
+			//KDEBUG("vbr for playing=%d, recording=%d\n", s->playing.vbr,
+			KDEBUG("vbr for playing=%d, recording=%d\n", s->playing.vbr,
+			       s->recording.vbr);
+			
+		    	value = read_codec_wrapper(s->codec, AC97_MIC_VOL);            //0eh
+			KDEBUG("sm501 mic vol: %x \n", value);
+			write_codec_wrapper(s->codec, AC97_MIC_VOL, value|0x8000&~0x40);
+
+		       SmWrite8(SRAM(buffer_status), 0x0);
+			   
+			/* Set default values. */
+			fs = get_fs();
+			set_fs(KERNEL_DS);
+			value = SOUND_MASK_LINE;
+			s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
+					      (unsigned long) &value);
+			for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++)
+			{
+			    value = initvol[i].vol;
+			    s->codec->mixer_ioctl(s->codec, initvol[i].mixch,
+						  (unsigned long) &value);
+			}
+			set_fs(fs);
+			return(0);
+
+		failed:
+		    /* Uninitialize anything we have done so far. */
+		    sm501_oss_remove(pdev);
+		    KDEBUG("probe: error=%d\n", res);
+		    return(res);
+}
+
+
+static struct platform_driver sm501_ac97_driver = {
+			.remove		= sm501_oss_remove,
+			.probe		= sm501_oss_probe,
+			.driver		= {
+			.name	= "sm501-audio",
+				.owner	= THIS_MODULE,
+			},
+};
+
+static int __devinit sm501_oss_init(void)
+{
+    return platform_driver_register(&sm501_ac97_driver);
+}
+
+static void __exit sm501_oss_cleanup(void)
+{
+	platform_driver_unregister(&sm501_ac97_driver);
+}
+
+
+module_init(sm501_oss_init);
+module_exit(sm501_oss_cleanup);
+
+		
+MODULE_AUTHOR("Frido Garritsen, Boyod Yang");
+MODULE_DESCRIPTION("SM501 OSS Driver");
+MODULE_LICENSE("Dual BSD/GPL");
+
diff -uNra linux-2.6.27.6/sound/pci/ac97/ac97_codec.c linux-2.6.27.6.yaffs/sound/pci/ac97/ac97_codec.c
--- linux-2.6.27.6/sound/pci/ac97/ac97_codec.c	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/pci/ac97/ac97_codec.c	2011-05-08 18:06:20.000000000 +0800
@@ -123,7 +123,8 @@
 { 0x414c4780, 0xfffffff0, "ALC658",		patch_alc655,	NULL },
 { 0x414c4790, 0xfffffff0, "ALC850",		patch_alc850,	NULL },
 { 0x414c4730, 0xffffffff, "ALC101",		NULL,		NULL },
-{ 0x414c4740, 0xfffffff0, "ALC202",		NULL,		NULL },
+//{ 0x414c4740, 0xfffffff0, "ALC202",		NULL,		NULL },  //mj
+{ 0x414c4740, 0xfffffff0, "ALC202mj",		patch_alc655,		NULL },//mj
 { 0x414c4750, 0xfffffff0, "ALC250",		NULL,		NULL },
 { 0x414c4770, 0xfffffff0, "ALC203",		NULL,		NULL },
 { 0x434d4941, 0xffffffff, "CMI9738",		patch_cm9738,	NULL },
diff -uNra linux-2.6.27.6/sound/pci/Kconfig linux-2.6.27.6.yaffs/sound/pci/Kconfig
--- linux-2.6.27.6/sound/pci/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/pci/Kconfig	2011-05-08 18:06:19.000000000 +0800
@@ -258,7 +258,7 @@
 
 config SND_CS5535AUDIO
 	tristate "CS5535/CS5536 Audio"
-	depends on X86 && !X86_64
+	depends on SND
 	select SND_PCM
 	select SND_AC97_CODEC
 	help
diff -uNra linux-2.6.27.6/sound/soc/Kconfig linux-2.6.27.6.yaffs/sound/soc/Kconfig
--- linux-2.6.27.6/sound/soc/Kconfig	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/Kconfig	2011-05-08 18:06:18.000000000 +0800
@@ -31,6 +31,7 @@
 source "sound/soc/fsl/Kconfig"
 source "sound/soc/davinci/Kconfig"
 source "sound/soc/omap/Kconfig"
+source "sound/soc/sm501/Kconfig"
 
 # Supported codecs
 source "sound/soc/codecs/Kconfig"
diff -uNra linux-2.6.27.6/sound/soc/Makefile linux-2.6.27.6.yaffs/sound/soc/Makefile
--- linux-2.6.27.6/sound/soc/Makefile	2008-11-14 01:56:21.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/Makefile	2011-05-08 18:06:18.000000000 +0800
@@ -3,3 +3,4 @@
 obj-$(CONFIG_SND_SOC)	+= snd-soc-core.o
 obj-$(CONFIG_SND_SOC)	+= codecs/ at32/ at91/ pxa/ s3c24xx/ sh/ fsl/ davinci/
 obj-$(CONFIG_SND_SOC)	+= omap/ au1x/
+obj-$(CONFIG_SND_SOC)	+= sm501/
diff -uNra linux-2.6.27.6/sound/soc/sm501/audfw.hex linux-2.6.27.6.yaffs/sound/soc/sm501/audfw.hex
--- linux-2.6.27.6/sound/soc/sm501/audfw.hex	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/audfw.hex	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,129 @@
+#define FIRMWARE \
+":030000000206876E" \
+":10068700787FE4F6D8FD9030007F007E10E4F0A379" \
+":0A069700DFFCDEFA7581321202BFAB" \
+":1002BF0075E80675F804D2AFC2ADC2ACC2ABC2AA24" \
+":1002CF00C2A9C2A8E4903FFFF0F52CF52B909180C6" \
+":1002DF0004F0E4909100F0A37480F0E4909105F0A5" \
+":1002EF00A3F0909108F0A3F0A3F090910CF0A3F07D" \
+":1002FF00A37408F0E4909110F0A3F0A37408F0E455" \
+":10030F00909141F0909140F0909146F0909145F08E" \
+":10031F00909144F090914AF0909149F0909148F06B" \
+":10032F0090918004F0909141E030E7F9903FFFE029" \
+":10033F0004F0903FF0740FF0903FF27400F0A3744C" \
+":10034F0060F0A3740AF0903FF6E47A04F0A3DAFCAD" \
+":10035F001204C5903FF6E055F060D7903FFFE004E0" \
+":10036F00F0E52C452B7009E52A60F61204C580F1E3" \
+":10037F00E52C452B60EBE52A60F61204C580F122CF" \
+":0F06F800903FF3E0909101F0903FF17401F022F8" \
+":1006A100903FF3E0FC903FF4E0909106F0909105CB" \
+":0906B100ECF0903FF17401F0221D" \
+":1005D100903FF2E0FC903FF3E0FD903FF4E090911A" \
+":1005E1000AF0ED909109F0EC909108F0903FF174D0" \
+":0305F10001F022F4" \
+":0D071600752800752930903FF17401F02224" \
+":1005F400903FF2E0FC903FF3E0F51F8C1E903FF437" \
+":10060400E0FC903FF5E0F5218C20903FF17401F07F" \
+":0106140022C3" \
+":1006D100903FF2E05403F9903FFCE049F0903FF184" \
+":0406E1007401F0228E" \
+":10061500903FFCE0FEA3E0FF903FF2E0FAA3E08A02" \
+":0F06250082F583EEF0EFA3F0903FF17401F02225" \
+":10063400903FF2E05401600B752B01752800752979" \
+":0D064400308003752B00903FF17401F0220F" \
+":0F070700909141E0903FF3F0903FF17401F022A8" \
+":1006BA00909145E0FCA3E0903FF4F0903FF3ECF01A" \
+":0706CA00903FF17401F022E2" \
+":10065100909148E0FCA3E0FDA3E0903FF2ECF0A311" \
+":0B066100EDF0A3F0903FF17401F022D7" \
+":0D0723007526F8752737903FF17401F0221C" \
+":10066C00903FF2E522F0A3E523F0903FF4E524F06F" \
+":0B067C00A3E525F0903FF17401F0228F" \
+":1006E500903FF2E044CFF9903FFCE059903FF17420" \
+":0306F50001F022EF" \
+":10058500903FF2E054016016903D20E4F07A07A315" \
+":10059500F0DAFC752600752736752C018027752C39" \
+":1005A50000E5269439F9E527400C752200850323DB" \
+":1005B500F5248925800F752400752503E5279436D4" \
+":0C05C500F523752200903FF1740EF02227" \
+":10044F0090910812055400000000903FF2E0FCA3C9" \
+":10045F00E0FDA3E0FEA3E0FF909104120548909108" \
+":10046F0001E044E0F0909106E0903D07F0E4F52DB7" \
+":10047F00F52EAE2DAF2EEE3395E0FDFC7B807A3856" \
+":10048F0079017800D31205324024909141E05460F5" \
+":10049F00600A909141E0903D06F08012909141E00A" \
+":1004AF00903D06F0052EE52E70C8052D80C4909165" \
+":0604BF0001E05498F02258" \
+":10038F00E4909108F0909109F090910AF0903FF26B" \
+":10039F00E0FCA3E0FDA3E09091064408F0909105E6" \
+":1003AF00EDF0909104ECF0909101E044E0F0E4F571" \
+":1003BF002FF530AE2FAF30EE3395E0FDFC7B807A1A" \
+":1003CF003879017800D31205325003020418909146" \
+":1003DF0001E044E0F0909141E05460602190910180" \
+":1003EF00E05498F0909148E0F9A3E0FAA3E0903F31" \
+":1003FF00F8F0903FF7EAF0903FF6E9F0800B053008" \
+":10040F00E5307002052F0203C2E4F52FF530AE2F51" \
+":10041F00AF30EE3395E0FDFC7B807A3879017800C0" \
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diff -uNra linux-2.6.27.6/sound/soc/sm501/Kconfig linux-2.6.27.6.yaffs/sound/soc/sm501/Kconfig
--- linux-2.6.27.6/sound/soc/sm501/Kconfig	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/Kconfig	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,27 @@
+config SND_SM501_SOC
+	tristate "SoC Audio for the Silion Motion SM501 chips"
+	depends on MFD_SM501 && SND_SOC
+	select SND_PCM
+	select SND_DRIVER_OWN_BUF
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the SM501 AC97 or I2S interface. You will also need
+	  to select the audio interfaces to support below.
+
+# config SND_SM501_SOC_I2S
+#	tristate
+
+config SND_SM501_SOC_AC97
+	tristate
+	select AC97_BUS
+	select SND_AC97_CODEC
+	select SND_SOC_AC97_BUS
+
+config SND_SM501_SOC_AC97_DEVICE
+	tristate "SoC AC97 Audio support SM501"
+	depends on SND_SM501_SOC
+	select SND_SM501_SOC_AC97
+	select SND_SOC_AC97_CODEC
+	help
+	  Say Y if you want to add support for SoC audio on SM501 AC97.
+
diff -uNra linux-2.6.27.6/sound/soc/sm501/Makefile linux-2.6.27.6.yaffs/sound/soc/sm501/Makefile
--- linux-2.6.27.6/sound/soc/sm501/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/Makefile	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,7 @@
+snd-soc-sm501-objs := sm501-pcm.o
+snd-soc-sm501-ac97-objs := sm501-ac97.o sm501-u8051.o
+snd-soc-sm501-ac97-dev-objs := sm501-ac97-dev.o
+
+obj-$(CONFIG_SND_SM501_SOC) += snd-soc-sm501.o
+obj-$(CONFIG_SND_SM501_SOC_AC97) += snd-soc-sm501-ac97.o
+obj-$(CONFIG_SND_SM501_SOC_AC97_DEVICE) += snd-soc-sm501-ac97-dev.o
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-ac97.c linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-ac97.c
--- linux-2.6.27.6/sound/soc/sm501/sm501-ac97.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-ac97.c	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,722 @@
+/*
+ * AC97 support for SM50X chipsets
+ *
+ * Based on Silicon Motion drivers
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <asm/irq.h>
+#include <linux/mutex.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+
+#include "sm501-ac97.h"
+#include "sm501-pcm.h"
+#include "sm501-u8051.h"
+#include "audfw.hex"
+
+/*
+ * Register address in the firmware
+ */
+#define SET_TX_SLOT_0                    0
+#define SET_TX_SLOT_1                    1
+#define SET_TX_SLOT_2                    2
+#define SET_PLAYBACK_BUFFER_ADDRESS      3
+#define SET_PLAYBACK_BUFFER_SIZE         4
+#define SET_PLAYBACK_BUFFER_READY        5
+#define GET_BUFFER_STATUS                6
+#define START_STOP_AUDIO_PLAYBACK        7
+#define GET_RX_SLOT0                     8
+#define GET_RX_SLOT1                     9
+#define GET_RX_SLOT2                    10
+#define SET_CAPTURE_BUFFER_ADDRESS      11
+#define SET_CAPTURE_BUFFER_SIZE         12
+#define SET_CAPTIRE_BUFFER_EMPTY        13
+#define START_STOP_AUDIO_CAPTURE        14
+#define SET_GET_AC97_REGISTER           15
+
+#define DRV_NAME			"sm501-audio"
+
+static int debug        = 0;
+#define dprintk(msg...) if (debug) { printk(KERN_DEBUG DRV_NAME ": " msg); }
+static struct sm501_audio *audio_dev;
+
+static void sm501_write_codec(struct sm501_audio *s, u8 addr, u16 data)
+{
+	unsigned int read_back;
+
+	//dprintk("%s: addr=%02x data=%04x\n", __func__, addr, data);
+
+	/* Write Codec register. */
+	if (!sm501_write_command(s, SET_GET_AC97_REGISTER, (unsigned int) addr << 12,
+	     (unsigned int) data << 4) && (addr != AC97_RESET))
+	{
+		//if write failed 
+		read_back = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+					SmRead8(SRAM(data_byte[5]))),
+					MAKEWORD(SmRead8(SRAM(data_byte[6])),
+					SmRead8(SRAM(data_byte[7])))) >> 4;
+
+		/*
+		 * Not dev_err here because the firmware returns an error
+		 * for R/O or not defined registers
+		 */
+		printk(s->dev, "%s failed: addr=%02x data=%04x read_back=%04x\n",
+			__func__, addr, data, read_back);
+	}
+	else
+	{	
+		printk(s->dev, "%s ok: addr=%02x data=%04x\n",
+		__func__, addr, data);
+	}
+}
+
+#if 1
+static u16 sm501_read_codec(struct sm501_audio * s,u8 addr)
+{
+	int failed;
+	u32 data;
+
+	//according to the implement of firmware,we can't tell if the read operate okay or not
+	//read command always return a 1 value
+	//but put the failed flag here for futhure nice upgrade
+	failed = !sm501_write_command(s,SET_GET_AC97_REGISTER,(u32)(addr<<12)|(1<<19),0);	
+	data = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+			SmRead8(SRAM(data_byte[5]))),
+			MAKEWORD(SmRead8(SRAM(data_byte[6])),
+			SmRead8(SRAM(data_byte[7])))) >> 4;
+	
+	if(failed)
+	{	
+		//read codec register failed
+		printk("%s: failed: addr=%02x data=%04x status=%02x\n", __func__, addr,data,SmRead8(SRAM(status_byte)));
+	}
+	return (u16)data;
+}
+#else
+static u16 sm501_read_codec(struct sm501_audio *s, u8 addr)
+{
+	unsigned int data;
+	int i;
+
+	/* Read Codec register. */
+	if (sm501_write_command(s, SET_GET_AC97_REGISTER,
+	    (unsigned int) (addr << 12) | (1 << 19), 0)) {
+		data = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+				SmRead8(SRAM(data_byte[5]))),
+				MAKEWORD(SmRead8(SRAM(data_byte[6])),
+				SmRead8(SRAM(data_byte[7])))) >> 4;
+	} else {
+		/* Read register from SRAM in case link failes. */
+		for (i = SM501_AC97_CODEC_TIMEOUT; i > 0; i--) {
+			data = SmRead16(SRAM(ac97_regs[addr >> 1]));
+			if (data != 0xFFFF)
+				break;
+			msleep(1);
+		}
+
+		dev_err(s->dev, "%s failed: addr=%02x sram=%04x\n", __func__, addr, data);
+	}
+
+	dprintk("%s: data=%04x\n", __func__, data);
+	return((unsigned short) data);
+}
+#endif
+/*
+ * AC97 functions
+ */
+static unsigned short snd_sm501_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
+{
+	unsigned int data;
+	unsigned long value;
+	unsigned long flags;
+	unsigned long i;
+
+	spin_lock_irqsave(&audio_dev->lock, flags);
+
+	if (audio_dev->firmware_loaded) {
+		data = sm501_read_codec(audio_dev, reg);
+	} else {
+
+		SmWrite32(AC97_TX_SLOT2, 0);
+
+		value = (unsigned long) reg << 12;
+		value = SET_FIELD(value, AC97_TX_SLOT1_READ_WRITE, READ);
+		SmWrite32(AC97_TX_SLOT1, value);
+
+		/* Enable Slot 0, 1, 2 for read */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_FRAME_TAG,
+				  INTERPRET);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+
+		udelay(150);
+
+		for (i = SM501_AC97_CODEC_TIMEOUT; i> 0; i--)
+		{
+			if (TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+			    AC97_RX_SLOT0_CODEC_READY_FLAG, READY))
+			{
+				if ((TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+				     AC97_RX_SLOT0_VALID_S1,
+				     DATA)) &&
+					 (TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+						     AC97_RX_SLOT0_VALID_S2, DATA)))
+					break;
+			}
+			udelay(1);
+		}
+		if (i == 0)
+			dev_err(audio_dev->dev, "%s: AC97 timeout\n", __func__);
+
+
+		data = SmRead32(AC97_RX_SLOT2);
+		data = GET_FIELD(data, AC97_RX_SLOT2_DATA);
+
+		/* Reset Slot 1,2 */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, NO_DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, NO_DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+	}
+
+	spin_unlock_irqrestore(&audio_dev->lock, flags);
+
+	return((unsigned short) data);
+}
+
+static snd_sm501_ac97_wait_codec(struct snd_ac97 * ac97)
+{
+	int i;
+	u16 data;
+	unsigned long flags;
+
+	spin_lock_irqsave(&audio_dev->lock, flags);
+	for(i=0;i<1000;i++)
+	{
+		data = sm501_read_codec(audio_dev,AC97_POWERDOWN);
+		if(data & 2)
+			break;
+	}
+	spin_unlock_irqrestore(&audio_dev->lock, flags);
+}
+
+
+static void snd_sm501_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+				 unsigned short val)
+{
+	unsigned long flags;
+	unsigned long value;
+	unsigned long i;
+
+	spin_lock_irqsave(&audio_dev->lock, flags);
+
+	if (audio_dev->firmware_loaded) {
+		sm501_write_codec(audio_dev, reg, val);
+	} else {
+		value = (unsigned long) reg << 12;
+		SmWrite32(AC97_TX_SLOT1, value);
+
+		value = ((unsigned int) val << 4);
+		SmWrite32(AC97_TX_SLOT2, value);
+
+		/* Enable Slot 0, 1, 2 for write */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_FRAME_TAG,
+				  INTERPRET);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+		for (i = SM501_AC97_CODEC_TIMEOUT; i> 0; i--)
+		{
+			if (TEST_FIELD(SmRead32(
+			    AC97_RX_SLOT0),AC97_RX_SLOT0_CODEC_READY_FLAG,
+			READY))
+			{
+				if ((TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+				     AC97_RX_SLOT0_VALID_S1,
+				     NO_DATA)) &&
+				(TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+						     AC97_RX_SLOT0_VALID_S2,
+						     NO_DATA)))
+					break;
+			}
+			udelay(1);
+		}
+		if (i == 0)
+			dev_err(audio_dev->dev, "%s: AC97 timeout\n", __func__);
+
+		/* Reset Slot 1,2 */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, NO_DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, NO_DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+	}
+
+	spin_unlock_irqrestore(&audio_dev->lock, flags);
+}
+
+static void snd_sm501_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+#warning FILL ME
+}
+
+static void snd_sm501_ac97_cold_reset(struct snd_ac97 *ac97)
+{
+#warning FILL ME
+}
+
+
+struct snd_ac97_bus_ops soc_ac97_ops = {
+	.read		= snd_sm501_ac97_read,
+	.write		= snd_sm501_ac97_write,
+	.warm_reset	= snd_sm501_ac97_warm_reset,
+	.reset		= snd_sm501_ac97_cold_reset,
+	.wait	= snd_sm501_ac97_wait_codec,
+};
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+static struct sm501_pcm_dma_params sm501_ac97_pcm_stereo_out;
+static struct sm501_pcm_dma_params sm501_ac97_pcm_stereo_in;
+
+/* hw_params callback */
+static int snd_sm501_ac97_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		cpu_dai->dma_data = &sm501_ac97_pcm_stereo_out;
+	else
+		cpu_dai->dma_data = &sm501_ac97_pcm_stereo_in;
+
+	return 0;
+}
+static int snd_sm501_ac97_prepare(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	int reg;
+	u16 vra;
+
+	vra = sm501_read_codec(audio_dev, AC97_EXTENDED_STATUS);
+	sm501_write_codec(audio_dev, AC97_EXTENDED_STATUS, vra | AC97_EA_VRA);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		reg = AC97_PCM_FRONT_DAC_RATE;
+	 else
+		reg = AC97_PCM_LR_ADC_RATE;
+
+	 sm501_write_codec(audio_dev, reg, runtime->rate);
+	 return 0;
+}
+
+static int snd_sm501_ac97_probe(struct platform_device *pdev)
+{
+	struct device   *dev = &pdev->dev;
+	struct resource *res;
+	int retry = 0;
+	int ret = 0;
+	int res_len;
+	unsigned long value;
+
+	audio_dev = kzalloc(sizeof(struct sm501_audio), GFP_KERNEL);
+	if (!audio_dev) {
+		dev_err(dev, "Allocation failure\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	audio_dev->dev = dev;
+	//monk add
+	audio_dev->hw_buffer_addr = SmIoAddress() + 0xC3000;
+	
+	sm501_ac97_pcm_stereo_out.s = audio_dev;
+	sm501_ac97_pcm_stereo_in.s = audio_dev;
+
+	/* Get irq number */
+//audio_dev->irq = 37; //platform_get_irq(pdev, 0);
+//mj chang
+	audio_dev->irq = 36; //platform_get_irq(pdev, 0);
+	if (!audio_dev->irq) {
+		dev_err(dev, "no irq found\n");
+		ret = -ENODEV;
+		goto err_alloc;
+	}
+
+	/* Get regs address */
+	res = (struct resource *)kzalloc(sizeof(struct resource), GFP_KERNEL);
+	if (res == NULL) {
+		dev_err(dev, "No memory resource found\n");
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+restart:
+
+//Reset AC97 codec
+
+	/* Put 8051 in reset state. */
+        value = SmRead32(U8051_RESET);
+        value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+        SmWrite32(U8051_RESET, value);
+
+        /* Reset GPIO lines. */
+        value = SmRead32(GPIO_CONTROL_LOW);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+        SmWrite32(GPIO_CONTROL_LOW, value);
+
+        /*Force GPIO28/SDIN GPIO27/SDOUT GPIO26/BIT_CLK GPIO25/SYNC to low*/
+        value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_28, OUTPUT);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_27, OUTPUT);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_26, OUTPUT);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_25, OUTPUT);
+        SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+        value = SmRead32(GPIO_DATA_LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_28, LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_27, LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_26, LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_25, LOW);
+        SmWrite32(GPIO_DATA_LOW, value);
+
+
+        /*Force GPIO24/AC97 Reset to low*/
+        value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+        SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+        value = SmRead32(GPIO_DATA_LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_24, LOW);
+        SmWrite32(GPIO_DATA_LOW, value);
+        msleep(10);
+
+        /*Force GPIO24/AC97 Reset to high*/
+        value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+        SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+    
+        value = SmRead32(GPIO_DATA_LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_24, HIGH);
+        SmWrite32(GPIO_DATA_LOW, value);
+
+////////////////////
+	value = SmRead32(GPIO_CONTROL_LOW);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_28, AC97_RX_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_27, AC97_TX_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_26, AC97_CLOCK_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_25, AC97_SYNC_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_24, AC97_RESET);
+	SmWrite32(GPIO_CONTROL_LOW, value);
+
+	/* Set arbitartion control */
+	value = SmRead32(ARBITRATION_CONTROL);
+	value = SET_FIELD(value, ARBITRATION_CONTROL_DMA, PRIORITY_1);
+	SmWrite32(ARBITRATION_CONTROL, value);
+
+	/* Enable interrupts */
+	value = SmRead32(INTERRUPT_MASK);
+	value = SET_FIELD(value, INTERRUPT_MASK_8051, ENABLE);
+	value = SET_FIELD(value, INTERRUPT_MASK_DMA, ENABLE);
+	SmWrite32(INTERRUPT_MASK, value);
+
+	/* Initialize chip. */
+	value = SmRead32(CURRENT_GATE);
+	value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, ENABLE);
+	value = SET_FIELD(value, CURRENT_GATE_8051, ENABLE);
+	value = SET_FIELD(value, CURRENT_GATE_HOST_COMMAND_LIST_DMA, ENABLE);
+	value = SET_FIELD(value, CURRENT_GATE_GPIO_PWM_I2C, ENABLE);
+	sm501_set_gate(value);
+
+	value = SmRead32(U8051_MODE_SELECT);
+	value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, ENABLED);
+	value = SET_FIELD(value, U8051_MODE_SELECT_TEST_MODE, NORMAL);
+	value = SET_FIELD(value, U8051_MODE_SELECT_CODEC_SELECT, AC97);
+	value = SET_FIELD(value, U8051_MODE_SELECT_DIVIDER, 2);
+	SmWrite32(U8051_MODE_SELECT, value);
+
+
+	value = SmRead32(AC97_CONTROL_STATUS);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_CONTROL, ENABLED);
+	SmWrite32(AC97_CONTROL_STATUS, value);
+
+	/*
+	 * We're failing here but one should be able to use the codec
+	 * without firmware according to the manual
+	 */
+	ret = sm501_load_firmware(audio_dev, FIRMWARE);
+	if (ret < 0) {
+		dev_err(dev, "Error while loading firmware (%d)\n", ret);
+		if(retry++ < 5) /* If load error, retry it */
+			goto restart;
+		goto err;
+	}
+
+	audio_dev->firmware_loaded = 1;
+	//monk add below,y not init the lock here
+	spin_lock_init(&audio_dev->lock);
+
+	dev_info(dev, "SM501 AC97 Found\n");
+	return 0;
+
+err_alloc:
+	kfree(audio_dev);
+err:
+	return ret;
+}
+
+static void snd_sm501_ac97_remove(struct platform_device *pdev)
+{
+	unsigned int value;
+
+	kfree(audio_dev);
+
+	/* Disable 8051 interrupt mask. */
+	value = SmRead32(INTERRUPT_MASK);
+	value = SET_FIELD(value, INTERRUPT_MASK_8051, DISABLE);
+	SmWrite32(INTERRUPT_MASK, value);
+
+
+	/* Put 8051 in reset state. */
+	value = SmRead32(U8051_RESET);
+	value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+	SmWrite32(U8051_RESET, value);
+
+	/* Disable SRAM. */
+	value = SmRead32(U8051_MODE_SELECT);
+	value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, DISABLED);
+	SmWrite32(U8051_MODE_SELECT, value);
+
+	/* Reset GPIO lines. */
+	value = SmRead32(GPIO_CONTROL_LOW);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+	SmWrite32(GPIO_CONTROL_LOW, value);
+
+	/* Disable 8051 and AC97. */
+	value = SmRead32(CURRENT_GATE);
+	value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, DISABLE);
+	value = SET_FIELD(value, CURRENT_GATE_8051, DISABLE);
+	sm501_set_gate(value);
+}
+
+static int snd_sm501_ac97_suspend (struct platform_device *pdev) {
+    
+    printk("SM502 AC97 Suspend....\n");
+
+    unsigned int value;
+    /* Disable 8051 interrupt mask. */
+    value = SmRead32(INTERRUPT_MASK);
+    value = SET_FIELD(value, INTERRUPT_MASK_8051, DISABLE);
+    SmWrite32(INTERRUPT_MASK, value);
+
+    /* Put 8051 in reset state. */
+    value = SmRead32(U8051_RESET);
+    value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+    SmWrite32(U8051_RESET, value);
+
+    /* Disable SRAM. */
+    value = SmRead32(U8051_MODE_SELECT);
+    value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, DISABLED);
+    SmWrite32(U8051_MODE_SELECT, value);
+
+    /* Reset GPIO lines. */
+    value = SmRead32(GPIO_CONTROL_LOW);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+    SmWrite32(GPIO_CONTROL_LOW, value);
+
+    /* Disable 8051 and AC97. */
+    value = SmRead32(CURRENT_GATE);
+    value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, DISABLE);
+    value = SET_FIELD(value, CURRENT_GATE_8051, DISABLE);
+    sm501_set_gate(value);
+    audio_dev->firmware_loaded = 0;
+}
+
+
+static int snd_sm501_ac97_resume (struct platform_device *pdev) {
+    struct device   *dev = &pdev->dev;
+    struct resource *res;
+    int ret = 0;
+    int res_len;
+    unsigned long value;
+
+    printk("SM502 AC97 Resume\n");
+
+    //Reset AC97 codec
+
+    /* Put 8051 in reset state. */
+    value = SmRead32(U8051_RESET);
+    value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+    SmWrite32(U8051_RESET, value);
+
+    /* Reset GPIO lines. */
+    value = SmRead32(GPIO_CONTROL_LOW);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+    SmWrite32(GPIO_CONTROL_LOW, value);
+
+    /*Force GPIO28/SDIN GPIO27/SDOUT GPIO25/SYNC to low*/
+    value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_28, OUTPUT);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_27, OUTPUT);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_25, OUTPUT);
+    SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+    value = SmRead32(GPIO_DATA_LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_28, LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_27, LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_25, LOW);
+    SmWrite32(GPIO_DATA_LOW, value);
+
+
+    /*Force GPIO24/AC97 Reset to low*/
+    value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+    SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+    value = SmRead32(GPIO_DATA_LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_24, LOW);
+    SmWrite32(GPIO_DATA_LOW, value);
+    msleep(10);
+
+    /*Force GPIO24/AC97 Reset to high*/
+    value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+    SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+    value = SmRead32(GPIO_DATA_LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_24, HIGH);
+    SmWrite32(GPIO_DATA_LOW, value);
+
+
+    ////////////////////
+    value = SmRead32(GPIO_CONTROL_LOW);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_28, AC97_RX_I2S);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_27, AC97_TX_I2S);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_26, AC97_CLOCK_I2S);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_25, AC97_SYNC_I2S);
+    //	value = SET_FIELD(value, GPIO_CONTROL_LOW_24, SM501_AC97_RESET);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_24, AC97_RESET);
+    SmWrite32(GPIO_CONTROL_LOW, value);
+
+    /* Set arbitartion control */
+    value = SmRead32(ARBITRATION_CONTROL);
+    value = SET_FIELD(value, ARBITRATION_CONTROL_DMA, PRIORITY_1);
+    SmWrite32(ARBITRATION_CONTROL, value);
+
+    /* Enable interrupts */
+    value = SmRead32(INTERRUPT_MASK);
+    value = SET_FIELD(value, INTERRUPT_MASK_8051, ENABLE);
+    value = SET_FIELD(value, INTERRUPT_MASK_DMA, ENABLE);
+    SmWrite32(INTERRUPT_MASK, value);
+
+    /* Initialize chip. */
+    value = SmRead32(CURRENT_GATE);
+    value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, ENABLE);
+    value = SET_FIELD(value, CURRENT_GATE_8051, ENABLE);
+    value = SET_FIELD(value, CURRENT_GATE_HOST_COMMAND_LIST_DMA, ENABLE);
+    value = SET_FIELD(value, CURRENT_GATE_GPIO_PWM_I2C, ENABLE);
+    sm501_set_gate(value);
+
+    value = SmRead32(U8051_MODE_SELECT);
+    value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, ENABLED);
+    value = SET_FIELD(value, U8051_MODE_SELECT_TEST_MODE, NORMAL);
+    value = SET_FIELD(value, U8051_MODE_SELECT_CODEC_SELECT, AC97);
+    value = SET_FIELD(value, U8051_MODE_SELECT_DIVIDER, 2);
+    SmWrite32(U8051_MODE_SELECT, value);
+
+    value = SmRead32(AC97_CONTROL_STATUS);
+    value = SET_FIELD(value, AC97_CONTROL_STATUS_CONTROL, ENABLED);
+    SmWrite32(AC97_CONTROL_STATUS, value);
+
+    /*
+     * We're failing here but one should be able to use the codec
+     * without firmware according to the manual
+     */
+    ret = sm501_load_firmware(audio_dev, FIRMWARE);
+    if (ret < 0) {
+        dev_err(dev, "Error while loading firmware (%d)\n", ret);
+    }
+
+    audio_dev->firmware_loaded = 1;
+
+    return 0;
+}
+
+
+
+struct snd_soc_dai sm501_ac97_dai[] = {{
+	.name = DRV_NAME,
+	.id = 0,
+	.type = SND_SOC_DAI_AC97,
+	.probe = snd_sm501_ac97_probe,
+	.remove = snd_sm501_ac97_remove,
+	.suspend = snd_sm501_ac97_suspend,
+        .resume = snd_sm501_ac97_resume,
+	.playback = {
+		.stream_name = "AC97 Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_48000, /* SNDRV_PCM_RATE_8000_48000,*/
+		/* change to be with be systems */
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
+	.capture = {
+		.stream_name = "AC97 Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
+	.ops = {
+		.hw_params = snd_sm501_ac97_hw_params,
+		.prepare   = snd_sm501_ac97_prepare,
+	},
+},
+#if 0
+#warning Put mic here
+{}
+#endif
+};
+EXPORT_SYMBOL_GPL(sm501_ac97_dai);
+
+MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_DESCRIPTION("ASoC AC97 driver for SM501 chip");
+MODULE_LICENSE("GPL");
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-ac97-dev.c linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-ac97-dev.c
--- linux-2.6.27.6/sound/soc/sm501/sm501-ac97-dev.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-ac97-dev.c	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,90 @@
+/*
+ * sm501-ac97-dev.c  --  SoC audio for gdium
+ *
+ * Based on smdk2443_wm9710.c
+ *
+ * Arnaud Patard <apatard@mandriva.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <asm/gpio.h>
+
+#include "../codecs/ac97.h"
+#include "sm501-pcm.h"
+#include "sm501-ac97.h"
+
+#define SPEAKER_PWM		2
+#define SPEAKER_PWM_PERIOD	(1000000000/20000) /* 20 kHz */
+
+#define MUTE_GPIO		192+0 /* pin 32 is mute */
+#define AMP_MUTE		1
+#define AMP_UNMUTE		0
+
+static struct snd_soc_dai_link gdium_dai[] = {
+{
+	.name = "AC97",
+	.stream_name = "AC97 HiFi",
+	.cpu_dai = &sm501_ac97_dai[0],
+	.codec_dai = &ac97_dai,
+},
+};
+
+static struct snd_soc_machine gdium_machine = {
+	.name = "lyn",
+	.dai_link = gdium_dai,
+	.num_links = ARRAY_SIZE(gdium_dai),
+};
+
+static struct snd_soc_device gdium_snd_devdata = {
+	.machine = &gdium_machine,
+	.platform = &sm501_soc_platform,
+	.codec_dev = &soc_codec_dev_ac97,
+};
+
+static struct platform_device *gdium_snd_ac97_device;
+
+static int __init snd_gdium_init(void)
+{
+	int ret;
+
+	gdium_snd_ac97_device = platform_device_alloc("soc-audio", -1);
+	if (!gdium_snd_ac97_device)
+		return -ENOMEM;
+
+	platform_set_drvdata(gdium_snd_ac97_device,
+				&gdium_snd_devdata);
+	gdium_snd_devdata.dev = &gdium_snd_ac97_device->dev;
+	ret = platform_device_add(gdium_snd_ac97_device);
+
+	if (ret)
+		platform_device_put(gdium_snd_ac97_device);
+
+	return ret;
+}
+
+static void __exit snd_gdium_exit(void)
+{
+	platform_device_unregister(gdium_snd_ac97_device);
+}
+
+module_init(snd_gdium_init);
+module_exit(snd_gdium_exit);
+
+/* Module information */
+MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_DESCRIPTION("ALSA SoC Gdium");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:gdium-audio");
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-ac97.h linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-ac97.h
--- linux-2.6.27.6/sound/soc/sm501/sm501-ac97.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-ac97.h	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,26 @@
+/*
+ * AC97 support for SM50X chipsets
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _SM501_AC97_H
+#define _SM501_AC97_H
+
+#define SM501_AC97_CODEC_TIMEOUT	1000
+
+struct sm501_audio {
+	struct device	*dev;
+    struct resource	*res;
+	void __iomem * hw_buffer_addr;//the 3kb sram buffer virtual address
+//	void __iomem	*regs;	
+	int		irq;
+	int		firmware_loaded;
+	spinlock_t	lock;
+};
+
+extern struct snd_soc_dai sm501_ac97_dai[1];
+extern struct snd_ac97_bus_ops sm501_ac97_ops;
+
+#endif
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-pcm.c linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-pcm.c
--- linux-2.6.27.6/sound/soc/sm501/sm501-pcm.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-pcm.c	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,712 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+
+#include "sm501-ac97.h"
+#include "sm501-pcm.h"
+#include "sm501-u8051.h"
+
+
+#define DRV_NAME                        "sm501-audio"
+
+#ifdef DEBUG
+#define dprintk(msg...) do { printk(KERN_DEBUG DRV_NAME ": " msg); } while (0)
+#else
+#define dprintk(msg...)
+#endif
+
+#ifndef NEW_BUFFER
+#define NEW_BUFFER 1
+#endif
+
+static void do_audio_p_tasklet(unsigned long);
+DECLARE_TASKLET(audio_p_tasklet,do_audio_p_tasklet,0);
+static void do_audio_c_tasklet(unsigned long);
+DECLARE_TASKLET(audio_c_tasklet,do_audio_c_tasklet,0);
+
+struct sm501_runtime_data_father{
+	struct sm501_runtime_data * play_data;
+	struct sm501_runtime_data * capture_data;
+};
+
+
+struct sm501_runtime_data {
+	spinlock_t lock;
+	struct sm501_pcm_dma_params *params;
+	struct snd_pcm_substream *psubstream;
+	unsigned long ppointer; /* playback pointer in bytes */
+	struct snd_pcm_substream *csubstream;
+	unsigned long cpointer;	//capture buffer pointer in bytes
+};
+
+/*hardware definition */
+static struct sm501_runtime_data_father * g_father = NULL;
+
+static struct snd_pcm_hardware snd_sm501_playback_hw = {
+	.info = (SNDRV_PCM_INFO_MMAP |
+			SNDRV_PCM_INFO_INTERLEAVED |
+			SNDRV_PCM_INFO_BLOCK_TRANSFER |
+			SNDRV_PCM_INFO_MMAP_VALID |
+			SNDRV_PCM_INFO_HALF_DUPLEX |
+			SNDRV_PCM_INFO_BATCH),
+	.formats =          SNDRV_PCM_FMTBIT_S16_LE,
+	.rates =            SNDRV_PCM_RATE_48000, /*SNDRV_PCM_RATE_8000_48000,*/
+	.rate_min =         48000, /* 8000,*/
+	.rate_max =         48000,
+	.channels_min =     2,
+	.channels_max =     2,
+	.buffer_bytes_max = SM501_AC97_P_PERIOD_SIZE * SM501_AC97_P_PERIOD_COUNT,
+	.period_bytes_min = SM501_AC97_P_PERIOD_SIZE,
+	.period_bytes_max = SM501_AC97_P_PERIOD_SIZE,
+	.periods_min =      32,//change to 32 from 4
+	.periods_max =      SM501_AC97_P_PERIOD_COUNT,
+};
+
+
+static struct snd_pcm_hardware snd_sm501_capture_hw = {
+	.info = (SNDRV_PCM_INFO_MMAP |
+			SNDRV_PCM_INFO_INTERLEAVED |
+			SNDRV_PCM_INFO_BLOCK_TRANSFER |
+			SNDRV_PCM_INFO_MMAP_VALID |
+			SNDRV_PCM_INFO_HALF_DUPLEX |
+			SNDRV_PCM_INFO_BATCH),
+	.formats =          SNDRV_PCM_FMTBIT_S16_LE,
+	.rates =            SNDRV_PCM_RATE_48000,
+	.rate_min =         48000,
+	.rate_max =         48000,
+	.channels_min =     2,
+	.channels_max =     2,
+	.buffer_bytes_max = SM501_AC97_C_PERIOD_SIZE * SM501_AC97_C_PERIOD_COUNT,
+	.period_bytes_min = SM501_AC97_C_PERIOD_SIZE,
+	.period_bytes_max = SM501_AC97_C_PERIOD_SIZE,
+	.periods_min =      32,//change to 32 from 4
+	.periods_max =      SM501_AC97_C_PERIOD_COUNT,
+};
+static void snd_sm501_copy_pdata(struct sm501_runtime_data *);
+static void snd_sm501_copy_cdata(struct sm501_runtime_data *);
+
+
+static void do_audio_p_tasklet(unsigned long ptr)
+{
+	struct sm501_runtime_data * rtdata;
+	rtdata = (struct sm501_runtime_data *)ptr;	
+	snd_sm501_copy_pdata(rtdata);
+}
+
+static void do_audio_c_tasklet(unsigned long ptr)
+{
+	struct sm501_runtime_data * rtdata;
+	rtdata = (struct sm501_runtime_data *)ptr;	
+	snd_sm501_copy_cdata(rtdata);
+}
+
+
+/*
+ * allocate a buffer via vmalloc_32().
+ * called from hw_params
+ * NOTE: this may be called not only once per pcm open!
+*/
+static int snd_sm501_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs,
+					      size_t size)
+{
+	struct snd_pcm_runtime *runtime = subs->runtime;
+	if (runtime->dma_area) {
+		/* already allocated */
+		if (runtime->dma_bytes >= size)
+			return 0; /* already enough large */
+		vfree(runtime->dma_area);
+	}
+	runtime->dma_area = vmalloc_32(size);
+	if (! runtime->dma_area)
+		return -ENOMEM;
+	memset(runtime->dma_area, 0, size);
+	runtime->dma_bytes = size;
+	return 1; /* changed */
+}
+
+/*
+ * free the buffer.
+ * called from hw_free callback
+ * NOTE: this may be called not only once per pcm open!
+ */
+static int snd_sm501_pcm_free_vmalloc_buffer(struct snd_pcm_substream *subs)
+{
+	struct snd_pcm_runtime *runtime = subs->runtime;
+	if (runtime->dma_area) {
+		vfree(runtime->dma_area);
+		runtime->dma_area = NULL;
+	}
+	return 0;
+}
+
+/*
+* Copy playback data into the hardware buffer
+*/
+#if 0
+static void snd_sm501_copy_pdata(struct sm501_runtime_data *rtdata)
+{
+	u16  *phalfframe;
+	u32  *pdest;
+	u32  *pborder;
+	struct snd_pcm_runtime *runtime;
+	unsigned char status;
+
+	if (rtdata->psubstream==NULL) {
+		return;
+	}
+
+	runtime = rtdata->psubstream->runtime;
+
+	if (runtime->dma_area == NULL) {
+		return;
+	}
+
+	status = SmRead8(SRAM(buffer_status)) & 0x3;
+	if (status==0x2)
+		pdest = (u32*)rtdata->params->s->hw_buffer_addr + 192;
+	else
+		pdest = (u32*)rtdata->params->s->hw_buffer_addr;
+
+	pborder = pdest + (SM501_AC97_P_PERIOD_SIZE / (sizeof(u32)));
+
+	do {
+		/* Sample format : */
+		/* 32 ... 20 | 19 ... 4 | 3-0 */
+		/* reserved  | 16b sampl| opt */
+		
+		/* Left */
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->ppointer);
+		*pdest++ = (u32)*phalfframe << 4;
+		phalfframe++;
+
+		/* Right */
+		*pdest++ = (u32)*phalfframe << 4;
+		rtdata->ppointer += 4;
+	} while (pdest < pborder);
+
+	rtdata->ppointer %= (SM501_AC97_P_PERIOD_SIZE) * runtime->periods;
+
+	snd_pcm_period_elapsed(rtdata->psubstream);
+
+}
+#endif
+
+static void snd_sm501_copy_pdata(struct sm501_runtime_data *rtdata)
+{
+#if NEW_BUFFER == 0
+	u16  *phalfframe;
+	u32  *pdest;
+	u32  *pborder;
+#else
+	const void * phalfframe;
+	volatile void __iomem * pdest;
+#endif
+	
+	struct snd_pcm_runtime *runtime;
+	unsigned char status;
+
+	if (rtdata->psubstream == NULL) {
+		return;
+	}
+
+	runtime = rtdata->psubstream->runtime;
+
+	if (runtime->dma_area == NULL) {
+		return;
+	}
+
+	status = SmRead8(SRAM(buffer_status));
+	
+	if (status & 2)
+		pdest = (u32*)rtdata->params->s->hw_buffer_addr + 255;//192
+	else
+		pdest = (u32*)rtdata->params->s->hw_buffer_addr;
+	
+#if NEW_BUFFER == 0
+	pborder = pdest + (SM501_AC97_P_PERIOD_SIZE / (sizeof(u32)));
+
+	do {				
+		/* Sample format : */
+		/* 32 ... 20   | 19 ... 4	   | 3-0 */
+		/* reserved  | 16b sample| opt	*/
+		
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->ppointer);		
+		/* Left channel */
+		*pdest++ = (u32)*phalfframe << 4;
+		phalfframe++;
+		/* Right channel*/
+		*pdest++ = (u32)*phalfframe << 4;
+		rtdata->ppointer += 4;
+	} while (pdest < pborder);
+#else
+	phalfframe = (const void *)(runtime->dma_area + rtdata->ppointer);
+
+	/* left and right channel transported together !! */
+	memcpy_toio(pdest,phalfframe,SM501_AC97_P_PERIOD_SIZE);
+	rtdata->ppointer += SM501_AC97_P_PERIOD_SIZE;	
+#endif
+
+	rtdata->ppointer %= (SM501_AC97_P_PERIOD_SIZE) * runtime->periods;
+
+	snd_pcm_period_elapsed(rtdata->psubstream);
+
+}
+
+
+/*
+ * Fill the playback buffers with audio data
+ * Just the first 768 bytes
+ */
+static void snd_sm501_pfill(struct sm501_runtime_data *rtdata)
+{
+	volatile void __iomem * pdest;
+	
+	if (rtdata->psubstream==NULL) {
+		//KERROR("rtdata->psubstream==NULL");
+		return;
+	}
+	
+	pdest = (u32*)rtdata->params->s->hw_buffer_addr;
+	
+	if(pdest == NULL){
+		//KERROR("pdest == NULL");
+		return;
+	}
+	
+	memset_io(pdest,0,SM501_AC97_P_PERIOD_SIZE*2);
+}
+
+/*
+ * Copy capture data into software buffer
+ * This function can also be called as tasklet!
+*/
+static void snd_sm501_copy_cdata(struct sm501_runtime_data *rtdata)
+{
+#if NEW_BUFFER == 1
+	void * phalfframe;
+	const volatile void __iomem * psrc;
+#else	
+	volatile u16 *phalfframe;
+	u32  *psrc;
+	u32  *pborder;
+#endif	
+	struct snd_pcm_runtime *runtime;
+	unsigned char status;
+
+	if (rtdata->csubstream==NULL) {
+		return;
+	}
+
+	runtime = rtdata->csubstream->runtime;
+
+	if (runtime->dma_area == NULL) {
+		return;
+	}
+
+	status = SmRead8(SRAM(buffer_status)) & 0x30;
+	if (status == 0x20)
+		psrc = (u32*)rtdata->params->s->hw_buffer_addr + 765;//from 576 to 765
+	else
+		psrc = (u32*)rtdata->params->s->hw_buffer_addr + 510;//from 384 to 510
+#if NEW_BUFFER == 0
+	pborder = psrc + (SM501_AC97_C_PERIOD_SIZE / (sizeof(u32)));
+	do {
+		/* Sample format : */
+		/* 32 ... 20 | 19 ... 4 | 3-0 */
+		/* reserved  | 16b sampl| opt */
+		/* Left */
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->cpointer);
+		//*phalfframe = (SmRead32((unsigned long) psrc) >> 4) & 0xffff;
+		*phalfframe = (*psrc++)>>4;
+		phalfframe++;
+
+		/* Right */
+		//*phalfframe = (SmRead32((unsigned long) psrc) >> 4) & 0xffff;
+		*phalfframe =(*psrc++)>>4;
+		rtdata->cpointer += 4;
+	} while (psrc < pborder);
+#else
+	phalfframe = (void*)(runtime->dma_area + rtdata->cpointer);
+	/* left and right channel transported together !! */
+	memcpy_fromio(phalfframe,psrc,SM501_AC97_C_PERIOD_SIZE);
+	rtdata->cpointer += SM501_AC97_C_PERIOD_SIZE;
+#endif
+
+	rtdata->cpointer %= (SM501_AC97_C_PERIOD_SIZE) * runtime->periods;
+
+	snd_pcm_period_elapsed(rtdata->csubstream);
+}
+
+/* hw_params callback */
+static int snd_sm501_pcm_hw_params(struct snd_pcm_substream *substream,
+				   struct snd_pcm_hw_params * hw_params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sm501_runtime_data *rtdata = runtime->private_data;
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct sm501_pcm_dma_params *dma = rtd->dai->cpu_dai->dma_data;
+
+	
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
+		printk("hw parms pcm for play\n");
+	}
+	else{
+
+		printk("hw parms pcm for capture\n");	}
+
+	if (rtdata->params == NULL) {
+		rtdata->params = dma;
+	}
+
+	return snd_sm501_pcm_alloc_vmalloc_buffer(substream,
+			params_buffer_bytes(hw_params));
+}
+
+
+/* hw_free callback */
+static int snd_sm501_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+	dprintk("pcm_hw_free\n");
+
+	return snd_sm501_pcm_free_vmalloc_buffer(substream);
+}
+
+
+/* prepare callback */
+static int snd_sm501_pcm_prepare(struct snd_pcm_substream *substream)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+
+	dprintk("pcm_playback_prepare\n");
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
+		rtdata->ppointer = 0;
+		printk("prepare pcm for play\n");
+	}
+	else{
+		rtdata->cpointer = 0;
+		printk("prepare pcm for capture\n");
+	}
+
+	return 0;
+}
+#if 1
+static irqreturn_t snd_sm501_u8051_irq(int irq,void * dev_id)
+{
+	struct sm501_runtime_data_father * father = (struct sm501_runtime_data_father *)dev_id;
+	u32 status,mask;
+	
+	status = SmRead32(INTERRUPT_STATUS);
+	if(TEST_FIELD(status,INTERRUPT_STATUS_8051,NOT_ACTIVE))
+		return IRQ_NONE;
+
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK,SET_FIELD(mask,INTERRUPT_MASK_8051,DISABLE));
+	
+	SmRead32(U8051_8051_PROTOCOL_INTERRUPT);
+	
+	status = SmRead8(SRAM(buffer_status));
+
+	if(status & 0x03){
+		if(father->play_data){
+			audio_p_tasklet.data = (ulong)father->play_data;
+			tasklet_hi_schedule(&audio_p_tasklet);
+		}
+	}
+
+	if(status & 0x30){
+		if(father->capture_data){
+			audio_c_tasklet.data = (ulong)father->capture_data;
+			tasklet_hi_schedule(&audio_c_tasklet);			
+		}
+	}
+
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK,SET_FIELD(mask,INTERRUPT_MASK_8051,ENABLE));
+	return IRQ_HANDLED;
+	
+}
+
+#else
+static irqreturn_t snd_sm501_u8051_irq(int irq, void* dev_id)
+{
+	struct sm501_runtime_data *rtdata = (struct sm501_runtime_data *)dev_id;
+	struct sm501_audio *s = rtdata->params->s;
+	unsigned int status, mask;
+	unsigned long flags;
+
+
+	/* Read interrupt status. */
+	status = SmRead32(INTERRUPT_STATUS);
+	if (TEST_FIELD(status, INTERRUPT_STATUS_8051, NOT_ACTIVE))
+		return IRQ_NONE;
+
+	/* Reset 8051 interrupt status. */
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK, SET_FIELD(mask, INTERRUPT_MASK_8051, DISABLE));
+
+	spin_lock_irqsave(&s->lock, flags);
+	SmRead32(U8051_8051_PROTOCOL_INTERRUPT);
+
+	/* Check 8051 buffer status. */
+	status = SmRead8(SRAM(buffer_status));
+
+	if (status != 0) {
+		if (status & 0x0F) {	//playback buffer full
+			snd_sm501_copy_pdata(rtdata);
+		}
+		if (status & 0xF0) {	//record buffer full
+ 			snd_sm501_copy_cdata(rtdata);
+		}
+	}
+
+	spin_unlock_irqrestore(&s->lock, flags);
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK, SET_FIELD(mask, INTERRUPT_MASK_8051, ENABLE));
+
+	return IRQ_HANDLED;
+}
+#endif
+
+
+/* trigger callback */
+static int snd_sm501_pcm_playback_trigger(struct snd_pcm_substream *substream,
+					  int cmd)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+	struct sm501_audio *s = rtdata->params->s;
+
+	//printk("triggle for play\n");
+
+	spin_lock(&s->lock);
+
+	switch (cmd) {
+		case SNDRV_PCM_TRIGGER_START:
+			dprintk("pcm_playback_trigger: start\n");
+			rtdata->psubstream = substream;
+			snd_sm501_pfill(rtdata);
+			//sm501_write_command(s, SET_PLAYBACK_BUFFER_READY, 3, 0);
+			sm501_write_command(s, START_STOP_AUDIO_PLAYBACK, 1, 0);
+			break;
+		case SNDRV_PCM_TRIGGER_STOP:
+			dprintk("pcm_playback_trigger: stop\n");
+			sm501_write_command(s, START_STOP_AUDIO_PLAYBACK, 0, 0);
+			rtdata->psubstream = NULL;
+			break;
+		default:
+			dprintk("pcm_playback_trigger: default (%i)\n", cmd);
+			return -EINVAL;
+	}
+	spin_unlock(&s->lock);
+
+	return 0;
+}
+static int snd_sm501_pcm_capture_trigger(struct snd_pcm_substream *substream,
+					 int cmd)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+	struct sm501_audio *s = rtdata->params->s;
+	printk("triggle for capture\n");
+
+	spin_lock(&s->lock);
+
+	switch (cmd) {
+		case SNDRV_PCM_TRIGGER_START:
+			sm501_write_command(s, SET_CAPTURE_BUFFER_EMPTY, 3, 0);
+			dprintk("pcm_capture_trigger: start\n");
+			rtdata->csubstream = substream;
+			sm501_write_command(s, START_STOP_AUDIO_CAPTURE, 1, 0);
+			break;
+		case SNDRV_PCM_TRIGGER_STOP:
+			dprintk("pcm_capture_trigger: stop\n");
+			sm501_write_command(s, START_STOP_AUDIO_CAPTURE, 0, 0);
+			rtdata->csubstream = NULL;
+			break;
+		default:
+			dprintk("pcm_capture_trigger: default (%i)\n", cmd);
+			return -EINVAL;
+	}
+
+	spin_unlock(&s->lock);
+
+	return 0;
+}
+
+static int snd_sm501_pcm_trigger(struct snd_pcm_substream *substream,
+					 int cmd)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		return snd_sm501_pcm_playback_trigger(substream, cmd);
+	else
+		return snd_sm501_pcm_capture_trigger(substream, cmd);
+
+}
+/* open callback */
+static int snd_sm501_open(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sm501_runtime_data *rtdata;
+	struct sm501_audio *s = rtdata->params->s;
+	int ret;
+
+	rtdata = kzalloc(sizeof(struct sm501_runtime_data), GFP_KERNEL);
+	if (rtdata == NULL)
+		return -ENOMEM;
+
+	//we do not need below lock initialized,because there is no use of it ...
+//	spin_lock_init(&rtdata->lock);
+	runtime->private_data = rtdata;
+	
+	
+#if 0
+		/* mute the record in */
+		u16 rg;
+		rg = soc_ac97_ops.read(NULL,AC97_MIC);
+		soc_ac97_ops.write(NULL,AC97_MIC,rg|0x8000);
+		
+		rg = soc_ac97_ops.read(NULL,AC97_LINE);
+		soc_ac97_ops.write(NULL,AC97_LINE,rg|0x8000); 
+	
+		/* setting codec */
+#endif
+
+	/* 	use global lock to prevent the simultaneous calling from 
+		capture open and playback open
+		we should use lock in every routine that access global resource 
+		and with re-entrance attribuite for thorough safety
+	*/
+	spin_lock(&s->lock);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
+		snd_soc_set_runtime_hwparams(substream, &snd_sm501_playback_hw);
+		g_father->play_data = rtdata;
+		printk("open,for play\n");
+	}
+	else{
+		snd_soc_set_runtime_hwparams(substream, &snd_sm501_capture_hw);
+		g_father->capture_data = rtdata;
+		printk("open,for capture\n");
+	}
+
+	spin_unlock(&s->lock);
+	
+	return 0;
+}
+
+static int snd_sm501_close(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sm501_runtime_data *rtdata = runtime->private_data;
+	struct sm501_audio *s = rtdata->params->s;
+
+	dprintk("Entered %s\n", __FUNCTION__);
+
+	if (rtdata)
+	{
+		kfree(rtdata);
+		spin_lock(&s->lock);
+		if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)			
+			g_father->play_data = NULL;
+		else
+			g_father->capture_data = NULL;
+		spin_unlock(&s->lock);
+	}
+	else
+		printk("%s called with rtdata == NULL\n", __func__);
+
+	return 0;
+}
+
+/* pointer callback */
+static snd_pcm_uframes_t snd_sm501_pcm_pointer(struct snd_pcm_substream *substream)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+	snd_pcm_uframes_t value = 0;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		value = bytes_to_frames(substream->runtime, rtdata->ppointer);
+	else
+		value = bytes_to_frames(substream->runtime, rtdata->cpointer);
+	return value;
+}
+
+/* get the physical page pointer on the given offset */
+static struct page *snd_sm501_pcm_get_vmalloc_page(struct snd_pcm_substream *subs,
+		unsigned long offset)
+{
+	void *pageptr = subs->runtime->dma_area + offset;
+
+	return vmalloc_to_page(pageptr);
+}
+
+
+/* operators */
+static struct snd_pcm_ops snd_sm501_ops = {
+	.open =		snd_sm501_open,
+	.close =	snd_sm501_close,
+	.ioctl =	snd_pcm_lib_ioctl,
+	.hw_params =	snd_sm501_pcm_hw_params,
+	.hw_free =	snd_sm501_pcm_hw_free,
+	.prepare =	snd_sm501_pcm_prepare,
+	.trigger =	snd_sm501_pcm_trigger,
+	.pointer =	snd_sm501_pcm_pointer,
+	.page =		snd_sm501_pcm_get_vmalloc_page,
+};
+
+int sm501_pcm_new(struct snd_card *card, struct snd_soc_codec_dai *dai,
+	struct snd_pcm *pcm)
+{
+	int ret = 0;
+	static int nt = 0;
+	struct sm501_runtime_data_father * father;
+	father = kzalloc(sizeof (*father),GFP_KERNEL);
+	if(!father)
+		return -ENOMEM;	
+	g_father = father;
+//	request_irq(36, snd_sm501_u8051_irq, //mj
+	request_irq(36, snd_sm501_u8051_irq,
+				IRQF_SHARED | IRQF_DISABLED, "sm501-pcm", g_father);
+
+	return ret;
+}
+
+static void sm501_pcm_free(struct snd_pcm *pcm)
+{
+//	free_irq(36, g_father); //mj
+	free_irq(36, g_father);
+	if(g_father)
+		kfree(g_father);
+	
+}
+
+struct snd_soc_platform sm501_soc_platform = {
+	.name		= "sm501-snd",
+	.pcm_ops 	= &snd_sm501_ops,
+	.pcm_new	= sm501_pcm_new,
+	.pcm_free	= sm501_pcm_free,
+};
+
+EXPORT_SYMBOL_GPL(sm501_soc_platform);
+
+
+MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_DESCRIPTION("SM501 pcm module");
+MODULE_LICENSE("GPL");
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-pcm.h linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-pcm.h
--- linux-2.6.27.6/sound/soc/sm501/sm501-pcm.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-pcm.h	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,27 @@
+/*
+ *  Based on s3c24xx-pcm.h
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef _SM501_PCM_H
+#define _SM501_PCM_H
+
+//#define SM501_AC97_P_PERIOD_SIZE  1152  //Modified on 23/03/2010 to fix the audio noise
+#define SM501_AC97_P_PERIOD_SIZE  1020
+#define SM501_AC97_P_PERIOD_COUNT 256
+#define SM501_AC97_C_PERIOD_SIZE  1020
+#define SM501_AC97_C_PERIOD_COUNT 256
+
+struct sm501_pcm_dma_params {
+	struct sm501_audio *s;
+};
+
+/* platform data */
+extern struct snd_soc_platform sm501_soc_platform;
+
+#endif
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-u8051.c linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-u8051.c
--- linux-2.6.27.6/sound/soc/sm501/sm501-u8051.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-u8051.c	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,224 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+
+#include "sm501-ac97.h"
+#include "sm501-u8051.h"
+//#include "sm501_fw.h"
+
+#define DRV_NAME                        "sm501-audio"
+#if 0
+#define dprintk(msg...) do { printk(KERN_DEBUG DRV_NAME ": " msg); } while (0)
+#else
+#define dprintk(msg...)
+#endif
+
+/* Functions for talking to the codec when firmware loaded */
+int sm501_write_command(struct sm501_audio *s, unsigned char command, unsigned int data0,
+			 unsigned int data1)
+{
+	int i;
+
+	/* Reset status. */
+	SmWrite8(SRAM(status_byte), 0);
+
+	/* Fill command and data bytes. */
+	dprintk("%s: %u %08x %08x\n", __func__, command, data0, data1);
+
+	SmWrite8(SRAM(command_byte), command);
+#if 1
+	SmWrite32(SRAM(data_byte[0]), data0);
+	SmWrite32(SRAM(data_byte[4]), data1);
+#else
+	SmWrite8(SRAM(data_byte[0]), LOBYTE(LOWORD(data0)));
+	SmWrite8(SRAM(data_byte[1]), HIBYTE(LOWORD(data0)));
+	SmWrite8(SRAM(data_byte[2]), LOBYTE(HIWORD(data0)));
+	SmWrite8(SRAM(data_byte[3]), HIBYTE(HIWORD(data0)));
+	SmWrite8(SRAM(data_byte[4]), LOBYTE(LOWORD(data1)));
+	SmWrite8(SRAM(data_byte[5]), HIBYTE(LOWORD(data1)));
+	SmWrite8(SRAM(data_byte[6]), LOBYTE(HIWORD(data1)));
+	SmWrite8(SRAM(data_byte[7]), HIBYTE(HIWORD(data1)));
+#endif
+
+	/* Interrupt 8051. */
+	SmWrite32(U8051_CPU_PROTOCOL_INTERRUPT, 1);
+
+	/* Wait for command to start. */
+	i = SM501_AC97_CODEC_TIMEOUT;
+	while (SmRead8(SRAM(command_busy)) == 0) {
+		if (i-- <= 0) {
+			dev_err(s->dev, "firmware did not accept command %u\n",
+				 command);
+			break;
+		}
+		udelay(1);
+	}
+
+	/* Wait for command to finish. */
+	while (SmRead8(SRAM(command_busy)) == 1)
+		udelay(1);
+
+	/* Return status byte. */
+	return(SmRead8(SRAM(status_byte)) == 1);
+}
+EXPORT_SYMBOL_GPL(sm501_write_command);
+
+static unsigned int __devinit ascii_hex(const char* text, int* index, int count)
+{
+	/* Initialize result. */
+	unsigned int result = 0;
+
+	/* Convert nibbles. */
+	while (count-- > 0)
+	{
+		/* Get Ascii nibble. */
+		char c = text[*index];
+
+		/* Convert from Ascii into hex. */
+		if (c >= '0' && c <= '9')
+			c -= '0';
+		else if (c >= 'A' && c <= 'F')
+			c -= 'A' - 10;
+		else if (c >= 'a' && c <= 'f')
+			c -= 'a' - 10;
+		else
+			/* Invalid digits, return 0. */
+			return 0;
+
+		/* Add nibble to result. */
+		result = (result << 4) | c;
+
+		/* Increment string index. */
+		(*index)++;
+	}
+
+	/* Return result. */
+	return result;
+}
+
+int __devinit sm501_load_firmware(struct sm501_audio *s, const char* firmware)
+{
+	unsigned int value;
+	int i, errors, retry;
+	unsigned int bytes, address, finish;
+
+	/* Put 8051 in reset state. */
+	value = SET_FIELD(0, U8051_RESET_CONTROL, RESET);
+	SmWrite32( U8051_RESET, value);
+
+	/* Cold reset AC97 controller */
+	value = SmRead32(AC97_CONTROL_STATUS);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_COLD_RESET, RESET);
+	SmWrite32(AC97_CONTROL_STATUS, value);
+
+	msleep(1);
+
+	value = SmRead32(AC97_CONTROL_STATUS);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_COLD_RESET, NORMAL);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_CONTROL, ENABLED);
+	SmWrite32(AC97_CONTROL_STATUS, value);
+
+	/* Retry loop for loading firmware. */
+	for (retry = 1; retry <= 3; retry++) {
+		dprintk("%s: loading firmware: retry %d\n", __func__, retry);
+
+		/* Reset error count. */
+		errors = 0;
+
+		/* !!BUGBUG!! Settle down 8051 or SRAM, seems to be required. */
+		msleep(250);
+
+		/* Zero SRAM. */
+		SmMemset(U8051_SRAM, 0, U8051_SRAM_SIZE);
+
+		/* Walk entire firmware. */
+		for (i = 0; i < strlen(firmware);) {
+			/* Skip colon (start of line). */
+			if (firmware[i] != ':') {
+				dev_err(s->dev, "%s: invalid firmware character '%c'\n",
+				       __func__, firmware[i]);
+				break;
+			}
+			i++;
+
+			/* Get number of bytes (first byte). */
+			bytes = ascii_hex(firmware, &i, 2);
+
+			/* Get address (second and third byte). */
+			address = ascii_hex(firmware, &i, 4);
+
+			/* Get finish flag (fourth byte). */
+			finish = ascii_hex(firmware, &i, 2);
+
+			/* Loop through all bytes. */
+			while (bytes-- > 0) {
+				/* Get byte. */
+				unsigned int value = ascii_hex(firmware,
+						&i, 2);
+
+				/* Write byte into SRAM address. */
+				SmWrite8( U8051_SRAM + address,
+						value);
+				if (SmRead8( U8051_SRAM + address) != value) {
+					if (errors++ < 10) {
+						dev_warn(s->dev, "%s: %04x: mismatch: "
+								"code(%02x) "
+								"sram(%02x)\n",
+						__func__, address, value,
+						(unsigned char)SmRead8( U8051_SRAM + address));
+					}
+				}
+
+				/* Increment address. */
+				address++;
+			}
+
+			/* Skip checksum. */
+			i += 2;
+
+			/* Finish when end of data. */
+			if (finish != 0)
+				break;
+		}
+
+		if (errors == 0)
+			break;
+	}
+
+	if (errors > 0)
+		return -EFAULT;
+
+	/* Enable 8051. */
+	value = SET_FIELD(0, U8051_RESET_CONTROL, ENABLE);
+	SmWrite32( U8051_RESET, value);
+
+	/* Wait until the init is complete. During its initialization the
+	firmware will increment the "init counter" twice, so that when the
+	counter becomes 2, we know that the initialization is complete. */
+	i = 800;
+	while (SmRead8( SRAM(init_count)) != 2) {
+		if (i-- <= 0) {
+			dev_err(s->dev, "%s: firmware timed out during reset init_count = 0x%x test_count = 0x%x \n", 
+				__func__, SmRead8(SRAM(init_count)), SmRead8(SRAM(filler4)));
+			return -ETIMEDOUT;
+		}
+		msleep(1);
+	}
+	dev_err(s->dev, "%s:  init_count = 0x%x test_count = 0x%x  \n", __func__, SmRead8(SRAM(init_count)),
+				SmRead8(SmRead8(SRAM(filler4))));
+
+	dprintk("%s: firmware loaded and running\n", __func__);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sm501_load_firmware);
diff -uNra linux-2.6.27.6/sound/soc/sm501/sm501-u8051.h linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-u8051.h
--- linux-2.6.27.6/sound/soc/sm501/sm501-u8051.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501/sm501-u8051.h	2011-06-21 14:32:45.000000000 +0800
@@ -0,0 +1,57 @@
+#ifndef _SM501_U8051_h
+#define _SM501_U8051_h
+#include "sm501-pcm.h"
+
+#define SET_TX_SLOT_0                    0
+#define SET_TX_SLOT_1                    1
+#define SET_TX_SLOT_2                    2
+#define SET_PLAYBACK_BUFFER_ADDRESS      3
+#define SET_PLAYBACK_BUFFER_SIZE         4
+#define SET_PLAYBACK_BUFFER_READY        5
+#define GET_BUFFER_STATUS                6
+#define START_STOP_AUDIO_PLAYBACK        7
+#define GET_RX_SLOT0                     8
+#define GET_RX_SLOT1                     9
+#define GET_RX_SLOT2                    10
+#define SET_CAPTURE_BUFFER_ADDRESS      11
+#define SET_CAPTURE_BUFFER_SIZE         12
+#define SET_CAPTURE_BUFFER_EMPTY        13
+#define START_STOP_AUDIO_CAPTURE        14
+#define SET_GET_AC97_REGISTER           15
+
+typedef struct
+{
+    unsigned char firmware[0x3000];                     /* 0x0000 */
+    union
+    {
+        struct
+        {
+            unsigned char playback_buffer_0[SM501_AC97_P_PERIOD_SIZE];    /* 0x3000 */
+            unsigned char playback_buffer_1[SM501_AC97_P_PERIOD_SIZE];    /* 0x37f8 - 1*/
+        }B;
+        struct
+        {
+            //unsigned char filler[0x0600];               /* 0x3000 */
+            unsigned char filler[SM501_AC97_P_PERIOD_SIZE * 2];
+            unsigned char capture_buffer_0[SM501_AC97_C_PERIOD_SIZE];     /* 0x37f8 */
+            unsigned char capture_buffer_1[SM501_AC97_C_PERIOD_SIZE];     /* 0x3ff0 - 1 */
+        }C;
+    }A;
+//    unsigned char filler1[0x0200];                      /* 0x3C00 */
+//    unsigned short ac97_regs[64];                       /* 0x3E00 */
+//    unsigned char filler2[0x0170];                      /* 0x3E80 */
+    unsigned char command_byte;                         /* 0x3FF0 */
+    unsigned char status_byte;                          /* 0x3FF1 */
+    unsigned char data_byte[8];                         /* 0x3FF2 */
+    unsigned char filler3[2];                           /* 0x3FFA */
+    unsigned char buffer_status;                        /* 0x3FFC */
+    unsigned char command_busy;                         /* 0x3FFD */
+    unsigned char filler4;                              /* 0x3FFE */
+    unsigned char init_count;                           /* 0x3FFF */
+}
+__attribute__((packed)) FIRMWARE_SRAM;
+
+extern int sm501_write_command(struct sm501_audio *s, unsigned char command, unsigned int data0, unsigned int data1);
+extern int __devinit sm501_load_firmware(struct sm501_audio *s, const char* firmware);
+
+#endif
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/Kconfig linux-2.6.27.6.yaffs/sound/soc/sm501.old/Kconfig
--- linux-2.6.27.6/sound/soc/sm501.old/Kconfig	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/Kconfig	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,27 @@
+config SND_SM501_SOC
+	tristate "SoC Audio for the Silion Motion SM501 chips"
+	depends on MFD_SM501 && SND_SOC
+	select SND_PCM
+	select SND_DRIVER_OWN_BUF
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the SM501 AC97 or I2S interface. You will also need
+	  to select the audio interfaces to support below.
+
+# config SND_SM501_SOC_I2S
+#	tristate
+
+config SND_SM501_SOC_AC97
+	tristate
+	select AC97_BUS
+	select SND_AC97_CODEC
+	select SND_SOC_AC97_BUS
+
+config SND_SM501_SOC_AC97_DEVICE
+	tristate "SoC AC97 Audio support SM501"
+	depends on SND_SM501_SOC
+	select SND_SM501_SOC_AC97
+	select SND_SOC_AC97_CODEC
+	help
+	  Say Y if you want to add support for SoC audio on SM501 AC97.
+
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/Makefile linux-2.6.27.6.yaffs/sound/soc/sm501.old/Makefile
--- linux-2.6.27.6/sound/soc/sm501.old/Makefile	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/Makefile	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,7 @@
+snd-soc-sm501-objs := sm501-pcm.o
+snd-soc-sm501-ac97-objs := sm501-ac97.o sm501-u8051.o
+snd-soc-sm501-ac97-dev-objs := sm501-ac97-dev.o
+
+obj-$(CONFIG_SND_SM501_SOC) += snd-soc-sm501.o
+obj-$(CONFIG_SND_SM501_SOC_AC97) += snd-soc-sm501-ac97.o
+obj-$(CONFIG_SND_SM501_SOC_AC97_DEVICE) += snd-soc-sm501-ac97-dev.o
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-ac97.c linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-ac97.c
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-ac97.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-ac97.c	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,868 @@
+/*
+ * AC97 support for SM50X chipsets
+ *
+ * Based on Silicon Motion drivers
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <asm/irq.h>
+#include <linux/mutex.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+
+#include "sm501-ac97.h"
+#include "sm501-pcm.h"
+#include "sm501-u8051.h"
+#include "sm501_fw.h"
+
+
+/*
+ * Register address in the firmware
+ */
+#define SET_TX_SLOT_0                    0
+#define SET_TX_SLOT_1                    1
+#define SET_TX_SLOT_2                    2
+#define SET_PLAYBACK_BUFFER_ADDRESS      3
+#define SET_PLAYBACK_BUFFER_SIZE         4
+#define SET_PLAYBACK_BUFFER_READY        5
+#define GET_BUFFER_STATUS                6
+#define START_STOP_AUDIO_PLAYBACK        7
+#define GET_RX_SLOT0                     8
+#define GET_RX_SLOT1                     9
+#define GET_RX_SLOT2                    10
+#define SET_CAPTURE_BUFFER_ADDRESS      11
+#define SET_CAPTURE_BUFFER_SIZE         12
+#define SET_CAPTIRE_BUFFER_EMPTY        13
+#define START_STOP_AUDIO_CAPTURE        14
+#define SET_GET_AC97_REGISTER           15
+
+#define DRV_NAME			"sm501-audio"
+
+static int debug        = 0;
+#define dprintk(msg...) if (debug) { printk(KERN_DEBUG DRV_NAME ": " msg); }
+static struct sm501_audio *audio_dev;
+
+static void sm501_write_codec(struct sm501_audio *s, u8 addr, u16 data)
+{
+	unsigned int read_back;
+
+	//dprintk("%s: addr=%02x data=%04x\n", __func__, addr, data);
+
+	/* Write Codec register. */
+	if (!sm501_write_command(s, SET_GET_AC97_REGISTER, (unsigned int) addr << 12,
+	     (unsigned int) data << 4) && (addr != AC97_RESET))
+	{
+		//if write failed 
+		read_back = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+					SmRead8(SRAM(data_byte[5]))),
+					MAKEWORD(SmRead8(SRAM(data_byte[6])),
+					SmRead8(SRAM(data_byte[7])))) >> 4;
+
+		/*
+		 * Not dev_err here because the firmware returns an error
+		 * for R/O or not defined registers
+		 */
+		dev_dbg(s->dev, "%s failed: addr=%02x data=%04x read_back=%04x\n",
+			__func__, addr, data, read_back);
+	}
+	else
+	{	
+		dev_dbg(s->dev, "%s ok: addr=%02x data=%04x\n",
+		__func__, addr, data);
+	}
+}
+
+#if 1
+static u16 sm501_read_codec(struct sm501_audio * s,u8 addr)
+{
+	int failed;
+	u32 data;
+
+	//according to the implement of firmware,we can't tell if the read operate okay or not
+	//read command always return a 1 value
+	//but put the failed flag here for futhure nice upgrade
+	failed = !sm501_write_command(s,SET_GET_AC97_REGISTER,(u32)(addr<<12)|(1<<19),0);	
+	data = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+			SmRead8(SRAM(data_byte[5]))),
+			MAKEWORD(SmRead8(SRAM(data_byte[6])),
+			SmRead8(SRAM(data_byte[7])))) >> 4;
+	
+	if(failed)
+	{	
+		//read codec register failed
+		printk("%s: failed: addr=%02x data=%04x status=%02x\n", __func__, addr,data,SmRead8(SRAM(status_byte)));
+	}
+	return (u16)data;
+}
+#else
+static u16 sm501_read_codec(struct sm501_audio *s, u8 addr)
+{
+	unsigned int data;
+	int i;
+
+	/* Read Codec register. */
+	if (sm501_write_command(s, SET_GET_AC97_REGISTER,
+	    (unsigned int) (addr << 12) | (1 << 19), 0)) {
+		data = MAKEDWORD(MAKEWORD(SmRead8(SRAM(data_byte[4])),
+				SmRead8(SRAM(data_byte[5]))),
+				MAKEWORD(SmRead8(SRAM(data_byte[6])),
+				SmRead8(SRAM(data_byte[7])))) >> 4;
+	} else {
+		/* Read register from SRAM in case link failes. */
+		for (i = SM501_AC97_CODEC_TIMEOUT; i > 0; i--) {
+			data = SmRead16(SRAM(ac97_regs[addr >> 1]));
+			if (data != 0xFFFF)
+				break;
+			msleep(1);
+		}
+
+		dev_err(s->dev, "%s failed: addr=%02x sram=%04x\n", __func__, addr, data);
+	}
+
+	dprintk("%s: data=%04x\n", __func__, data);
+	return((unsigned short) data);
+}
+#endif
+/*
+ * AC97 functions
+ */
+static unsigned short snd_sm501_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
+{
+	unsigned int data;
+	unsigned long value;
+	unsigned long flags;
+	unsigned long i;
+
+	spin_lock_irqsave(&audio_dev->lock, flags);
+
+	if (audio_dev->firmware_loaded) {
+		data = sm501_read_codec(audio_dev, reg);
+	} else {
+
+		SmWrite32(AC97_TX_SLOT2, 0);
+
+		value = (unsigned long) reg << 12;
+		value = SET_FIELD(value, AC97_TX_SLOT1_READ_WRITE, READ);
+		SmWrite32(AC97_TX_SLOT1, value);
+
+		/* Enable Slot 0, 1, 2 for read */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_FRAME_TAG,
+				  INTERPRET);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+
+		udelay(150);
+
+		for (i = SM501_AC97_CODEC_TIMEOUT; i> 0; i--)
+		{
+			if (TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+			    AC97_RX_SLOT0_CODEC_READY_FLAG, READY))
+			{
+				if ((TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+				     AC97_RX_SLOT0_VALID_S1,
+				     DATA)) &&
+					 (TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+						     AC97_RX_SLOT0_VALID_S2, DATA)))
+					break;
+			}
+			udelay(1);
+		}
+		if (i == 0)
+			dev_err(audio_dev->dev, "%s: AC97 timeout\n", __func__);
+
+
+		data = SmRead32(AC97_RX_SLOT2);
+		data = GET_FIELD(data, AC97_RX_SLOT2_DATA);
+
+		/* Reset Slot 1,2 */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, NO_DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, NO_DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+	}
+
+	spin_unlock_irqrestore(&audio_dev->lock, flags);
+
+	return((unsigned short) data);
+}
+
+static snd_sm501_ac97_wait_codec(struct snd_ac97 * ac97)
+{
+	int i;
+	u16 data;
+	unsigned long flags;
+
+	spin_lock_irqsave(&audio_dev->lock, flags);
+	for(i=0;i<1000;i++)
+	{
+		data = sm501_read_codec(audio_dev,AC97_POWERDOWN);
+		if(data & 2)
+			break;
+	}
+	spin_unlock_irqrestore(&audio_dev->lock, flags);
+}
+
+
+static void snd_sm501_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+				 unsigned short val)
+{
+	unsigned long flags;
+	unsigned long value;
+	unsigned long i;
+
+	spin_lock_irqsave(&audio_dev->lock, flags);
+
+	if (audio_dev->firmware_loaded) {
+		sm501_write_codec(audio_dev, reg, val);
+	} else {
+		value = (unsigned long) reg << 12;
+		SmWrite32(AC97_TX_SLOT1, value);
+
+		value = ((unsigned int) val << 4);
+		SmWrite32(AC97_TX_SLOT2, value);
+
+		/* Enable Slot 0, 1, 2 for write */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_FRAME_TAG,
+				  INTERPRET);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+		for (i = SM501_AC97_CODEC_TIMEOUT; i> 0; i--)
+		{
+			if (TEST_FIELD(SmRead32(
+			    AC97_RX_SLOT0),AC97_RX_SLOT0_CODEC_READY_FLAG,
+			READY))
+			{
+				if ((TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+				     AC97_RX_SLOT0_VALID_S1,
+				     NO_DATA)) &&
+				(TEST_FIELD(SmRead32(AC97_RX_SLOT0),
+						     AC97_RX_SLOT0_VALID_S2,
+						     NO_DATA)))
+					break;
+			}
+			udelay(1);
+		}
+		if (i == 0)
+			dev_err(audio_dev->dev, "%s: AC97 timeout\n", __func__);
+
+		/* Reset Slot 1,2 */
+		value = SmRead32(AC97_TX_SLOT0);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S1, NO_DATA);
+		value = SET_FIELD(value, AC97_TX_SLOT0_VALID_S2, NO_DATA);
+		SmWrite32(AC97_TX_SLOT0, value);
+	}
+
+	spin_unlock_irqrestore(&audio_dev->lock, flags);
+}
+
+static void snd_sm501_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+#warning FILL ME
+}
+
+static void snd_sm501_ac97_cold_reset(struct snd_ac97 *ac97)
+{
+#warning FILL ME
+}
+
+
+struct snd_ac97_bus_ops soc_ac97_ops = {
+	.read		= snd_sm501_ac97_read,
+	.write		= snd_sm501_ac97_write,
+	.warm_reset	= snd_sm501_ac97_warm_reset,
+	.reset		= snd_sm501_ac97_cold_reset,
+	.wait	= snd_sm501_ac97_wait_codec,
+};
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+static struct sm501_pcm_dma_params sm501_ac97_pcm_stereo_out;
+static struct sm501_pcm_dma_params sm501_ac97_pcm_stereo_in;
+
+/* hw_params callback */
+static int snd_sm501_ac97_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		cpu_dai->dma_data = &sm501_ac97_pcm_stereo_out;
+	else
+		cpu_dai->dma_data = &sm501_ac97_pcm_stereo_in;
+
+	return 0;
+}
+static int snd_sm501_ac97_prepare(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	int reg;
+	u16 vra;
+	u16 value;
+
+	vra = sm501_read_codec(audio_dev, AC97_EXTENDED_STATUS);
+	sm501_write_codec(audio_dev, AC97_EXTENDED_STATUS, vra | AC97_EA_VRA);
+
+
+#define AC97_DATA_FLOW_CONTROL 0x6a
+	value = sm501_read_codec(audio_dev, AC97_DATA_FLOW_CONTROL);
+	sm501_write_codec(audio_dev, AC97_DATA_FLOW_CONTROL, value | 0xc800);  //enable spdif in
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		reg = AC97_PCM_FRONT_DAC_RATE;
+	 else
+		reg = AC97_PCM_LR_ADC_RATE;
+
+	 sm501_write_codec(audio_dev, reg, runtime->rate);
+	 return 0;
+}
+
+static int snd_sm501_ac97_probe(struct platform_device *pdev)
+{
+	struct device   *dev = &pdev->dev;
+	struct resource *res;
+	int retry = 0;
+	int ret = 0;
+	int res_len;
+	unsigned long value;
+
+	audio_dev = kzalloc(sizeof(struct sm501_audio), GFP_KERNEL);
+	if (!audio_dev) {
+		dev_err(dev, "Allocation failure\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	audio_dev->dev = dev;
+
+	audio_dev->hw_buffer_addr = SmIoAddress() + 0xC3000;
+	
+	sm501_ac97_pcm_stereo_out.s = audio_dev;
+	sm501_ac97_pcm_stereo_in.s = audio_dev;
+
+	/* Get irq number */
+	audio_dev->irq = platform_get_irq(pdev, 0);
+	if (!audio_dev->irq) {
+		dev_err(dev, "no irq found\n");
+		ret = -ENODEV;
+		goto err_alloc;
+	}
+
+	/* Get regs address */
+	res = (struct resource *)kzalloc(sizeof(struct resource), GFP_KERNEL);
+	if (res == NULL) {
+		dev_err(dev, "No memory resource found\n");
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+restart:
+
+//Reset AC97 codec
+
+	/* Put 8051 in reset state. */
+        value = SmRead32(U8051_RESET);
+        value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+        SmWrite32(U8051_RESET, value);
+
+        /* Reset GPIO lines. */
+        value = SmRead32(GPIO_CONTROL_LOW);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+        value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+        SmWrite32(GPIO_CONTROL_LOW, value);
+
+        /*Force GPIO28/SDIN GPIO27/SDOUT GPIO26/BIT_CLK GPIO25/SYNC to low*/
+        value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_28, OUTPUT);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_27, OUTPUT);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_26, OUTPUT);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_25, OUTPUT);
+        SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+        value = SmRead32(GPIO_DATA_LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_28, LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_27, LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_26, LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_25, LOW);
+        SmWrite32(GPIO_DATA_LOW, value);
+
+
+        /*Force GPIO24/AC97 Reset to low*/
+        value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+        SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+        value = SmRead32(GPIO_DATA_LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_24, LOW);
+        SmWrite32(GPIO_DATA_LOW, value);
+        msleep(10);
+
+        /*Force GPIO24/AC97 Reset to high*/
+        value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+        value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+        SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+    
+        value = SmRead32(GPIO_DATA_LOW);
+        value = SET_FIELD(value, GPIO_DATA_LOW_24, HIGH);
+        SmWrite32(GPIO_DATA_LOW, value);
+
+////////////////////
+	value = SmRead32(GPIO_CONTROL_LOW);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_28, AC97_RX_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_27, AC97_TX_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_26, AC97_CLOCK_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_25, AC97_SYNC_I2S);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_24, AC97_RESET);
+	SmWrite32(GPIO_CONTROL_LOW, value);
+
+	/* Set arbitartion control */
+	value = SmRead32(ARBITRATION_CONTROL);
+	value = SET_FIELD(value, ARBITRATION_CONTROL_DMA, PRIORITY_1);
+	SmWrite32(ARBITRATION_CONTROL, value);
+
+	/* Enable interrupts */
+	value = SmRead32(INTERRUPT_MASK);
+	value = SET_FIELD(value, INTERRUPT_MASK_8051, ENABLE);
+	value = SET_FIELD(value, INTERRUPT_MASK_DMA, ENABLE);
+	SmWrite32(INTERRUPT_MASK, value);
+
+	/* Initialize chip. */
+	value = SmRead32(CURRENT_GATE);
+	value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, ENABLE);
+	value = SET_FIELD(value, CURRENT_GATE_8051, ENABLE);
+	value = SET_FIELD(value, CURRENT_GATE_HOST_COMMAND_LIST_DMA, ENABLE);
+	value = SET_FIELD(value, CURRENT_GATE_GPIO_PWM_I2C, ENABLE);
+	sm501_set_gate(value);
+
+	value = SmRead32(U8051_MODE_SELECT);
+	value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, ENABLED);
+	value = SET_FIELD(value, U8051_MODE_SELECT_TEST_MODE, NORMAL);
+	value = SET_FIELD(value, U8051_MODE_SELECT_CODEC_SELECT, AC97);
+	value = SET_FIELD(value, U8051_MODE_SELECT_DIVIDER, 2);
+	SmWrite32(U8051_MODE_SELECT, value);
+
+
+	value = SmRead32(AC97_CONTROL_STATUS);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_CONTROL, ENABLED);
+	SmWrite32(AC97_CONTROL_STATUS, value);
+
+	/*
+	 * We're failing here but one should be able to use the codec
+	 * without firmware according to the manual
+	 */
+	ret = sm501_load_firmware(audio_dev, FIRMWARE);
+	if (ret < 0) {
+		dev_err(dev, "Error while loading firmware (%d)\n", ret);
+		if(retry++ < 5) /* If load error, retry it */
+			goto restart;
+		goto err;
+	}
+
+	audio_dev->firmware_loaded = 1;
+
+	spin_lock_init(&audio_dev->lock);
+
+	dev_info(dev, "SM501 AC97 Found\n");
+	return 0;
+
+err_alloc:
+	kfree(audio_dev);
+err:
+	return ret;
+}
+
+static void snd_sm501_ac97_remove(struct platform_device *pdev)
+{
+	unsigned int value;
+
+	/* Disable 8051 interrupt mask. */
+	value = SmRead32(INTERRUPT_MASK);
+	value = SET_FIELD(value, INTERRUPT_MASK_8051, DISABLE);
+	SmWrite32(INTERRUPT_MASK, value);
+
+
+	/* Put 8051 in reset state. */
+	value = SmRead32(U8051_RESET);
+	value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+	SmWrite32(U8051_RESET, value);
+
+	/* Disable SRAM. */
+	value = SmRead32(U8051_MODE_SELECT);
+	value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, DISABLED);
+	SmWrite32(U8051_MODE_SELECT, value);
+
+	/* Reset GPIO lines. */
+	value = SmRead32(GPIO_CONTROL_LOW);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+	value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+	SmWrite32(GPIO_CONTROL_LOW, value);
+
+	/* Disable 8051 and AC97. */
+	value = SmRead32(CURRENT_GATE);
+	value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, DISABLE);
+	value = SET_FIELD(value, CURRENT_GATE_8051, DISABLE);
+	sm501_set_gate(value);
+}
+
+static int snd_sm501_ac97_suspend (struct platform_device *pdev) {
+    
+    printk("SM502 AC97 Suspend....\n");
+
+    unsigned int value;
+    /* Disable 8051 interrupt mask. */
+    value = SmRead32(INTERRUPT_MASK);
+    value = SET_FIELD(value, INTERRUPT_MASK_8051, DISABLE);
+    SmWrite32(INTERRUPT_MASK, value);
+
+    /* Put 8051 in reset state. */
+    value = SmRead32(U8051_RESET);
+    value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+    SmWrite32(U8051_RESET, value);
+
+    /* Disable SRAM. */
+    value = SmRead32(U8051_MODE_SELECT);
+    value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, DISABLED);
+    SmWrite32(U8051_MODE_SELECT, value);
+
+    /* Reset GPIO lines. */
+    value = SmRead32(GPIO_CONTROL_LOW);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+    SmWrite32(GPIO_CONTROL_LOW, value);
+
+    /* Disable 8051 and AC97. */
+    value = SmRead32(CURRENT_GATE);
+    value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, DISABLE);
+    value = SET_FIELD(value, CURRENT_GATE_8051, DISABLE);
+    sm501_set_gate(value);
+    audio_dev->firmware_loaded = 0;
+}
+
+
+static int snd_sm501_ac97_resume (struct platform_device *pdev) {
+    struct device   *dev = &pdev->dev;
+    struct resource *res;
+    int ret = 0;
+    int res_len;
+    unsigned long value;
+
+    printk("SM502 AC97 Resume\n");
+
+    //Reset AC97 codec
+
+    /* Put 8051 in reset state. */
+    value = SmRead32(U8051_RESET);
+    value = SET_FIELD(value, U8051_RESET_CONTROL, RESET);
+    SmWrite32(U8051_RESET, value);
+
+    /* Reset GPIO lines. */
+    value = SmRead32(GPIO_CONTROL_LOW);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_28, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_27, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_26, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_25, GPIO);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_24, GPIO);
+    SmWrite32(GPIO_CONTROL_LOW, value);
+
+    /*Force GPIO28/SDIN GPIO27/SDOUT GPIO25/SYNC to low*/
+    value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_28, OUTPUT);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_27, OUTPUT);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_25, OUTPUT);
+    SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+    value = SmRead32(GPIO_DATA_LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_28, LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_27, LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_25, LOW);
+    SmWrite32(GPIO_DATA_LOW, value);
+
+
+    /*Force GPIO24/AC97 Reset to low*/
+    value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+    SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+    value = SmRead32(GPIO_DATA_LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_24, LOW);
+    SmWrite32(GPIO_DATA_LOW, value);
+    msleep(10);
+
+    /*Force GPIO24/AC97 Reset to high*/
+    value = SmRead32(GPIO_DATA_DIRECTION_LOW);
+    value = SET_FIELD(value, GPIO_DATA_DIRECTION_LOW_24, OUTPUT);
+    SmWrite32(GPIO_DATA_DIRECTION_LOW, value);
+
+
+    value = SmRead32(GPIO_DATA_LOW);
+    value = SET_FIELD(value, GPIO_DATA_LOW_24, HIGH);
+    SmWrite32(GPIO_DATA_LOW, value);
+
+
+    ////////////////////
+    value = SmRead32(GPIO_CONTROL_LOW);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_28, AC97_RX_I2S);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_27, AC97_TX_I2S);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_26, AC97_CLOCK_I2S);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_25, AC97_SYNC_I2S);
+    //	value = SET_FIELD(value, GPIO_CONTROL_LOW_24, SM501_AC97_RESET);
+    value = SET_FIELD(value, GPIO_CONTROL_LOW_24, AC97_RESET);
+    SmWrite32(GPIO_CONTROL_LOW, value);
+
+    /* Set arbitartion control */
+    value = SmRead32(ARBITRATION_CONTROL);
+    value = SET_FIELD(value, ARBITRATION_CONTROL_DMA, PRIORITY_1);
+    SmWrite32(ARBITRATION_CONTROL, value);
+
+    /* Enable interrupts */
+    value = SmRead32(INTERRUPT_MASK);
+    value = SET_FIELD(value, INTERRUPT_MASK_8051, ENABLE);
+    value = SET_FIELD(value, INTERRUPT_MASK_DMA, ENABLE);
+    SmWrite32(INTERRUPT_MASK, value);
+
+    /* Initialize chip. */
+    value = SmRead32(CURRENT_GATE);
+    value = SET_FIELD(value, CURRENT_GATE_AC97_I2S, ENABLE);
+    value = SET_FIELD(value, CURRENT_GATE_8051, ENABLE);
+    value = SET_FIELD(value, CURRENT_GATE_HOST_COMMAND_LIST_DMA, ENABLE);
+    value = SET_FIELD(value, CURRENT_GATE_GPIO_PWM_I2C, ENABLE);
+    sm501_set_gate(value);
+
+    value = SmRead32(U8051_MODE_SELECT);
+    value = SET_FIELD(value, U8051_MODE_SELECT_SRAM, ENABLED);
+    value = SET_FIELD(value, U8051_MODE_SELECT_TEST_MODE, NORMAL);
+    value = SET_FIELD(value, U8051_MODE_SELECT_CODEC_SELECT, AC97);
+    value = SET_FIELD(value, U8051_MODE_SELECT_DIVIDER, 2);
+    SmWrite32(U8051_MODE_SELECT, value);
+
+    value = SmRead32(AC97_CONTROL_STATUS);
+    value = SET_FIELD(value, AC97_CONTROL_STATUS_CONTROL, ENABLED);
+    SmWrite32(AC97_CONTROL_STATUS, value);
+
+    /*
+     * We're failing here but one should be able to use the codec
+     * without firmware according to the manual
+     */
+    ret = sm501_load_firmware(audio_dev, FIRMWARE);
+    if (ret < 0) {
+        dev_err(dev, "Error while loading firmware (%d)\n", ret);
+    }
+
+    audio_dev->firmware_loaded = 1;
+
+    return 0;
+}
+
+
+
+struct snd_soc_dai sm501_ac97_dai[] = {{
+	.name = DRV_NAME,
+	.id = 0,
+	.type = SND_SOC_DAI_AC97,
+	.probe = snd_sm501_ac97_probe,
+	.remove = snd_sm501_ac97_remove,
+	.suspend = snd_sm501_ac97_suspend,
+        .resume = snd_sm501_ac97_resume,
+	.playback = {
+		.stream_name = "AC97 Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_48000, /* SNDRV_PCM_RATE_8000_48000,*/
+		/* change to be with be systems */
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
+	.capture = {
+		.stream_name = "AC97 Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
+	.ops = {
+		.hw_params = snd_sm501_ac97_hw_params,
+		.prepare   = snd_sm501_ac97_prepare,
+	},
+},
+#if 0
+#warning Put mic here
+{}
+#endif
+};
+#if 1 // mj add 
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/smp_lock.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <linux/types.h>
+#include <linux/cdev.h>
+
+struct sm502ac97_reg{
+	unsigned char add;
+	unsigned short data;
+};
+
+
+typedef union sm502ac97_type
+{
+	unsigned char val;
+	struct sm502ac97_reg  reg;
+}sm502ac97_t;
+
+
+#define MAX_PINS 1
+#define DEVNAME "sm502ac97"
+
+static int sm502ac97_open(struct inode *inode, struct file *file)
+{
+
+	return 0;
+}
+
+static int sm502ac97_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+ssize_t sm502ac97_write(struct file *file, const char __user *data,size_t len, loff_t *ppos)
+{
+	sm502ac97_t a;
+
+	if (copy_from_user(&a, (sm502ac97_t __user *)data,sizeof(sm502ac97_t)))
+	{
+		return -EFAULT;
+	}
+//printk("-----a.reg.add:%02x a.reg.data:%04x-----\n",a.reg.add,a.reg.data);
+	 sm501_write_codec(audio_dev, a.reg.add,a.reg.data);
+
+	return 0;
+}
+ssize_t  sm502ac97_read(struct file *file, char __user * buf,size_t len, loff_t * ppos)
+{
+	sm502ac97_t a;
+	unsigned int data;
+
+	if (copy_from_user(&a, (sm502ac97_t __user *)buf,sizeof(sm502ac97_t)))
+	{
+		return -EFAULT;
+	}
+	data = sm501_read_codec(audio_dev, a.val);
+
+
+	return data;
+}
+
+int sm502ac97_ioctl(struct inode * node,struct file *file,unsigned int cmd,unsigned long arg)
+{
+	return 0;
+}
+
+static const struct file_operations sm502ac97_fileops = {
+	.owner   = THIS_MODULE,
+	.write   = sm502ac97_write,
+	.read    = sm502ac97_read,
+	.open    = sm502ac97_open,
+#ifdef CONFIG_64BIT
+	.compat_ioctl   = sm502ac97_ioctl,
+#else
+	.ioctl   = sm502ac97_ioctl,
+#endif
+	.release = sm502ac97_release,
+};
+
+static struct cdev sm502ac97_cdev;  /* use 1 cdev for all pins */
+
+static int major = 0;		/* default to dynamic major */
+static int __init sm502ac97_init(void)
+{
+	int rc;
+	dev_t devid;
+	struct class *my_class;
+	unsigned int ret;
+	int i=0;
+
+		printk(KERN_ERR " sm502ac97device_init.\n");
+	if (major) {
+		devid = MKDEV(major, 130);
+		//rc = register_chrdev_region(devid, MAX_PINS, DEVNAME);
+		rc = register_chrdev_region(devid,MAX_PINS, DEVNAME);
+	} else {
+		rc = alloc_chrdev_region(&devid, 0, MAX_PINS, DEVNAME);
+		major = MAJOR(devid);
+	}
+	if(rc < 0){
+		printk(KERN_ERR " sm502ac97_initalloc region filed.\n");
+		return rc;
+	}
+	cdev_init(&sm502ac97_cdev, &sm502ac97_fileops);
+	sm502ac97_cdev.owner = THIS_MODULE;
+
+
+	cdev_add(&sm502ac97_cdev, devid, MAX_PINS);
+
+		my_class = class_create(THIS_MODULE, "my_audio");
+		if(IS_ERR(my_class))
+		{
+			printk("Err: failed in creating class.\n");
+			return -1;
+		}
+
+		//ret=device_create( my_class, NULL, MKDEV(major, 0), "ch7028%d", i );
+		ret=device_create(my_class, NULL, MKDEV(major, 0), "sm502ac97%d" ,"sm502ac97",i);
+		printk(KERN_ERR " sm502ac97_device_major:%d,ret:%08x.\n",major,ret);
+
+
+	return 0; /* succeed */
+}
+
+static void __exit sm502ac97_cleanup(void)
+{
+	cdev_del(&sm502ac97_cdev);
+
+	unregister_chrdev_region(MKDEV(major, 0), MAX_PINS);
+}
+
+module_init(sm502ac97_init);
+module_exit(sm502ac97_cleanup);
+#endif
+EXPORT_SYMBOL_GPL(sm501_ac97_dai);
+
+MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_DESCRIPTION("ASoC AC97 driver for SM501 chip");
+MODULE_LICENSE("GPL");
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-ac97-dev.c linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-ac97-dev.c
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-ac97-dev.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-ac97-dev.c	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,119 @@
+/*
+ * sm501-ac97-dev.c  --  SoC audio for gdium
+ *
+ * Based on smdk2443_wm9710.c
+ *
+ * Arnaud Patard <apatard@mandriva.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <asm/gpio.h>
+
+#include "../codecs/ac97.h"
+#include "sm501-pcm.h"
+#include "sm501-ac97.h"
+
+#define SPEAKER_PWM		2
+#define SPEAKER_PWM_PERIOD	(1000000000/20000) /* 20 kHz */
+
+#define MUTE_GPIO		192+0 /* pin 32 is mute */
+#define AMP_MUTE		1
+#define AMP_UNMUTE		0
+
+static struct snd_soc_dai_link gdium_dai[] = {
+{
+	.name = "AC97",
+	.stream_name = "AC97 HiFi",
+	.cpu_dai = &sm501_ac97_dai[0],
+	.codec_dai = &ac97_dai,
+},
+};
+
+static struct snd_soc_machine gdium_machine = {
+	.name = "lyn",
+	.dai_link = gdium_dai,
+	.num_links = ARRAY_SIZE(gdium_dai),
+};
+
+static struct snd_soc_device gdium_snd_devdata = {
+	.machine = &gdium_machine,
+	.platform = &sm501_soc_platform,
+	.codec_dev = &soc_codec_dev_ac97,
+};
+
+static struct platform_device *gdium_snd_ac97_device;
+
+
+
+
+static int sm501_snd_probe(struct platform_device *pdev)
+{
+
+	int ret;
+
+	gdium_snd_ac97_device = platform_device_alloc("soc-audio", 1);
+	if (!gdium_snd_ac97_device)
+		return -ENOMEM;
+
+	gdium_snd_ac97_device->num_resources = pdev->num_resources;
+	gdium_snd_ac97_device->resource = pdev->resource;
+    gdium_snd_ac97_device->dev.parent = &pdev->dev;
+
+	platform_set_drvdata(gdium_snd_ac97_device,
+				&gdium_snd_devdata);
+	gdium_snd_devdata.dev = &gdium_snd_ac97_device->dev;
+	ret = platform_device_add(gdium_snd_ac97_device);
+
+	if (ret)
+		platform_device_put(gdium_snd_ac97_device);
+
+	return ret;
+}
+
+static void sm501_snd_remove(struct platform_device * pdev)
+{
+	platform_device_unregister(gdium_snd_ac97_device);
+}
+static struct platform_driver sm501_ac97_driver = {
+			.remove		= sm501_snd_remove,
+			.probe		= sm501_snd_probe,
+			.driver		= {
+			.name	= "sm501-audio",
+				.owner	= THIS_MODULE,
+			},
+};
+
+static int __devinit sm501_snd_init(void)
+{
+    return platform_driver_register(&sm501_ac97_driver);
+}
+
+static void __exit sm501_snd_cleanup(void)
+{
+	platform_driver_unregister(&sm501_ac97_driver);
+}
+
+
+module_init(sm501_snd_init);
+module_exit(sm501_snd_cleanup);
+
+
+
+/* Module information */
+MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_DESCRIPTION("ALSA SoC Gdium");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:gdium-audio");
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-ac97.h linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-ac97.h
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-ac97.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-ac97.h	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,26 @@
+/*
+ * AC97 support for SM50X chipsets
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _SM501_AC97_H
+#define _SM501_AC97_H
+
+#define SM501_AC97_CODEC_TIMEOUT	1000
+
+struct sm501_audio {
+	struct device	*dev;
+    struct resource	*res;
+	void __iomem * hw_buffer_addr;//the 3kb sram buffer virtual address
+//	void __iomem	*regs;	
+	int		irq;
+	int		firmware_loaded;
+	spinlock_t	lock;
+};
+
+extern struct snd_soc_dai sm501_ac97_dai[1];
+extern struct snd_ac97_bus_ops sm501_ac97_ops;
+
+#endif
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501_fw.h linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501_fw.h
--- linux-2.6.27.6/sound/soc/sm501.old/sm501_fw.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501_fw.h	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,126 @@
+#define FIRMWARE \
+":0300000002064CA9"\
+":10064C00787FE4F6D8FD9030007F007E10E4F0A3B4"\
+":0A065C00DFFCDEFA75812F12028424"\
+":1002840075E80675F804D2AFC2ADC2ACC2ABC2AA5F"\
+":10029400C2A9C2A8E4903FFFF0F50DF50C9091803F"\
+":1002A40004F0E4909100F0A37480F0E4909105F0E0"\
+":1002B400A3F0909108F0A3F0A3F090910CF0A3F0B8"\
+":1002C400A37408F0E4909110F0A3F0A37408F0E490"\
+":1002D400909141F0909140F0909146F0909145F0CA"\
+":1002E400909144F090914AF0909149F0909148F0A7"\
+":1002F40090918004F0909141E030E7F9903FFFE065"\
+":1003040004F0903FF0740FF0903FF27400F0A37487"\
+":1003140060F0A3740AF0903FF6E47A04F0A3DAFCE8"\
+":1003240012048A903FF6E055F060D7903FFFE00456"\
+":10033400F0E50D450C7009E52A60F612048A80F197"\
+":10034400E50D450C60EBE52A60F612048A80F12283"\
+":0F06BD00903FF3E0909101F0903FF17401F02233"\
+":10066600903FF3E0FC903FF4E0909106F090910506"\
+":09067600ECF0903FF17401F02258"\
+":10059600903FF2E0FC903FF3E0FD903FF4E0909155"\
+":1005A6000AF0ED909109F0EC909108F0903FF1740B"\
+":0305B60001F0222F"\
+":0D06DB00752800752930903FF17401F02260"\
+":1005B900903FF2E0FC903FF3E0F51F8C1E903FF472"\
+":1005C900E0FC903FF5E0F5218C20903FF17401F0BB"\
+":0105D90022FF"\
+":10069600903FF2E05403F9903FFCE049F0903FF1BF"\
+":0406A6007401F022C9"\
+":1005DA00903FFCE0FEA3E0FF903FF2E0FAA3E08A3E"\
+":0F05EA0082F583EEF0EFA3F0903FF17401F02261"\
+":1005F900903FF2E05401600B750C017528007529D4"\
+":0D060900308003750C00903FF17401F02269"\
+":0F06CC00909141E0903FF3F0903FF17401F022E4"\
+":10067F00909145E0FCA3E0903FF4F0903FF3ECF055"\
+":07068F00903FF17401F0221D"\
+":10061600909148E0FCA3E0FDA3E0903FF2ECF0A34C"\
+":0B062600EDF0A3F0903FF17401F02212"\
+":0D06E800752600752736903FF17401F02251"\
+":10063100903FF2E522F0A3E523F0903FF4E524F0AA"\
+":0B064100A3E525F0903FF17401F022CA"\
+":1006AA00903FF2E044CFF9903FFCE059903FF1745B"\
+":0306BA0001F0222A"\
+":10054A00903FF2E054016016903D20E4F07A07A350"\
+":10055A00F0DAFC752600752736750D018027750DB2"\
+":10056A0000E5269439F9E527400C75220085032316"\
+":10057A00F5248925800F752400752503E52794360F"\
+":0C058A00F523752200903FF1740EF02262"\
+":1004140090910812051900000000903FF2E0FCA33F"\
+":10042400E0FDA3E0FEA3E0FF90910412050D90917E"\
+":1004340001E044E0F0909106E0903D07F0E4F50E11"\
+":10044400F50FAE0EAF0FEE3395E0FDFC7B807A38EE"\
+":1004540079017800D31204F74024909141E054606C"\
+":10046400600A909141E0903D06F08012909141E045"\
+":10047400903D06F0050FE50F70C8050E80C49091FD"\
+":0604840001E05498F02293"\
+":10035400E4909108F0909109F090910AF0903FF2A6"\
+":10036400E0FCA3E0FDA3E09091064408F090910521"\
+":10037400EDF0909104ECF0909101E044E0F0E4F5AC"\
+":100384002BF52CAE2BAF2CEE3395E0FDFC7B807A65"\
+":100394003879017800D31204F750030203DD9091F9"\
+":1003A40001E044E0F0909141E054606021909101BB"\
+":1003B400E05498F0909148E0F9A3E0FAA3E0903F6C"\
+":1003C400F8F0903FF7EAF0903FF6E9F0800B052C47"\
+":1003D400E52C7002052B020387E4F52BF52CAE2BDC"\
+":1003E400AF2CEE3395E0FDFC7B807A387901780000"\
+":1003F400D31204F74012909141E05460600A052C36"\
+":10040400E52C7002052B80D6909101E05498F022DF"\
+":1001A400903FF6E0F519A3E0F51AA3E0F51B903FA4"\
+":1001B400F2E0FCA3E0FDA3E0909106F0909105ED40"\
+":1001C400F0909104ECF0903FF6E0FCA3E0FDA3E096"\
+":1001D40090910AF0909109EDF0909108ECF0903F25"\
+":1001E400F17401F0909106E0540860041203542263"\
+":1001F400909101E044E0F0751D03E51D70FC9091C1"\
+":1002040001E05498F0751D14E51D70FCE4F52DF51E"\
+":100214002EAE2DAF2EEE3395E0FDFC7B807A38793F"\
+":10022400017800D31204F74012909141E0546060C9"\
+":100234000A052EE52E7002052D80D6AE2DAF2EEECA"\
+":100244003395E0FDFC7B807A3879017800D3120481"\
+":10025400F7401F120354903FF6E09519700DA3E088"\
+":10026400951A7007A3E0951B700122903FF1E5FFFA"\
+":10027400F022909101E05498F0903FF174FFF02245"\
+":10048A00903FFD7401F0E4903FF1F075F005903F64"\
+":10049A00F0E0A49004A1731206BD8049120666809A"\
+":1004AA0044120596803F1206DB803A1205B9803560"\
+":1004BA0012069680301205DA802B1205F980261270"\
+":1004CA0006CC802112067F801C120616801712069F"\
+":1004DA00E88012120631800D1206AA800812054A17"\
+":0D04EA0080031201A4E4F52A903FFDF022EA"\
+":0300430002004672"\
+":10004600C0E0C083C082C2AF53E8F9752F007518AF"\
+":1000560000E50D70030200DE909141E05418700334"\
+":100066000200DE90914CE0852682852783F00526E6"\
+":1000760090914DE0852682852783F0052690914E46"\
+":10008600E0852682852783F005260526909150E097"\
+":10009600852682852783F00526909151E085268264"\
+":1000A600852783F00526909152E085268285278351"\
+":1000B600F005260526E526701F0527E527643B7013"\
+":1000C60008431810752F01800FE527643E70094319"\
+":1000D6001820752738752F01E50C700302017390FF"\
+":1000E6009145E0540C600A909101E054E7F002015A"\
+":1000F60073909101E04498F0852882852983E090E9"\
+":10010600910CF00528852882852983E090910DF0D1"\
+":100116000528852882852983E090910EF00528051B"\
+":1001260028852882852983E0909110F00528852866"\
+":1001360082852983E0909111F005288528828529FA"\
+":1001460083E0909112F005280528E528701F0529FF"\
+":10015600E52964347008431801752F01800FE529DD"\
+":1001660064387009431802752930752F01E52F6030"\
+":100176000C903FFCE518F09090087401F090918186"\
+":05018600E054FC6004E0"\
+":10018B00E05403F0781DE660011643E80643F804DB"\
+":09019B00D2AFD082D083D0E03253"\
+":03003B00020003BD"\
+":10000300C0E0C083C082C0D075D010C2AF53E8F93E"\
+":10001300752A01903FFD7401F090900CE0FF339539"\
+":10002300E08F0BF50AF509F50843E806D2AFD0D007"\
+":07003300D082D083D0E0323F"\
+":1004F700EB9FF5F0EA9E42F0E99D42F0EC6480C87C"\
+":0605070064809845F0221B"\
+":0C050D00ECF0A3EDF0A3EEF0A3EFF02261"\
+":10051900A8828583F0D083D082120530120530126B"\
+":100529000530120530E473E493A3C583C5F0C58390"\
+":10053900C8C582C8F0A3C583C5F0C583C8C582C82C"\
+":01054900228F"\
+":00000001FF"
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501_fw.h.bak linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501_fw.h.bak
--- linux-2.6.27.6/sound/soc/sm501.old/sm501_fw.h.bak	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501_fw.h.bak	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,126 @@
+#define FIRMWARE \
+":0300000002064CA9" \
+":10064C00787FE4F6D8FD9030007F007E10E4F0A3B4" \
+":0A065C00DFFCDEFA75812F12028424" \
+":1002840075E80675F804D2AFC2ADC2ACC2ABC2AA5F" \
+":10029400C2A9C2A8E4903FFFF0F50DF50C9091803F" \
+":1002A40004F0E4909100F0A37480F0E4909105F0E0" \
+":1002B400A3F0909108F0A3F0A3F090910CF0A3F0B8" \
+":1002C400A37408F0E4909110F0A3F0A37408F0E490" \
+":1002D400909141F0909140F0909146F0909145F0CA" \
+":1002E400909144F090914AF0909149F0909148F0A7" \
+":1002F40090918004F0909141E030E7F9903FFFE065" \
+":1003040004F0903FF0740FF0903FF27400F0A37487" \
+":1003140060F0A3740AF0903FF6E47A04F0A3DAFCE8" \
+":1003240012048A903FF6E055F060D7903FFFE00456" \
+":10033400F0E50D450C7009E52A60F612048A80F197" \
+":10034400E50D450C60EBE52A60F612048A80F12283" \
+":0F06BD00903FF3E0909101F0903FF17401F02233" \
+":10066600903FF3E0FC903FF4E0909106F090910506" \
+":09067600ECF0903FF17401F02258" \
+":10059600903FF2E0FC903FF3E0FD903FF4E0909155" \
+":1005A6000AF0ED909109F0EC909108F0903FF1740B" \
+":0305B60001F0222F" \
+":0D06DB00752800752930903FF17401F02260" \
+":1005B900903FF2E0FC903FF3E0F51F8C1E903FF472" \
+":1005C900E0FC903FF5E0F5218C20903FF17401F0BB" \
+":0105D90022FF" \
+":10069600903FF2E05403F9903FFCE049F0903FF1BF" \
+":0406A6007401F022C9" \
+":1005DA00903FFCE0FEA3E0FF903FF2E0FAA3E08A3E" \
+":0F05EA0082F583EEF0EFA3F0903FF17401F02261" \
+":1005F900903FF2E05401600B750C017528007529D4" \
+":0D060900308003750C00903FF17401F02269" \
+":0F06CC00909141E0903FF3F0903FF17401F022E4" \
+":10067F00909145E0FCA3E0903FF4F0903FF3ECF055" \
+":07068F00903FF17401F0221D" \
+":10061600909148E0FCA3E0FDA3E0903FF2ECF0A34C" \
+":0B062600EDF0A3F0903FF17401F02212" \
+":0D06E800752600752736903FF17401F02251" \
+":10063100903FF2E522F0A3E523F0903FF4E524F0AA" \
+":0B064100A3E525F0903FF17401F022CA" \
+":1006AA00903FF2E044CFF9903FFCE059903FF1745B" \
+":0306BA0001F0222A" \
+":10054A00903FF2E054016016903D20E4F07A07A350" \
+":10055A00F0DAFC752600752736750D018027750DB2" \
+":10056A0000E5269439F9E527400C75220085032316" \
+":10057A00F5248925800F752400752503E52794360F" \
+":0C058A00F523752200903FF1740EF02262" \
+":1004140090910812051900000000903FF2E0FCA33F" \
+":10042400E0FDA3E0FEA3E0FF90910412050D90917E" \
+":1004340001E044E0F0909106E0903D07F0E4F50E11" \
+":10044400F50FAE0EAF0FEE3395E0FDFC7B807A38EE" \
+":1004540079017800D31204F74024909141E054606C" \
+":10046400600A909141E0903D06F08012909141E045" \
+":10047400903D06F0050FE50F70C8050E80C49091FD" \
+":0604840001E05498F02293" \
+":10035400E4909108F0909109F090910AF0903FF2A6" \
+":10036400E0FCA3E0FDA3E09091064408F090910521" \
+":10037400EDF0909104ECF0909101E044E0F0E4F5AC" \
+":100384002BF52CAE2BAF2CEE3395E0FDFC7B807A65" \
+":100394003879017800D31204F750030203DD9091F9" \
+":1003A40001E044E0F0909141E054606021909101BB" \
+":1003B400E05498F0909148E0F9A3E0FAA3E0903F6C" \
+":1003C400F8F0903FF7EAF0903FF6E9F0800B052C47" \
+":1003D400E52C7002052B020387E4F52BF52CAE2BDC" \
+":1003E400AF2CEE3395E0FDFC7B807A387901780000" \
+":1003F400D31204F74012909141E05460600A052C36" \
+":10040400E52C7002052B80D6909101E05498F022DF" \
+":1001A400903FF6E0F519A3E0F51AA3E0F51B903FA4" \
+":1001B400F2E0FCA3E0FDA3E0909106F0909105ED40" \
+":1001C400F0909104ECF0903FF6E0FCA3E0FDA3E096" \
+":1001D40090910AF0909109EDF0909108ECF0903F25" \
+":1001E400F17401F0909106E0540860041203542263" \
+":1001F400909101E044E0F0751D03E51D70FC9091C1" \
+":1002040001E05498F0751D14E51D70FCE4F52DF51E" \
+":100214002EAE2DAF2EEE3395E0FDFC7B807A38793F" \
+":10022400017800D31204F74012909141E0546060C9" \
+":100234000A052EE52E7002052D80D6AE2DAF2EEECA" \
+":100244003395E0FDFC7B807A3879017800D3120481" \
+":10025400F7401F120354903FF6E09519700DA3E088" \
+":10026400951A7007A3E0951B700122903FF1E5FFFA" \
+":10027400F022909101E05498F0903FF174FFF02245" \
+":10048A00903FFD7401F0E4903FF1F075F005903F64" \
+":10049A00F0E0A49004A1731206BD8049120666809A" \
+":1004AA0044120596803F1206DB803A1205B9803560" \
+":1004BA0012069680301205DA802B1205F980261270" \
+":1004CA0006CC802112067F801C120616801712069F" \
+":1004DA00E88012120631800D1206AA800812054A17" \
+":0D04EA0080031201A4E4F52A903FFDF022EA" \
+":0300430002004672" \
+":10004600C0E0C083C082C2AF53E8F9752F007518AF" \
+":1000560000E50D70030200DE909141E05418700334" \
+":100066000200DE90914CE0852682852783F00526E6" \
+":1000760090914DE0852682852783F0052690914E46" \
+":10008600E0852682852783F005260526909150E097" \
+":10009600852682852783F00526909151E085268264" \
+":1000A600852783F00526909152E085268285278351" \
+":1000B600F005260526E526701F0527E52764397015" \
+":1000C60008431810752F01800FE527643C7009431B" \
+":1000D6001820752736752F01E50C70030201739001" \
+":1000E6009145E0540C600A909101E054E7F002015A" \
+":1000F60073909101E04498F0852882852983E090E9" \
+":10010600910CF00528852882852983E090910DF0D1" \
+":100116000528852882852983E090910EF00528051B" \
+":1001260028852882852983E0909110F00528852866" \
+":1001360082852983E0909111F005288528828529FA" \
+":1001460083E0909112F005280528E528701F0529FF" \
+":10015600E52964337008431801752F01800FE529DE" \
+":1001660064367009431802752930752F01E52F6032" \
+":100176000C903FFCE518F09090087401F090918186" \
+":05018600E054FC6004E0" \
+":10018B00E05403F0781DE660011643E80643F804DB" \
+":09019B00D2AFD082D083D0E03253" \
+":03003B00020003BD" \
+":10000300C0E0C083C082C0D075D010C2AF53E8F93E" \
+":10001300752A01903FFD7401F090900CE0FF339539" \
+":10002300E08F0BF50AF509F50843E806D2AFD0D007" \
+":07003300D082D083D0E0323F" \
+":1004F700EB9FF5F0EA9E42F0E99D42F0EC6480C87C" \
+":0605070064809845F0221B" \
+":0C050D00ECF0A3EDF0A3EEF0A3EFF02261" \
+":10051900A8828583F0D083D082120530120530126B" \
+":100529000530120530E473E493A3C583C5F0C58390" \
+":10053900C8C582C8F0A3C583C5F0C583C8C582C82C" \
+":01054900228F" \
+":00000001FF"
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-pcm.c linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-pcm.c
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-pcm.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-pcm.c	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,659 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+
+#include "sm501-ac97.h"
+#include "sm501-pcm.h"
+#include "sm501-u8051.h"
+
+
+#define DRV_NAME                        "sm501-audio"
+
+#ifdef DEBUG
+#define dprintk(msg...) do { printk(KERN_DEBUG DRV_NAME ": " msg); } while (0)
+#else
+#define dprintk(msg...)
+#endif
+
+static void do_audio_p_tasklet(unsigned long);
+DECLARE_TASKLET(audio_p_tasklet,do_audio_p_tasklet,0);
+static void do_audio_c_tasklet(unsigned long);
+DECLARE_TASKLET(audio_c_tasklet,do_audio_c_tasklet,0);
+
+struct sm501_runtime_data_father{
+	struct sm501_runtime_data * play_data;
+	struct sm501_runtime_data * capture_data;
+};
+
+
+struct sm501_runtime_data {
+	spinlock_t lock;
+	struct sm501_pcm_dma_params *params;
+	struct snd_pcm_substream *psubstream;
+	unsigned long ppointer; /* playback pointer in bytes */
+	struct snd_pcm_substream *csubstream;
+	unsigned long cpointer;	//capture buffer pointer in bytes
+};
+
+/*hardware definition */
+static struct sm501_runtime_data_father * g_father = NULL;
+
+static struct snd_pcm_hardware snd_sm501_playback_hw = {
+	.info = (SNDRV_PCM_INFO_MMAP |
+			SNDRV_PCM_INFO_INTERLEAVED |
+			SNDRV_PCM_INFO_BLOCK_TRANSFER |
+			SNDRV_PCM_INFO_MMAP_VALID |
+			SNDRV_PCM_INFO_HALF_DUPLEX |
+			SNDRV_PCM_INFO_BATCH),
+	.formats =          SNDRV_PCM_FMTBIT_S16_LE,
+	.rates =            SNDRV_PCM_RATE_48000, /*SNDRV_PCM_RATE_8000_48000,*/
+	.rate_min =         48000, /* 8000,*/
+	.rate_max =         48000,
+	.channels_min =     2,
+	.channels_max =     2,
+	.buffer_bytes_max = SM501_AC97_P_PERIOD_SIZE * SM501_AC97_P_PERIOD_COUNT,
+	.period_bytes_min = SM501_AC97_P_PERIOD_SIZE,
+	.period_bytes_max = SM501_AC97_P_PERIOD_SIZE,
+	.periods_min =      32,//change to 32 from 4
+	.periods_max =      SM501_AC97_P_PERIOD_COUNT,
+};
+
+
+static struct snd_pcm_hardware snd_sm501_capture_hw = {
+	.info = (SNDRV_PCM_INFO_MMAP |
+			SNDRV_PCM_INFO_INTERLEAVED |
+			SNDRV_PCM_INFO_BLOCK_TRANSFER |
+			SNDRV_PCM_INFO_MMAP_VALID |
+			SNDRV_PCM_INFO_HALF_DUPLEX |
+			SNDRV_PCM_INFO_BATCH),
+	.formats =          SNDRV_PCM_FMTBIT_S16_LE,
+	.rates =            SNDRV_PCM_RATE_48000,
+	.rate_min =         48000,
+	.rate_max =         48000,
+	.channels_min =     2,
+	.channels_max =     2,
+	.buffer_bytes_max = SM501_AC97_C_PERIOD_SIZE * SM501_AC97_C_PERIOD_COUNT,
+	.period_bytes_min = SM501_AC97_C_PERIOD_SIZE,
+	.period_bytes_max = SM501_AC97_C_PERIOD_SIZE,
+	.periods_min =      32,//change to 32 from 4
+	.periods_max =      SM501_AC97_C_PERIOD_COUNT,
+};
+static void snd_sm501_copy_pdata(struct sm501_runtime_data *);
+static void snd_sm501_copy_cdata(struct sm501_runtime_data *);
+
+
+static void do_audio_p_tasklet(unsigned long ptr)
+{
+	struct sm501_runtime_data * rtdata;
+	rtdata = (struct sm501_runtime_data *)ptr;	
+	snd_sm501_copy_pdata(rtdata);
+}
+
+static void do_audio_c_tasklet(unsigned long ptr)
+{
+	struct sm501_runtime_data * rtdata;
+	rtdata = (struct sm501_runtime_data *)ptr;	
+	snd_sm501_copy_cdata(rtdata);
+}
+
+
+/*
+ * allocate a buffer via vmalloc_32().
+ * called from hw_params
+ * NOTE: this may be called not only once per pcm open!
+*/
+static int snd_sm501_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs,
+					      size_t size)
+{
+	struct snd_pcm_runtime *runtime = subs->runtime;
+	if (runtime->dma_area) {
+		/* already allocated */
+		if (runtime->dma_bytes >= size)
+			return 0; /* already enough large */
+		vfree(runtime->dma_area);
+	}
+	runtime->dma_area = vmalloc_32(size);
+	if (! runtime->dma_area)
+		return -ENOMEM;
+	memset(runtime->dma_area, 0, size);
+	runtime->dma_bytes = size;
+	return 1; /* changed */
+}
+
+/*
+ * free the buffer.
+ * called from hw_free callback
+ * NOTE: this may be called not only once per pcm open!
+ */
+static int snd_sm501_pcm_free_vmalloc_buffer(struct snd_pcm_substream *subs)
+{
+	struct snd_pcm_runtime *runtime = subs->runtime;
+	if (runtime->dma_area) {
+		vfree(runtime->dma_area);
+		runtime->dma_area = NULL;
+	}
+	return 0;
+}
+
+/*
+* Copy playback data into the hardware buffer
+*/
+static void snd_sm501_copy_pdata(struct sm501_runtime_data *rtdata)
+{
+	u16  *phalfframe;
+	u32  *pdest;
+	u32  *pborder;
+	struct snd_pcm_runtime *runtime;
+	unsigned char status;
+
+	if (rtdata->psubstream==NULL) {
+		return;
+	}
+
+	runtime = rtdata->psubstream->runtime;
+
+	if (runtime->dma_area == NULL) {
+		return;
+	}
+
+	status = SmRead8(SRAM(buffer_status)) & 0x3;
+	if (status==0x2)
+		pdest = (u32*)rtdata->params->s->hw_buffer_addr + 256;
+	else
+		pdest = (u32*)rtdata->params->s->hw_buffer_addr;
+
+	pborder = pdest + (SM501_AC97_P_PERIOD_SIZE / (sizeof(u32)));
+
+	do {
+		/* Sample format : */
+		/* 32 ... 20 | 19 ... 4 | 3-0 */
+		/* reserved  | 16b sampl| opt */
+		
+		/* Left */
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->ppointer);
+		*pdest++ = (u32)*phalfframe << 4;
+		phalfframe++;
+
+		/* Right */
+		*pdest++ = (u32)*phalfframe << 4;
+		rtdata->ppointer += 4;
+	} while (pdest < pborder);
+
+	rtdata->ppointer %= (SM501_AC97_P_PERIOD_SIZE) * runtime->periods;
+
+	snd_pcm_period_elapsed(rtdata->psubstream);
+
+}
+
+/*
+ * Fill the playback buffers with audio data
+ * Just the first 768 bytes
+ */
+static void snd_sm501_pfill(struct sm501_runtime_data *rtdata)
+{
+	u16 *phalfframe;
+	u32 *pdest;
+	u32 *pborder;
+	struct snd_pcm_runtime *runtime;
+
+	if (rtdata->psubstream==NULL) {
+		return;
+	}
+
+	runtime = rtdata->psubstream->runtime;
+
+	if (runtime->dma_area == NULL) {
+		return;
+	}
+
+	phalfframe = (u16 *) (runtime->dma_area	+ frames_to_bytes(runtime, rtdata->ppointer));
+	//pdest = (u32 *) SRAM(A.B.playback_buffer_0);
+	pdest = (u32*)rtdata->params->s->hw_buffer_addr;
+	pborder = pdest + (SM501_AC97_P_PERIOD_SIZE / (sizeof(u32)));
+	
+#if 1
+	do{
+		phalfframe = (u16*)(runtime->dma_area + rtdata->ppointer);
+		*pdest++ = (u32)((*phalfframe) << 4);
+		rtdata->ppointer += 2;
+
+		phalfframe = (u16*)(runtime->dma_area + rtdata->ppointer);
+		*pdest++ = (u32)((*phalfframe) << 4);
+		rtdata->ppointer += 2;
+	}while(pdest < pborder);	
+	
+#else
+	do {
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->ppointer);
+		SmWrite32((unsigned long) pdest,*phalfframe  << 4);
+		pdest++;
+		rtdata->ppointer += 2;
+
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->ppointer);
+		SmWrite32((unsigned long) pdest,*phalfframe << 4);
+		pdest++;
+		rtdata->ppointer += 2;
+	} while (pdest < pborder);
+#endif	
+}
+
+/*
+ * Copy capture data into software buffer
+ * This function can also be called as tasklet!
+*/
+static void snd_sm501_copy_cdata(struct sm501_runtime_data *rtdata)
+{
+	volatile u16 *phalfframe;
+	u32  *psrc;
+	u32  *pborder;
+	struct snd_pcm_runtime *runtime;
+	unsigned char status;
+
+	if (rtdata->csubstream==NULL) {
+		return;
+	}
+
+	runtime = rtdata->csubstream->runtime;
+
+	if (runtime->dma_area == NULL) {
+		return;
+	}
+
+	status = SmRead8(SRAM(buffer_status)) & 0x30;
+	if (status==0x20)
+		//psrc = (u32 *) SRAM(A.C.capture_buffer_1);
+		psrc = (u32*)rtdata->params->s->hw_buffer_addr + 704;
+	else
+		//psrc = (u32 *) SRAM(A.C.capture_buffer_0);
+		psrc = (u32*)rtdata->params->s->hw_buffer_addr + 512;
+
+	pborder = psrc + (SM501_AC97_C_PERIOD_SIZE / (sizeof(u32)));
+
+	do {
+		/* Sample format : */
+		/* 32 ... 20 | 19 ... 4 | 3-0 */
+		/* reserved  | 16b sampl| opt */
+		/* Left */
+		phalfframe = (u16 *) (runtime->dma_area + rtdata->cpointer);
+		//*phalfframe = (SmRead32((unsigned long) psrc) >> 4) & 0xffff;
+		*phalfframe = (*psrc++)>>4;
+		phalfframe++;
+
+		/* Right */
+		//*phalfframe = (SmRead32((unsigned long) psrc) >> 4) & 0xffff;
+		*phalfframe =(*psrc++)>>4;
+		rtdata->cpointer += 4;
+	} while (psrc < pborder);
+
+	rtdata->cpointer %= (SM501_AC97_C_PERIOD_SIZE) * runtime->periods;
+
+	snd_pcm_period_elapsed(rtdata->csubstream);
+}
+
+/* hw_params callback */
+static int snd_sm501_pcm_hw_params(struct snd_pcm_substream *substream,
+				   struct snd_pcm_hw_params * hw_params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sm501_runtime_data *rtdata = runtime->private_data;
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct sm501_pcm_dma_params *dma = rtd->dai->cpu_dai->dma_data;
+
+	
+	if (rtdata->params == NULL) {
+		rtdata->params = dma;
+	}
+
+	return snd_sm501_pcm_alloc_vmalloc_buffer(substream,
+			params_buffer_bytes(hw_params));
+}
+
+
+/* hw_free callback */
+static int snd_sm501_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+	dprintk("pcm_hw_free\n");
+
+	return snd_sm501_pcm_free_vmalloc_buffer(substream);
+}
+
+
+/* prepare callback */
+static int snd_sm501_pcm_prepare(struct snd_pcm_substream *substream)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+
+	dprintk("pcm_playback_prepare\n");
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
+		rtdata->ppointer = 0;
+	}
+	else{
+		rtdata->cpointer = 0;
+	}
+
+	return 0;
+}
+#if 1
+static irqreturn_t snd_sm501_u8051_irq(int irq,void * dev_id)
+{
+	struct sm501_runtime_data_father * father = (struct sm501_runtime_data_father *)dev_id;
+	u32 status,mask;
+	
+	status = SmRead32(INTERRUPT_STATUS);
+	if(TEST_FIELD(status,INTERRUPT_STATUS_8051,NOT_ACTIVE))
+		return IRQ_NONE;
+
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK,SET_FIELD(mask,INTERRUPT_MASK_8051,DISABLE));
+	
+	SmRead32(U8051_8051_PROTOCOL_INTERRUPT);
+	
+	status = SmRead8(SRAM(buffer_status));
+
+	if(status & 0x03){
+		//printk("b=%02x\n",status);
+		if(father->play_data){
+			audio_p_tasklet.data = (ulong)father->play_data;
+			tasklet_hi_schedule(&audio_p_tasklet);
+		}
+	}
+
+	if(status & 0x30){
+		if(father->capture_data){
+			audio_c_tasklet.data = (ulong)father->capture_data;
+			tasklet_hi_schedule(&audio_c_tasklet);			
+		}
+	}
+
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK,SET_FIELD(mask,INTERRUPT_MASK_8051,ENABLE));
+	return IRQ_HANDLED;
+	
+}
+
+#else
+static irqreturn_t snd_sm501_u8051_irq(int irq, void* dev_id)
+{
+	struct sm501_runtime_data *rtdata = (struct sm501_runtime_data *)dev_id;
+	struct sm501_audio *s = rtdata->params->s;
+	unsigned int status, mask;
+	unsigned long flags;
+
+
+	/* Read interrupt status. */
+	status = SmRead32(INTERRUPT_STATUS);
+	if (TEST_FIELD(status, INTERRUPT_STATUS_8051, NOT_ACTIVE))
+		return IRQ_NONE;
+
+	/* Reset 8051 interrupt status. */
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK, SET_FIELD(mask, INTERRUPT_MASK_8051, DISABLE));
+
+	spin_lock_irqsave(&s->lock, flags);
+	SmRead32(U8051_8051_PROTOCOL_INTERRUPT);
+
+	/* Check 8051 buffer status. */
+	status = SmRead8(SRAM(buffer_status));
+
+	if (status != 0) {
+		if (status & 0x0F) {	//playback buffer full
+			snd_sm501_copy_pdata(rtdata);
+		}
+		if (status & 0xF0) {	//record buffer full
+ 			snd_sm501_copy_cdata(rtdata);
+		}
+	}
+
+	spin_unlock_irqrestore(&s->lock, flags);
+	mask = SmRead32(INTERRUPT_MASK);
+	SmWrite32(INTERRUPT_MASK, SET_FIELD(mask, INTERRUPT_MASK_8051, ENABLE));
+
+	return IRQ_HANDLED;
+}
+#endif
+
+
+/* trigger callback */
+static int snd_sm501_pcm_playback_trigger(struct snd_pcm_substream *substream,
+					  int cmd)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+	struct sm501_audio *s = rtdata->params->s;
+
+
+	spin_lock(&s->lock);
+
+	switch (cmd) {
+		case SNDRV_PCM_TRIGGER_START:
+			dprintk("pcm_playback_trigger: start\n");
+			rtdata->psubstream = substream;
+			snd_sm501_pfill(rtdata);
+			//sm501_write_command(s, SET_PLAYBACK_BUFFER_READY, 3, 0);
+			sm501_write_command(s, START_STOP_AUDIO_PLAYBACK, 1, 0);
+			break;
+		case SNDRV_PCM_TRIGGER_STOP:
+			dprintk("pcm_playback_trigger: stop\n");
+			sm501_write_command(s, START_STOP_AUDIO_PLAYBACK, 0, 0);
+			rtdata->psubstream = NULL;
+			break;
+		default:
+			dprintk("pcm_playback_trigger: default (%i)\n", cmd);
+			return -EINVAL;
+	}
+	spin_unlock(&s->lock);
+
+	return 0;
+}
+static int snd_sm501_pcm_capture_trigger(struct snd_pcm_substream *substream,
+					 int cmd)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+	struct sm501_audio *s = rtdata->params->s;
+
+	spin_lock(&s->lock);
+
+	switch (cmd) {
+		case SNDRV_PCM_TRIGGER_START:
+			sm501_write_command(s, SET_CAPTURE_BUFFER_EMPTY, 3, 0);
+			dprintk("pcm_capture_trigger: start\n");
+			rtdata->csubstream = substream;
+			sm501_write_command(s, START_STOP_AUDIO_CAPTURE, 1, 0);
+			break;
+		case SNDRV_PCM_TRIGGER_STOP:
+			dprintk("pcm_capture_trigger: stop\n");
+			sm501_write_command(s, START_STOP_AUDIO_CAPTURE, 0, 0);
+			rtdata->csubstream = NULL;
+			break;
+		default:
+			dprintk("pcm_capture_trigger: default (%i)\n", cmd);
+			return -EINVAL;
+	}
+
+	spin_unlock(&s->lock);
+
+	return 0;
+}
+
+static int snd_sm501_pcm_trigger(struct snd_pcm_substream *substream,
+					 int cmd)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		return snd_sm501_pcm_playback_trigger(substream, cmd);
+	else
+		return snd_sm501_pcm_capture_trigger(substream, cmd);
+
+}
+/* open callback */
+static int snd_sm501_open(struct snd_pcm_substream *substream)
+{
+
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sm501_runtime_data *rtdata;
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai_link *machine = rtd->dai;
+	struct snd_soc_dai *cpu_dai = machine->cpu_dai;
+	struct sm501_audio *s;
+	int ret;
+	
+	cpu_dai->ops.hw_params(substream,0);
+	s = ((struct sm501_pcm_dma_params *)cpu_dai->dma_data)->s;
+
+	rtdata = kzalloc(sizeof(struct sm501_runtime_data), GFP_KERNEL);
+	if (rtdata == NULL)
+		return -ENOMEM;
+
+	//we do not need below lock initialized,because there is no use of it ...
+//	spin_lock_init(&rtdata->lock);
+	runtime->private_data = rtdata;
+	
+	
+#if 0
+		/* mute the record in */
+		u16 rg;
+		rg = soc_ac97_ops.read(NULL,AC97_MIC);
+		soc_ac97_ops.write(NULL,AC97_MIC,rg|0x8000);
+		
+		rg = soc_ac97_ops.read(NULL,AC97_LINE);
+		soc_ac97_ops.write(NULL,AC97_LINE,rg|0x8000); 
+	
+		/* setting codec */
+#endif
+
+	/* 	use global lock to prevent the simultaneous calling from 
+		capture open and playback open
+		we should use lock in every routine that access global resource 
+		and with re-entrance attribuite for thorough safety
+	*/
+	spin_lock(&s->lock);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
+		snd_soc_set_runtime_hwparams(substream, &snd_sm501_playback_hw);
+		g_father->play_data = rtdata;
+	}
+	else{
+		snd_soc_set_runtime_hwparams(substream, &snd_sm501_capture_hw);
+		g_father->capture_data = rtdata;
+	}
+
+	request_irq(s->irq, snd_sm501_u8051_irq,
+				IRQF_SHARED | IRQF_DISABLED, "sm501-pcm", g_father);
+
+	spin_unlock(&s->lock);
+	
+	return 0;
+}
+
+static int snd_sm501_close(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sm501_runtime_data *rtdata = runtime->private_data;
+	struct sm501_audio *s = rtdata->params->s;
+
+	dprintk("Entered %s\n", __FUNCTION__);
+
+	if (rtdata)
+	{
+		kfree(rtdata);
+		spin_lock(&s->lock);
+		if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)			
+			g_father->play_data = NULL;
+		else
+			g_father->capture_data = NULL;
+		spin_unlock(&s->lock);
+	}
+	else
+		printk("%s called with rtdata == NULL\n", __func__);
+
+	free_irq(s->irq, g_father);
+
+	return 0;
+}
+
+/* pointer callback */
+static snd_pcm_uframes_t snd_sm501_pcm_pointer(struct snd_pcm_substream *substream)
+{
+	struct sm501_runtime_data *rtdata = substream->runtime->private_data;
+	snd_pcm_uframes_t value = 0;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		value = bytes_to_frames(substream->runtime, rtdata->ppointer);
+	else
+		value = bytes_to_frames(substream->runtime, rtdata->cpointer);
+	return value;
+}
+
+/* get the physical page pointer on the given offset */
+static struct page *snd_sm501_pcm_get_vmalloc_page(struct snd_pcm_substream *subs,
+		unsigned long offset)
+{
+	void *pageptr = subs->runtime->dma_area + offset;
+
+	return vmalloc_to_page(pageptr);
+}
+
+
+/* operators */
+static struct snd_pcm_ops snd_sm501_ops = {
+	.open =		snd_sm501_open,
+	.close =	snd_sm501_close,
+	.ioctl =	snd_pcm_lib_ioctl,
+	.hw_params =	snd_sm501_pcm_hw_params,
+	.hw_free =	snd_sm501_pcm_hw_free,
+	.prepare =	snd_sm501_pcm_prepare,
+	.trigger =	snd_sm501_pcm_trigger,
+	.pointer =	snd_sm501_pcm_pointer,
+	.page =		snd_sm501_pcm_get_vmalloc_page,
+};
+
+int sm501_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
+	struct snd_pcm *pcm)
+{
+	int ret = 0;
+	static int nt = 0;
+	struct sm501_runtime_data_father * father;
+	father = kzalloc(sizeof (*father),GFP_KERNEL);
+	if(!father)
+		return -ENOMEM;	
+	g_father = father;
+
+	return ret;
+}
+
+static void sm501_pcm_free(struct snd_pcm *pcm)
+{
+	if(g_father)
+		kfree(g_father);
+}
+
+struct snd_soc_platform sm501_soc_platform = {
+	.name		= "sm501-snd",
+	.pcm_ops 	= &snd_sm501_ops,
+	.pcm_new	= sm501_pcm_new,
+	.pcm_free	= sm501_pcm_free,
+};
+
+EXPORT_SYMBOL_GPL(sm501_soc_platform);
+
+
+MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_DESCRIPTION("SM501 pcm module");
+MODULE_LICENSE("GPL");
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-pcm.h linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-pcm.h
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-pcm.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-pcm.h	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,27 @@
+/*
+ *  Based on s3c24xx-pcm.h
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef _SM501_PCM_H
+#define _SM501_PCM_H
+
+
+#define SM501_AC97_P_PERIOD_SIZE  1024
+#define SM501_AC97_P_PERIOD_COUNT 256
+#define SM501_AC97_C_PERIOD_SIZE  768
+#define SM501_AC97_C_PERIOD_COUNT 256
+
+struct sm501_pcm_dma_params {
+	struct sm501_audio *s;
+};
+
+/* platform data */
+extern struct snd_soc_platform sm501_soc_platform;
+
+#endif
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-u8051.c linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-u8051.c
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-u8051.c	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-u8051.c	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,224 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <linux/sm501.h>
+#include <linux/sm501_regs.h>
+
+#include "sm501-ac97.h"
+#include "sm501-u8051.h"
+#include "sm501_fw.h"
+
+#define DRV_NAME                        "sm501-audio"
+#if 0
+#define dprintk(msg...) do { printk(KERN_DEBUG DRV_NAME ": " msg); } while (0)
+#else
+#define dprintk(msg...)
+#endif
+
+/* Functions for talking to the codec when firmware loaded */
+int sm501_write_command(struct sm501_audio *s, unsigned char command, unsigned int data0,
+			 unsigned int data1)
+{
+	int i;
+
+	/* Reset status. */
+	SmWrite8(SRAM(status_byte), 0);
+
+	/* Fill command and data bytes. */
+	dprintk("%s: %u %08x %08x\n", __func__, command, data0, data1);
+
+	SmWrite8(SRAM(command_byte), command);
+#if 1
+	SmWrite32(SRAM(data_byte[0]), data0);
+	SmWrite32(SRAM(data_byte[4]), data1);
+#else
+	SmWrite8(SRAM(data_byte[0]), LOBYTE(LOWORD(data0)));
+	SmWrite8(SRAM(data_byte[1]), HIBYTE(LOWORD(data0)));
+	SmWrite8(SRAM(data_byte[2]), LOBYTE(HIWORD(data0)));
+	SmWrite8(SRAM(data_byte[3]), HIBYTE(HIWORD(data0)));
+	SmWrite8(SRAM(data_byte[4]), LOBYTE(LOWORD(data1)));
+	SmWrite8(SRAM(data_byte[5]), HIBYTE(LOWORD(data1)));
+	SmWrite8(SRAM(data_byte[6]), LOBYTE(HIWORD(data1)));
+	SmWrite8(SRAM(data_byte[7]), HIBYTE(HIWORD(data1)));
+#endif
+
+	/* Interrupt 8051. */
+	SmWrite32(U8051_CPU_PROTOCOL_INTERRUPT, 1);
+
+	/* Wait for command to start. */
+	i = SM501_AC97_CODEC_TIMEOUT;
+	while (SmRead8(SRAM(command_busy)) == 0) {
+		if (i-- <= 0) {
+			dev_err(s->dev, "firmware did not accept command %u\n",
+				 command);
+			break;
+		}
+		udelay(1);
+	}
+
+	/* Wait for command to finish. */
+	while (SmRead8(SRAM(command_busy)) == 1)
+		udelay(1);
+
+	/* Return status byte. */
+	return(SmRead8(SRAM(status_byte)) == 1);
+}
+EXPORT_SYMBOL_GPL(sm501_write_command);
+
+static unsigned int __devinit ascii_hex(const char* text, int* index, int count)
+{
+	/* Initialize result. */
+	unsigned int result = 0;
+
+	/* Convert nibbles. */
+	while (count-- > 0)
+	{
+		/* Get Ascii nibble. */
+		char c = text[*index];
+
+		/* Convert from Ascii into hex. */
+		if (c >= '0' && c <= '9')
+			c -= '0';
+		else if (c >= 'A' && c <= 'F')
+			c -= 'A' - 10;
+		else if (c >= 'a' && c <= 'f')
+			c -= 'a' - 10;
+		else
+			/* Invalid digits, return 0. */
+			return 0;
+
+		/* Add nibble to result. */
+		result = (result << 4) | c;
+
+		/* Increment string index. */
+		(*index)++;
+	}
+
+	/* Return result. */
+	return result;
+}
+
+int __devinit sm501_load_firmware(struct sm501_audio *s, const char* firmware)
+{
+	unsigned int value;
+	int i, errors, retry;
+	unsigned int bytes, address, finish;
+
+	/* Put 8051 in reset state. */
+	value = SET_FIELD(0, U8051_RESET_CONTROL, RESET);
+	SmWrite32( U8051_RESET, value);
+
+	/* Cold reset AC97 controller */
+	value = SmRead32(AC97_CONTROL_STATUS);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_COLD_RESET, RESET);
+	SmWrite32(AC97_CONTROL_STATUS, value);
+
+	msleep(1);
+
+	value = SmRead32(AC97_CONTROL_STATUS);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_COLD_RESET, NORMAL);
+	value = SET_FIELD(value, AC97_CONTROL_STATUS_CONTROL, ENABLED);
+	SmWrite32(AC97_CONTROL_STATUS, value);
+
+	/* Retry loop for loading firmware. */
+	for (retry = 1; retry <= 3; retry++) {
+		dprintk("%s: loading firmware: retry %d\n", __func__, retry);
+
+		/* Reset error count. */
+		errors = 0;
+
+		/* !!BUGBUG!! Settle down 8051 or SRAM, seems to be required. */
+		msleep(250);
+
+		/* Zero SRAM. */
+		SmMemset(U8051_SRAM, 0, U8051_SRAM_SIZE);
+
+		/* Walk entire firmware. */
+		for (i = 0; i < strlen(firmware);) {
+			/* Skip colon (start of line). */
+			if (firmware[i] != ':') {
+				dev_err(s->dev, "%s: invalid firmware character '%c'\n",
+				       __func__, firmware[i]);
+				break;
+			}
+			i++;
+
+			/* Get number of bytes (first byte). */
+			bytes = ascii_hex(firmware, &i, 2);
+
+			/* Get address (second and third byte). */
+			address = ascii_hex(firmware, &i, 4);
+
+			/* Get finish flag (fourth byte). */
+			finish = ascii_hex(firmware, &i, 2);
+
+			/* Loop through all bytes. */
+			while (bytes-- > 0) {
+				/* Get byte. */
+				unsigned int value = ascii_hex(firmware,
+						&i, 2);
+
+				/* Write byte into SRAM address. */
+				SmWrite8( U8051_SRAM + address,
+						value);
+				if (SmRead8( U8051_SRAM + address) != value) {
+					if (errors++ < 10) {
+						dev_warn(s->dev, "%s: %04x: mismatch: "
+								"code(%02x) "
+								"sram(%02x)\n",
+						__func__, address, value,
+						(unsigned char)SmRead8( U8051_SRAM + address));
+					}
+				}
+
+				/* Increment address. */
+				address++;
+			}
+
+			/* Skip checksum. */
+			i += 2;
+
+			/* Finish when end of data. */
+			if (finish != 0)
+				break;
+		}
+
+		if (errors == 0)
+			break;
+	}
+
+	if (errors > 0)
+		return -EFAULT;
+
+	/* Enable 8051. */
+	value = SET_FIELD(0, U8051_RESET_CONTROL, ENABLE);
+	SmWrite32( U8051_RESET, value);
+
+	/* Wait until the init is complete. During its initialization the
+	firmware will increment the "init counter" twice, so that when the
+	counter becomes 2, we know that the initialization is complete. */
+	i = 8000;
+	while (SmRead8( SRAM(init_count)) != 2) {
+		if (i-- <= 0) {
+			dev_err(s->dev, "%s: firmware timed out during reset init_count = 0x%x test_count = 0x%x \n", 
+				__func__, SmRead8(SRAM(init_count)), SmRead8(SRAM(filler4)));
+			return -ETIMEDOUT;
+		}
+		msleep(1);
+	}
+	dev_err(s->dev, "%s:  init_count = 0x%x test_count = 0x%x  \n", __func__, SmRead8(SRAM(init_count)),
+				SmRead8(SmRead8(SRAM(filler4))));
+
+	dprintk("%s: firmware loaded and running\n", __func__);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sm501_load_firmware);
diff -uNra linux-2.6.27.6/sound/soc/sm501.old/sm501-u8051.h linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-u8051.h
--- linux-2.6.27.6/sound/soc/sm501.old/sm501-u8051.h	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/sound/soc/sm501.old/sm501-u8051.h	2011-05-08 18:06:18.000000000 +0800
@@ -0,0 +1,56 @@
+#ifndef _SM501_U8051_h
+#define _SM501_U8051_h
+#include "sm501-pcm.h"
+
+#define SET_TX_SLOT_0                    0
+#define SET_TX_SLOT_1                    1
+#define SET_TX_SLOT_2                    2
+#define SET_PLAYBACK_BUFFER_ADDRESS      3
+#define SET_PLAYBACK_BUFFER_SIZE         4
+#define SET_PLAYBACK_BUFFER_READY        5
+#define GET_BUFFER_STATUS                6
+#define START_STOP_AUDIO_PLAYBACK        7
+#define GET_RX_SLOT0                     8
+#define GET_RX_SLOT1                     9
+#define GET_RX_SLOT2                    10
+#define SET_CAPTURE_BUFFER_ADDRESS      11
+#define SET_CAPTURE_BUFFER_SIZE         12
+#define SET_CAPTURE_BUFFER_EMPTY        13
+#define START_STOP_AUDIO_CAPTURE        14
+#define SET_GET_AC97_REGISTER           15
+
+typedef struct
+{
+    unsigned char firmware[0x3000];                     /* 0x0000 */
+    union
+    {
+        struct
+        {
+            unsigned char playback_buffer_0[SM501_AC97_P_PERIOD_SIZE];    /* 0x3000 */
+            unsigned char playback_buffer_1[SM501_AC97_P_PERIOD_SIZE];    /* 0x3800 */
+        }B;
+        struct
+        {
+            unsigned char filler[0x0800];               /* 0x3000 */
+            unsigned char capture_buffer_0[0x0300];     /* 0x3800 */
+            unsigned char capture_buffer_1[0x0300];     /* 0x3B00 */
+        }C;
+    }A;
+   // unsigned char filler1[0x0200];                      /* 0x3C00 */
+    unsigned short ac97_regs[64];                       /* 0x3E00 */
+    unsigned char filler2[0x0170];                      /* 0x3E80 */
+    unsigned char command_byte;                         /* 0x3FF0 */
+    unsigned char status_byte;                          /* 0x3FF1 */
+    unsigned char data_byte[8];                         /* 0x3FF2 */
+    unsigned char filler3[2];                           /* 0x3FFA */
+    unsigned char buffer_status;                        /* 0x3FFC */
+    unsigned char command_busy;                         /* 0x3FFD */
+    unsigned char filler4;                              /* 0x3FFE */
+    unsigned char init_count;                           /* 0x3FFF */
+}
+__attribute__((packed)) FIRMWARE_SRAM;
+
+extern int sm501_write_command(struct sm501_audio *s, unsigned char command, unsigned int data0, unsigned int data1);
+extern int __devinit sm501_load_firmware(struct sm501_audio *s, const char* firmware);
+
+#endif
diff -uNra linux-2.6.27.6/.version linux-2.6.27.6.yaffs/.version
--- linux-2.6.27.6/.version	1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.27.6.yaffs/.version	2012-03-14 10:55:24.000000000 +0800
@@ -0,0 +1 @@
+586
